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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.jou

vivado_18960.backup.jou 8.4KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Wed May 18 19:29:49 2022

  6. # Process ID: 18960

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr

  15. update_compile_order -fileset sources_1

  16. reset_run synth_1

  17. launch_runs synth_1 -jobs 6

  18. wait_on_run synth_1

  19. launch_simulation

  20. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  21. source pwm_test_db.tcl

  22. close_sim

  23. launch_simulation

  24. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  25. source pwm_test_db.tcl

  26. reset_run synth_1

  27. launch_runs synth_1 -jobs 6

  28. wait_on_run synth_1

  29. close_sim

  30. launch_simulation

  31. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  32. source pwm_test_db.tcl

  33. reset_run synth_1

  34. launch_runs synth_1 -jobs 6

  35. wait_on_run synth_1

  36. reset_run synth_1

  37. launch_runs synth_1 -jobs 6

  38. wait_on_run synth_1

  39. close_sim

  40. launch_simulation

  41. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  42. source pwm_test_db.tcl

  43. reset_run synth_1

  44. launch_runs synth_1 -jobs 6

  45. wait_on_run synth_1

  46. close_sim

  47. launch_simulation

  48. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  49. source pwm_test_db.tcl

  50. reset_run synth_1

  51. launch_runs synth_1 -jobs 6

  52. wait_on_run synth_1

  53. close_sim

  54. launch_simulation

  55. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  56. source pwm_test_db.tcl

  57. reset_run synth_1

  58. launch_runs synth_1 -jobs 6

  59. wait_on_run synth_1

  60. close_sim

  61. launch_simulation

  62. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  63. source pwm_test_db.tcl

  64. reset_run synth_1

  65. launch_runs synth_1 -jobs 6

  66. wait_on_run synth_1

  67. close_sim

  68. launch_simulation

  69. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  70. source pwm_test_db.tcl

  71. close_sim

  72. launch_simulation

  73. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  74. source pwm_test_db.tcl

  75. reset_run synth_1

  76. launch_runs synth_1 -jobs 6

  77. wait_on_run synth_1

  78. close_sim

  79. launch_simulation

  80. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  81. source pwm_test_db.tcl

  82. close_sim

  83. launch_simulation

  84. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  85. source pwm_test_db.tcl

  86. set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]

  87. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  88. close_sim

  89. launch_simulation

  90. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  91. source pwm_test_db.tcl

  92. close_sim

  93. launch_simulation

  94. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  95. source pwm_test_db.tcl

  96. reset_run synth_1

  97. launch_runs synth_1 -jobs 6

  98. wait_on_run synth_1

  99. close_sim

  100. launch_simulation

  101. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  102. source pwm_test_db.tcl

  103. reset_run synth_1

  104. launch_runs synth_1 -jobs 6

  105. wait_on_run synth_1

  106. close_sim

  107. launch_simulation

  108. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  109. source pwm_test_db.tcl

  110. close_sim

  111. launch_simulation

  112. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  113. source pwm_test_db.tcl

  114. close_sim

  115. launch_simulation

  116. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  117. source pwm_test_db.tcl

  118. close_sim

  119. launch_simulation

  120. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  121. source pwm_test_db.tcl

  122. close_sim

  123. launch_simulation

  124. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  125. source pwm_test_db.tcl

  126. reset_run synth_1

  127. launch_runs synth_1 -jobs 6

  128. wait_on_run synth_1

  129. close_sim

  130. launch_simulation

  131. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  132. source pwm_test_db.tcl

  133. close_sim

  134. launch_simulation

  135. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  136. source pwm_test_db.tcl

  137. reset_run synth_1

  138. launch_runs synth_1 -jobs 6

  139. wait_on_run synth_1

  140. close_sim

  141. launch_simulation

  142. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  143. source pwm_test_db.tcl

  144. reset_run synth_1

  145. close_sim

  146. launch_simulation

  147. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  148. source pwm_test_db.tcl

  149. close_sim

  150. launch_simulation

  151. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  152. source pwm_test_db.tcl

  153. close_sim