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RTC funktionierende Version, sunset und sunrise calc, sleepMode

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steineral61021
2021-01-12 10:03:01 +01:00
parent 9c371b9469
commit 1f4423a2bb
133 changed files with 14416 additions and 60716 deletions
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RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h
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RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h
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/**
******************************************************************************
* @file stm32l1xx.h
* @author MCD Application Team
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L1xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l1xx
* @{
*/
#ifndef __STM32L1XX_H
#define __STM32L1XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32L1)
#define STM32L1
#endif /* STM32L1 */
/* Uncomment the line below according to the target STM32L device used in your
application
*/
#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
!defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \
!defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \
!defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE)
/* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
/* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
/* #define STM32L100xC */ /*!< STM32L100RC Devices */
/* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
/* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */
/* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
/* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
/* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
/* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */
/* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
/* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
/* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
/* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
/* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
/* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */
/* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */
/* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
/* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */
/* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
/* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
/* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */
/* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.1
*/
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L1xx_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32L100xB)
#include "stm32l100xb.h"
#elif defined(STM32L100xBA)
#include "stm32l100xba.h"
#elif defined(STM32L100xC)
#include "stm32l100xc.h"
#elif defined(STM32L151xB)
#include "stm32l151xb.h"
#elif defined(STM32L151xBA)
#include "stm32l151xba.h"
#elif defined(STM32L151xC)
#include "stm32l151xc.h"
#elif defined(STM32L151xCA)
#include "stm32l151xca.h"
#elif defined(STM32L151xD)
#include "stm32l151xd.h"
#elif defined(STM32L151xDX)
#include "stm32l151xdx.h"
#elif defined(STM32L151xE)
#include "stm32l151xe.h"
#elif defined(STM32L152xB)
#include "stm32l152xb.h"
#elif defined(STM32L152xBA)
#include "stm32l152xba.h"
#elif defined(STM32L152xC)
#include "stm32l152xc.h"
#elif defined(STM32L152xCA)
#include "stm32l152xca.h"
#elif defined(STM32L152xD)
#include "stm32l152xd.h"
#elif defined(STM32L152xDX)
#include "stm32l152xdx.h"
#elif defined(STM32L152xE)
#include "stm32l152xe.h"
#elif defined(STM32L162xC)
#include "stm32l162xc.h"
#elif defined(STM32L162xCA)
#include "stm32l162xca.h"
#elif defined(STM32L162xD)
#include "stm32l162xd.h"
#elif defined(STM32L162xDX)
#include "stm32l162xdx.h"
#elif defined(STM32L162xE)
#include "stm32l162xe.h"
#else
#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32l1xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32L1xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h
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/**
******************************************************************************
* @file system_stm32l1xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l1xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32L1XX_H
#define __SYSTEM_STM32L1XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32L1xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L1xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32L1XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h
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/**
******************************************************************************
* @file stm32l1xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_H
#define __STM32L1xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_conf.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
#define HAL_TICK_FREQ_10HZ 100U
#define HAL_TICK_FREQ_100HZ 10U
#define HAL_TICK_FREQ_1KHZ 1U
#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \
((__FREQ__) == HAL_TICK_FREQ_100HZ) || \
((__FREQ__) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH (0x00000000U)
#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
#if defined(FSMC_R_BASE)
#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
#endif /* FSMC_R_BASE */
#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RI_Constants RI: Routing Interface
* @{
*/
/** @defgroup RI_InputCapture Input Capture
* @{
*/
#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
/**
* @}
*/
/** @defgroup TIM_Select TIM Select
* @{
*/
#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */
#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
((__TIM__) == TIM_SELECT_TIM2) || \
((__TIM__) == TIM_SELECT_TIM3) || \
((__TIM__) == TIM_SELECT_TIM4))
/**
* @}
*/
/** @defgroup RI_InputCaptureRouting Input Capture Routing
* @{
*/
/* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
/**
* @}
*/
/** @defgroup RI_IOSwitch IO Switch
* @{
*/
#define RI_ASCR1_REGISTER (0x80000000U)
/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
#endif /* RI_ASCR2_CH1b */
/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)
#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)
#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)
#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)
#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)
#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)
#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)
#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)
#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)
#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)
#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)
#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)
#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)
#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)
#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)
#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)
#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)
#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)
#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)
#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)
#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)
#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)
#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)
#endif /* RI_ASCR2_CH1b */
#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)
#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)
#endif /* RI_ASCR2_CH0b */
#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \
((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \
((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \
((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \
((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \
((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \
((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \
((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \
((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \
((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \
((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \
((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \
((__IOSWITCH__) == RI_IOSWITCH_CH12b))
#else /* !RI_ASCR2_CH1b */
#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */
#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \
((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \
((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \
((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \
((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \
((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \
((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \
((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \
((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \
((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \
((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \
((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \
((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \
((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \
((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \
((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
#endif /* RI_ASCR2_CH0b */
#endif /* RI_ASCR2_CH1b */
/**
* @}
*/
/** @defgroup RI_Pin PIN define
* @{
*/
#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
* @{
*/
/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
* @brief Freeze/Unfreeze Peripherals in Debug mode
* @{
*/
/**
* @brief TIM2 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#endif
/**
* @brief TIM3 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#endif
/**
* @brief TIM4 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#endif
/**
* @brief TIM5 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#endif
/**
* @brief TIM6 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#endif
/**
* @brief TIM7 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#endif
/**
* @brief RTC Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
#endif
/**
* @brief WWDG Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
#endif
/**
* @brief IWDG Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
#endif
/**
* @brief I2C1 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
#endif
/**
* @brief I2C2 Peripherals Debug mode
*/
#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
#endif
/**
* @brief TIM9 Peripherals Debug mode
*/
#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
#endif
/**
* @brief TIM10 Peripherals Debug mode
*/
#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
#endif
/**
* @brief TIM11 Peripherals Debug mode
*/
#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
#endif
/**
* @}
*/
/**
* @}
*/
/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
* @{
*/
/** @defgroup SYSCFG_VrefInt VREFINT configuration
* @{
*/
/**
* @brief Enables or disables the output of internal reference voltage
* (VrefInt) on I/O pin.
* @note The VrefInt output can be routed to any I/O in group 3:
* - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
* - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
* - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
* CH1b (PF11) or CH2b (PF12).
* Note: Comparator peripheral clock must be preliminarily enabled,
* either in COMP user function "HAL_COMP_MspInit()" (should be
* done if comparators are used) or by direct clock enable:
* Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
* Note: In addition with this macro, VrefInt output buffer must be
* connected to the selected I/O pin. Refer to macro
* "__HAL_RI_IOSWITCH_CLOSE()".
* @note VrefInt output enable: Internal reference voltage connected to I/O group 3
* VrefInt output disable: Internal reference voltage disconnected from I/O group 3
* @retval None
*/
#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
/**
* @}
*/
/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
* @{
*/
/**
* @brief Main Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief System Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
/** @brief Embedded SRAM mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
#if defined(FSMC_R_BASE)
/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* FSMC_R_BASE */
/**
* @brief Returns the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
* @arg SYSCFG_BOOT_MAINFLASH
* @arg SYSCFG_BOOT_SYSTEMFLASH
* @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
* @arg SYSCFG_BOOT_SRAM
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
/**
* @}
*/
/** @defgroup SYSCFG_USBConfig USB DP line Configuration
* @{
*/
/**
* @brief Control the internal pull-up on USB DP line.
*/
#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RI_Macris RI: Routing Interface
* @{
*/
/** @defgroup RI_InputCaputureConfig Input Capture configuration
* @{
*/
/**
* @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
* @param __TIMSELECT__ Timer select.
* This parameter can be one of the following values:
* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
* @param __INPUT__ selects which pin to be routed to Input Capture.
* This parameter must be a value of @ref RI_InputCaptureRouting
* e.g.
* __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
* allows routing of Input capture IC1 of TIM2 to PA4.
* For details about correspondence between RI_INPUTCAPTUREROUTING_x
* and I/O pins refer to the parameters' description in the header file
* or refer to the product reference manual.
* @note Input capture selection bits are not reset by this function.
* To reset input capture selection bits, use SYSCFG_RIDeInit() function.
* @note The I/O should be configured in alternate function mode (AF14) using
* GPIO_PinAFConfig() function.
* @retval None.
*/
#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \
do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
}while(0)
/**
* @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
* @param __TIMSELECT__ Timer select.
* This parameter can be one of the following values:
* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
* @param __INPUT__ selects which pin to be routed to Input Capture.
* This parameter must be a value of @ref RI_InputCaptureRouting
* @retval None.
*/
#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \
do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
}while(0)
/**
* @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
* @param __TIMSELECT__ Timer select.
* This parameter can be one of the following values:
* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
* @param __INPUT__ selects which pin to be routed to Input Capture.
* This parameter must be a value of @ref RI_InputCaptureRouting
* @retval None.
*/
#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \
do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
}while(0)
/**
* @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
* @param __TIMSELECT__ Timer select.
* This parameter can be one of the following values:
* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
* @param __INPUT__ selects which pin to be routed to Input Capture.
* This parameter must be a value of @ref RI_InputCaptureRouting
* @retval None.
*/
#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \
do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
}while(0)
/**
* @}
*/
/** @defgroup RI_SwitchControlConfig Switch Control configuration
* @{
*/
/**
* @brief Enable or disable the switch control mode.
* @note ENABLE: ADC analog switches closed if the corresponding
* I/O switch is also closed.
* When using COMP1, switch control mode must be enabled.
* @note DISABLE: ADC analog switches open or controlled by the ADC interface.
* When using the ADC for acquisition, switch control mode
* must be disabled.
* @note COMP1 comparator and ADC cannot be used at the same time since
* they share the ADC switch matrix.
* @retval None
*/
#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
/*
* @brief Close or Open the routing interface Input Output switches.
* @param __IOSWITCH__ selects the I/O analog switch number.
* This parameter must be a value of @ref RI_IOSwitch
* @retval None
*/
#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
if ((__IOSWITCH__) >> 31 != 0 ) \
{ \
SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
} \
else \
{ \
SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
} \
}while(0)
#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
if ((__IOSWITCH__) >> 31 != 0 ) \
{ \
CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
} \
else \
{ \
CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
} \
}while(0)
#if defined (COMP_CSR_SW1)
/**
* @brief Close or open the internal switch COMP1_SW1.
* This switch connects I/O pin PC3 (can be used as ADC channel 13)
* and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
* 26) and COMP1 non-inverting input.
* Pin PC3 connection depends on another switch setting, refer to
* macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
* @retval None.
*/
#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)
#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
#endif /* COMP_CSR_SW1 */
/**
* @}
*/
/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
* @{
*/
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports A
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR1, (__IOPIN__)); \
} while(0)
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports B
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
} while(0)
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports C
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR2, (__IOPIN__)); \
} while(0)
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports D
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
} while(0)
#if defined (GPIOE_BASE)
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports E
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR3, (__IOPIN__)); \
} while(0)
#endif /* GPIOE_BASE */
#if defined(GPIOF_BASE) || defined(GPIOG_BASE)
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports F
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
} while(0)
/**
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports G
* When the I/Os are programmed in input mode by standard I/O port
* registers, the Schmitt trigger and the hysteresis are enabled by default.
* When hysteresis is disabled, it is possible to read the
* corresponding port with a trigger level of VDDIO/2.
* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
* This parameter must be a value of @ref RI_Pin
* @retval None
*/
#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
} while(0)
#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
SET_BIT(RI->HYSCR4, (__IOPIN__)); \
} while(0)
#endif /* GPIOF_BASE || GPIOG_BASE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern uint32_t uwTickFreq;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
uint32_t HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h
-437
View File
@@ -1,437 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_CORTEX_H
#define __STM32L1xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported Macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
* @{
*/
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
/**
* @}
*/
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h
-198
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@@ -1,198 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_DEF
#define __STM32L1xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx.h"
#include "Legacy/stm32_hal_legacy.h"
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
(__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0)
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1)
/* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release"
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifdef __cplusplus
}
#endif
#endif /* ___STM32L1xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h
-652
View File
@@ -1,652 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L1xx_HAL_DMA_H
#define STM32L1xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
}DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE
#define DMA_IT_HT DMA_CCR_HTIE
#define DMA_IT_TE DMA_CCR_TEIE
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 DMA_ISR_GIF1
#define DMA_FLAG_TC1 DMA_ISR_TCIF1
#define DMA_FLAG_HT1 DMA_ISR_HTIF1
#define DMA_FLAG_TE1 DMA_ISR_TEIF1
#define DMA_FLAG_GL2 DMA_ISR_GIF2
#define DMA_FLAG_TC2 DMA_ISR_TCIF2
#define DMA_FLAG_HT2 DMA_ISR_HTIF2
#define DMA_FLAG_TE2 DMA_ISR_TEIF2
#define DMA_FLAG_GL3 DMA_ISR_GIF3
#define DMA_FLAG_TC3 DMA_ISR_TCIF3
#define DMA_FLAG_HT3 DMA_ISR_HTIF3
#define DMA_FLAG_TE3 DMA_ISR_TEIF3
#define DMA_FLAG_GL4 DMA_ISR_GIF4
#define DMA_FLAG_TC4 DMA_ISR_TCIF4
#define DMA_FLAG_HT4 DMA_ISR_HTIF4
#define DMA_FLAG_TE4 DMA_ISR_TEIF4
#define DMA_FLAG_GL5 DMA_ISR_GIF5
#define DMA_FLAG_TC5 DMA_ISR_TCIF5
#define DMA_FLAG_HT5 DMA_ISR_HTIF5
#define DMA_FLAG_TE5 DMA_ISR_TEIF5
#define DMA_FLAG_GL6 DMA_ISR_GIF6
#define DMA_FLAG_TC6 DMA_ISR_TCIF6
#define DMA_FLAG_HT6 DMA_ISR_HTIF6
#define DMA_FLAG_TE6 DMA_ISR_TEIF6
#define DMA_FLAG_GL7 DMA_ISR_GIF7
#define DMA_FLAG_TC7 DMA_ISR_TCIF7
#define DMA_FLAG_HT7 DMA_ISR_HTIF7
#define DMA_FLAG_TE7 DMA_ISR_TEIF7
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#else
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCIFx: Transfer complete flag
* @arg DMA_FLAG_HTIFx: Half transfer complete flag
* @arg DMA_FLAG_TEIFx: Transfer error flag
* @arg DMA_ISR_GIFx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__ DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L1xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h
-316
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@@ -1,316 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L1xx_HAL_EXTI_H
#define STM32L1xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event */
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */
#if defined(EXTI_IMR_IM23)
#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the channel acquisition interrupt */
#endif /* EXTI_IMR_IM23 */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#if defined (GPIOE)
#define EXTI_GPIOE 0x00000004u
#endif /* GPIOE */
#if defined (GPIOF)
#define EXTI_GPIOF 0x00000005u
#endif /* GPIOF */
#if defined (GPIOG)
#define EXTI_GPIOG 0x00000006u
#endif /* GPIOG */
#define EXTI_GPIOH 0x00000007u
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI bit usage
*/
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#if defined(EXTI_IMR_IM23)
#define EXTI_LINE_NB 24UL
#else
#define EXTI_LINE_NB 23UL
#endif /* EXTI_IMR_IM23 */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#if !defined (GPIOE)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOH))
#elif !defined (GPIOF)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#endif /* GPIOE */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32l1xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h
-409
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@@ -1,409 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_flash.h
* @author MCD Application Team
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_FLASH_H
#define __STM32L1xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
/**
* @}
*/
/** @addtogroup FLASH_Private_Macros
* @{
*/
#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
{
FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_PROGRAM = 2U,
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
__IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */
HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code
This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */
#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */
#define HAL_FLASH_ERROR_OPTVUSR 0x20U /*!< Option UserValidity Error. */
#define HAL_FLASH_ERROR_OPERATION 0x40U /*!< Not used */
/**
* @}
*/
/** @defgroup FLASH_Page_Size FLASH size information
* @{
*/
#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U)
#define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
/**
* @}
*/
/** @defgroup FLASH_Interrupts FLASH Interrupts
* @{
*/
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
/**
* @}
*/
/** @defgroup FLASH_Flags FLASH Flags
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
#define FLASH_FLAG_ENDHV FLASH_SR_ENDHV /*!< FLASH End of High Voltage flag */
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
/* Cat2 & Cat3*/
#if defined(FLASH_SR_RDERR)
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */
#endif /* FLASH_SR_RDERR */
/* Cat3, Cat4 & Cat5*/
#if defined(FLASH_SR_OPTVERRUSR)
#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
#endif /* FLASH_SR_OPTVERRUSR */
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */
#define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
#define FLASH_PEKEY1 (0x89ABCDEFU) /*!< Flash program erase key1 */
#define FLASH_PEKEY2 (0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
to unlock the write access to the FLASH_PECR register and
data EEPROM */
#define FLASH_PRGKEY1 (0x8C9DAEBFU) /*!< Flash program memory key1 */
#define FLASH_PRGKEY2 (0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
to unlock the program memory */
#define FLASH_OPTKEY1 (0xFBEAD9C8U) /*!< Flash option key1 */
#define FLASH_OPTKEY2 (0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
unlock the write access to the option byte block */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features
* @{
*/
/** @defgroup FLASH_Interrupt FLASH Interrupts
* @brief macros to handle FLASH interrupts
* @{
*/
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->PECR), (__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__))
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag
* @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag
@if STM32L100xB
@elif STM32L100xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L151xB
@elif STM32L151xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L152xB
@elif STM32L152xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L100xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L151xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L152xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L162xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@else
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@endif
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag
@if STM32L100xB
@elif STM32L100xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L151xB
@elif STM32L151xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L152xB
@elif STM32L152xBA
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
@elif STM32L100xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L151xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L152xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@elif STM32L162xC
* @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP)
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@else
* @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error
@endif
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Include FLASH HAL Extended module */
#include "stm32l1xx_hal_flash_ex.h"
#include "stm32l1xx_hal_flash_ramfunc.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
/* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h
-968
View File
@@ -1,968 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_FLASH_EX_H
#define __STM32L1xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
#elif defined(FLASH_SR_RDERR)
#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
FLASH_FLAG_RDERR)
#elif defined(FLASH_SR_OPTVERRUSR)
#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
FLASH_FLAG_OPTVERRUSR)
#else
#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
#endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
|| defined(STM32L151xBA) || defined(STM32L152xBA)
/******* Devices with FLASH 128K *******/
#define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */
#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
|| defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
/******* Devices with FLASH 256K *******/
#define FLASH_NBPAGES_MAX 1025U /* 1025 pages from page 0 to page 1024U */
#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX)
/******* Devices with FLASH 384K *******/
#define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */
#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
/******* Devices with FLASH 512K *******/
#define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */
#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
#define WRP_MASK_LOW (0x0000FFFFU)
#define WRP_MASK_HIGH (0xFFFF0000U)
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Macros
* @{
*/
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
((__VALUE__) == OB_WRPSTATE_ENABLE))
#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
((__LEVEL__) == OB_RDP_LEVEL_1) ||\
((__LEVEL__) == OB_RDP_LEVEL_2))
#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
((__LEVEL__) == OB_BOR_LEVEL1) || \
((__LEVEL__) == OB_BOR_LEVEL2) || \
((__LEVEL__) == OB_BOR_LEVEL3) || \
((__LEVEL__) == OB_BOR_LEVEL4) || \
((__LEVEL__) == OB_BOR_LEVEL5))
#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
#if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
#elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
#elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
#endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */
#if defined(FLASH_OBR_SPRMOD)
#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
((__VALUE__) == OB_PCROP_STATE_ENABLE))
#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
#endif /* FLASH_OBR_SPRMOD */
#if defined(FLASH_OBR_nRST_BFB2)
#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
#endif /* FLASH_OBR_nRST_BFB2 */
#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
/** @defgroup FLASHEx_Address FLASHEx Address
* @{
*/
#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
|| defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \
|| defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \
|| defined(STM32L162xCA)
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))
#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))
#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
/**
* @}
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< TypeErase: Page Erase only.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Option Bytes PROGRAM structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
|| defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
|| defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
|| defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
|| defined(STM32L152xDX) || defined(STM32L162xDX)
uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or
Sectors 96 to 111 for STM32L1xxxDX devices.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */
#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
@ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
} FLASH_OBProgramInitTypeDef;
#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
/**
* @brief FLASH Advanced Option Bytes Program structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
#if defined(FLASH_OBR_SPRMOD)
uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
This parameter can be a value of @ref FLASHEx_PCROP_State */
uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
#endif /* FLASH_OBR_SPRMOD */
#if defined(FLASH_OBR_nRST_BFB2)
uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
#endif /* FLASH_OBR_nRST_BFB2*/
} FLASH_AdvOBProgramInitTypeDef;
/**
* @}
*/
#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/
/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Page erase only*/
/**
* @}
*/
/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
* @{
*/
#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
#define OPTIONBYTE_BOR (0x08U) /*!<BOR option byte configuration*/
/**
* @}
*/
/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired sectors*/
#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired sectors*/
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
* @{
*/
/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
#define OB_WRP1_PAGES0TO15 (0x00000001U) /* Write protection of Sector0 */
#define OB_WRP1_PAGES16TO31 (0x00000002U) /* Write protection of Sector1 */
#define OB_WRP1_PAGES32TO47 (0x00000004U) /* Write protection of Sector2 */
#define OB_WRP1_PAGES48TO63 (0x00000008U) /* Write protection of Sector3 */
#define OB_WRP1_PAGES64TO79 (0x00000010U) /* Write protection of Sector4 */
#define OB_WRP1_PAGES80TO95 (0x00000020U) /* Write protection of Sector5 */
#define OB_WRP1_PAGES96TO111 (0x00000040U) /* Write protection of Sector6 */
#define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */
#define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */
#define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */
#define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */
#define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */
#define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */
#define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */
#define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */
#define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */
#define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */
#define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */
#define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */
#define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */
#define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */
#define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */
#define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */
#define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */
#define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */
#define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */
#define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */
#define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */
#define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */
#define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */
#define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */
#define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */
#define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
/**
* @}
*/
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
|| defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
|| defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
|| defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
* @{
*/
/* Pages for Cat3, Cat4 & Cat5 devices*/
#define OB_WRP2_PAGES512TO527 (0x00000001U) /* Write protection of Sector32 */
#define OB_WRP2_PAGES528TO543 (0x00000002U) /* Write protection of Sector33 */
#define OB_WRP2_PAGES544TO559 (0x00000004U) /* Write protection of Sector34 */
#define OB_WRP2_PAGES560TO575 (0x00000008U) /* Write protection of Sector35 */
#define OB_WRP2_PAGES576TO591 (0x00000010U) /* Write protection of Sector36 */
#define OB_WRP2_PAGES592TO607 (0x00000020U) /* Write protection of Sector37 */
#define OB_WRP2_PAGES608TO623 (0x00000040U) /* Write protection of Sector38 */
#define OB_WRP2_PAGES624TO639 (0x00000080U) /* Write protection of Sector39 */
#define OB_WRP2_PAGES640TO655 (0x00000100U) /* Write protection of Sector40 */
#define OB_WRP2_PAGES656TO671 (0x00000200U) /* Write protection of Sector41 */
#define OB_WRP2_PAGES672TO687 (0x00000400U) /* Write protection of Sector42 */
#define OB_WRP2_PAGES688TO703 (0x00000800U) /* Write protection of Sector43 */
#define OB_WRP2_PAGES704TO719 (0x00001000U) /* Write protection of Sector44 */
#define OB_WRP2_PAGES720TO735 (0x00002000U) /* Write protection of Sector45 */
#define OB_WRP2_PAGES736TO751 (0x00004000U) /* Write protection of Sector46 */
#define OB_WRP2_PAGES752TO767 (0x00008000U) /* Write protection of Sector47 */
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
|| defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
|| defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
#define OB_WRP2_PAGES768TO783 (0x00010000U) /* Write protection of Sector48 */
#define OB_WRP2_PAGES784TO799 (0x00020000U) /* Write protection of Sector49 */
#define OB_WRP2_PAGES800TO815 (0x00040000U) /* Write protection of Sector50 */
#define OB_WRP2_PAGES816TO831 (0x00080000U) /* Write protection of Sector51 */
#define OB_WRP2_PAGES832TO847 (0x00100000U) /* Write protection of Sector52 */
#define OB_WRP2_PAGES848TO863 (0x00200000U) /* Write protection of Sector53 */
#define OB_WRP2_PAGES864TO879 (0x00400000U) /* Write protection of Sector54 */
#define OB_WRP2_PAGES880TO895 (0x00800000U) /* Write protection of Sector55 */
#define OB_WRP2_PAGES896TO911 (0x01000000U) /* Write protection of Sector56 */
#define OB_WRP2_PAGES912TO927 (0x02000000U) /* Write protection of Sector57 */
#define OB_WRP2_PAGES928TO943 (0x04000000U) /* Write protection of Sector58 */
#define OB_WRP2_PAGES944TO959 (0x08000000U) /* Write protection of Sector59 */
#define OB_WRP2_PAGES960TO975 (0x10000000U) /* Write protection of Sector60 */
#define OB_WRP2_PAGES976TO991 (0x20000000U) /* Write protection of Sector61 */
#define OB_WRP2_PAGES992TO1007 (0x40000000U) /* Write protection of Sector62 */
#define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
#define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */
#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|| defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
|| defined(STM32L162xE)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
* @{
*/
/* Pages for devices with FLASH >= 256KB*/
#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */
#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */
#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */
#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */
#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */
#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */
#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */
#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */
#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */
#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */
#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */
#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */
#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */
#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */
#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */
#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */
#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */
#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */
#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */
#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */
#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */
#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */
#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */
#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */
#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */
#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */
#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */
#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */
#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */
#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */
#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */
#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */
#define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
|| defined(STM32L152xDX) || defined(STM32L162xDX)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
* @{
*/
/* Pages for Cat5 devices*/
#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/
#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/
#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/
#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/
#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/
#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/
#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/
#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/
#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/
#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/
#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/
#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/
#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/
#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/
#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/
#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/
#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/
#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/
#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/
#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/
#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/
#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/
#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/
#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/
#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/
#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/
#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/
#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/
#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/
#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/
#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/
#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/
#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
#define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
it is no more possible to go back to level 1 or 0 */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
* @{
*/
#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
* @{
*/
#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
#if defined(FLASH_OBR_SPRMOD)
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
* @{
*/
#define OPTIONBYTE_PCROP (0x01U) /*!<PCROP option byte configuration*/
/**
* @}
*/
#endif /* FLASH_OBR_SPRMOD */
#if defined(FLASH_OBR_nRST_BFB2)
/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
* @{
*/
#define OPTIONBYTE_BOOTCONFIG (0x02U) /*!<BOOTConfig option byte configuration*/
/**
* @}
*/
#endif /* FLASH_OBR_nRST_BFB2 */
#if defined(FLASH_OBR_SPRMOD)
/** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
* @{
*/
#define OB_PCROP_STATE_DISABLE (0x00U) /*!<Disable PCROP for selected sectors */
#define OB_PCROP_STATE_ENABLE (0x01U) /*!<Enable PCROP for selected sectors */
/**
* @}
*/
/** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
* @{
*/
#define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
#define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
/**
* @}
*/
#endif /* FLASH_OBR_SPRMOD */
#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
|| defined(STM32L162xC)
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
* @{
*/
/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
#define OB_PCROP1_PAGES0TO15 (0x00000001U) /* PC Read/Write protection of Sector0 */
#define OB_PCROP1_PAGES16TO31 (0x00000002U) /* PC Read/Write protection of Sector1 */
#define OB_PCROP1_PAGES32TO47 (0x00000004U) /* PC Read/Write protection of Sector2 */
#define OB_PCROP1_PAGES48TO63 (0x00000008U) /* PC Read/Write protection of Sector3 */
#define OB_PCROP1_PAGES64TO79 (0x00000010U) /* PC Read/Write protection of Sector4 */
#define OB_PCROP1_PAGES80TO95 (0x00000020U) /* PC Read/Write protection of Sector5 */
#define OB_PCROP1_PAGES96TO111 (0x00000040U) /* PC Read/Write protection of Sector6 */
#define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write protection of Sector7 */
#define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write protection of Sector8 */
#define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write protection of Sector9 */
#define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write protection of Sector10 */
#define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write protection of Sector11 */
#define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write protection of Sector12 */
#define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write protection of Sector13 */
#define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write protection of Sector14 */
#define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write protection of Sector15 */
#define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write protection of Sector16 */
#define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write protection of Sector17 */
#define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write protection of Sector18 */
#define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write protection of Sector19 */
#define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write protection of Sector20 */
#define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write protection of Sector21 */
#define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write protection of Sector22 */
#define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write protection of Sector23 */
#define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write protection of Sector24 */
#define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write protection of Sector25 */
#define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write protection of Sector26 */
#define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write protection of Sector27 */
#define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write protection of Sector28 */
#define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write protection of Sector29 */
#define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write protection of Sector30 */
#define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write protection of Sector31 */
#define OB_PCROP1_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
* @{
*/
/* Pages for Cat3, Cat4 & Cat5 devices*/
#define OB_PCROP2_PAGES512TO527 (0x00000001U) /* PC Read/Write protection of Sector32 */
#define OB_PCROP2_PAGES528TO543 (0x00000002U) /* PC Read/Write protection of Sector33 */
#define OB_PCROP2_PAGES544TO559 (0x00000004U) /* PC Read/Write protection of Sector34 */
#define OB_PCROP2_PAGES560TO575 (0x00000008U) /* PC Read/Write protection of Sector35 */
#define OB_PCROP2_PAGES576TO591 (0x00000010U) /* PC Read/Write protection of Sector36 */
#define OB_PCROP2_PAGES592TO607 (0x00000020U) /* PC Read/Write protection of Sector37 */
#define OB_PCROP2_PAGES608TO623 (0x00000040U) /* PC Read/Write protection of Sector38 */
#define OB_PCROP2_PAGES624TO639 (0x00000080U) /* PC Read/Write protection of Sector39 */
#define OB_PCROP2_PAGES640TO655 (0x00000100U) /* PC Read/Write protection of Sector40 */
#define OB_PCROP2_PAGES656TO671 (0x00000200U) /* PC Read/Write protection of Sector41 */
#define OB_PCROP2_PAGES672TO687 (0x00000400U) /* PC Read/Write protection of Sector42 */
#define OB_PCROP2_PAGES688TO703 (0x00000800U) /* PC Read/Write protection of Sector43 */
#define OB_PCROP2_PAGES704TO719 (0x00001000U) /* PC Read/Write protection of Sector44 */
#define OB_PCROP2_PAGES720TO735 (0x00002000U) /* PC Read/Write protection of Sector45 */
#define OB_PCROP2_PAGES736TO751 (0x00004000U) /* PC Read/Write protection of Sector46 */
#define OB_PCROP2_PAGES752TO767 (0x00008000U) /* PC Read/Write protection of Sector47 */
#define OB_PCROP2_PAGES768TO783 (0x00010000U) /* PC Read/Write protection of Sector48 */
#define OB_PCROP2_PAGES784TO799 (0x00020000U) /* PC Read/Write protection of Sector49 */
#define OB_PCROP2_PAGES800TO815 (0x00040000U) /* PC Read/Write protection of Sector50 */
#define OB_PCROP2_PAGES816TO831 (0x00080000U) /* PC Read/Write protection of Sector51 */
#define OB_PCROP2_PAGES832TO847 (0x00100000U) /* PC Read/Write protection of Sector52 */
#define OB_PCROP2_PAGES848TO863 (0x00200000U) /* PC Read/Write protection of Sector53 */
#define OB_PCROP2_PAGES864TO879 (0x00400000U) /* PC Read/Write protection of Sector54 */
#define OB_PCROP2_PAGES880TO895 (0x00800000U) /* PC Read/Write protection of Sector55 */
#define OB_PCROP2_PAGES896TO911 (0x01000000U) /* PC Read/Write protection of Sector56 */
#define OB_PCROP2_PAGES912TO927 (0x02000000U) /* PC Read/Write protection of Sector57 */
#define OB_PCROP2_PAGES928TO943 (0x04000000U) /* PC Read/Write protection of Sector58 */
#define OB_PCROP2_PAGES944TO959 (0x08000000U) /* PC Read/Write protection of Sector59 */
#define OB_PCROP2_PAGES960TO975 (0x10000000U) /* PC Read/Write protection of Sector60 */
#define OB_PCROP2_PAGES976TO991 (0x20000000U) /* PC Read/Write protection of Sector61 */
#define OB_PCROP2_PAGES992TO1007 (0x40000000U) /* PC Read/Write protection of Sector62 */
#define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write protection of Sector63 */
#define OB_PCROP2_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
/**
* @}
*/
#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
/** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
* @{
*/
#define FLASH_TYPEERASEDATA_BYTE (0x00U) /*!<Erase byte (8-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_HALFWORD (0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEERASEDATA_WORD (0x02U) /*!<Erase a word (32-bit) at a specified address.*/
/**
* @}
*/
/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
* @{
*/
#define FLASH_TYPEPROGRAMDATA_BYTE (0x00U) /*!<Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTBYTE (0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD (0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAMDATA_FASTWORD (0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
/**
* @}
*/
#if defined(FLASH_OBR_nRST_BFB2)
/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
* @{
*/
#define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank 2
or Bank 1, depending on the activation of the bank */
#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position
and this parameter is selected the device will boot from Bank1(Default) */
/**
* @}
*/
#endif /* FLASH_OBR_nRST_BFB2 */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
* @retval none
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \
if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
} while(0U)
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @brief Enable the FLASH 64-bit access.
* @note Read access 64 bit is used.
* @note This bit cannot be written at the same time as the LATENCY and
* PRFTEN bits.
* @retval none
*/
#define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
/**
* @brief Disable the FLASH 64-bit access.
* @note Read access 32 bit is used
* @note To reset this bit, the LATENCY should be zero wait state and the
* prefetch off.
* @retval none
*/
#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
/**
* @brief Enable the FLASH prefetch buffer.
* @retval none
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \
SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
} while(0U)
/**
* @brief Disable the FLASH prefetch buffer.
* @retval none
*/
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
/**
* @brief Enable the FLASH power down during Sleep mode
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Disable the FLASH power down during Sleep mode
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Enable the Flash Run power down mode.
* @note Writing this bit to 0 this bit, automatically the keys are
* loss and a new unlock sequence is necessary to re-write it to 1.
*/
#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
FLASH->PDKEYR = FLASH_PDKEY2; \
SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
} while (0U)
/**
* @brief Disable the Flash Run power down mode.
* @note Writing this bit to 0 this bit, automatically the keys are
* loss and a new unlock sequence is necessary to re-write it to 1.
*/
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
FLASH->PDKEYR = FLASH_PDKEY2; \
CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
} while (0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
#if defined(FLASH_OBR_SPRMOD)
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
#endif /* FLASH_OBR_SPRMOD */
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h
-119
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@@ -1,119 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_FLASH_RAMFUNC_H
#define __STM32L1xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH_RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{
*/
/*
* @brief FLASH memory functions that should be executed from internal SRAM.
* These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c"
* file.
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2
* @{
*/
#if defined(FLASH_PECR_PARALLBANK)
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
#endif /* FLASH_PECR_PARALLBANK */
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3
* @{
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t *Error);
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group4
* @{
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_FLASH_RAMFUNC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h
-320
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@@ -1,320 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_GPIO_H
#define __STM32L1xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
((MODE) == GPIO_MODE_AF_PP) ||\
((MODE) == GPIO_MODE_AF_OD) ||\
((MODE) == GPIO_MODE_IT_RISING) ||\
((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
/**
* @}
*/
/* Include GPIO HAL Extension module */
#include "stm32l1xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @brief GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h
-205
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@@ -1,205 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_GPIO_EX_H
#define __STM32L1xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
* @{
*/
/* AF 0 selection */
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
#define GPIO_AF0_TAMPER ((uint8_t)0x00) /*!< TAMPER Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_OUT Alternate Function mapping */
/* AF 1 selection */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
/* AF 2 selection */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */
/* AF 3 selection */
#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */
/* AF 4 selection */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
/* AF 5 selection */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */
/* AF 6 selection */
#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\
defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */
#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE || STM32L162xDX */
/* AF 7 selection */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
/* AF 8 selection */
#if defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\
defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */
#endif /* STM32L151xD || STM32L151xE || STM32L151xDX || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE || STM32L162xDX */
/* AF 9 selection */
/* AF 10 selection */
/* AF 11 selection */
#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\
defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX)
#define GPIO_AF11_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */
#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
/* AF 12 selection */
#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
#define GPIO_AF12_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */
#define GPIO_AF12_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
/* AF 13 selection */
/* AF 14 selection */
#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */
#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */
#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */
#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */
/* AF 15 selection */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
/**
* @}
*/
/**
* @}
*/
/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
* @{
*/
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOH))? 5U :\
((__GPIOx__) == (GPIOF))? 6U : 7U)
#endif
#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U : 5U)
#endif
#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U : 5U)
#endif
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_GPIO_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h
-486
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@@ -1,486 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_PWR_H
#define __STM32L1xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;
/**
* @}
*/
/* Internal constants --------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants
* @{
*/
#define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_register_alias_address PWR Register alias address
* @{
*/
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define PWR_CR_OFFSET 0x00
#define PWR_CSR_OFFSET 0x04
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
/**
* @}
*/
/** @defgroup PWR_CR_register_alias PWR CR Register alias address
* @{
*/
/* --- CR Register ---*/
/* Alias word address of LPSDSR bit */
#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR)
#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
/* Alias word address of DBP bit */
#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
/* Alias word address of LPRUN bit */
#define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN)
#define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
/* Alias word address of PVDE bit */
#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
/* Alias word address of FWU bit */
#define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU)
#define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
/* Alias word address of ULP bit */
#define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP)
#define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
/**
* @}
*/
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
* @{
*/
/* --- CSR Register ---*/
/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
/**
* @}
*/
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
(Compare internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON (0x00000000U)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
/**
* @}
*/
/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#define PWR_FLAG_VOS PWR_CSR_VOSF
#define PWR_FLAG_REGLP PWR_CSR_REGLPF
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{
*/
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__ specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
* System frequency up to 32 MHz.
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
* System frequency up to 16 MHz.
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
* System frequency up to 4.2 MHz
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
/** @brief Check PWR flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm (Alarm B),
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
* An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
* This bit indicates the state of the internal voltage reference, VREFINT.
* @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
* the internal regulator to be ready after the voltage range is changed.
* The VOSF bit indicates that the regulator has reached the voltage level
* defined with bits VOS of PWR_CR register.
* @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
* mode, this bit stays at 1 until the regulator is ready in main mode.
* A polling on this bit is recommended to wait for the regulator main mode.
* This bit is reset by hardware when the regulator is ready.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the PWR's pending flags.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
/**
* @brief Enable interrupt on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable interrupt on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
/**
* @brief Enable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
/**
* @}
*/
/* Include PWR HAL Extension module */
#include "stm32l1xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h
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/**
******************************************************************************
* @file stm32l1xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_PWR_EX_H
#define __STM32L1xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
* @{
*/
#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3))
#else
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1
#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2))
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1
* @{
*/
/* Peripheral Control methods ************************************************/
uint32_t HAL_PWREx_GetVoltageRange(void);
void HAL_PWREx_EnableFastWakeUp(void);
void HAL_PWREx_DisableFastWakeUp(void);
void HAL_PWREx_EnableUltraLowPower(void);
void HAL_PWREx_DisableUltraLowPower(void);
void HAL_PWREx_EnableLowPowerRunMode(void);
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_PWR_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h
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RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h
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RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h
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/**
******************************************************************************
* @file stm32l1xx_hal_rtc.h
* @author MCD Application Team
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_RTC_H
#define __STM32L1xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup RTC RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
} HAL_RTCStateTypeDef;
/**
* @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
} RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
} RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
} RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
uint32_t Alarm; /*!< Specifies the alarm .
This parameter can be a value of @ref RTC_Alarms_Definitions */
} RTC_AlarmTypeDef;
/**
* @brief RTC Handle Structure definition
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
typedef struct __RTC_HandleTypeDef
#else
typedef struct
#endif
{
RTC_TypeDef *Instance; /*!< Register base address */
RTC_InitTypeDef Init; /*!< RTC required parameters */
HAL_LockTypeDef Lock; /*!< RTC locking object */
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
} RTC_HandleTypeDef;
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LPTIM Callback ID enumeration definition
*/
typedef enum
{
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
} HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 (0x00000000U)
#define RTC_HOURFORMAT_12 (0x00000040U)
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
/**
* @}
*/
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U)
#define RTC_OUTPUT_POLARITY_LOW (0x00100000U)
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
/**
* @}
*/
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U)
#define RTC_OUTPUT_TYPE_PUSHPULL (0x00040000U)
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
/**
* @}
*/
/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider
* @{
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
/**
* @}
*/
/** @defgroup RTC_Time_Definitions Time Definitions
* @{
*/
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H (0x00020000U)
#define RTC_DAYLIGHTSAVING_ADD1H (0x00010000U)
#define RTC_DAYLIGHTSAVING_NONE (0x00000000U)
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
/**
* @}
*/
/** @defgroup RTC_StoreOperation_Definitions StoreOperation
* @{
*/
#define RTC_STOREOPERATION_RESET (0x00000000U)
#define RTC_STOREOPERATION_SET (0x00040000U)
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
* @{
*/
#define RTC_FORMAT_BIN (0x000000000U)
#define RTC_FORMAT_BCD (0x000000001U)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
/**
* @}
*/
/** @defgroup RTC_Year_Date_Definitions Year Definitions
* @{
*/
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions Month Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
/** @defgroup RTC_Alarm_Definitions Alarm Definitions
* @{
*/
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
/**
* @}
*/
/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY (0x40000000U)
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
/**
* @}
*/
/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE (0x00000000U)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL (0x80808080U)
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTC_Exported_macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
* @param __HANDLE__ RTC handle.
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xCAU; \
(__HANDLE__)->Instance->WPR = 0x53U; \
} while(0U)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0U)
/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
/**
* @brief Disable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
/**
* @brief Enable the RTC ALARMB peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
/**
* @brief Disable the RTC ALARMB peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
/**
* @brief Enable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag sources to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
* @arg RTC_FLAG_ALRAWF
* @arg RTC_FLAG_ALRBWF
* @retval None
*/
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @brief Clear the RTC Alarm's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
* @retval None
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
} while(0U)
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Clear the RTC Alarm associated Exti line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @}
*/
/* Include RTC HAL Extended module */
#include "stm32l1xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @{
*/
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @{
*/
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
#define RTC_TIMEOUT_VALUE 1000U
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/**
* @}
*/
/* Private functions -------------------------------------------------------------*/
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_RTC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h
-1218
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RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h
-1828
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RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h
-182
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/**
******************************************************************************
* @file stm32l1xx_hal_tim_ex.h
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L1xx_HAL_TIM_EX_H
#define STM32L1xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
/* @note STM32L1XX devices are organized in 6 categories: Cat.1, Cat.2, Cat.3, Cat.4, Cat.5, Cat.6.
Remap capabilities depend on the device category. As the DMA2 controller is available only in
Cat.3, Cat.4,Cat.5 and Cat.6 devices it is used to discriminate Cat.1 and Cat.2 devices v.s.
Cat.3, Cat.4, Cat.5 and Cat.6 devices. */
#if defined(DMA2)
#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /*!< TIM2 ITR1 input is connected to TIM10 OC */
#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM2 ITR1 input is connected to TIM5 TGO */
#endif /* DMA2 */
#if defined(DMA2)
#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /*!< TIM3 ITR2 input is connected to TIM11 OC */
#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM3 ITR2 input is connected to TIM5 TGO */
#endif /* DMA2 */
#if defined(DMA2)
#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /*!< TIM9 ITR1 input is connected to TIM3 TGO */
#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /*!< TIM9 ITR1 input is connected to touch sensing I/O */
#endif /* DMA2 */
#define TIM_TIM9_GPIO (0x00000000) /*!< TIM9 Channel1 is connected to GPIO */
#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /*!< TIM9 Channel1 is connected to LSE internal clock */
#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /*!< TIM9 Channel1 is connected to GPIO */
#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /*!< TIM9 Channel1 is connected to GPIO */
#if defined(DMA2)
#define TIM_TIM10_TI1RMP (0x00000000) /*!< TIM10 Channel 1 depends on TI1_RMP */
#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /*!< TIM10 Channel 1 is connected to RI */
#define TIM_TIM10_ETR_LSE (0x00000000) /*!< TIM10 ETR input is connected to LSE clock */
#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM10 ETR input is connected to TIM9 TGO */
#endif /* DMA2 */
#define TIM_TIM10_GPIO (0x00000000) /*!< TIM10 Channel1 is connected to GPIO */
#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /*!< TIM10 Channel1 is connected to LSI internal clock */
#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /*!< TIM10 Channel1 is connected to LSE internal clock */
#define TIM_TIM10_RTC TIM_OR_TI1RMP /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */
#if defined(DMA2)
#define TIM_TIM11_TI1RMP (0x00000000) /*!< TIM11 Channel 1 depends on TI1_RMP */
#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /*!< TIM11 Channel 1 is connected to RI */
#define TIM_TIM11_ETR_LSE (0x00000000) /*!< TIM11 ETR input is connected to LSE clock */
#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM11 ETR input is connected to TIM9 TGO */
#endif /* DMA2 */
#define TIM_TIM11_GPIO (0x00000000) /*!< TIM11 Channel1 is connected to GPIO */
#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /*!< TIM11 Channel1 is connected to MSI internal clock */
#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /*!< TIM11 Channel1 is connected to HSE_RTC clock */
#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /*!< TIM11 Channel1 is connected to GPIO */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/**
* @}
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#if defined(DMA2)
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \
(((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \
(((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \
(((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \
(((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \
)
#else
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \
(((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \
)
#endif /* DMA2 */
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32L1xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h
-846
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@@ -1,846 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_uart.h
* @author MCD Application Team
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L1xx_HAL_UART_H
#define __STM32L1xx_HAL_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal_def.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UART_Word_Length */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref UART_Stop_Bits */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref UART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
This parameter can be a value of @ref UART_Over_Sampling */
} UART_InitTypeDef;
/**
* @brief HAL UART State structures definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_UART_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
} HAL_UART_StateTypeDef;
/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< UART registers base address */
UART_InitTypeDef Init; /*!< UART communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
} UART_HandleTypeDef;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL UART Callback ID enumeration definition
*/
typedef enum
{
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
} HAL_UART_CallbackIDTypeDef;
/**
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
/** @defgroup UART_Error_Code UART Error Code
* @{
*/
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup UART_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B 0x00000000U
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 0x00000000U
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
/**
* @}
*/
/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE 0x00000000U
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE 0x00000000U
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
/**
* @}
*/
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
/**
* @}
*/
/** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE 0x00000000U
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
/**
* @}
*/
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 0x00000000U
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
/**
* @}
*/
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
/**
* @}
*/
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
/**
* @}
*/
/** @defgroup UART_Flags UART FLags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
* - 0001: CR1 register
* - 0010: CR2 register
* - 0011: CR3 register
* @{
*/
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup UART_Exported_Macros UART Exported Macros
* @{
*/
/** @brief Reset UART handle gstate & RxState
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
/** @brief Flushes the UART DR register
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified UART flag is set or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
* @arg UART_FLAG_LBD: LIN Break detection flag
* @arg UART_FLAG_TXE: Transmit data register empty flag
* @arg UART_FLAG_TC: Transmission Complete flag
* @arg UART_FLAG_RXNE: Receive data register not empty flag
* @arg UART_FLAG_IDLE: Idle Line detection flag
* @arg UART_FLAG_ORE: Overrun Error flag
* @arg UART_FLAG_NE: Noise Error flag
* @arg UART_FLAG_FE: Framing Error flag
* @arg UART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
* @arg UART_FLAG_LBD: LIN Break detection flag.
* @arg UART_FLAG_TC: Transmission Complete flag.
* @arg UART_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
*
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clears the UART PE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
/** @brief Clears the UART FE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clears the UART NE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clears the UART ORE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clears the UART IDLE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Checks whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __IT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_ERR: Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
/** @brief Enable CTS flow control
* @note This macro allows to enable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0U)
/** @brief Disable CTS flow control
* @note This macro allows to disable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0U)
/** @brief Enable RTS flow control
* This macro allows to enable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0U)
/** @brief Disable RTS flow control
* This macro allows to disable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0U)
/** @brief Macro to enable the UART's one bit sample method
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Macro to disable the UART's one bit sample method
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable UART
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions
* @{
*/
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
/** @brief UART interruptions flag mask
*
*/
#define UART_IT_MASK 0x0000FFFFU
#define UART_CR1_REG_INDEX 1U
#define UART_CR2_REG_INDEX 2U
#define UART_CR3_REG_INDEX 3U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
((STOPBITS) == UART_STOPBITS_2))
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
((PARITY) == UART_PARITY_EVEN) || \
((PARITY) == UART_PARITY_ODD))
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HWCONTROL_NONE) || \
((CONTROL) == UART_HWCONTROL_RTS) || \
((CONTROL) == UART_HWCONTROL_CTS) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
((STATE) == UART_STATE_ENABLE))
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
((SAMPLING) == UART_OVERSAMPLING_8))
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4000000U)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup UART_Private_Functions UART Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32L1xx_HAL_UART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c
-569
View File
@@ -1,569 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
#ifdef HAL_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup HAL_Private_Defines HAL Private Defines
* @{
*/
/**
* @brief STM32L1xx HAL Driver version number V1.4.3
*/
#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L1xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
|(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
|(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\
|(__STM32L1xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK (0x00000FFFU)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the Flash interface, the NVIC allocation and initial clock
configuration. It initializes the source of time base also when timeout
is needed and the backup domain when enabled.
(+) De-initialize common part of the HAL.
(+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief This function configures the Flash prefetch,
* configures time base source, NVIC and Low level hardware
* @note This function is called at the beginning of program after reset and before
* the clock configuration
* @note The time base configuration is based on MSI clock when exiting from Reset.
* Once done, time base tick start incrementing.
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
status = HAL_ERROR;
}
else
{
/* Init the low level hardware */
HAL_MspInit();
}
/* Return function status */
return status;
}
/**
* @brief This function de-initializes common part of the HAL and stops the source
* of time base.
* @note This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB_FORCE_RESET();
__HAL_RCC_AHB_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitialize the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base:
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
HAL_StatusTypeDef status = HAL_OK;
if (uwTickFreq != 0U)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
/* Return function status */
return status;
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
(+) Get the unique device identifier
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += uwTickFreq;
}
/**
* @brief Provide a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @param Freq tick frequency
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
uint32_t HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)(uwTickFreq);
}
while((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspend the Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Resume the Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Return the HAL revision
* @retval version: 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32L1xx_HAL_VERSION;
}
/**
* @brief Return the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> 16U);
}
/**
* @brief Return the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/**
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier 31:0 bits
*/
uint32_t HAL_GetUIDw0(void)
{
return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier 63:32 bits
*/
uint32_t HAL_GetUIDw1(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U))));
}
/**
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier 95:64 bits
*/
uint32_t HAL_GetUIDw2(void)
{
return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U))));
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions
* @brief DBGMCU Peripheral Control functions
*
@verbatim
===============================================================================
##### DBGMCU Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief Enable the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c
-513
View File
@@ -1,513 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_cortex.c
* @author MCD Application Team
* @brief CORTEX HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
* @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using Cortex HAL driver ***
===========================================================
[..]
This section provide functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M3 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest pre-emption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure Systick using Cortex HAL driver ***
========================================================
[..]
Setup SysTick Timer for 1 msec interrupts.
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32l1xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/*
Additional Tables: CORTEX_NVIC_Priority_Table
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
==========================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
==========================================================================================================================
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
| | | 4 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
| | | 3 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
| | | 2 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
| | | 1 bits for subpriority
--------------------------------------------------------------------------------------------------------------------------
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
| | | 0 bits for subpriority
==========================================================================================================================
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provide the Cortex HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
* @{
*/
/**
* @brief Sets the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
* @param PreemptPriority The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Enable the MPU.
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged accessto the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Disable the MPU.
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
}
#endif /* __MPU_PRESENT */
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
* @param PriorityGroup the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configures the SysTick clock source.
* @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c
-908
View File
@@ -1,908 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_dma.c
* @author MCD Application Team
* @brief DMA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is
necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests.
(#) For a given Channel, program the required configuration through the following parameters:
Channel request, Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function.
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection.
(#) Use HAL_DMA_Abort() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation ***
=================================
[..]
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
address and destination address and the Length of data to be transferred
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
case a fixed Timeout can be configured by User depending from his application.
*** Interrupt mode IO operation ***
===================================
[..]
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred.
In this case the DMA interrupt is configured
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function to register callbacks with HAL_DMA_RegisterCallback().
*** DMA HAL driver macros list ***
=============================================
[..]
Below the list of macros in DMA HAL driver.
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
[..]
(@) You can refer to the DMA HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup DMA DMA
* @brief DMA HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @{
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup DMA_Exported_Functions DMA Exported Functions
* @{
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize the DMA Channel source
and destination addresses, incrementation and data sizes, transfer direction,
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
[..]
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
reference manual.
@endverbatim
* @{
*/
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
uint32_t tmp;
/* Check the DMA handle allocation */
if(hdma == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
#if defined (DMA2)
/* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA2;
}
#else
/* calculation of the channel index */
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
#endif
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Get the CR register value */
tmp = hdma->Instance->CCR;
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
hdma->Init.PeriphInc | hdma->Init.MemInc |
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
hdma->Init.Mode | hdma->Init.Priority;
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
return HAL_OK;
}
/**
* @brief DeInitialize the DMA peripheral.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
/* Check the DMA handle allocation */
if (NULL == hdma )
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma);
#if defined (DMA2)
/* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA2;
}
#else
/* calculation of the channel index */
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
#endif
/* Reset DMA Channel CR register */
hdma->Instance->CCR = 0U;
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @brief Input and Output operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start DMA transfer
(+) Configure the source, destination address and data length and
Start DMA transfer with interrupt
(+) Abort DMA transfer
(+) Poll for transfer complete
(+) Handle DMA interrupt request
@endverbatim
* @{
*/
/**
* @brief Start the DMA Transfer.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
status = HAL_BUSY;
}
return status;
}
/**
* @brief Start the DMA Transfer with interrupt enabled.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if(NULL != hdma->XferHalfCpltCallback )
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Remain BUSY */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Abort the DMA Transfer.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the DMA peripheral state */
if(hdma->State != HAL_DMA_STATE_BUSY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return status;
}
}
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
HAL_StatusTypeDef status = HAL_OK;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
status = HAL_ERROR;
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
}
return status;
}
/**
* @brief Polling for transfer complete.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CompleteLevel Specifies the DMA level complete.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
{
uint32_t temp;
uint32_t tickstart;
if(HAL_DMA_STATE_BUSY != hdma->State)
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Polling mode not supported in circular mode */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Get the level transfer complete flag */
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Transfer Complete flag */
temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
}
else
{
/* Half Transfer Complete flag */
temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
}
/* Get tick */
tickstart = HAL_GetTick();
while((hdma->DmaBaseAddress->ISR & temp) == 0U)
{
if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR;
}
}
}
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
{
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
}
else
{
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
}
/* Process unlocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
}
/**
* @brief Handle DMA interrupt request.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
uint32_t source_it = hdma->Instance->CCR;
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
}
/* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
/* Transfer Complete Interrupt management ***********************************/
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
{
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
/* Disable the transfer complete and error interrupt */
/* if the DMA mode is not CIRCULAR */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
}
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
}
}
/* Transfer Error Interrupt management **************************************/
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if (hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
else
{
/* Nothing To Do */
}
return;
}
/**
* @brief Register callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = pCallback;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = pCallback;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = pCallback;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = pCallback;
break;
default:
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @brief UnRegister callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
switch (CallbackID)
{
case HAL_DMA_XFER_CPLT_CB_ID:
hdma->XferCpltCallback = NULL;
break;
case HAL_DMA_XFER_HALFCPLT_CB_ID:
hdma->XferHalfCpltCallback = NULL;
break;
case HAL_DMA_XFER_ERROR_CB_ID:
hdma->XferErrorCallback = NULL;
break;
case HAL_DMA_XFER_ABORT_CB_ID:
hdma->XferAbortCallback = NULL;
break;
case HAL_DMA_XFER_ALL_CB_ID:
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
break;
default:
status = HAL_ERROR;
break;
}
}
else
{
status = HAL_ERROR;
}
/* Release Lock */
__HAL_UNLOCK(hdma);
return status;
}
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DMA state
(+) Get error code
@endverbatim
* @{
*/
/**
* @brief Return the DMA handle state.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{
/* Return DMA handle state */
return hdma->State;
}
/**
* @brief Return the DMA error code.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval DMA Error Code
*/
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
{
return hdma->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMA_Private_Functions
* @{
*/
/**
* @brief Sets the DMA Transfer parameter.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @param SrcAddress The source memory Buffer address
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
}
/* Peripheral to Memory */
else
{
/* Configure DMA Channel source address */
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c
-559
View File
@@ -1,559 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line mask */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
EXTI->RTSR |= maskline;
}
else
{
EXTI->RTSR &= ~maskline;
}
/* Configure falling trigger */
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
EXTI->FTSR |= maskline;
}
else
{
EXTI->FTSR &= ~maskline;
}
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
EXTI->IMR |= maskline;
}
else
{
EXTI->IMR &= ~maskline;
}
/* Configure event mode : read current mode */
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
EXTI->EMR |= maskline;
}
else
{
EXTI->EMR &= ~maskline;
}
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* Compute line mask */
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
/* Check if selected line is enable */
if ((EXTI->IMR & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
/* Check if selected line is enable */
if ((EXTI->EMR & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
/* Check if configuration of selected line is enable */
if ((EXTI->RTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
/* Check if configuration of selected line is enable */
if ((EXTI->FTSR & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
/* No Trigger selected */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
EXTI->IMR = (EXTI->IMR & ~maskline);
/* 2] Clear event mode */
EXTI->EMR = (EXTI->EMR & ~maskline);
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
EXTI->RTSR = (EXTI->RTSR & ~maskline);
EXTI->FTSR = (EXTI->FTSR & ~maskline);
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
uint32_t regval;
uint32_t maskline;
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regval = (EXTI->PR & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
EXTI->PR = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line mask */
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* return 1 if bit is set else 0 */
regval = ((EXTI->PR & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Clear Pending bit */
EXTI->PR = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
uint32_t maskline;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* Compute line mask */
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Generate Software interrupt */
EXTI->SWIER = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c
-721
View File
@@ -1,721 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_flash.c
* @author MCD Application Team
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Prefetch on I-Code
(+) Option Bytes programming
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32L1xx devices.
(#) FLASH Memory I/O Programming functions: this group includes all needed
functions to erase and program the main memory:
(++) Lock and Unlock the FLASH interface
(++) Erase function: Erase page
(++) Program functions: Fast Word and Half Page(should be
executed from internal SRAM).
(#) DATA EEPROM Programming functions: this group includes all
needed functions to erase and program the DATA EEPROM memory:
(++) Lock and Unlock the DATA EEPROM interface.
(++) Erase function: Erase Byte, erase HalfWord, erase Word, erase
Double Word (should be executed from internal SRAM).
(++) Program functions: Fast Program Byte, Fast Program Half-Word,
FastProgramWord, Program Byte, Program Half-Word,
Program Word and Program Double-Word (should be executed
from internal SRAM).
(#) FLASH Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
(++) Lock and Unlock the Option Bytes
(++) Set/Reset the write protection
(++) Set the Read protection Level
(++) Program the user Option Bytes
(++) Launch the Option Bytes loader
(++) Set/Get the Read protection Level.
(++) Set/Get the BOR level.
(++) Get the Write protection.
(++) Get the user option bytes.
(#) Interrupts and flags management functions : this group
includes all needed functions to:
(++) Handle FLASH interrupts
(++) Wait for last FLASH operation according to its status
(++) Get error flag status
(#) FLASH Interface configuration functions: this group includes
the management of following features:
(++) Enable/Disable the RUN PowerDown mode.
(++) Enable/Disable the SLEEP PowerDown mode.
(#) FLASH Peripheral State methods: this group includes
the management of following features:
(++) Wait for the FLASH operation
(++) Get the specific FLASH error flag
[..] In addition to these function, this driver includes a set of macros allowing
to handle the following operations:
(+) Set/Get the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the 64 bit Read Access.
(+) Enable/Disable the Flash power-down
(+) Enable/Disable the FLASH interrupts
(+) Monitor the FLASH flags status
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
[..] The FLASH Memory Programming functions, includes the following functions:
(+) HAL_FLASH_Unlock(void);
(+) HAL_FLASH_Lock(void);
(+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
(+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
[..] Any operation of erase or program should follow these steps:
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
program memory access.
(#) Call the desired function to erase page or program data.
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
(recommended to protect the FLASH memory against possible unwanted operation).
##### Option Bytes Programming functions #####
==============================================================================
[..] The FLASH_Option Bytes Programming_functions, includes the following functions:
(+) HAL_FLASH_OB_Unlock(void);
(+) HAL_FLASH_OB_Lock(void);
(+) HAL_FLASH_OB_Launch(void);
(+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
(+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
[..] Any operation of erase or program should follow these steps:
(#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control
register access.
(#) Call the following functions to program the desired option bytes.
(++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
(#) Once all needed option bytes to be programmed are correctly written, call the
HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
(#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
to protect the option Bytes against possible unwanted operations).
[..] Proprietary code Read Out Protection (PcROP):
(#) The PcROP sector is selected by using the same option bytes as the Write
protection. As a result, these 2 options are exclusive each other.
(#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below:
(++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
/**
* @}
*/
/* Private macro ---------------------------- ---------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/* Variables used for Erase pages under interruption*/
FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
static void FLASH_SetErrorCode(void);
extern void FLASH_PageErase(uint32_t PageAddress);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
@endverbatim
* @{
*/
/**
* @brief Program word at a specified address
* @note To correctly run this function, the HAL_FLASH_Unlock() function
* must be called before.
* Call the HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
*
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address Specifie the address to be programmed.
* @param Data Specifie the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/*Program word (32-bit) at a specified address.*/
*(__IO uint32_t *)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Program word at a specified address with interrupt enabled.
*
* @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address Specifie the address to be programmed.
* @param Data Specifie the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
/* Enable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
pFlash.Address = Address;
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
/* Clean the error context */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/* Program word (32-bit) at a specified address. */
*(__IO uint32_t *)Address = Data;
}
return status;
}
/**
* @brief This function handles FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t addresstmp = 0U;
/* Check FLASH operation error flags */
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
#if defined(FLASH_SR_RDERR)
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
#endif /* FLASH_SR_OPTVERRUSR */
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) )
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
{
/* Return the faulty sector */
addresstmp = pFlash.Page;
pFlash.Page = 0xFFFFFFFFU;
}
else
{
/* Return the faulty address */
addresstmp = pFlash.Address;
}
/* Save the Error code */
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(addresstmp);
/* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
/* Process can continue only if no error detected */
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
{
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
{
/* Nb of pages to erased can be decreased */
pFlash.NbPagesToErase--;
/* Check if there are still pages to erase */
if(pFlash.NbPagesToErase != 0U)
{
addresstmp = pFlash.Page;
/*Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(addresstmp);
/*Increment sector number*/
addresstmp = pFlash.Page + FLASH_PAGE_SIZE;
pFlash.Page = addresstmp;
/* If the erase operation is completed, disable the ERASE Bit */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
FLASH_PageErase(addresstmp);
}
else
{
/* No more pages to Erase, user callback can be called. */
/* Reset Sector and stop Erase pages procedure */
pFlash.Page = addresstmp = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(addresstmp);
}
}
else
{
/* If the program operation is completed, disable the PROG Bit */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
/* Reset Address and stop Program procedure */
pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
/* Operation is completed, disable the PROG and ERASE */
CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG));
/* Disable End of FLASH Operation and Error source interrupts */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Pages Erase: Address of the page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
* - Program: Address which was selected for data program
* @retval none
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Pages Erase: Address of the page which returned an error
* - Program: Address which was selected for data program
* @retval none
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
{
/* Unlocking FLASH_PECR register access*/
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
{
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
/* Verify that PELOCK is unlocked */
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
{
return HAL_ERROR;
}
}
/* Unlocking the program memory access */
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);
/* Verify that PRGLOCK is unlocked */
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the PRGLOCK Bit to lock the FLASH Registers access */
SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Control Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
{
/* Unlocking FLASH_PECR register access*/
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
{
/* Unlocking FLASH_PECR register access*/
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
/* Verify that PELOCK is unlocked */
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
{
return HAL_ERROR;
}
}
/* Unlocking the option bytes block access */
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
/* Verify that OPTLOCK is unlocked */
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
{
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Control Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the option bytes block access */
SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);
return HAL_OK;
}
/**
* @brief Launch the option byte loading.
* @note This function will reset automatically the MCU.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the OBL_Launch bit to launch the option byte loading */
SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode The returned value can be:
* @ref FLASH_Error_Codes
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operation timeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
uint32_t tickstart = HAL_GetTick();
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
if (Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
#if defined(FLASH_SR_RDERR)
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
#endif /* FLASH_SR_OPTVERRUSR */
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
/* There is no error flag set */
return HAL_OK;
}
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
uint32_t flags = 0U;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
flags |= FLASH_FLAG_WRPERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
flags |= FLASH_FLAG_PGAERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
flags |= FLASH_FLAG_OPTVERR;
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
flags |= FLASH_FLAG_RDERR;
}
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
flags |= FLASH_FLAG_OPTVERRUSR;
}
#endif /* FLASH_SR_OPTVERRUSR */
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c
-1873
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RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c
-644
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@@ -1,644 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_flash_ramfunc.c
* @author MCD Application Team
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
*
* @verbatim
*** ARM Compiler ***
--------------------
[..] RAM functions are defined using the toolchain options.
Functions that are be executed in RAM should reside in a separate
source module. Using the 'Options for File' dialog you can simply change
the 'Code / Const' area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the
Options for Target' dialog.
*** ICCARM Compiler ***
-----------------------
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
*** GNU Compiler ***
--------------------
[..] RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Variables
* @{
*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
* @{
*/
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
*
@verbatim
===============================================================================
##### ramfunc functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM
transfers.
@endverbatim
* @{
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
* @{
*/
/**
* @brief Enable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
{
/* Enable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_ENABLE();
return HAL_OK;
}
/**
* @brief Disable the power down mode during RUN mode.
* @note This function can be used only when the user code is running from Internal SRAM.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
{
/* Disable the Power Down in Run mode*/
__HAL_FLASH_POWER_DOWN_DISABLE();
return HAL_OK;
}
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
*
@verbatim
@endverbatim
* @{
*/
#if defined(FLASH_PECR_PARALLBANK)
/**
* @brief Erases a specified 2 pages in program memory in parallel.
* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
* To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @param Page_Address1: The page address in program memory to be erased in
* the first Bank (BANK1). This parameter should be between FLASH_BASE
* and FLASH_BANK1_END.
* @param Page_Address2: The page address in program memory to be erased in
* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
* and FLASH_BANK2_END.
* @note A Page is erased in the Program memory only if the address to load
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
{
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Proceed to erase the page */
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write 00000000h to the first word of the first program page to erase */
*(__IO uint32_t *)Page_Address1 = 0x00000000U;
/* Write 00000000h to the first word of the second program page to erase */
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
}
/* Return the Erase Status */
return status;
}
/**
* @brief Program 2 half pages in program memory in parallel (half page size is 32 Words).
* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
* @param Address1: specifies the first address to be written in the first bank
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
* @param pBuffer1: pointer to the buffer containing the data to be written
* to the first half page in the first bank.
* @param Address2: specifies the second address to be written in the second bank
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
* @param pBuffer2: pointer to the buffer containing the data to be written
* to the second half page in the second bank.
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation).
* @note Half page write is possible only from SRAM.
* @note If there are more than 32 words to write, after 32 words another
* Half Page programming operation starts and has to be finished.
* @note A half page is written to the program memory only if the first
* address to load is the start address of a half page (multiple of 128
* bytes) and the 31 remaining words to load are in the same half page.
* @note During the Program memory half page write all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @note If a PGAERR is set during a Program memory half page write, the
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
{
uint32_t primask_bit;
uint32_t count = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Disable all IRQs */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Proceed to program the new half page */
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write the first half page directly with 32 different words */
while(count < 32U)
{
*(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
pBuffer1++;
count ++;
}
/* Write the second half page directly with 32 different words */
count = 0U;
while(count < 32U)
{
*(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
pBuffer2++;
count ++;
}
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
/* Enable IRQs */
__set_PRIMASK(primask_bit);
}
/* Return the Write Status */
return status;
}
#endif /* FLASH_PECR_PARALLBANK */
/**
* @brief Program a half page in program memory.
* @param Address specifies the address to be written.
* @param pBuffer pointer to the buffer containing the data to be written to
* the half page.
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
* must be called before.
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note Half page write is possible only from SRAM.
* @note If there are more than 32 words to write, after 32 words another
* Half Page programming operation starts and has to be finished.
* @note A half page is written to the program memory only if the first
* address to load is the start address of a half page (multiple of 128
* bytes) and the 31 remaining words to load are in the same half page.
* @note During the Program memory half page write all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @note If a PGAERR is set during a Program memory half page write, the
* complete write operation is aborted. Software should then reset the
* FPRG and PROG/DATA bits and restart the write operation from the
* beginning.
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
{
uint32_t primask_bit;
uint32_t count = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Disable all IRQs */
primask_bit = __get_PRIMASK();
__disable_irq();
/* Proceed to program the new half page */
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
/* Write one half page directly with 32 different words */
while(count < 32U)
{
*(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
pBuffer++;
count ++;
}
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the write operation is completed, disable the PROG and FPRG bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
/* Enable IRQs */
__set_PRIMASK(primask_bit);
}
/* Return the Write Status */
return status;
}
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
* @brief Peripheral errors functions
*
@verbatim
===============================================================================
##### Peripheral errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH errors flag.
* @param Error pointer is the error value. It can be a mixed of:
@if STM32L100xB
@elif STM32L100xBA
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
@elif STM32L151xB
@elif STM32L151xBA
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
@elif STM32L152xB
@elif STM32L152xBA
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
@elif STM32L100xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@elif STM32L151xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@elif STM32L152xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@elif STM32L162xC
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@else
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
@endif
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
* @retval HAL Status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)
{
*Error = pFlash.ErrorCode;
return HAL_OK;
}
/**
* @}
*/
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions
*
* @{
*/
/**
* @brief Erase a double word in data memory.
* @param Address specifies the address to be erased.
* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
* must be called before.
* Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note Data memory double word erase is possible only from SRAM.
* @note A double word is erased to the data memory only if the first address
* to load is the start address of a double word (multiple of 8 bytes).
* @note During the Data memory double word erase, all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
{
uint32_t primask_bit;
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Disable all IRQs */
primask_bit = __get_PRIMASK();
__disable_irq();
/* If the previous operation is completed, proceed to erase the next double word */
/* Set the ERASE bit */
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
/* Set DATA bit */
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
/* Write 00000000h to the 2 words to erase */
*(__IO uint32_t *)Address = 0x00000000U;
Address += 4U;
*(__IO uint32_t *)Address = 0x00000000U;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the ERASE and DATA bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
/* Enable IRQs */
__set_PRIMASK(primask_bit);
}
/* Return the erase status */
return status;
}
/**
* @brief Write a double word in data memory without erase.
* @param Address specifies the address to be written.
* @param Data specifies the data to be written.
* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
* must be called before.
* Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
* and Flash program erase control register access(recommended to protect
* the DATA_EEPROM against possible unwanted operation).
* @note Data memory double word write is possible only from SRAM.
* @note A data memory double word is written to the data memory only if the
* first address to load is the start address of a double word (multiple
* of double word).
* @note During the Data memory double word write, all read operations are
* forbidden (this includes DMA read operations and debugger read
* operations such as breakpoints, periodic updates, etc.).
* @retval HAL status
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
{
uint32_t primask_bit;
HAL_StatusTypeDef status = HAL_OK;
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Disable all IRQs */
primask_bit = __get_PRIMASK();
__disable_irq();
/* If the previous operation is completed, proceed to program the new data*/
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
/* Write the 2 words */
*(__IO uint32_t *)Address = (uint32_t) Data;
Address += 4U;
*(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
/* Wait for last operation to be completed */
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the write operation is completed, disable the FPRG and DATA bits */
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
/* Enable IRQs */
__set_PRIMASK(primask_bit);
}
/* Return the Write Status */
return status;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASH_RAMFUNC_Private_Functions
* @{
*/
/**
* @brief Set the specific FLASH error flag.
* @retval HAL Status
*/
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)
{
uint32_t flags = 0U;
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
flags |= FLASH_FLAG_WRPERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
flags |= FLASH_FLAG_PGAERR;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
flags |= FLASH_FLAG_OPTVERR;
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
flags |= FLASH_FLAG_RDERR;
}
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
flags |= FLASH_FLAG_OPTVERRUSR;
}
#endif /* FLASH_SR_OPTVERRUSR */
/* Clear FLASH error pending bits */
__HAL_FLASH_CLEAR_FLAG(flags);
return HAL_OK;
}
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operationtimeout
* @retval HAL status
*/
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)
{
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
{
Timeout--;
}
if(Timeout == 0x00U)
{
return HAL_TIMEOUT;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
#if defined(FLASH_SR_RDERR)
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
#endif /* FLASH_SR_RDERR */
#if defined(FLASH_SR_OPTVERRUSR)
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
#endif /* FLASH_SR_OPTVERRUSR */
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
{
/*Save the error code*/
FLASHRAM_SetErrorCode();
return HAL_ERROR;
}
/* There is no error flag set */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c
-550
View File
@@ -1,550 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
Each port bit of the general-purpose I/O (GPIO) ports can be individually
configured by software in several modes:
(+) Input mode
(+) Analog mode
(+) Output mode
(+) Alternate function mode
(+) External interrupt/event lines
[..]
During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
[..]
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
[..]
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
[..]
The microcontroller IO pins are connected to onboard peripherals/modules through a
multiplexer that allows only one peripheral s alternate function (AF) connected
to an IO pin at a time. In this way, there can be no conflict between peripherals
sharing the same IO pin.
[..]
All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
[..]
The external interrupt/event controller consists of up to 28 edge detectors
(depending on products 16 lines are connected to GPIO) for generating event/interrupt
requests (each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising or falling or both).
Each line can also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure,
the speed is configurable: Low, Medium and High.
(++) If alternate mode is selected, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
recommended to use it to unconfigure pin which was used as an external interrupt
or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
registers.
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @brief GPIO HAL module driver
* @{
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants
* @{
*/
#define GPIO_MODE (0x00000003U)
#define EXTI_MODE (0x10000000U)
#define GPIO_MODE_IT (0x00010000U)
#define GPIO_MODE_EVT (0x00020000U)
#define RISING_EDGE (0x00100000U)
#define FALLING_EDGE (0x00200000U)
#define GPIO_OUTPUT_TYPE (0x00000010U)
#define GPIO_NUMBER (16U)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00;
uint32_t iocurrent = 0x00;
uint32_t temp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
if (iocurrent)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
/* Identify AFRL or AFRH register based on IO position*/
temp = GPIOx->AFR[position >> 3];
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2];
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR;
CLEAR_BIT(temp, (uint32_t)iocurrent);
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
SET_BIT(temp, iocurrent);
}
EXTI->IMR = temp;
temp = EXTI->EMR;
CLEAR_BIT(temp, (uint32_t)iocurrent);
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
SET_BIT(temp, iocurrent);
}
EXTI->EMR = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
CLEAR_BIT(temp, (uint32_t)iocurrent);
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
SET_BIT(temp, iocurrent);
}
EXTI->RTSR = temp;
temp = EXTI->FTSR;
CLEAR_BIT(temp, (uint32_t)iocurrent);
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
SET_BIT(temp, iocurrent);
}
EXTI->FTSR = temp;
}
}
position++;
}
}
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position = 0x00;
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
while ((GPIO_Pin >> position) != 0)
{
/* Get current io position */
iocurrent = (GPIO_Pin) & (1U << position);
if (iocurrent)
{
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2];
tmp &= ((0x0FU) << (4 * (position & 0x03)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
{
/* Clear EXTI line configuration */
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
tmp = (0x0FU) << (4 * (position & 0x03));
CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */
CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2));
/* Configure the default Alternate Function in current IO */
CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));
/* Configure the default value IO Output Type */
CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
/* Configure the default value for IO Speed */
CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
}
position++;
}
}
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Sets or clears the selected data port bit.
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
}
}
/**
* @brief Toggles the specified GPIO pin
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
* @param GPIO_Pin specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Ouput Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
* @brief Locks GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8
* depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i].
* GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8].
* It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also
* GPIOx_OTYPER[i-8].
* Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15,
* you must call also HAL_GPIO_LockPin with GPIO_Pin - 8.
* (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding
* GPIO_PIN_0 to GPIO_PIN_7).
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
* @param GPIO_Pin Specifies the port bit to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
SET_BIT(tmp, GPIO_Pin);
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
/* Read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line detection callbacks.
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c
-650
View File
@@ -1,650 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_pwr.c
* @author MCD Application Team
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization/de-initialization functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define PVD_MODE_IT (0x00010000U)
#define PVD_MODE_EVT (0x00020000U)
#define PVD_RISING_EDGE (0x00000001U)
#define PVD_FALLING_EDGE (0x00000002U)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
After reset, the backup domain (RTC registers, RTC backup data
registers) is protected against possible unwanted
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
__HAL_RCC_PWR_CLK_ENABLE() macro.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default reset values.
* @note Before calling this function, the VOS[1:0] bits should be configured
* to "10" and the system frequency has to be configured accordingly.
* To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
* function.
* @note ULP and FWU bits are not reset by this function.
* @retval None
*/
void HAL_PWR_DeInit(void)
{
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}
/**
* @brief Enables access to the backup domain (RTC registers, RTC
* backup data registers ).
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
/* Enable access to RTC and backup registers */
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables access to the backup domain (RTC registers, RTC
* backup data registers).
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
{
/* Disable access to RTC and backup registers */
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
(+) The PVD can use an external input analog voltage (PVD_IN) which is compared
internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
*** WakeUp pin configuration ***
================================
[..]
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is
forced in input pull-down configuration and is active on rising edges.
(+) There are two or three WakeUp pins:
WakeUp Pin 1 on PA.00.
WakeUp Pin 2 on PC.13.
WakeUp Pin 3 on PE.06. : Only on product with GPIOE available
[..]
*** Main and Backup Regulators configuration ***
================================================
(+) The main internal regulator can be configured to have a tradeoff between
performance and power consumption when the device does not operate at
the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
macro which configure VOS bit in PWR_CR register:
(++) When this bit is set (Regulator voltage output Scale 1 mode selected)
the System frequency can go up to 32 MHz.
(++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
the System frequency can go up to 16 MHz.
(++) When this bit is reset (Regulator voltage output Scale 3 mode selected)
the System frequency can go up to 4.2 MHz.
Refer to the datasheets for more details.
*** Low Power modes configuration ***
=====================================
[..]
The device features 5 low-power modes:
(+) Low power run mode: regulator in low power mode, limited clock frequency,
limited number of peripherals running.
(+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
(+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
limited number of peripherals running, regulator in low power mode.
(+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
(+) Standby mode: VCORE domain powered off
*** Low power run mode ***
=========================
[..]
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low power mode. In this mode, the system frequency should not exceed
MSI frequency range1.
In Low power run mode, all I/O pins keep the same state as in Run mode.
(+) Entry:
(++) VCORE in range2
(++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1.
(++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
function.
(+) Exit:
(++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
function.
(++) Increase the system frequency if needed.
*** Sleep mode ***
==================
[..]
(+) Entry:
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
functions with
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) Exit:
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from Sleep mode.
*** Low power sleep mode ***
============================
[..]
(+) Entry:
The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
functions with
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
This reduces power consumption but increases the wake-up time.
(+) Exit:
(++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
the MCU exits Sleep mode as soon as an event occurs.
*** Stop mode ***
=================
[..]
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
To get the lowest consumption in Stop mode, the internal Flash memory also enters low
power mode. When the Flash memory is in power-down mode, an additional startup delay is
incurred when waking up from Stop mode.
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
sensor can be switched off before entering Stop mode. They can be switched on again by
software after exiting Stop mode using the ULP bit in the PWR_CR register.
In Stop mode, all I/O pins keep the same state as in Run mode.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI )
function with:
(++) Main regulator ON.
(++) Low Power regulator ON.
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
(+) Exit:
(++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
*** Standby mode ***
====================
[..]
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is
consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
also switched off. SRAM and register contents are lost except for the RTC registers, RTC
backup registers and Standby circuitry.
To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
sensor can be switched off before entering the Standby mode. They can be switched
on again by software after exiting the Standby mode.
function.
(+) Entry:
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
without depending on an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop mode
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT()
function
(+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
and HAL_RTC_SetTime() functions.
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to:
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and
Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT()
or HAL_RTCEx_SetTimeStamp_IT() functions.
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
(+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and
Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function.
(+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer()
function.
(+) RTC auto-wakeup (AWU) from the Standby mode
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
(+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function.
(+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
and HAL_RTC_SetTime() functions.
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
is necessary to:
(+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to
detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT()
or HAL_RTCEx_SetTamper_IT()functions.
(++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
(+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event
using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions.
(+) Comparator auto-wakeup (AWU) from the Stop mode
(++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
event, it is necessary to:
(+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the
selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using
the COMP functions.
(+++) Configure the comparator to generate the event.
@endverbatim
* @{
*/
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
* information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @retval None
*/
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
/**
* @brief Enables the Power Voltage Detector(PVD).
* @retval None
*/
void HAL_PWR_EnablePVD(void)
{
/* Enable the power voltage detector */
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the Power Voltage Detector(PVD).
* @retval None
*/
void HAL_PWR_DisablePVD(void)
{
/* Disable the power voltage detector */
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
}
/**
* @brief Enables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @arg PWR_WAKEUP_PIN2
* @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Enable the EWUPx pin */
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
}
/**
* @brief Disables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @arg PWR_WAKEUP_PIN2
* @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
/* Check the parameter */
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
/* Disable the EWUPx pin */
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
}
/**
* @brief Enters Sleep mode.
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
* @param Regulator: Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
* When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
/**
* @brief Enters Stop mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by using an interrupt or a wakeup event,
* MSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
* @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
* @retval None
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Enters Standby mode.
* @note In Standby mode, all I/O pins are high impedance except for:
* - Reset pad (still available)
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
* Alarm out, or RTC clock calibration out.
* - WKUP pin 1 (PA0) if enabled.
* - WKUP pin 2 (PC13) if enabled.
* - WKUP pin 3 (PE6) if enabled.
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby mode */
SET_BIT(PWR->CR, PWR_CR_PDDS);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on
* interruptions handling.
* @retval None
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enables CORTEX M3 SEVONPEND bit.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Disables CORTEX M3 SEVONPEND bit.
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler().
* @retval None
*/
void HAL_PWR_PVD_IRQHandler(void)
{
/* Check PWR exti flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR Exti pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
/**
* @brief PWR PVD interrupt callback
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PWR_PVDCallback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c
-161
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@@ -1,161 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_pwr_ex.c
* @author MCD Application Team
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Extended Initialization and de-initialization functions
* + Extended Peripheral Control functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup PWREx PWREx
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral extended features functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
return (PWR->CR & PWR_CR_VOS);
}
/**
* @brief Enables the Fast WakeUp from Ultra Low Power mode.
* @note This bit works in conjunction with ULP bit.
* Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when
* exiting from low power mode.
* @retval None
*/
void HAL_PWREx_EnableFastWakeUp(void)
{
/* Enable the fast wake up */
*(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the Fast WakeUp from Ultra Low Power mode.
* @retval None
*/
void HAL_PWREx_DisableFastWakeUp(void)
{
/* Disable the fast wake up */
*(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE;
}
/**
* @brief Enables the Ultra Low Power mode
* @retval None
*/
void HAL_PWREx_EnableUltraLowPower(void)
{
/* Enable the Ultra Low Power mode */
*(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the Ultra Low Power mode
* @retval None
*/
void HAL_PWREx_DisableUltraLowPower(void)
{
/* Disable the Ultra Low Power mode */
*(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE;
}
/**
* @brief Enters the Low Power Run mode.
* @note Low power run mode can only be entered when VCORE is in range 2.
* In addition, the dynamic voltage scaling must not be used when Low
* power run mode is selected. Only Stop and Sleep modes with regulator
* configured in Low power mode is allowed when Low power run mode is
* selected.
* @note In Low power run mode, all I/O pins keep the same state as in Run mode.
* @retval None
*/
void HAL_PWREx_EnableLowPowerRunMode(void)
{
/* Enters the Low Power Run mode */
*(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE;
*(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE;
}
/**
* @brief Exits the Low Power Run mode.
* @retval None
*/
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
{
/* Exits the Low Power Run mode */
*(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE;
*(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE;
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c
-1394
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RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c
-440
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@@ -1,440 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_rcc_ex.c
* @author MCD Application Team
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
#ifdef HAL_RCC_MODULE_ENABLED
/** @defgroup RCCEx RCCEx
* @brief RCC Extension HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
* @{
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
* @{
*/
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
[..]
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
select the RTC clock source; in this case the Backup domain will be reset in
order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) are set to their reset values.
@endverbatim
* @{
*/
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
* @retval HAL status
* @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
* to possibly update HSE divider.
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart;
uint32_t temp_reg;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
#if defined(LCD)
|| (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
#endif /* LCD */
)
{
/* check for RTC Parameters used to output RTCCLK */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
{
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
}
#if defined(LCD)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
{
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
}
#endif /* LCD */
FlagStatus pwrclkchanged = RESET;
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
temp_reg = (RCC->CR & RCC_CR_RTCPRE);
if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
#if defined (LCD)
|| (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
#endif /* LCD */
)
{ /* Check HSE State */
if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
{
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
{
/* To update HSE divider, first switch-OFF HSE clock oscillator*/
return HAL_ERROR;
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#if defined(LCD)
|| ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
#endif /* LCD */
))
{
/* Store the content of CSR register before the reset of Backup Domain */
temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of CSR register */
RCC->CSR = temp_reg;
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
{
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
{
__HAL_RCC_PWR_CLK_DISABLE();
}
}
return HAL_OK;
}
/**
* @brief Get the PeriphClkInit according to the internal RCC configuration registers.
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t srcclk;
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
#if defined(LCD)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
#endif /* LCD */
/* Get the RTC/LCD configuration -----------------------------------------------*/
srcclk = __HAL_RCC_GET_RTC_SOURCE();
if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
{
/* Source clock is LSE or LSI*/
PeriphClkInit->RTCClockSelection = srcclk;
}
else
{
/* Source clock is HSE. Need to get the prescaler value*/
PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
}
#if defined(LCD)
PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
#endif /* LCD */
}
/**
* @brief Return the peripheral clock frequency
* @note Return 0 if peripheral clock is unknown
* @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*)
* @note (*) means that this peripheral is not present on all the devices
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
uint32_t frequency = 0;
uint32_t srcclk;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
switch (PeriphClk)
{
case RCC_PERIPHCLK_RTC:
#if defined(LCD)
case RCC_PERIPHCLK_LCD:
#endif /* LCD */
{
/* Get the current RTC source */
srcclk = __HAL_RCC_GET_RTC_SOURCE();
/* Check if LSE is ready if RTC clock selection is LSE */
if (srcclk == RCC_RTCCLKSOURCE_LSE)
{
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
{
frequency = LSE_VALUE;
}
}
/* Check if LSI is ready if RTC clock selection is LSI */
else if (srcclk == RCC_RTCCLKSOURCE_LSI)
{
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
{
frequency = LSI_VALUE;
}
}
/* Check if HSE is ready and if RTC clock selection is HSE */
else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX)
{
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
{
/* Get the current HSE clock divider */
switch (__HAL_RCC_GET_RTC_HSE_PRESCALER())
{
case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
{
frequency = HSE_VALUE / 16U;
break;
}
case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
{
frequency = HSE_VALUE / 8U;
break;
}
case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
{
frequency = HSE_VALUE / 4U;
break;
}
default: /* HSE DIV2 has been selected */
{
frequency = HSE_VALUE / 2U;
break;
}
}
}
}
else
{
/* No clock source, frequency default init at 0 */
}
break;
}
default:
break;
}
return(frequency);
}
#if defined(RCC_LSECSS_SUPPORT)
/**
* @brief Enables the LSE Clock Security System.
* @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
* to the RTC but no hardware action is made to the registers.
* In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
* the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
* The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
* (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
* RTCSEL), or take any required action to secure the application.
* @note LSE CSS available only for high density and medium+ devices
* @retval None
*/
void HAL_RCCEx_EnableLSECSS(void)
{
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
}
/**
* @brief Disables the LSE Clock Security System.
* @note Once enabled this bit cannot be disabled, except after an LSE failure detection
* (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
* Reset by power on reset and RTC software reset (RTCRST bit).
* @note LSE CSS available only for high density and medium+ devices
* @retval None
*/
void HAL_RCCEx_DisableLSECSS(void)
{
/* Disable LSE CSS */
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
/* Disable LSE CSS IT */
__HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
}
/**
* @brief Enable the LSE Clock Security System IT & corresponding EXTI line.
* @note LSE Clock Security System IT is mapped on RTC EXTI line 19
* @retval None
*/
void HAL_RCCEx_EnableLSECSS_IT(void)
{
/* Enable LSE CSS */
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
/* Enable LSE CSS IT */
__HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
/* Enable IT on EXTI Line 19 */
__HAL_RCC_LSECSS_EXTI_ENABLE_IT();
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
}
/**
* @brief Handle the RCC LSE Clock Security System interrupt request.
* @retval None
*/
void HAL_RCCEx_LSECSS_IRQHandler(void)
{
/* Check RCC LSE CSSF flag */
if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
{
/* RCC LSE Clock Security System interrupt user callback */
HAL_RCCEx_LSECSS_Callback();
/* Clear RCC LSE CSS pending bit */
__HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
}
}
/**
* @brief RCCEx LSE Clock Security System interrupt callback.
* @retval none
*/
__weak void HAL_RCCEx_LSECSS_Callback(void)
{
/* NOTE : This function should not be modified, when the callback is needed,
the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
*/
}
#endif /* RCC_LSECSS_SUPPORT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_RCC_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c
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RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c
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RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c
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RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c
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@@ -1,227 +0,0 @@
/**
******************************************************************************
* @file stm32l1xx_hal_tim_ex.c
* @author MCD Application Team
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
* + Time Master and Slave synchronization configuration
* + Time OCRef clear configuration
* + Timer remapping capabilities configuration
@verbatim
==============================================================================
##### TIMER Extended features #####
==============================================================================
[..]
The Timer Extended features include:
(#) Synchronization circuit to control the timer with external signals and to
interconnect several timers together.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32l1xx_hal.h"
/** @addtogroup STM32L1xx_HAL_Driver
* @{
*/
/** @defgroup TIMEx TIMEx
* @brief TIM Extended HAL module driver
* @{
*/
#ifdef HAL_TIM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Configure Master synchronization.
(+) Configure timer remapping capabilities.
@endverbatim
* @{
*/
/**
* @brief Configures the TIM in master mode.
* @param htim TIM handle.
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
uint32_t tmpcr2;
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @brief Configures the TIMx Remapping input capabilities.
* @param htim TIM handle.
* @param Remap specifies the TIM remapping source.
*
* For TIM2, the parameter can have the following values:(see note)
* @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC
* @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO
*
* For TIM3, the parameter can have the following values:(see note)
* @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC
* @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO
*
* For TIM9, the parameter is a combination of 2 fields (field1 | field2):
*
* field1 can have the following values:(see note)
* @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO
* @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O
*
* field2 can have the following values:
* @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO
* @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock
* @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO
* @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO
*
* For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3):
*
* field1 can have the following values:(see note)
* @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP
* @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI
*
* field2 can have the following values:(see note)
* @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock
* @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO
*
* field3 can have the following values:
* @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO
* @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock
* @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock
* @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt
*
* For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3):
*
* field1 can have the following values:(see note)
* @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP
* @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI
*
* field2 can have the following values:(see note)
* @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock
* @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO
*
* field3 can have the following values:
* @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO
* @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock
* @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock
* @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO
*
* @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
__HAL_LOCK(htim);
/* Check parameters */
assert_param(IS_TIM_REMAP(htim->Instance, Remap));
/* Set the Timer remapping configuration */
WRITE_REG(htim->Instance->OR, Remap);
__HAL_UNLOCK(htim);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_TIM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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