projekt_wuest_steiner/RTC/Debug/RTC.list

RTC.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000194  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00005de4  08000198  08000198  00010198  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000290  08005f80  08005f80  00015f80  2**3
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08006210  08006210  00020088  2**0
                  CONTENTS
  4 .ARM          00000008  08006210  08006210  00016210  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08006218  08006218  00020088  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08006218  08006218  00016218  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  0800621c  0800621c  0001621c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         00000088  20000000  08006220  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          000000c0  20000088  080062a8  00020088  2**2
                  ALLOC
 10 ._user_heap_stack 00000600  20000148  080062a8  00020148  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  00020088  2**0
                  CONTENTS, READONLY
 12 .debug_info   000098e6  00000000  00000000  000200b8  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_abbrev 0000196e  00000000  00000000  0002999e  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_aranges 00000910  00000000  00000000  0002b310  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges 00000838  00000000  00000000  0002bc20  2**3
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macro  00015f3a  00000000  00000000  0002c458  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .debug_line   00007bf1  00000000  00000000  00042392  2**0
                  CONTENTS, READONLY, DEBUGGING
 18 .debug_str    00089db1  00000000  00000000  00049f83  2**0
                  CONTENTS, READONLY, DEBUGGING
 19 .comment      0000007b  00000000  00000000  000d3d34  2**0
                  CONTENTS, READONLY
 20 .debug_frame  000029c4  00000000  00000000  000d3db0  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

08000198 <__do_global_dtors_aux>:
 8000198:	b510      	push	{r4, lr}
 800019a:	4c05      	ldr	r4, [pc, #20]	; (80001b0 <__do_global_dtors_aux+0x18>)
 800019c:	7823      	ldrb	r3, [r4, #0]
 800019e:	b933      	cbnz	r3, 80001ae <__do_global_dtors_aux+0x16>
 80001a0:	4b04      	ldr	r3, [pc, #16]	; (80001b4 <__do_global_dtors_aux+0x1c>)
 80001a2:	b113      	cbz	r3, 80001aa <__do_global_dtors_aux+0x12>
 80001a4:	4804      	ldr	r0, [pc, #16]	; (80001b8 <__do_global_dtors_aux+0x20>)
 80001a6:	f3af 8000 	nop.w
 80001aa:	2301      	movs	r3, #1
 80001ac:	7023      	strb	r3, [r4, #0]
 80001ae:	bd10      	pop	{r4, pc}
 80001b0:	20000088 	.word	0x20000088
 80001b4:	00000000 	.word	0x00000000
 80001b8:	08005f64 	.word	0x08005f64

080001bc <frame_dummy>:
 80001bc:	b508      	push	{r3, lr}
 80001be:	4b03      	ldr	r3, [pc, #12]	; (80001cc <frame_dummy+0x10>)
 80001c0:	b11b      	cbz	r3, 80001ca <frame_dummy+0xe>
 80001c2:	4903      	ldr	r1, [pc, #12]	; (80001d0 <frame_dummy+0x14>)
 80001c4:	4803      	ldr	r0, [pc, #12]	; (80001d4 <frame_dummy+0x18>)
 80001c6:	f3af 8000 	nop.w
 80001ca:	bd08      	pop	{r3, pc}
 80001cc:	00000000 	.word	0x00000000
 80001d0:	2000008c 	.word	0x2000008c
 80001d4:	08005f64 	.word	0x08005f64

080001d8 <strlen>:
 80001d8:	4603      	mov	r3, r0
 80001da:	f813 2b01 	ldrb.w	r2, [r3], #1
 80001de:	2a00      	cmp	r2, #0
 80001e0:	d1fb      	bne.n	80001da <strlen+0x2>
 80001e2:	1a18      	subs	r0, r3, r0
 80001e4:	3801      	subs	r0, #1
 80001e6:	4770      	bx	lr

080001e8 <__aeabi_drsub>:
 80001e8:	f081 4100 	eor.w	r1, r1, #2147483648	; 0x80000000
 80001ec:	e002      	b.n	80001f4 <__adddf3>
 80001ee:	bf00      	nop

080001f0 <__aeabi_dsub>:
 80001f0:	f083 4300 	eor.w	r3, r3, #2147483648	; 0x80000000

080001f4 <__adddf3>:
 80001f4:	b530      	push	{r4, r5, lr}
 80001f6:	ea4f 0441 	mov.w	r4, r1, lsl #1
 80001fa:	ea4f 0543 	mov.w	r5, r3, lsl #1
 80001fe:	ea94 0f05 	teq	r4, r5
 8000202:	bf08      	it	eq
 8000204:	ea90 0f02 	teqeq	r0, r2
 8000208:	bf1f      	itttt	ne
 800020a:	ea54 0c00 	orrsne.w	ip, r4, r0
 800020e:	ea55 0c02 	orrsne.w	ip, r5, r2
 8000212:	ea7f 5c64 	mvnsne.w	ip, r4, asr #21
 8000216:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 800021a:	f000 80e2 	beq.w	80003e2 <__adddf3+0x1ee>
 800021e:	ea4f 5454 	mov.w	r4, r4, lsr #21
 8000222:	ebd4 5555 	rsbs	r5, r4, r5, lsr #21
 8000226:	bfb8      	it	lt
 8000228:	426d      	neglt	r5, r5
 800022a:	dd0c      	ble.n	8000246 <__adddf3+0x52>
 800022c:	442c      	add	r4, r5
 800022e:	ea80 0202 	eor.w	r2, r0, r2
 8000232:	ea81 0303 	eor.w	r3, r1, r3
 8000236:	ea82 0000 	eor.w	r0, r2, r0
 800023a:	ea83 0101 	eor.w	r1, r3, r1
 800023e:	ea80 0202 	eor.w	r2, r0, r2
 8000242:	ea81 0303 	eor.w	r3, r1, r3
 8000246:	2d36      	cmp	r5, #54	; 0x36
 8000248:	bf88      	it	hi
 800024a:	bd30      	pophi	{r4, r5, pc}
 800024c:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 8000250:	ea4f 3101 	mov.w	r1, r1, lsl #12
 8000254:	f44f 1c80 	mov.w	ip, #1048576	; 0x100000
 8000258:	ea4c 3111 	orr.w	r1, ip, r1, lsr #12
 800025c:	d002      	beq.n	8000264 <__adddf3+0x70>
 800025e:	4240      	negs	r0, r0
 8000260:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 8000264:	f013 4f00 	tst.w	r3, #2147483648	; 0x80000000
 8000268:	ea4f 3303 	mov.w	r3, r3, lsl #12
 800026c:	ea4c 3313 	orr.w	r3, ip, r3, lsr #12
 8000270:	d002      	beq.n	8000278 <__adddf3+0x84>
 8000272:	4252      	negs	r2, r2
 8000274:	eb63 0343 	sbc.w	r3, r3, r3, lsl #1
 8000278:	ea94 0f05 	teq	r4, r5
 800027c:	f000 80a7 	beq.w	80003ce <__adddf3+0x1da>
 8000280:	f1a4 0401 	sub.w	r4, r4, #1
 8000284:	f1d5 0e20 	rsbs	lr, r5, #32
 8000288:	db0d      	blt.n	80002a6 <__adddf3+0xb2>
 800028a:	fa02 fc0e 	lsl.w	ip, r2, lr
 800028e:	fa22 f205 	lsr.w	r2, r2, r5
 8000292:	1880      	adds	r0, r0, r2
 8000294:	f141 0100 	adc.w	r1, r1, #0
 8000298:	fa03 f20e 	lsl.w	r2, r3, lr
 800029c:	1880      	adds	r0, r0, r2
 800029e:	fa43 f305 	asr.w	r3, r3, r5
 80002a2:	4159      	adcs	r1, r3
 80002a4:	e00e      	b.n	80002c4 <__adddf3+0xd0>
 80002a6:	f1a5 0520 	sub.w	r5, r5, #32
 80002aa:	f10e 0e20 	add.w	lr, lr, #32
 80002ae:	2a01      	cmp	r2, #1
 80002b0:	fa03 fc0e 	lsl.w	ip, r3, lr
 80002b4:	bf28      	it	cs
 80002b6:	f04c 0c02 	orrcs.w	ip, ip, #2
 80002ba:	fa43 f305 	asr.w	r3, r3, r5
 80002be:	18c0      	adds	r0, r0, r3
 80002c0:	eb51 71e3 	adcs.w	r1, r1, r3, asr #31
 80002c4:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 80002c8:	d507      	bpl.n	80002da <__adddf3+0xe6>
 80002ca:	f04f 0e00 	mov.w	lr, #0
 80002ce:	f1dc 0c00 	rsbs	ip, ip, #0
 80002d2:	eb7e 0000 	sbcs.w	r0, lr, r0
 80002d6:	eb6e 0101 	sbc.w	r1, lr, r1
 80002da:	f5b1 1f80 	cmp.w	r1, #1048576	; 0x100000
 80002de:	d31b      	bcc.n	8000318 <__adddf3+0x124>
 80002e0:	f5b1 1f00 	cmp.w	r1, #2097152	; 0x200000
 80002e4:	d30c      	bcc.n	8000300 <__adddf3+0x10c>
 80002e6:	0849      	lsrs	r1, r1, #1
 80002e8:	ea5f 0030 	movs.w	r0, r0, rrx
 80002ec:	ea4f 0c3c 	mov.w	ip, ip, rrx
 80002f0:	f104 0401 	add.w	r4, r4, #1
 80002f4:	ea4f 5244 	mov.w	r2, r4, lsl #21
 80002f8:	f512 0f80 	cmn.w	r2, #4194304	; 0x400000
 80002fc:	f080 809a 	bcs.w	8000434 <__adddf3+0x240>
 8000300:	f1bc 4f00 	cmp.w	ip, #2147483648	; 0x80000000
 8000304:	bf08      	it	eq
 8000306:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 800030a:	f150 0000 	adcs.w	r0, r0, #0
 800030e:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 8000312:	ea41 0105 	orr.w	r1, r1, r5
 8000316:	bd30      	pop	{r4, r5, pc}
 8000318:	ea5f 0c4c 	movs.w	ip, ip, lsl #1
 800031c:	4140      	adcs	r0, r0
 800031e:	eb41 0101 	adc.w	r1, r1, r1
 8000322:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 8000326:	f1a4 0401 	sub.w	r4, r4, #1
 800032a:	d1e9      	bne.n	8000300 <__adddf3+0x10c>
 800032c:	f091 0f00 	teq	r1, #0
 8000330:	bf04      	itt	eq
 8000332:	4601      	moveq	r1, r0
 8000334:	2000      	moveq	r0, #0
 8000336:	fab1 f381 	clz	r3, r1
 800033a:	bf08      	it	eq
 800033c:	3320      	addeq	r3, #32
 800033e:	f1a3 030b 	sub.w	r3, r3, #11
 8000342:	f1b3 0220 	subs.w	r2, r3, #32
 8000346:	da0c      	bge.n	8000362 <__adddf3+0x16e>
 8000348:	320c      	adds	r2, #12
 800034a:	dd08      	ble.n	800035e <__adddf3+0x16a>
 800034c:	f102 0c14 	add.w	ip, r2, #20
 8000350:	f1c2 020c 	rsb	r2, r2, #12
 8000354:	fa01 f00c 	lsl.w	r0, r1, ip
 8000358:	fa21 f102 	lsr.w	r1, r1, r2
 800035c:	e00c      	b.n	8000378 <__adddf3+0x184>
 800035e:	f102 0214 	add.w	r2, r2, #20
 8000362:	bfd8      	it	le
 8000364:	f1c2 0c20 	rsble	ip, r2, #32
 8000368:	fa01 f102 	lsl.w	r1, r1, r2
 800036c:	fa20 fc0c 	lsr.w	ip, r0, ip
 8000370:	bfdc      	itt	le
 8000372:	ea41 010c 	orrle.w	r1, r1, ip
 8000376:	4090      	lslle	r0, r2
 8000378:	1ae4      	subs	r4, r4, r3
 800037a:	bfa2      	ittt	ge
 800037c:	eb01 5104 	addge.w	r1, r1, r4, lsl #20
 8000380:	4329      	orrge	r1, r5
 8000382:	bd30      	popge	{r4, r5, pc}
 8000384:	ea6f 0404 	mvn.w	r4, r4
 8000388:	3c1f      	subs	r4, #31
 800038a:	da1c      	bge.n	80003c6 <__adddf3+0x1d2>
 800038c:	340c      	adds	r4, #12
 800038e:	dc0e      	bgt.n	80003ae <__adddf3+0x1ba>
 8000390:	f104 0414 	add.w	r4, r4, #20
 8000394:	f1c4 0220 	rsb	r2, r4, #32
 8000398:	fa20 f004 	lsr.w	r0, r0, r4
 800039c:	fa01 f302 	lsl.w	r3, r1, r2
 80003a0:	ea40 0003 	orr.w	r0, r0, r3
 80003a4:	fa21 f304 	lsr.w	r3, r1, r4
 80003a8:	ea45 0103 	orr.w	r1, r5, r3
 80003ac:	bd30      	pop	{r4, r5, pc}
 80003ae:	f1c4 040c 	rsb	r4, r4, #12
 80003b2:	f1c4 0220 	rsb	r2, r4, #32
 80003b6:	fa20 f002 	lsr.w	r0, r0, r2
 80003ba:	fa01 f304 	lsl.w	r3, r1, r4
 80003be:	ea40 0003 	orr.w	r0, r0, r3
 80003c2:	4629      	mov	r1, r5
 80003c4:	bd30      	pop	{r4, r5, pc}
 80003c6:	fa21 f004 	lsr.w	r0, r1, r4
 80003ca:	4629      	mov	r1, r5
 80003cc:	bd30      	pop	{r4, r5, pc}
 80003ce:	f094 0f00 	teq	r4, #0
 80003d2:	f483 1380 	eor.w	r3, r3, #1048576	; 0x100000
 80003d6:	bf06      	itte	eq
 80003d8:	f481 1180 	eoreq.w	r1, r1, #1048576	; 0x100000
 80003dc:	3401      	addeq	r4, #1
 80003de:	3d01      	subne	r5, #1
 80003e0:	e74e      	b.n	8000280 <__adddf3+0x8c>
 80003e2:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 80003e6:	bf18      	it	ne
 80003e8:	ea7f 5c65 	mvnsne.w	ip, r5, asr #21
 80003ec:	d029      	beq.n	8000442 <__adddf3+0x24e>
 80003ee:	ea94 0f05 	teq	r4, r5
 80003f2:	bf08      	it	eq
 80003f4:	ea90 0f02 	teqeq	r0, r2
 80003f8:	d005      	beq.n	8000406 <__adddf3+0x212>
 80003fa:	ea54 0c00 	orrs.w	ip, r4, r0
 80003fe:	bf04      	itt	eq
 8000400:	4619      	moveq	r1, r3
 8000402:	4610      	moveq	r0, r2
 8000404:	bd30      	pop	{r4, r5, pc}
 8000406:	ea91 0f03 	teq	r1, r3
 800040a:	bf1e      	ittt	ne
 800040c:	2100      	movne	r1, #0
 800040e:	2000      	movne	r0, #0
 8000410:	bd30      	popne	{r4, r5, pc}
 8000412:	ea5f 5c54 	movs.w	ip, r4, lsr #21
 8000416:	d105      	bne.n	8000424 <__adddf3+0x230>
 8000418:	0040      	lsls	r0, r0, #1
 800041a:	4149      	adcs	r1, r1
 800041c:	bf28      	it	cs
 800041e:	f041 4100 	orrcs.w	r1, r1, #2147483648	; 0x80000000
 8000422:	bd30      	pop	{r4, r5, pc}
 8000424:	f514 0480 	adds.w	r4, r4, #4194304	; 0x400000
 8000428:	bf3c      	itt	cc
 800042a:	f501 1180 	addcc.w	r1, r1, #1048576	; 0x100000
 800042e:	bd30      	popcc	{r4, r5, pc}
 8000430:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 8000434:	f045 41fe 	orr.w	r1, r5, #2130706432	; 0x7f000000
 8000438:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 800043c:	f04f 0000 	mov.w	r0, #0
 8000440:	bd30      	pop	{r4, r5, pc}
 8000442:	ea7f 5c64 	mvns.w	ip, r4, asr #21
 8000446:	bf1a      	itte	ne
 8000448:	4619      	movne	r1, r3
 800044a:	4610      	movne	r0, r2
 800044c:	ea7f 5c65 	mvnseq.w	ip, r5, asr #21
 8000450:	bf1c      	itt	ne
 8000452:	460b      	movne	r3, r1
 8000454:	4602      	movne	r2, r0
 8000456:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 800045a:	bf06      	itte	eq
 800045c:	ea52 3503 	orrseq.w	r5, r2, r3, lsl #12
 8000460:	ea91 0f03 	teqeq	r1, r3
 8000464:	f441 2100 	orrne.w	r1, r1, #524288	; 0x80000
 8000468:	bd30      	pop	{r4, r5, pc}
 800046a:	bf00      	nop

0800046c <__aeabi_ui2d>:
 800046c:	f090 0f00 	teq	r0, #0
 8000470:	bf04      	itt	eq
 8000472:	2100      	moveq	r1, #0
 8000474:	4770      	bxeq	lr
 8000476:	b530      	push	{r4, r5, lr}
 8000478:	f44f 6480 	mov.w	r4, #1024	; 0x400
 800047c:	f104 0432 	add.w	r4, r4, #50	; 0x32
 8000480:	f04f 0500 	mov.w	r5, #0
 8000484:	f04f 0100 	mov.w	r1, #0
 8000488:	e750      	b.n	800032c <__adddf3+0x138>
 800048a:	bf00      	nop

0800048c <__aeabi_i2d>:
 800048c:	f090 0f00 	teq	r0, #0
 8000490:	bf04      	itt	eq
 8000492:	2100      	moveq	r1, #0
 8000494:	4770      	bxeq	lr
 8000496:	b530      	push	{r4, r5, lr}
 8000498:	f44f 6480 	mov.w	r4, #1024	; 0x400
 800049c:	f104 0432 	add.w	r4, r4, #50	; 0x32
 80004a0:	f010 4500 	ands.w	r5, r0, #2147483648	; 0x80000000
 80004a4:	bf48      	it	mi
 80004a6:	4240      	negmi	r0, r0
 80004a8:	f04f 0100 	mov.w	r1, #0
 80004ac:	e73e      	b.n	800032c <__adddf3+0x138>
 80004ae:	bf00      	nop

080004b0 <__aeabi_f2d>:
 80004b0:	0042      	lsls	r2, r0, #1
 80004b2:	ea4f 01e2 	mov.w	r1, r2, asr #3
 80004b6:	ea4f 0131 	mov.w	r1, r1, rrx
 80004ba:	ea4f 7002 	mov.w	r0, r2, lsl #28
 80004be:	bf1f      	itttt	ne
 80004c0:	f012 437f 	andsne.w	r3, r2, #4278190080	; 0xff000000
 80004c4:	f093 4f7f 	teqne	r3, #4278190080	; 0xff000000
 80004c8:	f081 5160 	eorne.w	r1, r1, #939524096	; 0x38000000
 80004cc:	4770      	bxne	lr
 80004ce:	f032 427f 	bics.w	r2, r2, #4278190080	; 0xff000000
 80004d2:	bf08      	it	eq
 80004d4:	4770      	bxeq	lr
 80004d6:	f093 4f7f 	teq	r3, #4278190080	; 0xff000000
 80004da:	bf04      	itt	eq
 80004dc:	f441 2100 	orreq.w	r1, r1, #524288	; 0x80000
 80004e0:	4770      	bxeq	lr
 80004e2:	b530      	push	{r4, r5, lr}
 80004e4:	f44f 7460 	mov.w	r4, #896	; 0x380
 80004e8:	f001 4500 	and.w	r5, r1, #2147483648	; 0x80000000
 80004ec:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 80004f0:	e71c      	b.n	800032c <__adddf3+0x138>
 80004f2:	bf00      	nop

080004f4 <__aeabi_ul2d>:
 80004f4:	ea50 0201 	orrs.w	r2, r0, r1
 80004f8:	bf08      	it	eq
 80004fa:	4770      	bxeq	lr
 80004fc:	b530      	push	{r4, r5, lr}
 80004fe:	f04f 0500 	mov.w	r5, #0
 8000502:	e00a      	b.n	800051a <__aeabi_l2d+0x16>

08000504 <__aeabi_l2d>:
 8000504:	ea50 0201 	orrs.w	r2, r0, r1
 8000508:	bf08      	it	eq
 800050a:	4770      	bxeq	lr
 800050c:	b530      	push	{r4, r5, lr}
 800050e:	f011 4500 	ands.w	r5, r1, #2147483648	; 0x80000000
 8000512:	d502      	bpl.n	800051a <__aeabi_l2d+0x16>
 8000514:	4240      	negs	r0, r0
 8000516:	eb61 0141 	sbc.w	r1, r1, r1, lsl #1
 800051a:	f44f 6480 	mov.w	r4, #1024	; 0x400
 800051e:	f104 0432 	add.w	r4, r4, #50	; 0x32
 8000522:	ea5f 5c91 	movs.w	ip, r1, lsr #22
 8000526:	f43f aed8 	beq.w	80002da <__adddf3+0xe6>
 800052a:	f04f 0203 	mov.w	r2, #3
 800052e:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 8000532:	bf18      	it	ne
 8000534:	3203      	addne	r2, #3
 8000536:	ea5f 0cdc 	movs.w	ip, ip, lsr #3
 800053a:	bf18      	it	ne
 800053c:	3203      	addne	r2, #3
 800053e:	eb02 02dc 	add.w	r2, r2, ip, lsr #3
 8000542:	f1c2 0320 	rsb	r3, r2, #32
 8000546:	fa00 fc03 	lsl.w	ip, r0, r3
 800054a:	fa20 f002 	lsr.w	r0, r0, r2
 800054e:	fa01 fe03 	lsl.w	lr, r1, r3
 8000552:	ea40 000e 	orr.w	r0, r0, lr
 8000556:	fa21 f102 	lsr.w	r1, r1, r2
 800055a:	4414      	add	r4, r2
 800055c:	e6bd      	b.n	80002da <__adddf3+0xe6>
 800055e:	bf00      	nop

08000560 <__aeabi_dmul>:
 8000560:	b570      	push	{r4, r5, r6, lr}
 8000562:	f04f 0cff 	mov.w	ip, #255	; 0xff
 8000566:	f44c 6ce0 	orr.w	ip, ip, #1792	; 0x700
 800056a:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 800056e:	bf1d      	ittte	ne
 8000570:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 8000574:	ea94 0f0c 	teqne	r4, ip
 8000578:	ea95 0f0c 	teqne	r5, ip
 800057c:	f000 f8de 	bleq	800073c <__aeabi_dmul+0x1dc>
 8000580:	442c      	add	r4, r5
 8000582:	ea81 0603 	eor.w	r6, r1, r3
 8000586:	ea21 514c 	bic.w	r1, r1, ip, lsl #21
 800058a:	ea23 534c 	bic.w	r3, r3, ip, lsl #21
 800058e:	ea50 3501 	orrs.w	r5, r0, r1, lsl #12
 8000592:	bf18      	it	ne
 8000594:	ea52 3503 	orrsne.w	r5, r2, r3, lsl #12
 8000598:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 800059c:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 80005a0:	d038      	beq.n	8000614 <__aeabi_dmul+0xb4>
 80005a2:	fba0 ce02 	umull	ip, lr, r0, r2
 80005a6:	f04f 0500 	mov.w	r5, #0
 80005aa:	fbe1 e502 	umlal	lr, r5, r1, r2
 80005ae:	f006 4200 	and.w	r2, r6, #2147483648	; 0x80000000
 80005b2:	fbe0 e503 	umlal	lr, r5, r0, r3
 80005b6:	f04f 0600 	mov.w	r6, #0
 80005ba:	fbe1 5603 	umlal	r5, r6, r1, r3
 80005be:	f09c 0f00 	teq	ip, #0
 80005c2:	bf18      	it	ne
 80005c4:	f04e 0e01 	orrne.w	lr, lr, #1
 80005c8:	f1a4 04ff 	sub.w	r4, r4, #255	; 0xff
 80005cc:	f5b6 7f00 	cmp.w	r6, #512	; 0x200
 80005d0:	f564 7440 	sbc.w	r4, r4, #768	; 0x300
 80005d4:	d204      	bcs.n	80005e0 <__aeabi_dmul+0x80>
 80005d6:	ea5f 0e4e 	movs.w	lr, lr, lsl #1
 80005da:	416d      	adcs	r5, r5
 80005dc:	eb46 0606 	adc.w	r6, r6, r6
 80005e0:	ea42 21c6 	orr.w	r1, r2, r6, lsl #11
 80005e4:	ea41 5155 	orr.w	r1, r1, r5, lsr #21
 80005e8:	ea4f 20c5 	mov.w	r0, r5, lsl #11
 80005ec:	ea40 505e 	orr.w	r0, r0, lr, lsr #21
 80005f0:	ea4f 2ece 	mov.w	lr, lr, lsl #11
 80005f4:	f1b4 0cfd 	subs.w	ip, r4, #253	; 0xfd
 80005f8:	bf88      	it	hi
 80005fa:	f5bc 6fe0 	cmphi.w	ip, #1792	; 0x700
 80005fe:	d81e      	bhi.n	800063e <__aeabi_dmul+0xde>
 8000600:	f1be 4f00 	cmp.w	lr, #2147483648	; 0x80000000
 8000604:	bf08      	it	eq
 8000606:	ea5f 0e50 	movseq.w	lr, r0, lsr #1
 800060a:	f150 0000 	adcs.w	r0, r0, #0
 800060e:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 8000612:	bd70      	pop	{r4, r5, r6, pc}
 8000614:	f006 4600 	and.w	r6, r6, #2147483648	; 0x80000000
 8000618:	ea46 0101 	orr.w	r1, r6, r1
 800061c:	ea40 0002 	orr.w	r0, r0, r2
 8000620:	ea81 0103 	eor.w	r1, r1, r3
 8000624:	ebb4 045c 	subs.w	r4, r4, ip, lsr #1
 8000628:	bfc2      	ittt	gt
 800062a:	ebd4 050c 	rsbsgt	r5, r4, ip
 800062e:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 8000632:	bd70      	popgt	{r4, r5, r6, pc}
 8000634:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 8000638:	f04f 0e00 	mov.w	lr, #0
 800063c:	3c01      	subs	r4, #1
 800063e:	f300 80ab 	bgt.w	8000798 <__aeabi_dmul+0x238>
 8000642:	f114 0f36 	cmn.w	r4, #54	; 0x36
 8000646:	bfde      	ittt	le
 8000648:	2000      	movle	r0, #0
 800064a:	f001 4100 	andle.w	r1, r1, #2147483648	; 0x80000000
 800064e:	bd70      	pople	{r4, r5, r6, pc}
 8000650:	f1c4 0400 	rsb	r4, r4, #0
 8000654:	3c20      	subs	r4, #32
 8000656:	da35      	bge.n	80006c4 <__aeabi_dmul+0x164>
 8000658:	340c      	adds	r4, #12
 800065a:	dc1b      	bgt.n	8000694 <__aeabi_dmul+0x134>
 800065c:	f104 0414 	add.w	r4, r4, #20
 8000660:	f1c4 0520 	rsb	r5, r4, #32
 8000664:	fa00 f305 	lsl.w	r3, r0, r5
 8000668:	fa20 f004 	lsr.w	r0, r0, r4
 800066c:	fa01 f205 	lsl.w	r2, r1, r5
 8000670:	ea40 0002 	orr.w	r0, r0, r2
 8000674:	f001 4200 	and.w	r2, r1, #2147483648	; 0x80000000
 8000678:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 800067c:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 8000680:	fa21 f604 	lsr.w	r6, r1, r4
 8000684:	eb42 0106 	adc.w	r1, r2, r6
 8000688:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 800068c:	bf08      	it	eq
 800068e:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 8000692:	bd70      	pop	{r4, r5, r6, pc}
 8000694:	f1c4 040c 	rsb	r4, r4, #12
 8000698:	f1c4 0520 	rsb	r5, r4, #32
 800069c:	fa00 f304 	lsl.w	r3, r0, r4
 80006a0:	fa20 f005 	lsr.w	r0, r0, r5
 80006a4:	fa01 f204 	lsl.w	r2, r1, r4
 80006a8:	ea40 0002 	orr.w	r0, r0, r2
 80006ac:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 80006b0:	eb10 70d3 	adds.w	r0, r0, r3, lsr #31
 80006b4:	f141 0100 	adc.w	r1, r1, #0
 80006b8:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 80006bc:	bf08      	it	eq
 80006be:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 80006c2:	bd70      	pop	{r4, r5, r6, pc}
 80006c4:	f1c4 0520 	rsb	r5, r4, #32
 80006c8:	fa00 f205 	lsl.w	r2, r0, r5
 80006cc:	ea4e 0e02 	orr.w	lr, lr, r2
 80006d0:	fa20 f304 	lsr.w	r3, r0, r4
 80006d4:	fa01 f205 	lsl.w	r2, r1, r5
 80006d8:	ea43 0302 	orr.w	r3, r3, r2
 80006dc:	fa21 f004 	lsr.w	r0, r1, r4
 80006e0:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 80006e4:	fa21 f204 	lsr.w	r2, r1, r4
 80006e8:	ea20 0002 	bic.w	r0, r0, r2
 80006ec:	eb00 70d3 	add.w	r0, r0, r3, lsr #31
 80006f0:	ea5e 0e43 	orrs.w	lr, lr, r3, lsl #1
 80006f4:	bf08      	it	eq
 80006f6:	ea20 70d3 	biceq.w	r0, r0, r3, lsr #31
 80006fa:	bd70      	pop	{r4, r5, r6, pc}
 80006fc:	f094 0f00 	teq	r4, #0
 8000700:	d10f      	bne.n	8000722 <__aeabi_dmul+0x1c2>
 8000702:	f001 4600 	and.w	r6, r1, #2147483648	; 0x80000000
 8000706:	0040      	lsls	r0, r0, #1
 8000708:	eb41 0101 	adc.w	r1, r1, r1
 800070c:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 8000710:	bf08      	it	eq
 8000712:	3c01      	subeq	r4, #1
 8000714:	d0f7      	beq.n	8000706 <__aeabi_dmul+0x1a6>
 8000716:	ea41 0106 	orr.w	r1, r1, r6
 800071a:	f095 0f00 	teq	r5, #0
 800071e:	bf18      	it	ne
 8000720:	4770      	bxne	lr
 8000722:	f003 4600 	and.w	r6, r3, #2147483648	; 0x80000000
 8000726:	0052      	lsls	r2, r2, #1
 8000728:	eb43 0303 	adc.w	r3, r3, r3
 800072c:	f413 1f80 	tst.w	r3, #1048576	; 0x100000
 8000730:	bf08      	it	eq
 8000732:	3d01      	subeq	r5, #1
 8000734:	d0f7      	beq.n	8000726 <__aeabi_dmul+0x1c6>
 8000736:	ea43 0306 	orr.w	r3, r3, r6
 800073a:	4770      	bx	lr
 800073c:	ea94 0f0c 	teq	r4, ip
 8000740:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 8000744:	bf18      	it	ne
 8000746:	ea95 0f0c 	teqne	r5, ip
 800074a:	d00c      	beq.n	8000766 <__aeabi_dmul+0x206>
 800074c:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000750:	bf18      	it	ne
 8000752:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 8000756:	d1d1      	bne.n	80006fc <__aeabi_dmul+0x19c>
 8000758:	ea81 0103 	eor.w	r1, r1, r3
 800075c:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 8000760:	f04f 0000 	mov.w	r0, #0
 8000764:	bd70      	pop	{r4, r5, r6, pc}
 8000766:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 800076a:	bf06      	itte	eq
 800076c:	4610      	moveq	r0, r2
 800076e:	4619      	moveq	r1, r3
 8000770:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 8000774:	d019      	beq.n	80007aa <__aeabi_dmul+0x24a>
 8000776:	ea94 0f0c 	teq	r4, ip
 800077a:	d102      	bne.n	8000782 <__aeabi_dmul+0x222>
 800077c:	ea50 3601 	orrs.w	r6, r0, r1, lsl #12
 8000780:	d113      	bne.n	80007aa <__aeabi_dmul+0x24a>
 8000782:	ea95 0f0c 	teq	r5, ip
 8000786:	d105      	bne.n	8000794 <__aeabi_dmul+0x234>
 8000788:	ea52 3603 	orrs.w	r6, r2, r3, lsl #12
 800078c:	bf1c      	itt	ne
 800078e:	4610      	movne	r0, r2
 8000790:	4619      	movne	r1, r3
 8000792:	d10a      	bne.n	80007aa <__aeabi_dmul+0x24a>
 8000794:	ea81 0103 	eor.w	r1, r1, r3
 8000798:	f001 4100 	and.w	r1, r1, #2147483648	; 0x80000000
 800079c:	f041 41fe 	orr.w	r1, r1, #2130706432	; 0x7f000000
 80007a0:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 80007a4:	f04f 0000 	mov.w	r0, #0
 80007a8:	bd70      	pop	{r4, r5, r6, pc}
 80007aa:	f041 41fe 	orr.w	r1, r1, #2130706432	; 0x7f000000
 80007ae:	f441 0178 	orr.w	r1, r1, #16252928	; 0xf80000
 80007b2:	bd70      	pop	{r4, r5, r6, pc}

080007b4 <__aeabi_ddiv>:
 80007b4:	b570      	push	{r4, r5, r6, lr}
 80007b6:	f04f 0cff 	mov.w	ip, #255	; 0xff
 80007ba:	f44c 6ce0 	orr.w	ip, ip, #1792	; 0x700
 80007be:	ea1c 5411 	ands.w	r4, ip, r1, lsr #20
 80007c2:	bf1d      	ittte	ne
 80007c4:	ea1c 5513 	andsne.w	r5, ip, r3, lsr #20
 80007c8:	ea94 0f0c 	teqne	r4, ip
 80007cc:	ea95 0f0c 	teqne	r5, ip
 80007d0:	f000 f8a7 	bleq	8000922 <__aeabi_ddiv+0x16e>
 80007d4:	eba4 0405 	sub.w	r4, r4, r5
 80007d8:	ea81 0e03 	eor.w	lr, r1, r3
 80007dc:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 80007e0:	ea4f 3101 	mov.w	r1, r1, lsl #12
 80007e4:	f000 8088 	beq.w	80008f8 <__aeabi_ddiv+0x144>
 80007e8:	ea4f 3303 	mov.w	r3, r3, lsl #12
 80007ec:	f04f 5580 	mov.w	r5, #268435456	; 0x10000000
 80007f0:	ea45 1313 	orr.w	r3, r5, r3, lsr #4
 80007f4:	ea43 6312 	orr.w	r3, r3, r2, lsr #24
 80007f8:	ea4f 2202 	mov.w	r2, r2, lsl #8
 80007fc:	ea45 1511 	orr.w	r5, r5, r1, lsr #4
 8000800:	ea45 6510 	orr.w	r5, r5, r0, lsr #24
 8000804:	ea4f 2600 	mov.w	r6, r0, lsl #8
 8000808:	f00e 4100 	and.w	r1, lr, #2147483648	; 0x80000000
 800080c:	429d      	cmp	r5, r3
 800080e:	bf08      	it	eq
 8000810:	4296      	cmpeq	r6, r2
 8000812:	f144 04fd 	adc.w	r4, r4, #253	; 0xfd
 8000816:	f504 7440 	add.w	r4, r4, #768	; 0x300
 800081a:	d202      	bcs.n	8000822 <__aeabi_ddiv+0x6e>
 800081c:	085b      	lsrs	r3, r3, #1
 800081e:	ea4f 0232 	mov.w	r2, r2, rrx
 8000822:	1ab6      	subs	r6, r6, r2
 8000824:	eb65 0503 	sbc.w	r5, r5, r3
 8000828:	085b      	lsrs	r3, r3, #1
 800082a:	ea4f 0232 	mov.w	r2, r2, rrx
 800082e:	f44f 1080 	mov.w	r0, #1048576	; 0x100000
 8000832:	f44f 2c00 	mov.w	ip, #524288	; 0x80000
 8000836:	ebb6 0e02 	subs.w	lr, r6, r2
 800083a:	eb75 0e03 	sbcs.w	lr, r5, r3
 800083e:	bf22      	ittt	cs
 8000840:	1ab6      	subcs	r6, r6, r2
 8000842:	4675      	movcs	r5, lr
 8000844:	ea40 000c 	orrcs.w	r0, r0, ip
 8000848:	085b      	lsrs	r3, r3, #1
 800084a:	ea4f 0232 	mov.w	r2, r2, rrx
 800084e:	ebb6 0e02 	subs.w	lr, r6, r2
 8000852:	eb75 0e03 	sbcs.w	lr, r5, r3
 8000856:	bf22      	ittt	cs
 8000858:	1ab6      	subcs	r6, r6, r2
 800085a:	4675      	movcs	r5, lr
 800085c:	ea40 005c 	orrcs.w	r0, r0, ip, lsr #1
 8000860:	085b      	lsrs	r3, r3, #1
 8000862:	ea4f 0232 	mov.w	r2, r2, rrx
 8000866:	ebb6 0e02 	subs.w	lr, r6, r2
 800086a:	eb75 0e03 	sbcs.w	lr, r5, r3
 800086e:	bf22      	ittt	cs
 8000870:	1ab6      	subcs	r6, r6, r2
 8000872:	4675      	movcs	r5, lr
 8000874:	ea40 009c 	orrcs.w	r0, r0, ip, lsr #2
 8000878:	085b      	lsrs	r3, r3, #1
 800087a:	ea4f 0232 	mov.w	r2, r2, rrx
 800087e:	ebb6 0e02 	subs.w	lr, r6, r2
 8000882:	eb75 0e03 	sbcs.w	lr, r5, r3
 8000886:	bf22      	ittt	cs
 8000888:	1ab6      	subcs	r6, r6, r2
 800088a:	4675      	movcs	r5, lr
 800088c:	ea40 00dc 	orrcs.w	r0, r0, ip, lsr #3
 8000890:	ea55 0e06 	orrs.w	lr, r5, r6
 8000894:	d018      	beq.n	80008c8 <__aeabi_ddiv+0x114>
 8000896:	ea4f 1505 	mov.w	r5, r5, lsl #4
 800089a:	ea45 7516 	orr.w	r5, r5, r6, lsr #28
 800089e:	ea4f 1606 	mov.w	r6, r6, lsl #4
 80008a2:	ea4f 03c3 	mov.w	r3, r3, lsl #3
 80008a6:	ea43 7352 	orr.w	r3, r3, r2, lsr #29
 80008aa:	ea4f 02c2 	mov.w	r2, r2, lsl #3
 80008ae:	ea5f 1c1c 	movs.w	ip, ip, lsr #4
 80008b2:	d1c0      	bne.n	8000836 <__aeabi_ddiv+0x82>
 80008b4:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 80008b8:	d10b      	bne.n	80008d2 <__aeabi_ddiv+0x11e>
 80008ba:	ea41 0100 	orr.w	r1, r1, r0
 80008be:	f04f 0000 	mov.w	r0, #0
 80008c2:	f04f 4c00 	mov.w	ip, #2147483648	; 0x80000000
 80008c6:	e7b6      	b.n	8000836 <__aeabi_ddiv+0x82>
 80008c8:	f411 1f80 	tst.w	r1, #1048576	; 0x100000
 80008cc:	bf04      	itt	eq
 80008ce:	4301      	orreq	r1, r0
 80008d0:	2000      	moveq	r0, #0
 80008d2:	f1b4 0cfd 	subs.w	ip, r4, #253	; 0xfd
 80008d6:	bf88      	it	hi
 80008d8:	f5bc 6fe0 	cmphi.w	ip, #1792	; 0x700
 80008dc:	f63f aeaf 	bhi.w	800063e <__aeabi_dmul+0xde>
 80008e0:	ebb5 0c03 	subs.w	ip, r5, r3
 80008e4:	bf04      	itt	eq
 80008e6:	ebb6 0c02 	subseq.w	ip, r6, r2
 80008ea:	ea5f 0c50 	movseq.w	ip, r0, lsr #1
 80008ee:	f150 0000 	adcs.w	r0, r0, #0
 80008f2:	eb41 5104 	adc.w	r1, r1, r4, lsl #20
 80008f6:	bd70      	pop	{r4, r5, r6, pc}
 80008f8:	f00e 4e00 	and.w	lr, lr, #2147483648	; 0x80000000
 80008fc:	ea4e 3111 	orr.w	r1, lr, r1, lsr #12
 8000900:	eb14 045c 	adds.w	r4, r4, ip, lsr #1
 8000904:	bfc2      	ittt	gt
 8000906:	ebd4 050c 	rsbsgt	r5, r4, ip
 800090a:	ea41 5104 	orrgt.w	r1, r1, r4, lsl #20
 800090e:	bd70      	popgt	{r4, r5, r6, pc}
 8000910:	f441 1180 	orr.w	r1, r1, #1048576	; 0x100000
 8000914:	f04f 0e00 	mov.w	lr, #0
 8000918:	3c01      	subs	r4, #1
 800091a:	e690      	b.n	800063e <__aeabi_dmul+0xde>
 800091c:	ea45 0e06 	orr.w	lr, r5, r6
 8000920:	e68d      	b.n	800063e <__aeabi_dmul+0xde>
 8000922:	ea0c 5513 	and.w	r5, ip, r3, lsr #20
 8000926:	ea94 0f0c 	teq	r4, ip
 800092a:	bf08      	it	eq
 800092c:	ea95 0f0c 	teqeq	r5, ip
 8000930:	f43f af3b 	beq.w	80007aa <__aeabi_dmul+0x24a>
 8000934:	ea94 0f0c 	teq	r4, ip
 8000938:	d10a      	bne.n	8000950 <__aeabi_ddiv+0x19c>
 800093a:	ea50 3401 	orrs.w	r4, r0, r1, lsl #12
 800093e:	f47f af34 	bne.w	80007aa <__aeabi_dmul+0x24a>
 8000942:	ea95 0f0c 	teq	r5, ip
 8000946:	f47f af25 	bne.w	8000794 <__aeabi_dmul+0x234>
 800094a:	4610      	mov	r0, r2
 800094c:	4619      	mov	r1, r3
 800094e:	e72c      	b.n	80007aa <__aeabi_dmul+0x24a>
 8000950:	ea95 0f0c 	teq	r5, ip
 8000954:	d106      	bne.n	8000964 <__aeabi_ddiv+0x1b0>
 8000956:	ea52 3503 	orrs.w	r5, r2, r3, lsl #12
 800095a:	f43f aefd 	beq.w	8000758 <__aeabi_dmul+0x1f8>
 800095e:	4610      	mov	r0, r2
 8000960:	4619      	mov	r1, r3
 8000962:	e722      	b.n	80007aa <__aeabi_dmul+0x24a>
 8000964:	ea50 0641 	orrs.w	r6, r0, r1, lsl #1
 8000968:	bf18      	it	ne
 800096a:	ea52 0643 	orrsne.w	r6, r2, r3, lsl #1
 800096e:	f47f aec5 	bne.w	80006fc <__aeabi_dmul+0x19c>
 8000972:	ea50 0441 	orrs.w	r4, r0, r1, lsl #1
 8000976:	f47f af0d 	bne.w	8000794 <__aeabi_dmul+0x234>
 800097a:	ea52 0543 	orrs.w	r5, r2, r3, lsl #1
 800097e:	f47f aeeb 	bne.w	8000758 <__aeabi_dmul+0x1f8>
 8000982:	e712      	b.n	80007aa <__aeabi_dmul+0x24a>

08000984 <__gedf2>:
 8000984:	f04f 3cff 	mov.w	ip, #4294967295
 8000988:	e006      	b.n	8000998 <__cmpdf2+0x4>
 800098a:	bf00      	nop

0800098c <__ledf2>:
 800098c:	f04f 0c01 	mov.w	ip, #1
 8000990:	e002      	b.n	8000998 <__cmpdf2+0x4>
 8000992:	bf00      	nop

08000994 <__cmpdf2>:
 8000994:	f04f 0c01 	mov.w	ip, #1
 8000998:	f84d cd04 	str.w	ip, [sp, #-4]!
 800099c:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 80009a0:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 80009a4:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 80009a8:	bf18      	it	ne
 80009aa:	ea7f 5c6c 	mvnsne.w	ip, ip, asr #21
 80009ae:	d01b      	beq.n	80009e8 <__cmpdf2+0x54>
 80009b0:	b001      	add	sp, #4
 80009b2:	ea50 0c41 	orrs.w	ip, r0, r1, lsl #1
 80009b6:	bf0c      	ite	eq
 80009b8:	ea52 0c43 	orrseq.w	ip, r2, r3, lsl #1
 80009bc:	ea91 0f03 	teqne	r1, r3
 80009c0:	bf02      	ittt	eq
 80009c2:	ea90 0f02 	teqeq	r0, r2
 80009c6:	2000      	moveq	r0, #0
 80009c8:	4770      	bxeq	lr
 80009ca:	f110 0f00 	cmn.w	r0, #0
 80009ce:	ea91 0f03 	teq	r1, r3
 80009d2:	bf58      	it	pl
 80009d4:	4299      	cmppl	r1, r3
 80009d6:	bf08      	it	eq
 80009d8:	4290      	cmpeq	r0, r2
 80009da:	bf2c      	ite	cs
 80009dc:	17d8      	asrcs	r0, r3, #31
 80009de:	ea6f 70e3 	mvncc.w	r0, r3, asr #31
 80009e2:	f040 0001 	orr.w	r0, r0, #1
 80009e6:	4770      	bx	lr
 80009e8:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 80009ec:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 80009f0:	d102      	bne.n	80009f8 <__cmpdf2+0x64>
 80009f2:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 80009f6:	d107      	bne.n	8000a08 <__cmpdf2+0x74>
 80009f8:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 80009fc:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a00:	d1d6      	bne.n	80009b0 <__cmpdf2+0x1c>
 8000a02:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000a06:	d0d3      	beq.n	80009b0 <__cmpdf2+0x1c>
 8000a08:	f85d 0b04 	ldr.w	r0, [sp], #4
 8000a0c:	4770      	bx	lr
 8000a0e:	bf00      	nop

08000a10 <__aeabi_cdrcmple>:
 8000a10:	4684      	mov	ip, r0
 8000a12:	4610      	mov	r0, r2
 8000a14:	4662      	mov	r2, ip
 8000a16:	468c      	mov	ip, r1
 8000a18:	4619      	mov	r1, r3
 8000a1a:	4663      	mov	r3, ip
 8000a1c:	e000      	b.n	8000a20 <__aeabi_cdcmpeq>
 8000a1e:	bf00      	nop

08000a20 <__aeabi_cdcmpeq>:
 8000a20:	b501      	push	{r0, lr}
 8000a22:	f7ff ffb7 	bl	8000994 <__cmpdf2>
 8000a26:	2800      	cmp	r0, #0
 8000a28:	bf48      	it	mi
 8000a2a:	f110 0f00 	cmnmi.w	r0, #0
 8000a2e:	bd01      	pop	{r0, pc}

08000a30 <__aeabi_dcmpeq>:
 8000a30:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a34:	f7ff fff4 	bl	8000a20 <__aeabi_cdcmpeq>
 8000a38:	bf0c      	ite	eq
 8000a3a:	2001      	moveq	r0, #1
 8000a3c:	2000      	movne	r0, #0
 8000a3e:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a42:	bf00      	nop

08000a44 <__aeabi_dcmplt>:
 8000a44:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a48:	f7ff ffea 	bl	8000a20 <__aeabi_cdcmpeq>
 8000a4c:	bf34      	ite	cc
 8000a4e:	2001      	movcc	r0, #1
 8000a50:	2000      	movcs	r0, #0
 8000a52:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a56:	bf00      	nop

08000a58 <__aeabi_dcmple>:
 8000a58:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a5c:	f7ff ffe0 	bl	8000a20 <__aeabi_cdcmpeq>
 8000a60:	bf94      	ite	ls
 8000a62:	2001      	movls	r0, #1
 8000a64:	2000      	movhi	r0, #0
 8000a66:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a6a:	bf00      	nop

08000a6c <__aeabi_dcmpge>:
 8000a6c:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a70:	f7ff ffce 	bl	8000a10 <__aeabi_cdrcmple>
 8000a74:	bf94      	ite	ls
 8000a76:	2001      	movls	r0, #1
 8000a78:	2000      	movhi	r0, #0
 8000a7a:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a7e:	bf00      	nop

08000a80 <__aeabi_dcmpgt>:
 8000a80:	f84d ed08 	str.w	lr, [sp, #-8]!
 8000a84:	f7ff ffc4 	bl	8000a10 <__aeabi_cdrcmple>
 8000a88:	bf34      	ite	cc
 8000a8a:	2001      	movcc	r0, #1
 8000a8c:	2000      	movcs	r0, #0
 8000a8e:	f85d fb08 	ldr.w	pc, [sp], #8
 8000a92:	bf00      	nop

08000a94 <__aeabi_dcmpun>:
 8000a94:	ea4f 0c41 	mov.w	ip, r1, lsl #1
 8000a98:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000a9c:	d102      	bne.n	8000aa4 <__aeabi_dcmpun+0x10>
 8000a9e:	ea50 3c01 	orrs.w	ip, r0, r1, lsl #12
 8000aa2:	d10a      	bne.n	8000aba <__aeabi_dcmpun+0x26>
 8000aa4:	ea4f 0c43 	mov.w	ip, r3, lsl #1
 8000aa8:	ea7f 5c6c 	mvns.w	ip, ip, asr #21
 8000aac:	d102      	bne.n	8000ab4 <__aeabi_dcmpun+0x20>
 8000aae:	ea52 3c03 	orrs.w	ip, r2, r3, lsl #12
 8000ab2:	d102      	bne.n	8000aba <__aeabi_dcmpun+0x26>
 8000ab4:	f04f 0000 	mov.w	r0, #0
 8000ab8:	4770      	bx	lr
 8000aba:	f04f 0001 	mov.w	r0, #1
 8000abe:	4770      	bx	lr

08000ac0 <__aeabi_d2iz>:
 8000ac0:	ea4f 0241 	mov.w	r2, r1, lsl #1
 8000ac4:	f512 1200 	adds.w	r2, r2, #2097152	; 0x200000
 8000ac8:	d215      	bcs.n	8000af6 <__aeabi_d2iz+0x36>
 8000aca:	d511      	bpl.n	8000af0 <__aeabi_d2iz+0x30>
 8000acc:	f46f 7378 	mvn.w	r3, #992	; 0x3e0
 8000ad0:	ebb3 5262 	subs.w	r2, r3, r2, asr #21
 8000ad4:	d912      	bls.n	8000afc <__aeabi_d2iz+0x3c>
 8000ad6:	ea4f 23c1 	mov.w	r3, r1, lsl #11
 8000ada:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 8000ade:	ea43 5350 	orr.w	r3, r3, r0, lsr #21
 8000ae2:	f011 4f00 	tst.w	r1, #2147483648	; 0x80000000
 8000ae6:	fa23 f002 	lsr.w	r0, r3, r2
 8000aea:	bf18      	it	ne
 8000aec:	4240      	negne	r0, r0
 8000aee:	4770      	bx	lr
 8000af0:	f04f 0000 	mov.w	r0, #0
 8000af4:	4770      	bx	lr
 8000af6:	ea50 3001 	orrs.w	r0, r0, r1, lsl #12
 8000afa:	d105      	bne.n	8000b08 <__aeabi_d2iz+0x48>
 8000afc:	f011 4000 	ands.w	r0, r1, #2147483648	; 0x80000000
 8000b00:	bf08      	it	eq
 8000b02:	f06f 4000 	mvneq.w	r0, #2147483648	; 0x80000000
 8000b06:	4770      	bx	lr
 8000b08:	f04f 0000 	mov.w	r0, #0
 8000b0c:	4770      	bx	lr
 8000b0e:	bf00      	nop

08000b10 <__aeabi_uldivmod>:
 8000b10:	b953      	cbnz	r3, 8000b28 <__aeabi_uldivmod+0x18>
 8000b12:	b94a      	cbnz	r2, 8000b28 <__aeabi_uldivmod+0x18>
 8000b14:	2900      	cmp	r1, #0
 8000b16:	bf08      	it	eq
 8000b18:	2800      	cmpeq	r0, #0
 8000b1a:	bf1c      	itt	ne
 8000b1c:	f04f 31ff 	movne.w	r1, #4294967295
 8000b20:	f04f 30ff 	movne.w	r0, #4294967295
 8000b24:	f000 b972 	b.w	8000e0c <__aeabi_idiv0>
 8000b28:	f1ad 0c08 	sub.w	ip, sp, #8
 8000b2c:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 8000b30:	f000 f806 	bl	8000b40 <__udivmoddi4>
 8000b34:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000b38:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000b3c:	b004      	add	sp, #16
 8000b3e:	4770      	bx	lr

08000b40 <__udivmoddi4>:
 8000b40:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000b44:	9e08      	ldr	r6, [sp, #32]
 8000b46:	4604      	mov	r4, r0
 8000b48:	4688      	mov	r8, r1
 8000b4a:	2b00      	cmp	r3, #0
 8000b4c:	d14b      	bne.n	8000be6 <__udivmoddi4+0xa6>
 8000b4e:	428a      	cmp	r2, r1
 8000b50:	4615      	mov	r5, r2
 8000b52:	d967      	bls.n	8000c24 <__udivmoddi4+0xe4>
 8000b54:	fab2 f282 	clz	r2, r2
 8000b58:	b14a      	cbz	r2, 8000b6e <__udivmoddi4+0x2e>
 8000b5a:	f1c2 0720 	rsb	r7, r2, #32
 8000b5e:	fa01 f302 	lsl.w	r3, r1, r2
 8000b62:	fa20 f707 	lsr.w	r7, r0, r7
 8000b66:	4095      	lsls	r5, r2
 8000b68:	ea47 0803 	orr.w	r8, r7, r3
 8000b6c:	4094      	lsls	r4, r2
 8000b6e:	ea4f 4e15 	mov.w	lr, r5, lsr #16
 8000b72:	0c23      	lsrs	r3, r4, #16
 8000b74:	fbb8 f7fe 	udiv	r7, r8, lr
 8000b78:	fa1f fc85 	uxth.w	ip, r5
 8000b7c:	fb0e 8817 	mls	r8, lr, r7, r8
 8000b80:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 8000b84:	fb07 f10c 	mul.w	r1, r7, ip
 8000b88:	4299      	cmp	r1, r3
 8000b8a:	d909      	bls.n	8000ba0 <__udivmoddi4+0x60>
 8000b8c:	18eb      	adds	r3, r5, r3
 8000b8e:	f107 30ff 	add.w	r0, r7, #4294967295
 8000b92:	f080 811b 	bcs.w	8000dcc <__udivmoddi4+0x28c>
 8000b96:	4299      	cmp	r1, r3
 8000b98:	f240 8118 	bls.w	8000dcc <__udivmoddi4+0x28c>
 8000b9c:	3f02      	subs	r7, #2
 8000b9e:	442b      	add	r3, r5
 8000ba0:	1a5b      	subs	r3, r3, r1
 8000ba2:	b2a4      	uxth	r4, r4
 8000ba4:	fbb3 f0fe 	udiv	r0, r3, lr
 8000ba8:	fb0e 3310 	mls	r3, lr, r0, r3
 8000bac:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 8000bb0:	fb00 fc0c 	mul.w	ip, r0, ip
 8000bb4:	45a4      	cmp	ip, r4
 8000bb6:	d909      	bls.n	8000bcc <__udivmoddi4+0x8c>
 8000bb8:	192c      	adds	r4, r5, r4
 8000bba:	f100 33ff 	add.w	r3, r0, #4294967295
 8000bbe:	f080 8107 	bcs.w	8000dd0 <__udivmoddi4+0x290>
 8000bc2:	45a4      	cmp	ip, r4
 8000bc4:	f240 8104 	bls.w	8000dd0 <__udivmoddi4+0x290>
 8000bc8:	3802      	subs	r0, #2
 8000bca:	442c      	add	r4, r5
 8000bcc:	ea40 4007 	orr.w	r0, r0, r7, lsl #16
 8000bd0:	eba4 040c 	sub.w	r4, r4, ip
 8000bd4:	2700      	movs	r7, #0
 8000bd6:	b11e      	cbz	r6, 8000be0 <__udivmoddi4+0xa0>
 8000bd8:	40d4      	lsrs	r4, r2
 8000bda:	2300      	movs	r3, #0
 8000bdc:	e9c6 4300 	strd	r4, r3, [r6]
 8000be0:	4639      	mov	r1, r7
 8000be2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000be6:	428b      	cmp	r3, r1
 8000be8:	d909      	bls.n	8000bfe <__udivmoddi4+0xbe>
 8000bea:	2e00      	cmp	r6, #0
 8000bec:	f000 80eb 	beq.w	8000dc6 <__udivmoddi4+0x286>
 8000bf0:	2700      	movs	r7, #0
 8000bf2:	e9c6 0100 	strd	r0, r1, [r6]
 8000bf6:	4638      	mov	r0, r7
 8000bf8:	4639      	mov	r1, r7
 8000bfa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000bfe:	fab3 f783 	clz	r7, r3
 8000c02:	2f00      	cmp	r7, #0
 8000c04:	d147      	bne.n	8000c96 <__udivmoddi4+0x156>
 8000c06:	428b      	cmp	r3, r1
 8000c08:	d302      	bcc.n	8000c10 <__udivmoddi4+0xd0>
 8000c0a:	4282      	cmp	r2, r0
 8000c0c:	f200 80fa 	bhi.w	8000e04 <__udivmoddi4+0x2c4>
 8000c10:	1a84      	subs	r4, r0, r2
 8000c12:	eb61 0303 	sbc.w	r3, r1, r3
 8000c16:	2001      	movs	r0, #1
 8000c18:	4698      	mov	r8, r3
 8000c1a:	2e00      	cmp	r6, #0
 8000c1c:	d0e0      	beq.n	8000be0 <__udivmoddi4+0xa0>
 8000c1e:	e9c6 4800 	strd	r4, r8, [r6]
 8000c22:	e7dd      	b.n	8000be0 <__udivmoddi4+0xa0>
 8000c24:	b902      	cbnz	r2, 8000c28 <__udivmoddi4+0xe8>
 8000c26:	deff      	udf	#255	; 0xff
 8000c28:	fab2 f282 	clz	r2, r2
 8000c2c:	2a00      	cmp	r2, #0
 8000c2e:	f040 808f 	bne.w	8000d50 <__udivmoddi4+0x210>
 8000c32:	1b49      	subs	r1, r1, r5
 8000c34:	ea4f 4e15 	mov.w	lr, r5, lsr #16
 8000c38:	fa1f f885 	uxth.w	r8, r5
 8000c3c:	2701      	movs	r7, #1
 8000c3e:	fbb1 fcfe 	udiv	ip, r1, lr
 8000c42:	0c23      	lsrs	r3, r4, #16
 8000c44:	fb0e 111c 	mls	r1, lr, ip, r1
 8000c48:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 8000c4c:	fb08 f10c 	mul.w	r1, r8, ip
 8000c50:	4299      	cmp	r1, r3
 8000c52:	d907      	bls.n	8000c64 <__udivmoddi4+0x124>
 8000c54:	18eb      	adds	r3, r5, r3
 8000c56:	f10c 30ff 	add.w	r0, ip, #4294967295
 8000c5a:	d202      	bcs.n	8000c62 <__udivmoddi4+0x122>
 8000c5c:	4299      	cmp	r1, r3
 8000c5e:	f200 80cd 	bhi.w	8000dfc <__udivmoddi4+0x2bc>
 8000c62:	4684      	mov	ip, r0
 8000c64:	1a59      	subs	r1, r3, r1
 8000c66:	b2a3      	uxth	r3, r4
 8000c68:	fbb1 f0fe 	udiv	r0, r1, lr
 8000c6c:	fb0e 1410 	mls	r4, lr, r0, r1
 8000c70:	ea43 4404 	orr.w	r4, r3, r4, lsl #16
 8000c74:	fb08 f800 	mul.w	r8, r8, r0
 8000c78:	45a0      	cmp	r8, r4
 8000c7a:	d907      	bls.n	8000c8c <__udivmoddi4+0x14c>
 8000c7c:	192c      	adds	r4, r5, r4
 8000c7e:	f100 33ff 	add.w	r3, r0, #4294967295
 8000c82:	d202      	bcs.n	8000c8a <__udivmoddi4+0x14a>
 8000c84:	45a0      	cmp	r8, r4
 8000c86:	f200 80b6 	bhi.w	8000df6 <__udivmoddi4+0x2b6>
 8000c8a:	4618      	mov	r0, r3
 8000c8c:	eba4 0408 	sub.w	r4, r4, r8
 8000c90:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
 8000c94:	e79f      	b.n	8000bd6 <__udivmoddi4+0x96>
 8000c96:	f1c7 0c20 	rsb	ip, r7, #32
 8000c9a:	40bb      	lsls	r3, r7
 8000c9c:	fa22 fe0c 	lsr.w	lr, r2, ip
 8000ca0:	ea4e 0e03 	orr.w	lr, lr, r3
 8000ca4:	fa01 f407 	lsl.w	r4, r1, r7
 8000ca8:	fa20 f50c 	lsr.w	r5, r0, ip
 8000cac:	fa21 f30c 	lsr.w	r3, r1, ip
 8000cb0:	ea4f 481e 	mov.w	r8, lr, lsr #16
 8000cb4:	4325      	orrs	r5, r4
 8000cb6:	fbb3 f9f8 	udiv	r9, r3, r8
 8000cba:	0c2c      	lsrs	r4, r5, #16
 8000cbc:	fb08 3319 	mls	r3, r8, r9, r3
 8000cc0:	fa1f fa8e 	uxth.w	sl, lr
 8000cc4:	ea44 4303 	orr.w	r3, r4, r3, lsl #16
 8000cc8:	fb09 f40a 	mul.w	r4, r9, sl
 8000ccc:	429c      	cmp	r4, r3
 8000cce:	fa02 f207 	lsl.w	r2, r2, r7
 8000cd2:	fa00 f107 	lsl.w	r1, r0, r7
 8000cd6:	d90b      	bls.n	8000cf0 <__udivmoddi4+0x1b0>
 8000cd8:	eb1e 0303 	adds.w	r3, lr, r3
 8000cdc:	f109 30ff 	add.w	r0, r9, #4294967295
 8000ce0:	f080 8087 	bcs.w	8000df2 <__udivmoddi4+0x2b2>
 8000ce4:	429c      	cmp	r4, r3
 8000ce6:	f240 8084 	bls.w	8000df2 <__udivmoddi4+0x2b2>
 8000cea:	f1a9 0902 	sub.w	r9, r9, #2
 8000cee:	4473      	add	r3, lr
 8000cf0:	1b1b      	subs	r3, r3, r4
 8000cf2:	b2ad      	uxth	r5, r5
 8000cf4:	fbb3 f0f8 	udiv	r0, r3, r8
 8000cf8:	fb08 3310 	mls	r3, r8, r0, r3
 8000cfc:	ea45 4403 	orr.w	r4, r5, r3, lsl #16
 8000d00:	fb00 fa0a 	mul.w	sl, r0, sl
 8000d04:	45a2      	cmp	sl, r4
 8000d06:	d908      	bls.n	8000d1a <__udivmoddi4+0x1da>
 8000d08:	eb1e 0404 	adds.w	r4, lr, r4
 8000d0c:	f100 33ff 	add.w	r3, r0, #4294967295
 8000d10:	d26b      	bcs.n	8000dea <__udivmoddi4+0x2aa>
 8000d12:	45a2      	cmp	sl, r4
 8000d14:	d969      	bls.n	8000dea <__udivmoddi4+0x2aa>
 8000d16:	3802      	subs	r0, #2
 8000d18:	4474      	add	r4, lr
 8000d1a:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
 8000d1e:	fba0 8902 	umull	r8, r9, r0, r2
 8000d22:	eba4 040a 	sub.w	r4, r4, sl
 8000d26:	454c      	cmp	r4, r9
 8000d28:	46c2      	mov	sl, r8
 8000d2a:	464b      	mov	r3, r9
 8000d2c:	d354      	bcc.n	8000dd8 <__udivmoddi4+0x298>
 8000d2e:	d051      	beq.n	8000dd4 <__udivmoddi4+0x294>
 8000d30:	2e00      	cmp	r6, #0
 8000d32:	d069      	beq.n	8000e08 <__udivmoddi4+0x2c8>
 8000d34:	ebb1 050a 	subs.w	r5, r1, sl
 8000d38:	eb64 0403 	sbc.w	r4, r4, r3
 8000d3c:	fa04 fc0c 	lsl.w	ip, r4, ip
 8000d40:	40fd      	lsrs	r5, r7
 8000d42:	40fc      	lsrs	r4, r7
 8000d44:	ea4c 0505 	orr.w	r5, ip, r5
 8000d48:	e9c6 5400 	strd	r5, r4, [r6]
 8000d4c:	2700      	movs	r7, #0
 8000d4e:	e747      	b.n	8000be0 <__udivmoddi4+0xa0>
 8000d50:	f1c2 0320 	rsb	r3, r2, #32
 8000d54:	fa20 f703 	lsr.w	r7, r0, r3
 8000d58:	4095      	lsls	r5, r2
 8000d5a:	fa01 f002 	lsl.w	r0, r1, r2
 8000d5e:	fa21 f303 	lsr.w	r3, r1, r3
 8000d62:	ea4f 4e15 	mov.w	lr, r5, lsr #16
 8000d66:	4338      	orrs	r0, r7
 8000d68:	0c01      	lsrs	r1, r0, #16
 8000d6a:	fbb3 f7fe 	udiv	r7, r3, lr
 8000d6e:	fa1f f885 	uxth.w	r8, r5
 8000d72:	fb0e 3317 	mls	r3, lr, r7, r3
 8000d76:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 8000d7a:	fb07 f308 	mul.w	r3, r7, r8
 8000d7e:	428b      	cmp	r3, r1
 8000d80:	fa04 f402 	lsl.w	r4, r4, r2
 8000d84:	d907      	bls.n	8000d96 <__udivmoddi4+0x256>
 8000d86:	1869      	adds	r1, r5, r1
 8000d88:	f107 3cff 	add.w	ip, r7, #4294967295
 8000d8c:	d22f      	bcs.n	8000dee <__udivmoddi4+0x2ae>
 8000d8e:	428b      	cmp	r3, r1
 8000d90:	d92d      	bls.n	8000dee <__udivmoddi4+0x2ae>
 8000d92:	3f02      	subs	r7, #2
 8000d94:	4429      	add	r1, r5
 8000d96:	1acb      	subs	r3, r1, r3
 8000d98:	b281      	uxth	r1, r0
 8000d9a:	fbb3 f0fe 	udiv	r0, r3, lr
 8000d9e:	fb0e 3310 	mls	r3, lr, r0, r3
 8000da2:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 8000da6:	fb00 f308 	mul.w	r3, r0, r8
 8000daa:	428b      	cmp	r3, r1
 8000dac:	d907      	bls.n	8000dbe <__udivmoddi4+0x27e>
 8000dae:	1869      	adds	r1, r5, r1
 8000db0:	f100 3cff 	add.w	ip, r0, #4294967295
 8000db4:	d217      	bcs.n	8000de6 <__udivmoddi4+0x2a6>
 8000db6:	428b      	cmp	r3, r1
 8000db8:	d915      	bls.n	8000de6 <__udivmoddi4+0x2a6>
 8000dba:	3802      	subs	r0, #2
 8000dbc:	4429      	add	r1, r5
 8000dbe:	1ac9      	subs	r1, r1, r3
 8000dc0:	ea40 4707 	orr.w	r7, r0, r7, lsl #16
 8000dc4:	e73b      	b.n	8000c3e <__udivmoddi4+0xfe>
 8000dc6:	4637      	mov	r7, r6
 8000dc8:	4630      	mov	r0, r6
 8000dca:	e709      	b.n	8000be0 <__udivmoddi4+0xa0>
 8000dcc:	4607      	mov	r7, r0
 8000dce:	e6e7      	b.n	8000ba0 <__udivmoddi4+0x60>
 8000dd0:	4618      	mov	r0, r3
 8000dd2:	e6fb      	b.n	8000bcc <__udivmoddi4+0x8c>
 8000dd4:	4541      	cmp	r1, r8
 8000dd6:	d2ab      	bcs.n	8000d30 <__udivmoddi4+0x1f0>
 8000dd8:	ebb8 0a02 	subs.w	sl, r8, r2
 8000ddc:	eb69 020e 	sbc.w	r2, r9, lr
 8000de0:	3801      	subs	r0, #1
 8000de2:	4613      	mov	r3, r2
 8000de4:	e7a4      	b.n	8000d30 <__udivmoddi4+0x1f0>
 8000de6:	4660      	mov	r0, ip
 8000de8:	e7e9      	b.n	8000dbe <__udivmoddi4+0x27e>
 8000dea:	4618      	mov	r0, r3
 8000dec:	e795      	b.n	8000d1a <__udivmoddi4+0x1da>
 8000dee:	4667      	mov	r7, ip
 8000df0:	e7d1      	b.n	8000d96 <__udivmoddi4+0x256>
 8000df2:	4681      	mov	r9, r0
 8000df4:	e77c      	b.n	8000cf0 <__udivmoddi4+0x1b0>
 8000df6:	3802      	subs	r0, #2
 8000df8:	442c      	add	r4, r5
 8000dfa:	e747      	b.n	8000c8c <__udivmoddi4+0x14c>
 8000dfc:	f1ac 0c02 	sub.w	ip, ip, #2
 8000e00:	442b      	add	r3, r5
 8000e02:	e72f      	b.n	8000c64 <__udivmoddi4+0x124>
 8000e04:	4638      	mov	r0, r7
 8000e06:	e708      	b.n	8000c1a <__udivmoddi4+0xda>
 8000e08:	4637      	mov	r7, r6
 8000e0a:	e6e9      	b.n	8000be0 <__udivmoddi4+0xa0>

08000e0c <__aeabi_idiv0>:
 8000e0c:	4770      	bx	lr
 8000e0e:	bf00      	nop

08000e10 <deg_to_rad>:
* Function Name  : deg_to_rad
* Description    : converts degrees to radians
* Return         : angle in radians
*******************************************************************************/
double deg_to_rad(double deg)
{
 8000e10:	b590      	push	{r4, r7, lr}
 8000e12:	b085      	sub	sp, #20
 8000e14:	af00      	add	r7, sp, #0
 8000e16:	ed87 0b00 	vstr	d0, [r7]
	double rad = deg*(M_PI/180);
 8000e1a:	a30b      	add	r3, pc, #44	; (adr r3, 8000e48 <deg_to_rad+0x38>)
 8000e1c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8000e20:	e9d7 0100 	ldrd	r0, r1, [r7]
 8000e24:	f7ff fb9c 	bl	8000560 <__aeabi_dmul>
 8000e28:	4603      	mov	r3, r0
 8000e2a:	460c      	mov	r4, r1
 8000e2c:	e9c7 3402 	strd	r3, r4, [r7, #8]
	return rad;
 8000e30:	e9d7 3402 	ldrd	r3, r4, [r7, #8]
 8000e34:	ec44 3b17 	vmov	d7, r3, r4
}
 8000e38:	eeb0 0a47 	vmov.f32	s0, s14
 8000e3c:	eef0 0a67 	vmov.f32	s1, s15
 8000e40:	3714      	adds	r7, #20
 8000e42:	46bd      	mov	sp, r7
 8000e44:	bd90      	pop	{r4, r7, pc}
 8000e46:	bf00      	nop
 8000e48:	a2529d39 	.word	0xa2529d39
 8000e4c:	3f91df46 	.word	0x3f91df46

08000e50 <rad_to_deg>:
* Function Name  : rad_to_deg
* Description    : converts radians to degrees
* Return         : angle in degrees
*******************************************************************************/
double rad_to_deg(double rad)
{
 8000e50:	b590      	push	{r4, r7, lr}
 8000e52:	b085      	sub	sp, #20
 8000e54:	af00      	add	r7, sp, #0
 8000e56:	ed87 0b00 	vstr	d0, [r7]
	double deg = rad*(180/M_PI);
 8000e5a:	a30b      	add	r3, pc, #44	; (adr r3, 8000e88 <rad_to_deg+0x38>)
 8000e5c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8000e60:	e9d7 0100 	ldrd	r0, r1, [r7]
 8000e64:	f7ff fb7c 	bl	8000560 <__aeabi_dmul>
 8000e68:	4603      	mov	r3, r0
 8000e6a:	460c      	mov	r4, r1
 8000e6c:	e9c7 3402 	strd	r3, r4, [r7, #8]
	return deg;
 8000e70:	e9d7 3402 	ldrd	r3, r4, [r7, #8]
 8000e74:	ec44 3b17 	vmov	d7, r3, r4
}
 8000e78:	eeb0 0a47 	vmov.f32	s0, s14
 8000e7c:	eef0 0a67 	vmov.f32	s1, s15
 8000e80:	3714      	adds	r7, #20
 8000e82:	46bd      	mov	sp, r7
 8000e84:	bd90      	pop	{r4, r7, pc}
 8000e86:	bf00      	nop
 8000e88:	1a63c1f8 	.word	0x1a63c1f8
 8000e8c:	404ca5dc 	.word	0x404ca5dc

08000e90 <leap_year_check>:
* Function Name  : leap_year_check
* Description    : checks if year is a leap year
* Return         : false: no leap year, true: leap year
*******************************************************************************/
int leap_year_check(int year)
{
 8000e90:	b480      	push	{r7}
 8000e92:	b083      	sub	sp, #12
 8000e94:	af00      	add	r7, sp, #0
 8000e96:	6078      	str	r0, [r7, #4]
	if((year % 4 == 0 && year % 100 != 0) || (year % 400 == 0))
 8000e98:	687b      	ldr	r3, [r7, #4]
 8000e9a:	f003 0303 	and.w	r3, r3, #3
 8000e9e:	2b00      	cmp	r3, #0
 8000ea0:	d10c      	bne.n	8000ebc <leap_year_check+0x2c>
 8000ea2:	687a      	ldr	r2, [r7, #4]
 8000ea4:	4b11      	ldr	r3, [pc, #68]	; (8000eec <leap_year_check+0x5c>)
 8000ea6:	fb83 1302 	smull	r1, r3, r3, r2
 8000eaa:	1159      	asrs	r1, r3, #5
 8000eac:	17d3      	asrs	r3, r2, #31
 8000eae:	1acb      	subs	r3, r1, r3
 8000eb0:	2164      	movs	r1, #100	; 0x64
 8000eb2:	fb01 f303 	mul.w	r3, r1, r3
 8000eb6:	1ad3      	subs	r3, r2, r3
 8000eb8:	2b00      	cmp	r3, #0
 8000eba:	d10d      	bne.n	8000ed8 <leap_year_check+0x48>
 8000ebc:	687a      	ldr	r2, [r7, #4]
 8000ebe:	4b0b      	ldr	r3, [pc, #44]	; (8000eec <leap_year_check+0x5c>)
 8000ec0:	fb83 1302 	smull	r1, r3, r3, r2
 8000ec4:	11d9      	asrs	r1, r3, #7
 8000ec6:	17d3      	asrs	r3, r2, #31
 8000ec8:	1acb      	subs	r3, r1, r3
 8000eca:	f44f 71c8 	mov.w	r1, #400	; 0x190
 8000ece:	fb01 f303 	mul.w	r3, r1, r3
 8000ed2:	1ad3      	subs	r3, r2, r3
 8000ed4:	2b00      	cmp	r3, #0
 8000ed6:	d101      	bne.n	8000edc <leap_year_check+0x4c>
	{
		return true;
 8000ed8:	2301      	movs	r3, #1
 8000eda:	e000      	b.n	8000ede <leap_year_check+0x4e>
	}
	return false;
 8000edc:	2300      	movs	r3, #0
}
 8000ede:	4618      	mov	r0, r3
 8000ee0:	370c      	adds	r7, #12
 8000ee2:	46bd      	mov	sp, r7
 8000ee4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000ee8:	4770      	bx	lr
 8000eea:	bf00      	nop
 8000eec:	51eb851f 	.word	0x51eb851f

08000ef0 <calc_day_of_year>:
* Description    : calculates the day of year
* Return         : day of year (1.1.. = 1, 2.1.. = 2,...)
* Source		 : https://overiq.com/c-examples/c-program-to-calculate-the-day-of-year-from-the-date/
*******************************************************************************/
int calc_day_of_year(int day, int mon, int year)
{
 8000ef0:	b580      	push	{r7, lr}
 8000ef2:	b088      	sub	sp, #32
 8000ef4:	af00      	add	r7, sp, #0
 8000ef6:	60f8      	str	r0, [r7, #12]
 8000ef8:	60b9      	str	r1, [r7, #8]
 8000efa:	607a      	str	r2, [r7, #4]
	int days_in_feb = 28;
 8000efc:	231c      	movs	r3, #28
 8000efe:	61fb      	str	r3, [r7, #28]
	int doy = day;   //day of year
 8000f00:	68fb      	ldr	r3, [r7, #12]
 8000f02:	61bb      	str	r3, [r7, #24]

	// check for leap year
	bool leap_year = leap_year_check(year);
 8000f04:	6878      	ldr	r0, [r7, #4]
 8000f06:	f7ff ffc3 	bl	8000e90 <leap_year_check>
 8000f0a:	4603      	mov	r3, r0
 8000f0c:	2b00      	cmp	r3, #0
 8000f0e:	bf14      	ite	ne
 8000f10:	2301      	movne	r3, #1
 8000f12:	2300      	moveq	r3, #0
 8000f14:	75fb      	strb	r3, [r7, #23]
	if(leap_year == true)
 8000f16:	7dfb      	ldrb	r3, [r7, #23]
 8000f18:	2b00      	cmp	r3, #0
 8000f1a:	d001      	beq.n	8000f20 <calc_day_of_year+0x30>
	{
	    days_in_feb = 29;
 8000f1c:	231d      	movs	r3, #29
 8000f1e:	61fb      	str	r3, [r7, #28]
	}

	switch(mon)
 8000f20:	68bb      	ldr	r3, [r7, #8]
 8000f22:	3b02      	subs	r3, #2
 8000f24:	2b0a      	cmp	r3, #10
 8000f26:	d85b      	bhi.n	8000fe0 <calc_day_of_year+0xf0>
 8000f28:	a201      	add	r2, pc, #4	; (adr r2, 8000f30 <calc_day_of_year+0x40>)
 8000f2a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 8000f2e:	bf00      	nop
 8000f30:	08000f5d 	.word	0x08000f5d
 8000f34:	08000f65 	.word	0x08000f65
 8000f38:	08000f71 	.word	0x08000f71
 8000f3c:	08000f7d 	.word	0x08000f7d
 8000f40:	08000f89 	.word	0x08000f89
 8000f44:	08000f95 	.word	0x08000f95
 8000f48:	08000fa1 	.word	0x08000fa1
 8000f4c:	08000fad 	.word	0x08000fad
 8000f50:	08000fb9 	.word	0x08000fb9
 8000f54:	08000fc5 	.word	0x08000fc5
 8000f58:	08000fd3 	.word	0x08000fd3
	{
		case 2:
			doy += 31;
 8000f5c:	69bb      	ldr	r3, [r7, #24]
 8000f5e:	331f      	adds	r3, #31
 8000f60:	61bb      	str	r3, [r7, #24]
			break;
 8000f62:	e03d      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 3:
			doy += 31+days_in_feb;
 8000f64:	69fb      	ldr	r3, [r7, #28]
 8000f66:	331f      	adds	r3, #31
 8000f68:	69ba      	ldr	r2, [r7, #24]
 8000f6a:	4413      	add	r3, r2
 8000f6c:	61bb      	str	r3, [r7, #24]
			break;
 8000f6e:	e037      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 4:
			doy += days_in_feb+62;
 8000f70:	69fb      	ldr	r3, [r7, #28]
 8000f72:	333e      	adds	r3, #62	; 0x3e
 8000f74:	69ba      	ldr	r2, [r7, #24]
 8000f76:	4413      	add	r3, r2
 8000f78:	61bb      	str	r3, [r7, #24]
			break;
 8000f7a:	e031      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 5:
			doy += days_in_feb+92;
 8000f7c:	69fb      	ldr	r3, [r7, #28]
 8000f7e:	335c      	adds	r3, #92	; 0x5c
 8000f80:	69ba      	ldr	r2, [r7, #24]
 8000f82:	4413      	add	r3, r2
 8000f84:	61bb      	str	r3, [r7, #24]
			break;
 8000f86:	e02b      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 6:
			doy += days_in_feb+123;
 8000f88:	69fb      	ldr	r3, [r7, #28]
 8000f8a:	337b      	adds	r3, #123	; 0x7b
 8000f8c:	69ba      	ldr	r2, [r7, #24]
 8000f8e:	4413      	add	r3, r2
 8000f90:	61bb      	str	r3, [r7, #24]
			break;
 8000f92:	e025      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 7:
			doy += days_in_feb+153;
 8000f94:	69fb      	ldr	r3, [r7, #28]
 8000f96:	3399      	adds	r3, #153	; 0x99
 8000f98:	69ba      	ldr	r2, [r7, #24]
 8000f9a:	4413      	add	r3, r2
 8000f9c:	61bb      	str	r3, [r7, #24]
			break;
 8000f9e:	e01f      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 8:
			doy += days_in_feb+184;
 8000fa0:	69fb      	ldr	r3, [r7, #28]
 8000fa2:	33b8      	adds	r3, #184	; 0xb8
 8000fa4:	69ba      	ldr	r2, [r7, #24]
 8000fa6:	4413      	add	r3, r2
 8000fa8:	61bb      	str	r3, [r7, #24]
			break;
 8000faa:	e019      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 9:
			doy += days_in_feb+215;
 8000fac:	69fb      	ldr	r3, [r7, #28]
 8000fae:	33d7      	adds	r3, #215	; 0xd7
 8000fb0:	69ba      	ldr	r2, [r7, #24]
 8000fb2:	4413      	add	r3, r2
 8000fb4:	61bb      	str	r3, [r7, #24]
			break;
 8000fb6:	e013      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 10:
			doy += days_in_feb+245;
 8000fb8:	69fb      	ldr	r3, [r7, #28]
 8000fba:	33f5      	adds	r3, #245	; 0xf5
 8000fbc:	69ba      	ldr	r2, [r7, #24]
 8000fbe:	4413      	add	r3, r2
 8000fc0:	61bb      	str	r3, [r7, #24]
			break;
 8000fc2:	e00d      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 11:
			doy += days_in_feb+276;
 8000fc4:	69fb      	ldr	r3, [r7, #28]
 8000fc6:	f503 738a 	add.w	r3, r3, #276	; 0x114
 8000fca:	69ba      	ldr	r2, [r7, #24]
 8000fcc:	4413      	add	r3, r2
 8000fce:	61bb      	str	r3, [r7, #24]
			break;
 8000fd0:	e006      	b.n	8000fe0 <calc_day_of_year+0xf0>
		case 12:
			doy += days_in_feb+306;
 8000fd2:	69fb      	ldr	r3, [r7, #28]
 8000fd4:	f503 7399 	add.w	r3, r3, #306	; 0x132
 8000fd8:	69ba      	ldr	r2, [r7, #24]
 8000fda:	4413      	add	r3, r2
 8000fdc:	61bb      	str	r3, [r7, #24]
			break;
 8000fde:	bf00      	nop
	}
	return doy;
 8000fe0:	69bb      	ldr	r3, [r7, #24]
}
 8000fe2:	4618      	mov	r0, r3
 8000fe4:	3720      	adds	r7, #32
 8000fe6:	46bd      	mov	sp, r7
 8000fe8:	bd80      	pop	{r7, pc}
 8000fea:	bf00      	nop
 8000fec:	0000      	movs	r0, r0
	...

08000ff0 <calc_sunrise_sunset>:
* Function Name  : calc_sunrise_sunset
* Description    : calculates the sunrise and sunset time of a specific date
* Source		 : General Solar Position Calculations, NOAA Global Monitoring Division
*******************************************************************************/
void calc_sunrise_sunset(int date, int month, int year, int sunrise_time[2], int sunset_time[2])
{
 8000ff0:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
 8000ff4:	b0a3      	sub	sp, #140	; 0x8c
 8000ff6:	af00      	add	r7, sp, #0
 8000ff8:	60f8      	str	r0, [r7, #12]
 8000ffa:	60b9      	str	r1, [r7, #8]
 8000ffc:	607a      	str	r2, [r7, #4]
 8000ffe:	603b      	str	r3, [r7, #0]
	double gamma = 0;
 8001000:	f04f 0300 	mov.w	r3, #0
 8001004:	f04f 0400 	mov.w	r4, #0
 8001008:	e9c7 3420 	strd	r3, r4, [r7, #128]	; 0x80
	bool leap_year;
	double eqtime = 0;
 800100c:	f04f 0300 	mov.w	r3, #0
 8001010:	f04f 0400 	mov.w	r4, #0
 8001014:	e9c7 341a 	strd	r3, r4, [r7, #104]	; 0x68
	double decl = 0;
 8001018:	f04f 0300 	mov.w	r3, #0
 800101c:	f04f 0400 	mov.w	r4, #0
 8001020:	e9c7 3418 	strd	r3, r4, [r7, #96]	; 0x60
	double decl_deg = 0;
 8001024:	f04f 0300 	mov.w	r3, #0
 8001028:	f04f 0400 	mov.w	r4, #0
 800102c:	e9c7 3416 	strd	r3, r4, [r7, #88]	; 0x58
	double zenith_sun = 0;
 8001030:	f04f 0300 	mov.w	r3, #0
 8001034:	f04f 0400 	mov.w	r4, #0
 8001038:	e9c7 3414 	strd	r3, r4, [r7, #80]	; 0x50
	double lat_nbg_rad = 0;
 800103c:	f04f 0300 	mov.w	r3, #0
 8001040:	f04f 0400 	mov.w	r4, #0
 8001044:	e9c7 3412 	strd	r3, r4, [r7, #72]	; 0x48
	double ha = 0;
 8001048:	f04f 0300 	mov.w	r3, #0
 800104c:	f04f 0400 	mov.w	r4, #0
 8001050:	e9c7 3410 	strd	r3, r4, [r7, #64]	; 0x40
	double sunrise = 0;
 8001054:	f04f 0300 	mov.w	r3, #0
 8001058:	f04f 0400 	mov.w	r4, #0
 800105c:	e9c7 340e 	strd	r3, r4, [r7, #56]	; 0x38
	double sunset = 0;
 8001060:	f04f 0300 	mov.w	r3, #0
 8001064:	f04f 0400 	mov.w	r4, #0
 8001068:	e9c7 340c 	strd	r3, r4, [r7, #48]	; 0x30
	double ha_deg = 0;
 800106c:	f04f 0300 	mov.w	r3, #0
 8001070:	f04f 0400 	mov.w	r4, #0
 8001074:	e9c7 340a 	strd	r3, r4, [r7, #40]	; 0x28
	int sunrise_h = 0;
 8001078:	2300      	movs	r3, #0
 800107a:	67fb      	str	r3, [r7, #124]	; 0x7c
	int sunset_h = 0;
 800107c:	2300      	movs	r3, #0
 800107e:	67bb      	str	r3, [r7, #120]	; 0x78
	double sunrise_min = 0;
 8001080:	f04f 0300 	mov.w	r3, #0
 8001084:	f04f 0400 	mov.w	r4, #0
 8001088:	e9c7 3408 	strd	r3, r4, [r7, #32]
	double sunset_min = 0;
 800108c:	f04f 0300 	mov.w	r3, #0
 8001090:	f04f 0400 	mov.w	r4, #0
 8001094:	e9c7 3406 	strd	r3, r4, [r7, #24]
	int int_sunrise_min = 0;
 8001098:	2300      	movs	r3, #0
 800109a:	677b      	str	r3, [r7, #116]	; 0x74
	int int_sunset_min = 0;
 800109c:	2300      	movs	r3, #0
 800109e:	673b      	str	r3, [r7, #112]	; 0x70

	//day of year calculation
	int day_of_year = calc_day_of_year(date, month, year);
 80010a0:	687a      	ldr	r2, [r7, #4]
 80010a2:	68b9      	ldr	r1, [r7, #8]
 80010a4:	68f8      	ldr	r0, [r7, #12]
 80010a6:	f7ff ff23 	bl	8000ef0 <calc_day_of_year>
 80010aa:	6178      	str	r0, [r7, #20]

	// fractional year (γ) in radians
    // check for leap year
	leap_year = leap_year_check(year);
 80010ac:	6878      	ldr	r0, [r7, #4]
 80010ae:	f7ff feef 	bl	8000e90 <leap_year_check>
 80010b2:	4603      	mov	r3, r0
 80010b4:	2b00      	cmp	r3, #0
 80010b6:	bf14      	ite	ne
 80010b8:	2301      	movne	r3, #1
 80010ba:	2300      	moveq	r3, #0
 80010bc:	74fb      	strb	r3, [r7, #19]
	if(leap_year == false)
 80010be:	7cfb      	ldrb	r3, [r7, #19]
 80010c0:	f083 0301 	eor.w	r3, r3, #1
 80010c4:	b2db      	uxtb	r3, r3
 80010c6:	2b00      	cmp	r3, #0
 80010c8:	d00f      	beq.n	80010ea <calc_sunrise_sunset+0xfa>
	{
		//The back part of the formula was omitted, because there is no difference in the result
		gamma = ((2 * M_PI)/365)*(day_of_year - 1);
 80010ca:	697b      	ldr	r3, [r7, #20]
 80010cc:	3b01      	subs	r3, #1
 80010ce:	4618      	mov	r0, r3
 80010d0:	f7ff f9dc 	bl	800048c <__aeabi_i2d>
 80010d4:	f20f 537c 	addw	r3, pc, #1404	; 0x57c
 80010d8:	e9d3 2300 	ldrd	r2, r3, [r3]
 80010dc:	f7ff fa40 	bl	8000560 <__aeabi_dmul>
 80010e0:	4603      	mov	r3, r0
 80010e2:	460c      	mov	r4, r1
 80010e4:	e9c7 3420 	strd	r3, r4, [r7, #128]	; 0x80
 80010e8:	e00e      	b.n	8001108 <calc_sunrise_sunset+0x118>
	} else {
		//The back part of the formula was omitted, because there is no difference in the result
		gamma = ((2 * M_PI)/366)*(day_of_year - 1);
 80010ea:	697b      	ldr	r3, [r7, #20]
 80010ec:	3b01      	subs	r3, #1
 80010ee:	4618      	mov	r0, r3
 80010f0:	f7ff f9cc 	bl	800048c <__aeabi_i2d>
 80010f4:	f20f 5364 	addw	r3, pc, #1380	; 0x564
 80010f8:	e9d3 2300 	ldrd	r2, r3, [r3]
 80010fc:	f7ff fa30 	bl	8000560 <__aeabi_dmul>
 8001100:	4603      	mov	r3, r0
 8001102:	460c      	mov	r4, r1
 8001104:	e9c7 3420 	strd	r3, r4, [r7, #128]	; 0x80
	}

	//Equation of time in minutes
	eqtime = 229.18*(0.000075 + 0.001868*cos(gamma) - 0.032077*sin(gamma) - 0.014615*cos(2*gamma) - 0.040849*sin(2*gamma));
 8001108:	ed97 0b20 	vldr	d0, [r7, #128]	; 0x80
 800110c:	f003 f968 	bl	80043e0 <cos>
 8001110:	ec51 0b10 	vmov	r0, r1, d0
 8001114:	f20f 534c 	addw	r3, pc, #1356	; 0x54c
 8001118:	e9d3 2300 	ldrd	r2, r3, [r3]
 800111c:	f7ff fa20 	bl	8000560 <__aeabi_dmul>
 8001120:	4603      	mov	r3, r0
 8001122:	460c      	mov	r4, r1
 8001124:	4618      	mov	r0, r3
 8001126:	4621      	mov	r1, r4
 8001128:	f20f 5340 	addw	r3, pc, #1344	; 0x540
 800112c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001130:	f7ff f860 	bl	80001f4 <__adddf3>
 8001134:	4603      	mov	r3, r0
 8001136:	460c      	mov	r4, r1
 8001138:	4625      	mov	r5, r4
 800113a:	461c      	mov	r4, r3
 800113c:	ed97 0b20 	vldr	d0, [r7, #128]	; 0x80
 8001140:	f003 fa16 	bl	8004570 <sin>
 8001144:	ec51 0b10 	vmov	r0, r1, d0
 8001148:	f20f 5328 	addw	r3, pc, #1320	; 0x528
 800114c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001150:	f7ff fa06 	bl	8000560 <__aeabi_dmul>
 8001154:	4602      	mov	r2, r0
 8001156:	460b      	mov	r3, r1
 8001158:	4620      	mov	r0, r4
 800115a:	4629      	mov	r1, r5
 800115c:	f7ff f848 	bl	80001f0 <__aeabi_dsub>
 8001160:	4603      	mov	r3, r0
 8001162:	460c      	mov	r4, r1
 8001164:	4625      	mov	r5, r4
 8001166:	461c      	mov	r4, r3
 8001168:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 800116c:	4602      	mov	r2, r0
 800116e:	460b      	mov	r3, r1
 8001170:	f7ff f840 	bl	80001f4 <__adddf3>
 8001174:	4602      	mov	r2, r0
 8001176:	460b      	mov	r3, r1
 8001178:	ec43 2b17 	vmov	d7, r2, r3
 800117c:	eeb0 0a47 	vmov.f32	s0, s14
 8001180:	eef0 0a67 	vmov.f32	s1, s15
 8001184:	f003 f92c 	bl	80043e0 <cos>
 8001188:	ec51 0b10 	vmov	r0, r1, d0
 800118c:	f20f 43ec 	addw	r3, pc, #1260	; 0x4ec
 8001190:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001194:	f7ff f9e4 	bl	8000560 <__aeabi_dmul>
 8001198:	4602      	mov	r2, r0
 800119a:	460b      	mov	r3, r1
 800119c:	4620      	mov	r0, r4
 800119e:	4629      	mov	r1, r5
 80011a0:	f7ff f826 	bl	80001f0 <__aeabi_dsub>
 80011a4:	4603      	mov	r3, r0
 80011a6:	460c      	mov	r4, r1
 80011a8:	4625      	mov	r5, r4
 80011aa:	461c      	mov	r4, r3
 80011ac:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 80011b0:	4602      	mov	r2, r0
 80011b2:	460b      	mov	r3, r1
 80011b4:	f7ff f81e 	bl	80001f4 <__adddf3>
 80011b8:	4602      	mov	r2, r0
 80011ba:	460b      	mov	r3, r1
 80011bc:	ec43 2b17 	vmov	d7, r2, r3
 80011c0:	eeb0 0a47 	vmov.f32	s0, s14
 80011c4:	eef0 0a67 	vmov.f32	s1, s15
 80011c8:	f003 f9d2 	bl	8004570 <sin>
 80011cc:	ec51 0b10 	vmov	r0, r1, d0
 80011d0:	f20f 43b0 	addw	r3, pc, #1200	; 0x4b0
 80011d4:	e9d3 2300 	ldrd	r2, r3, [r3]
 80011d8:	f7ff f9c2 	bl	8000560 <__aeabi_dmul>
 80011dc:	4602      	mov	r2, r0
 80011de:	460b      	mov	r3, r1
 80011e0:	4620      	mov	r0, r4
 80011e2:	4629      	mov	r1, r5
 80011e4:	f7ff f804 	bl	80001f0 <__aeabi_dsub>
 80011e8:	4603      	mov	r3, r0
 80011ea:	460c      	mov	r4, r1
 80011ec:	4618      	mov	r0, r3
 80011ee:	4621      	mov	r1, r4
 80011f0:	f20f 4398 	addw	r3, pc, #1176	; 0x498
 80011f4:	e9d3 2300 	ldrd	r2, r3, [r3]
 80011f8:	f7ff f9b2 	bl	8000560 <__aeabi_dmul>
 80011fc:	4603      	mov	r3, r0
 80011fe:	460c      	mov	r4, r1
 8001200:	e9c7 341a 	strd	r3, r4, [r7, #104]	; 0x68

	//Solar declination angle in radians
	decl = 0.006918 - 0.399912*cos(gamma) + 0.070257*sin(gamma) - 0.006758*cos(2*gamma) + 0.000907*sin(2*gamma) - 0.002697*cos(3*gamma) + 0.00148*sin(3*gamma);
 8001204:	ed97 0b20 	vldr	d0, [r7, #128]	; 0x80
 8001208:	f003 f8ea 	bl	80043e0 <cos>
 800120c:	ec51 0b10 	vmov	r0, r1, d0
 8001210:	f20f 4380 	addw	r3, pc, #1152	; 0x480
 8001214:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001218:	f7ff f9a2 	bl	8000560 <__aeabi_dmul>
 800121c:	4603      	mov	r3, r0
 800121e:	460c      	mov	r4, r1
 8001220:	461a      	mov	r2, r3
 8001222:	4623      	mov	r3, r4
 8001224:	f20f 4174 	addw	r1, pc, #1140	; 0x474
 8001228:	e9d1 0100 	ldrd	r0, r1, [r1]
 800122c:	f7fe ffe0 	bl	80001f0 <__aeabi_dsub>
 8001230:	4603      	mov	r3, r0
 8001232:	460c      	mov	r4, r1
 8001234:	4625      	mov	r5, r4
 8001236:	461c      	mov	r4, r3
 8001238:	ed97 0b20 	vldr	d0, [r7, #128]	; 0x80
 800123c:	f003 f998 	bl	8004570 <sin>
 8001240:	ec51 0b10 	vmov	r0, r1, d0
 8001244:	f20f 435c 	addw	r3, pc, #1116	; 0x45c
 8001248:	e9d3 2300 	ldrd	r2, r3, [r3]
 800124c:	f7ff f988 	bl	8000560 <__aeabi_dmul>
 8001250:	4602      	mov	r2, r0
 8001252:	460b      	mov	r3, r1
 8001254:	4620      	mov	r0, r4
 8001256:	4629      	mov	r1, r5
 8001258:	f7fe ffcc 	bl	80001f4 <__adddf3>
 800125c:	4603      	mov	r3, r0
 800125e:	460c      	mov	r4, r1
 8001260:	4625      	mov	r5, r4
 8001262:	461c      	mov	r4, r3
 8001264:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 8001268:	4602      	mov	r2, r0
 800126a:	460b      	mov	r3, r1
 800126c:	f7fe ffc2 	bl	80001f4 <__adddf3>
 8001270:	4602      	mov	r2, r0
 8001272:	460b      	mov	r3, r1
 8001274:	ec43 2b17 	vmov	d7, r2, r3
 8001278:	eeb0 0a47 	vmov.f32	s0, s14
 800127c:	eef0 0a67 	vmov.f32	s1, s15
 8001280:	f003 f8ae 	bl	80043e0 <cos>
 8001284:	ec51 0b10 	vmov	r0, r1, d0
 8001288:	f20f 4320 	addw	r3, pc, #1056	; 0x420
 800128c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001290:	f7ff f966 	bl	8000560 <__aeabi_dmul>
 8001294:	4602      	mov	r2, r0
 8001296:	460b      	mov	r3, r1
 8001298:	4620      	mov	r0, r4
 800129a:	4629      	mov	r1, r5
 800129c:	f7fe ffa8 	bl	80001f0 <__aeabi_dsub>
 80012a0:	4603      	mov	r3, r0
 80012a2:	460c      	mov	r4, r1
 80012a4:	4625      	mov	r5, r4
 80012a6:	461c      	mov	r4, r3
 80012a8:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 80012ac:	4602      	mov	r2, r0
 80012ae:	460b      	mov	r3, r1
 80012b0:	f7fe ffa0 	bl	80001f4 <__adddf3>
 80012b4:	4602      	mov	r2, r0
 80012b6:	460b      	mov	r3, r1
 80012b8:	ec43 2b17 	vmov	d7, r2, r3
 80012bc:	eeb0 0a47 	vmov.f32	s0, s14
 80012c0:	eef0 0a67 	vmov.f32	s1, s15
 80012c4:	f003 f954 	bl	8004570 <sin>
 80012c8:	ec51 0b10 	vmov	r0, r1, d0
 80012cc:	a3f9      	add	r3, pc, #996	; (adr r3, 80016b4 <calc_sunrise_sunset+0x6c4>)
 80012ce:	e9d3 2300 	ldrd	r2, r3, [r3]
 80012d2:	f7ff f945 	bl	8000560 <__aeabi_dmul>
 80012d6:	4602      	mov	r2, r0
 80012d8:	460b      	mov	r3, r1
 80012da:	4620      	mov	r0, r4
 80012dc:	4629      	mov	r1, r5
 80012de:	f7fe ff89 	bl	80001f4 <__adddf3>
 80012e2:	4603      	mov	r3, r0
 80012e4:	460c      	mov	r4, r1
 80012e6:	4625      	mov	r5, r4
 80012e8:	461c      	mov	r4, r3
 80012ea:	f04f 0200 	mov.w	r2, #0
 80012ee:	4bd0      	ldr	r3, [pc, #832]	; (8001630 <calc_sunrise_sunset+0x640>)
 80012f0:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 80012f4:	f7ff f934 	bl	8000560 <__aeabi_dmul>
 80012f8:	4602      	mov	r2, r0
 80012fa:	460b      	mov	r3, r1
 80012fc:	ec43 2b17 	vmov	d7, r2, r3
 8001300:	eeb0 0a47 	vmov.f32	s0, s14
 8001304:	eef0 0a67 	vmov.f32	s1, s15
 8001308:	f003 f86a 	bl	80043e0 <cos>
 800130c:	ec51 0b10 	vmov	r0, r1, d0
 8001310:	a3c1      	add	r3, pc, #772	; (adr r3, 8001618 <calc_sunrise_sunset+0x628>)
 8001312:	e9d3 2300 	ldrd	r2, r3, [r3]
 8001316:	f7ff f923 	bl	8000560 <__aeabi_dmul>
 800131a:	4602      	mov	r2, r0
 800131c:	460b      	mov	r3, r1
 800131e:	4620      	mov	r0, r4
 8001320:	4629      	mov	r1, r5
 8001322:	f7fe ff65 	bl	80001f0 <__aeabi_dsub>
 8001326:	4603      	mov	r3, r0
 8001328:	460c      	mov	r4, r1
 800132a:	4625      	mov	r5, r4
 800132c:	461c      	mov	r4, r3
 800132e:	f04f 0200 	mov.w	r2, #0
 8001332:	4bbf      	ldr	r3, [pc, #764]	; (8001630 <calc_sunrise_sunset+0x640>)
 8001334:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 8001338:	f7ff f912 	bl	8000560 <__aeabi_dmul>
 800133c:	4602      	mov	r2, r0
 800133e:	460b      	mov	r3, r1
 8001340:	ec43 2b17 	vmov	d7, r2, r3
 8001344:	eeb0 0a47 	vmov.f32	s0, s14
 8001348:	eef0 0a67 	vmov.f32	s1, s15
 800134c:	f003 f910 	bl	8004570 <sin>
 8001350:	ec51 0b10 	vmov	r0, r1, d0
 8001354:	a3b2      	add	r3, pc, #712	; (adr r3, 8001620 <calc_sunrise_sunset+0x630>)
 8001356:	e9d3 2300 	ldrd	r2, r3, [r3]
 800135a:	f7ff f901 	bl	8000560 <__aeabi_dmul>
 800135e:	4602      	mov	r2, r0
 8001360:	460b      	mov	r3, r1
 8001362:	4620      	mov	r0, r4
 8001364:	4629      	mov	r1, r5
 8001366:	f7fe ff45 	bl	80001f4 <__adddf3>
 800136a:	4603      	mov	r3, r0
 800136c:	460c      	mov	r4, r1
 800136e:	e9c7 3418 	strd	r3, r4, [r7, #96]	; 0x60

	//Solar declination angle in degrees
	decl_deg = rad_to_deg(decl);
 8001372:	ed97 0b18 	vldr	d0, [r7, #96]	; 0x60
 8001376:	f7ff fd6b 	bl	8000e50 <rad_to_deg>
 800137a:	ed87 0b16 	vstr	d0, [r7, #88]	; 0x58

	//Hour angle in degrees, positive number corresponds to sunrise, negative to sunset
	//special case of sunrise or sunset, the zenith is set to 90.833Deg
	zenith_sun = deg_to_rad(90.833);
 800137e:	ed9f 0baa 	vldr	d0, [pc, #680]	; 8001628 <calc_sunrise_sunset+0x638>
 8001382:	f7ff fd45 	bl	8000e10 <deg_to_rad>
 8001386:	ed87 0b14 	vstr	d0, [r7, #80]	; 0x50
	//Latitude of Nuernberg in rad
	lat_nbg_rad = deg_to_rad(latitude_nbg);
 800138a:	4baa      	ldr	r3, [pc, #680]	; (8001634 <calc_sunrise_sunset+0x644>)
 800138c:	681b      	ldr	r3, [r3, #0]
 800138e:	4618      	mov	r0, r3
 8001390:	f7ff f87c 	bl	800048c <__aeabi_i2d>
 8001394:	4603      	mov	r3, r0
 8001396:	460c      	mov	r4, r1
 8001398:	ec44 3b10 	vmov	d0, r3, r4
 800139c:	f7ff fd38 	bl	8000e10 <deg_to_rad>
 80013a0:	ed87 0b12 	vstr	d0, [r7, #72]	; 0x48
	ha = acos((cos(zenith_sun)/(cos(lat_nbg_rad)*cos(decl)))-(tan(lat_nbg_rad)*tan(decl)));
 80013a4:	ed97 0b14 	vldr	d0, [r7, #80]	; 0x50
 80013a8:	f003 f81a 	bl	80043e0 <cos>
 80013ac:	ec56 5b10 	vmov	r5, r6, d0
 80013b0:	ed97 0b12 	vldr	d0, [r7, #72]	; 0x48
 80013b4:	f003 f814 	bl	80043e0 <cos>
 80013b8:	ec59 8b10 	vmov	r8, r9, d0
 80013bc:	ed97 0b18 	vldr	d0, [r7, #96]	; 0x60
 80013c0:	f003 f80e 	bl	80043e0 <cos>
 80013c4:	ec54 3b10 	vmov	r3, r4, d0
 80013c8:	461a      	mov	r2, r3
 80013ca:	4623      	mov	r3, r4
 80013cc:	4640      	mov	r0, r8
 80013ce:	4649      	mov	r1, r9
 80013d0:	f7ff f8c6 	bl	8000560 <__aeabi_dmul>
 80013d4:	4603      	mov	r3, r0
 80013d6:	460c      	mov	r4, r1
 80013d8:	461a      	mov	r2, r3
 80013da:	4623      	mov	r3, r4
 80013dc:	4628      	mov	r0, r5
 80013de:	4631      	mov	r1, r6
 80013e0:	f7ff f9e8 	bl	80007b4 <__aeabi_ddiv>
 80013e4:	4603      	mov	r3, r0
 80013e6:	460c      	mov	r4, r1
 80013e8:	4625      	mov	r5, r4
 80013ea:	461c      	mov	r4, r3
 80013ec:	ed97 0b12 	vldr	d0, [r7, #72]	; 0x48
 80013f0:	f003 f906 	bl	8004600 <tan>
 80013f4:	ec59 8b10 	vmov	r8, r9, d0
 80013f8:	ed97 0b18 	vldr	d0, [r7, #96]	; 0x60
 80013fc:	f003 f900 	bl	8004600 <tan>
 8001400:	ec53 2b10 	vmov	r2, r3, d0
 8001404:	4640      	mov	r0, r8
 8001406:	4649      	mov	r1, r9
 8001408:	f7ff f8aa 	bl	8000560 <__aeabi_dmul>
 800140c:	4602      	mov	r2, r0
 800140e:	460b      	mov	r3, r1
 8001410:	4620      	mov	r0, r4
 8001412:	4629      	mov	r1, r5
 8001414:	f7fe feec 	bl	80001f0 <__aeabi_dsub>
 8001418:	4603      	mov	r3, r0
 800141a:	460c      	mov	r4, r1
 800141c:	ec44 3b17 	vmov	d7, r3, r4
 8001420:	eeb0 0a47 	vmov.f32	s0, s14
 8001424:	eef0 0a67 	vmov.f32	s1, s15
 8001428:	f003 f91a 	bl	8004660 <acos>
 800142c:	ed87 0b10 	vstr	d0, [r7, #64]	; 0x40
	ha_deg = rad_to_deg(ha);
 8001430:	ed97 0b10 	vldr	d0, [r7, #64]	; 0x40
 8001434:	f7ff fd0c 	bl	8000e50 <rad_to_deg>
 8001438:	ed87 0b0a 	vstr	d0, [r7, #40]	; 0x28

	//UTC time of sunrise (or sunset) in minutes
	sunrise = (720-4*(longitude_nbg+ha_deg)-eqtime);
 800143c:	4b7e      	ldr	r3, [pc, #504]	; (8001638 <calc_sunrise_sunset+0x648>)
 800143e:	681b      	ldr	r3, [r3, #0]
 8001440:	4618      	mov	r0, r3
 8001442:	f7ff f823 	bl	800048c <__aeabi_i2d>
 8001446:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
 800144a:	f7fe fed3 	bl	80001f4 <__adddf3>
 800144e:	4603      	mov	r3, r0
 8001450:	460c      	mov	r4, r1
 8001452:	4618      	mov	r0, r3
 8001454:	4621      	mov	r1, r4
 8001456:	f04f 0200 	mov.w	r2, #0
 800145a:	4b78      	ldr	r3, [pc, #480]	; (800163c <calc_sunrise_sunset+0x64c>)
 800145c:	f7ff f880 	bl	8000560 <__aeabi_dmul>
 8001460:	4603      	mov	r3, r0
 8001462:	460c      	mov	r4, r1
 8001464:	461a      	mov	r2, r3
 8001466:	4623      	mov	r3, r4
 8001468:	f04f 0000 	mov.w	r0, #0
 800146c:	4974      	ldr	r1, [pc, #464]	; (8001640 <calc_sunrise_sunset+0x650>)
 800146e:	f7fe febf 	bl	80001f0 <__aeabi_dsub>
 8001472:	4603      	mov	r3, r0
 8001474:	460c      	mov	r4, r1
 8001476:	4618      	mov	r0, r3
 8001478:	4621      	mov	r1, r4
 800147a:	e9d7 231a 	ldrd	r2, r3, [r7, #104]	; 0x68
 800147e:	f7fe feb7 	bl	80001f0 <__aeabi_dsub>
 8001482:	4603      	mov	r3, r0
 8001484:	460c      	mov	r4, r1
 8001486:	e9c7 340e 	strd	r3, r4, [r7, #56]	; 0x38
	sunset = 720-4*(longitude_nbg-ha_deg)-eqtime;
 800148a:	4b6b      	ldr	r3, [pc, #428]	; (8001638 <calc_sunrise_sunset+0x648>)
 800148c:	681b      	ldr	r3, [r3, #0]
 800148e:	4618      	mov	r0, r3
 8001490:	f7fe fffc 	bl	800048c <__aeabi_i2d>
 8001494:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
 8001498:	f7fe feaa 	bl	80001f0 <__aeabi_dsub>
 800149c:	4603      	mov	r3, r0
 800149e:	460c      	mov	r4, r1
 80014a0:	4618      	mov	r0, r3
 80014a2:	4621      	mov	r1, r4
 80014a4:	f04f 0200 	mov.w	r2, #0
 80014a8:	4b64      	ldr	r3, [pc, #400]	; (800163c <calc_sunrise_sunset+0x64c>)
 80014aa:	f7ff f859 	bl	8000560 <__aeabi_dmul>
 80014ae:	4603      	mov	r3, r0
 80014b0:	460c      	mov	r4, r1
 80014b2:	461a      	mov	r2, r3
 80014b4:	4623      	mov	r3, r4
 80014b6:	f04f 0000 	mov.w	r0, #0
 80014ba:	4961      	ldr	r1, [pc, #388]	; (8001640 <calc_sunrise_sunset+0x650>)
 80014bc:	f7fe fe98 	bl	80001f0 <__aeabi_dsub>
 80014c0:	4603      	mov	r3, r0
 80014c2:	460c      	mov	r4, r1
 80014c4:	4618      	mov	r0, r3
 80014c6:	4621      	mov	r1, r4
 80014c8:	e9d7 231a 	ldrd	r2, r3, [r7, #104]	; 0x68
 80014cc:	f7fe fe90 	bl	80001f0 <__aeabi_dsub>
 80014d0:	4603      	mov	r3, r0
 80014d2:	460c      	mov	r4, r1
 80014d4:	e9c7 340c 	strd	r3, r4, [r7, #48]	; 0x30

	//Convert sunrise (or sunset) UTC time in hours
	sunrise = sunrise/60;
 80014d8:	f04f 0200 	mov.w	r2, #0
 80014dc:	4b59      	ldr	r3, [pc, #356]	; (8001644 <calc_sunrise_sunset+0x654>)
 80014de:	e9d7 010e 	ldrd	r0, r1, [r7, #56]	; 0x38
 80014e2:	f7ff f967 	bl	80007b4 <__aeabi_ddiv>
 80014e6:	4603      	mov	r3, r0
 80014e8:	460c      	mov	r4, r1
 80014ea:	e9c7 340e 	strd	r3, r4, [r7, #56]	; 0x38
	sunset = sunset/60;
 80014ee:	f04f 0200 	mov.w	r2, #0
 80014f2:	4b54      	ldr	r3, [pc, #336]	; (8001644 <calc_sunrise_sunset+0x654>)
 80014f4:	e9d7 010c 	ldrd	r0, r1, [r7, #48]	; 0x30
 80014f8:	f7ff f95c 	bl	80007b4 <__aeabi_ddiv>
 80014fc:	4603      	mov	r3, r0
 80014fe:	460c      	mov	r4, r1
 8001500:	e9c7 340c 	strd	r3, r4, [r7, #48]	; 0x30

	//Seperate hours and minutes
	sunrise_h = floor(sunrise);
 8001504:	ed97 0b0e 	vldr	d0, [r7, #56]	; 0x38
 8001508:	f002 ffae 	bl	8004468 <floor>
 800150c:	ec54 3b10 	vmov	r3, r4, d0
 8001510:	4618      	mov	r0, r3
 8001512:	4621      	mov	r1, r4
 8001514:	f7ff fad4 	bl	8000ac0 <__aeabi_d2iz>
 8001518:	4603      	mov	r3, r0
 800151a:	67fb      	str	r3, [r7, #124]	; 0x7c
	sunrise_min = sunrise - sunrise_h;
 800151c:	6ff8      	ldr	r0, [r7, #124]	; 0x7c
 800151e:	f7fe ffb5 	bl	800048c <__aeabi_i2d>
 8001522:	4603      	mov	r3, r0
 8001524:	460c      	mov	r4, r1
 8001526:	461a      	mov	r2, r3
 8001528:	4623      	mov	r3, r4
 800152a:	e9d7 010e 	ldrd	r0, r1, [r7, #56]	; 0x38
 800152e:	f7fe fe5f 	bl	80001f0 <__aeabi_dsub>
 8001532:	4603      	mov	r3, r0
 8001534:	460c      	mov	r4, r1
 8001536:	e9c7 3408 	strd	r3, r4, [r7, #32]
	//Cut off after two decimal places
	int_sunrise_min = floor(sunrise_min * 100.0);
 800153a:	f04f 0200 	mov.w	r2, #0
 800153e:	4b42      	ldr	r3, [pc, #264]	; (8001648 <calc_sunrise_sunset+0x658>)
 8001540:	e9d7 0108 	ldrd	r0, r1, [r7, #32]
 8001544:	f7ff f80c 	bl	8000560 <__aeabi_dmul>
 8001548:	4603      	mov	r3, r0
 800154a:	460c      	mov	r4, r1
 800154c:	ec44 3b17 	vmov	d7, r3, r4
 8001550:	eeb0 0a47 	vmov.f32	s0, s14
 8001554:	eef0 0a67 	vmov.f32	s1, s15
 8001558:	f002 ff86 	bl	8004468 <floor>
 800155c:	ec54 3b10 	vmov	r3, r4, d0
 8001560:	4618      	mov	r0, r3
 8001562:	4621      	mov	r1, r4
 8001564:	f7ff faac 	bl	8000ac0 <__aeabi_d2iz>
 8001568:	4603      	mov	r3, r0
 800156a:	677b      	str	r3, [r7, #116]	; 0x74
	if (int_sunrise_min >= 60)
 800156c:	6f7b      	ldr	r3, [r7, #116]	; 0x74
 800156e:	2b3b      	cmp	r3, #59	; 0x3b
 8001570:	dd05      	ble.n	800157e <calc_sunrise_sunset+0x58e>
	{
		sunrise_h = sunrise_h + 1;
 8001572:	6ffb      	ldr	r3, [r7, #124]	; 0x7c
 8001574:	3301      	adds	r3, #1
 8001576:	67fb      	str	r3, [r7, #124]	; 0x7c
		int_sunrise_min = int_sunrise_min - 60;
 8001578:	6f7b      	ldr	r3, [r7, #116]	; 0x74
 800157a:	3b3c      	subs	r3, #60	; 0x3c
 800157c:	677b      	str	r3, [r7, #116]	; 0x74
	}
	sunset_h = floor(sunset);
 800157e:	ed97 0b0c 	vldr	d0, [r7, #48]	; 0x30
 8001582:	f002 ff71 	bl	8004468 <floor>
 8001586:	ec54 3b10 	vmov	r3, r4, d0
 800158a:	4618      	mov	r0, r3
 800158c:	4621      	mov	r1, r4
 800158e:	f7ff fa97 	bl	8000ac0 <__aeabi_d2iz>
 8001592:	4603      	mov	r3, r0
 8001594:	67bb      	str	r3, [r7, #120]	; 0x78
	sunset_min = sunset - sunset_h;
 8001596:	6fb8      	ldr	r0, [r7, #120]	; 0x78
 8001598:	f7fe ff78 	bl	800048c <__aeabi_i2d>
 800159c:	4603      	mov	r3, r0
 800159e:	460c      	mov	r4, r1
 80015a0:	461a      	mov	r2, r3
 80015a2:	4623      	mov	r3, r4
 80015a4:	e9d7 010c 	ldrd	r0, r1, [r7, #48]	; 0x30
 80015a8:	f7fe fe22 	bl	80001f0 <__aeabi_dsub>
 80015ac:	4603      	mov	r3, r0
 80015ae:	460c      	mov	r4, r1
 80015b0:	e9c7 3406 	strd	r3, r4, [r7, #24]
	//Cut off after two decimal places
	int_sunset_min = floor(sunset_min * 100.0);
 80015b4:	f04f 0200 	mov.w	r2, #0
 80015b8:	4b23      	ldr	r3, [pc, #140]	; (8001648 <calc_sunrise_sunset+0x658>)
 80015ba:	e9d7 0106 	ldrd	r0, r1, [r7, #24]
 80015be:	f7fe ffcf 	bl	8000560 <__aeabi_dmul>
 80015c2:	4603      	mov	r3, r0
 80015c4:	460c      	mov	r4, r1
 80015c6:	ec44 3b17 	vmov	d7, r3, r4
 80015ca:	eeb0 0a47 	vmov.f32	s0, s14
 80015ce:	eef0 0a67 	vmov.f32	s1, s15
 80015d2:	f002 ff49 	bl	8004468 <floor>
 80015d6:	ec54 3b10 	vmov	r3, r4, d0
 80015da:	4618      	mov	r0, r3
 80015dc:	4621      	mov	r1, r4
 80015de:	f7ff fa6f 	bl	8000ac0 <__aeabi_d2iz>
 80015e2:	4603      	mov	r3, r0
 80015e4:	673b      	str	r3, [r7, #112]	; 0x70
	if (int_sunset_min >= 60)
 80015e6:	6f3b      	ldr	r3, [r7, #112]	; 0x70
 80015e8:	2b3b      	cmp	r3, #59	; 0x3b
 80015ea:	dd05      	ble.n	80015f8 <calc_sunrise_sunset+0x608>
	{
		sunset_h = sunset_h + 1;
 80015ec:	6fbb      	ldr	r3, [r7, #120]	; 0x78
 80015ee:	3301      	adds	r3, #1
 80015f0:	67bb      	str	r3, [r7, #120]	; 0x78
		int_sunset_min = int_sunset_min - 60;
 80015f2:	6f3b      	ldr	r3, [r7, #112]	; 0x70
 80015f4:	3b3c      	subs	r3, #60	; 0x3c
 80015f6:	673b      	str	r3, [r7, #112]	; 0x70
	}

	//Add time difference from German time to UTC Time
	//Private variable winterTime must be initialized accordingly
	if (winterTime)
 80015f8:	4b14      	ldr	r3, [pc, #80]	; (800164c <calc_sunrise_sunset+0x65c>)
 80015fa:	781b      	ldrb	r3, [r3, #0]
 80015fc:	2b00      	cmp	r3, #0
 80015fe:	d05d      	beq.n	80016bc <calc_sunrise_sunset+0x6cc>
	{
		sunrise_h = sunrise_h + UTC_DER_win;
 8001600:	4b13      	ldr	r3, [pc, #76]	; (8001650 <calc_sunrise_sunset+0x660>)
 8001602:	681b      	ldr	r3, [r3, #0]
 8001604:	6ffa      	ldr	r2, [r7, #124]	; 0x7c
 8001606:	4413      	add	r3, r2
 8001608:	67fb      	str	r3, [r7, #124]	; 0x7c
		sunset_h = sunset_h + UTC_DER_win;
 800160a:	4b11      	ldr	r3, [pc, #68]	; (8001650 <calc_sunrise_sunset+0x660>)
 800160c:	681b      	ldr	r3, [r3, #0]
 800160e:	6fba      	ldr	r2, [r7, #120]	; 0x78
 8001610:	4413      	add	r3, r2
 8001612:	67bb      	str	r3, [r7, #120]	; 0x78
 8001614:	e05c      	b.n	80016d0 <calc_sunrise_sunset+0x6e0>
 8001616:	bf00      	nop
 8001618:	d9839475 	.word	0xd9839475
 800161c:	3f661804 	.word	0x3f661804
 8001620:	e646f156 	.word	0xe646f156
 8001624:	3f583f91 	.word	0x3f583f91
 8001628:	df3b645a 	.word	0xdf3b645a
 800162c:	4056b54f 	.word	0x4056b54f
 8001630:	40080000 	.word	0x40080000
 8001634:	20000000 	.word	0x20000000
 8001638:	20000004 	.word	0x20000004
 800163c:	40100000 	.word	0x40100000
 8001640:	40868000 	.word	0x40868000
 8001644:	404e0000 	.word	0x404e0000
 8001648:	40590000 	.word	0x40590000
 800164c:	20000010 	.word	0x20000010
 8001650:	2000000c 	.word	0x2000000c
 8001654:	d4b3ac9a 	.word	0xd4b3ac9a
 8001658:	3f91a099 	.word	0x3f91a099
 800165c:	79e42523 	.word	0x79e42523
 8001660:	3f919445 	.word	0x3f919445
 8001664:	ba2be059 	.word	0xba2be059
 8001668:	3f5e9af5 	.word	0x3f5e9af5
 800166c:	30553261 	.word	0x30553261
 8001670:	3f13a92a 	.word	0x3f13a92a
 8001674:	83e8576d 	.word	0x83e8576d
 8001678:	3fa06c65 	.word	0x3fa06c65
 800167c:	183f91e6 	.word	0x183f91e6
 8001680:	3f8dee78 	.word	0x3f8dee78
 8001684:	fe260b2d 	.word	0xfe260b2d
 8001688:	3fa4ea28 	.word	0x3fa4ea28
 800168c:	8f5c28f6 	.word	0x8f5c28f6
 8001690:	406ca5c2 	.word	0x406ca5c2
 8001694:	8051c9f7 	.word	0x8051c9f7
 8001698:	3fd99828 	.word	0x3fd99828
 800169c:	7c0f4517 	.word	0x7c0f4517
 80016a0:	3f7c560c 	.word	0x3f7c560c
 80016a4:	dd50a88f 	.word	0xdd50a88f
 80016a8:	3fb1fc5c 	.word	0x3fb1fc5c
 80016ac:	cfc829d0 	.word	0xcfc829d0
 80016b0:	3f7bae46 	.word	0x3f7bae46
 80016b4:	ab324852 	.word	0xab324852
 80016b8:	3f4db877 	.word	0x3f4db877
	} else {
		sunrise_h = sunrise_h + UTC_DER_sum;
 80016bc:	4b0f      	ldr	r3, [pc, #60]	; (80016fc <calc_sunrise_sunset+0x70c>)
 80016be:	681b      	ldr	r3, [r3, #0]
 80016c0:	6ffa      	ldr	r2, [r7, #124]	; 0x7c
 80016c2:	4413      	add	r3, r2
 80016c4:	67fb      	str	r3, [r7, #124]	; 0x7c
	    sunset_h = sunset_h + UTC_DER_sum;
 80016c6:	4b0d      	ldr	r3, [pc, #52]	; (80016fc <calc_sunrise_sunset+0x70c>)
 80016c8:	681b      	ldr	r3, [r3, #0]
 80016ca:	6fba      	ldr	r2, [r7, #120]	; 0x78
 80016cc:	4413      	add	r3, r2
 80016ce:	67bb      	str	r3, [r7, #120]	; 0x78
	}

	sunrise_time[0] = sunrise_h;
 80016d0:	683b      	ldr	r3, [r7, #0]
 80016d2:	6ffa      	ldr	r2, [r7, #124]	; 0x7c
 80016d4:	601a      	str	r2, [r3, #0]
	sunrise_time[1] = int_sunrise_min;
 80016d6:	683b      	ldr	r3, [r7, #0]
 80016d8:	3304      	adds	r3, #4
 80016da:	6f7a      	ldr	r2, [r7, #116]	; 0x74
 80016dc:	601a      	str	r2, [r3, #0]
	sunset_time[0] = sunset_h;
 80016de:	f8d7 30a8 	ldr.w	r3, [r7, #168]	; 0xa8
 80016e2:	6fba      	ldr	r2, [r7, #120]	; 0x78
 80016e4:	601a      	str	r2, [r3, #0]
	sunset_time[1] = int_sunset_min;
 80016e6:	f8d7 30a8 	ldr.w	r3, [r7, #168]	; 0xa8
 80016ea:	3304      	adds	r3, #4
 80016ec:	6f3a      	ldr	r2, [r7, #112]	; 0x70
 80016ee:	601a      	str	r2, [r3, #0]
}
 80016f0:	bf00      	nop
 80016f2:	378c      	adds	r7, #140	; 0x8c
 80016f4:	46bd      	mov	sp, r7
 80016f6:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
 80016fa:	bf00      	nop
 80016fc:	20000008 	.word	0x20000008

08001700 <calc_tomorrows_date>:
* Function Name  : calc_tomorrows_date
* Description    : calculates tomorrow's date
* Source		 : https://github.com/vyacht/stm32/blob/master/vynmea/rtc.c
*******************************************************************************/
void calc_tomorrows_date(int day, int wday, int month, int year, int DaysInMonth[12], int tomorrows_date[4])
{
 8001700:	b480      	push	{r7}
 8001702:	b085      	sub	sp, #20
 8001704:	af00      	add	r7, sp, #0
 8001706:	60f8      	str	r0, [r7, #12]
 8001708:	60b9      	str	r1, [r7, #8]
 800170a:	607a      	str	r2, [r7, #4]
 800170c:	603b      	str	r3, [r7, #0]
	bool leap_year;

	day++;							// next day
 800170e:	68fb      	ldr	r3, [r7, #12]
 8001710:	3301      	adds	r3, #1
 8001712:	60fb      	str	r3, [r7, #12]
	wday++;							// next weekday
 8001714:	68bb      	ldr	r3, [r7, #8]
 8001716:	3301      	adds	r3, #1
 8001718:	60bb      	str	r3, [r7, #8]
	if(wday == 8)
 800171a:	68bb      	ldr	r3, [r7, #8]
 800171c:	2b08      	cmp	r3, #8
 800171e:	d101      	bne.n	8001724 <calc_tomorrows_date+0x24>
	{
		wday = 1;					// Monday
 8001720:	2301      	movs	r3, #1
 8001722:	60bb      	str	r3, [r7, #8]
	}
	if(day > DaysInMonth[month-1])
 8001724:	687b      	ldr	r3, [r7, #4]
 8001726:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
 800172a:	3b01      	subs	r3, #1
 800172c:	009b      	lsls	r3, r3, #2
 800172e:	69ba      	ldr	r2, [r7, #24]
 8001730:	4413      	add	r3, r2
 8001732:	681b      	ldr	r3, [r3, #0]
 8001734:	68fa      	ldr	r2, [r7, #12]
 8001736:	429a      	cmp	r2, r3
 8001738:	dd04      	ble.n	8001744 <calc_tomorrows_date+0x44>
	{								// next month
		day = 1;
 800173a:	2301      	movs	r3, #1
 800173c:	60fb      	str	r3, [r7, #12]
		month++;
 800173e:	687b      	ldr	r3, [r7, #4]
 8001740:	3301      	adds	r3, #1
 8001742:	607b      	str	r3, [r7, #4]
	}
	if(day > 31 && month == 12)     // next year
 8001744:	68fb      	ldr	r3, [r7, #12]
 8001746:	2b1f      	cmp	r3, #31
 8001748:	dd09      	ble.n	800175e <calc_tomorrows_date+0x5e>
 800174a:	687b      	ldr	r3, [r7, #4]
 800174c:	2b0c      	cmp	r3, #12
 800174e:	d106      	bne.n	800175e <calc_tomorrows_date+0x5e>
	{
		day = 1;
 8001750:	2301      	movs	r3, #1
 8001752:	60fb      	str	r3, [r7, #12]
		month = 1;
 8001754:	2301      	movs	r3, #1
 8001756:	607b      	str	r3, [r7, #4]
		year++;
 8001758:	683b      	ldr	r3, [r7, #0]
 800175a:	3301      	adds	r3, #1
 800175c:	603b      	str	r3, [r7, #0]
	}

	tomorrows_date[0] = day;
 800175e:	69fb      	ldr	r3, [r7, #28]
 8001760:	68fa      	ldr	r2, [r7, #12]
 8001762:	601a      	str	r2, [r3, #0]
	tomorrows_date[1] = wday;
 8001764:	69fb      	ldr	r3, [r7, #28]
 8001766:	3304      	adds	r3, #4
 8001768:	68ba      	ldr	r2, [r7, #8]
 800176a:	601a      	str	r2, [r3, #0]
	tomorrows_date[2] = month;
 800176c:	69fb      	ldr	r3, [r7, #28]
 800176e:	3308      	adds	r3, #8
 8001770:	687a      	ldr	r2, [r7, #4]
 8001772:	601a      	str	r2, [r3, #0]
	tomorrows_date[3] = year;
 8001774:	69fb      	ldr	r3, [r7, #28]
 8001776:	330c      	adds	r3, #12
 8001778:	683a      	ldr	r2, [r7, #0]
 800177a:	601a      	str	r2, [r3, #0]

}
 800177c:	bf00      	nop
 800177e:	3714      	adds	r7, #20
 8001780:	46bd      	mov	sp, r7
 8001782:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001786:	4770      	bx	lr

08001788 <set_Alarm>:
/*******************************************************************************
* Function Name  : set_Alarm
* Description    : sets the wake up Alarm
*******************************************************************************/
void set_Alarm(int h, int min, int weekDay)
{
 8001788:	b580      	push	{r7, lr}
 800178a:	b084      	sub	sp, #16
 800178c:	af00      	add	r7, sp, #0
 800178e:	60f8      	str	r0, [r7, #12]
 8001790:	60b9      	str	r1, [r7, #8]
 8001792:	607a      	str	r2, [r7, #4]
	/** Enable the Alarm A*/
	sAlarm.AlarmTime.Hours = h;
 8001794:	68fb      	ldr	r3, [r7, #12]
 8001796:	b2da      	uxtb	r2, r3
 8001798:	4b19      	ldr	r3, [pc, #100]	; (8001800 <set_Alarm+0x78>)
 800179a:	701a      	strb	r2, [r3, #0]
	sAlarm.AlarmTime.Minutes = min;
 800179c:	68bb      	ldr	r3, [r7, #8]
 800179e:	b2da      	uxtb	r2, r3
 80017a0:	4b17      	ldr	r3, [pc, #92]	; (8001800 <set_Alarm+0x78>)
 80017a2:	705a      	strb	r2, [r3, #1]
	sAlarm.AlarmTime.Seconds = 0;
 80017a4:	4b16      	ldr	r3, [pc, #88]	; (8001800 <set_Alarm+0x78>)
 80017a6:	2200      	movs	r2, #0
 80017a8:	709a      	strb	r2, [r3, #2]
	sAlarm.AlarmTime.SubSeconds = 0;
 80017aa:	4b15      	ldr	r3, [pc, #84]	; (8001800 <set_Alarm+0x78>)
 80017ac:	2200      	movs	r2, #0
 80017ae:	605a      	str	r2, [r3, #4]
	sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
 80017b0:	4b13      	ldr	r3, [pc, #76]	; (8001800 <set_Alarm+0x78>)
 80017b2:	2200      	movs	r2, #0
 80017b4:	60da      	str	r2, [r3, #12]
	sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET;
 80017b6:	4b12      	ldr	r3, [pc, #72]	; (8001800 <set_Alarm+0x78>)
 80017b8:	2200      	movs	r2, #0
 80017ba:	611a      	str	r2, [r3, #16]
	sAlarm.AlarmMask = RTC_ALARMMASK_NONE;						//only by specific time
 80017bc:	4b10      	ldr	r3, [pc, #64]	; (8001800 <set_Alarm+0x78>)
 80017be:	2200      	movs	r2, #0
 80017c0:	615a      	str	r2, [r3, #20]
	sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL;
 80017c2:	4b0f      	ldr	r3, [pc, #60]	; (8001800 <set_Alarm+0x78>)
 80017c4:	2200      	movs	r2, #0
 80017c6:	619a      	str	r2, [r3, #24]
	sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_WEEKDAY;
 80017c8:	4b0d      	ldr	r3, [pc, #52]	; (8001800 <set_Alarm+0x78>)
 80017ca:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
 80017ce:	61da      	str	r2, [r3, #28]
	sAlarm.AlarmDateWeekDay = weekDay;
 80017d0:	687b      	ldr	r3, [r7, #4]
 80017d2:	b2da      	uxtb	r2, r3
 80017d4:	4b0a      	ldr	r3, [pc, #40]	; (8001800 <set_Alarm+0x78>)
 80017d6:	f883 2020 	strb.w	r2, [r3, #32]
	sAlarm.Alarm = RTC_ALARM_A;
 80017da:	4b09      	ldr	r3, [pc, #36]	; (8001800 <set_Alarm+0x78>)
 80017dc:	f44f 7280 	mov.w	r2, #256	; 0x100
 80017e0:	625a      	str	r2, [r3, #36]	; 0x24
	if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BIN) != HAL_OK)
 80017e2:	2200      	movs	r2, #0
 80017e4:	4906      	ldr	r1, [pc, #24]	; (8001800 <set_Alarm+0x78>)
 80017e6:	4807      	ldr	r0, [pc, #28]	; (8001804 <set_Alarm+0x7c>)
 80017e8:	f001 ff04 	bl	80035f4 <HAL_RTC_SetAlarm_IT>
 80017ec:	4603      	mov	r3, r0
 80017ee:	2b00      	cmp	r3, #0
 80017f0:	d001      	beq.n	80017f6 <set_Alarm+0x6e>
	{
		Error_Handler();
 80017f2:	f000 fa7d 	bl	8001cf0 <Error_Handler>
	}
}
 80017f6:	bf00      	nop
 80017f8:	3710      	adds	r7, #16
 80017fa:	46bd      	mov	sp, r7
 80017fc:	bd80      	pop	{r7, pc}
 80017fe:	bf00      	nop
 8001800:	200000b8 	.word	0x200000b8
 8001804:	200000e4 	.word	0x200000e4

08001808 <transmit_uart>:

// sending to UART
void transmit_uart(char *string){
 8001808:	b580      	push	{r7, lr}
 800180a:	b084      	sub	sp, #16
 800180c:	af00      	add	r7, sp, #0
 800180e:	6078      	str	r0, [r7, #4]
	uint8_t len = strlen(string);
 8001810:	6878      	ldr	r0, [r7, #4]
 8001812:	f7fe fce1 	bl	80001d8 <strlen>
 8001816:	4603      	mov	r3, r0
 8001818:	73fb      	strb	r3, [r7, #15]
	HAL_UART_Transmit(&huart2, (uint8_t*) string, len, 200);
 800181a:	7bfb      	ldrb	r3, [r7, #15]
 800181c:	b29a      	uxth	r2, r3
 800181e:	23c8      	movs	r3, #200	; 0xc8
 8001820:	6879      	ldr	r1, [r7, #4]
 8001822:	4803      	ldr	r0, [pc, #12]	; (8001830 <transmit_uart+0x28>)
 8001824:	f002 f94b 	bl	8003abe <HAL_UART_Transmit>
}
 8001828:	bf00      	nop
 800182a:	3710      	adds	r7, #16
 800182c:	46bd      	mov	sp, r7
 800182e:	bd80      	pop	{r7, pc}
 8001830:	20000104 	.word	0x20000104

08001834 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8001834:	b5b0      	push	{r4, r5, r7, lr}
 8001836:	b0ae      	sub	sp, #184	; 0xb8
 8001838:	af02      	add	r7, sp, #8
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 800183a:	f000 fb6b 	bl	8001f14 <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 800183e:	f000 f8e1 	bl	8001a04 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8001842:	f000 f9e5 	bl	8001c10 <MX_GPIO_Init>
  MX_USART2_UART_Init();
 8001846:	f000 f9b9 	bl	8001bbc <MX_USART2_UART_Init>
  MX_RTC_Init();
 800184a:	f000 f95f 	bl	8001b0c <MX_RTC_Init>
  /* USER CODE BEGIN 2 */
  int hours = 0;
 800184e:	2300      	movs	r3, #0
 8001850:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
  int minutes = 0;
 8001854:	2300      	movs	r3, #0
 8001856:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
  int seconds = 0;
 800185a:	2300      	movs	r3, #0
 800185c:	f8c7 3094 	str.w	r3, [r7, #148]	; 0x94
  int weekDay = 0;
 8001860:	2300      	movs	r3, #0
 8001862:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
  int month = 0;
 8001866:	2300      	movs	r3, #0
 8001868:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
  int date = 0;
 800186c:	2300      	movs	r3, #0
 800186e:	f8c7 30a4 	str.w	r3, [r7, #164]	; 0xa4
  int year = 0;
 8001872:	2300      	movs	r3, #0
 8001874:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0

  int sunrise_h = 0;
 8001878:	2300      	movs	r3, #0
 800187a:	f8c7 3090 	str.w	r3, [r7, #144]	; 0x90
  int sunset_h = 0;
 800187e:	2300      	movs	r3, #0
 8001880:	f8c7 308c 	str.w	r3, [r7, #140]	; 0x8c
  int int_sunrise_min = 0;
 8001884:	2300      	movs	r3, #0
 8001886:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
  int int_sunset_min = 0;
 800188a:	2300      	movs	r3, #0
 800188c:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
  int sunrise_time[2] = {0};
 8001890:	f107 0378 	add.w	r3, r7, #120	; 0x78
 8001894:	2200      	movs	r2, #0
 8001896:	601a      	str	r2, [r3, #0]
 8001898:	605a      	str	r2, [r3, #4]
  int sunset_time[2] = {0};
 800189a:	f107 0370 	add.w	r3, r7, #112	; 0x70
 800189e:	2200      	movs	r2, #0
 80018a0:	601a      	str	r2, [r3, #0]
 80018a2:	605a      	str	r2, [r3, #4]
  int tomorrows_date[4] = {0};
 80018a4:	f107 0360 	add.w	r3, r7, #96	; 0x60
 80018a8:	2200      	movs	r2, #0
 80018aa:	601a      	str	r2, [r3, #0]
 80018ac:	605a      	str	r2, [r3, #4]
 80018ae:	609a      	str	r2, [r3, #8]
 80018b0:	60da      	str	r2, [r3, #12]
  int DaysInMonth[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
 80018b2:	4b4d      	ldr	r3, [pc, #308]	; (80019e8 <main+0x1b4>)
 80018b4:	f107 0430 	add.w	r4, r7, #48	; 0x30
 80018b8:	461d      	mov	r5, r3
 80018ba:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
 80018bc:	c40f      	stmia	r4!, {r0, r1, r2, r3}
 80018be:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
 80018c0:	c40f      	stmia	r4!, {r0, r1, r2, r3}
 80018c2:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
 80018c6:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
  int DaysInMonthLeapYear[12] = {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
 80018ca:	4b48      	ldr	r3, [pc, #288]	; (80019ec <main+0x1b8>)
 80018cc:	463c      	mov	r4, r7
 80018ce:	461d      	mov	r5, r3
 80018d0:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
 80018d2:	c40f      	stmia	r4!, {r0, r1, r2, r3}
 80018d4:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
 80018d6:	c40f      	stmia	r4!, {r0, r1, r2, r3}
 80018d8:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
 80018dc:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
  bool leap_year = false;
 80018e0:	2300      	movs	r3, #0
 80018e2:	f887 3083 	strb.w	r3, [r7, #131]	; 0x83
  /* USER CODE BEGIN WHILE */
  while (1)
  {

	//Get Time and Date
	if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK)
 80018e6:	2200      	movs	r2, #0
 80018e8:	4941      	ldr	r1, [pc, #260]	; (80019f0 <main+0x1bc>)
 80018ea:	4842      	ldr	r0, [pc, #264]	; (80019f4 <main+0x1c0>)
 80018ec:	f001 fd2e 	bl	800334c <HAL_RTC_GetTime>
 80018f0:	4603      	mov	r3, r0
 80018f2:	2b00      	cmp	r3, #0
 80018f4:	d10b      	bne.n	800190e <main+0xda>
	{
		hours = sTime.Hours;
 80018f6:	4b3e      	ldr	r3, [pc, #248]	; (80019f0 <main+0x1bc>)
 80018f8:	781b      	ldrb	r3, [r3, #0]
 80018fa:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
		minutes = sTime.Minutes;
 80018fe:	4b3c      	ldr	r3, [pc, #240]	; (80019f0 <main+0x1bc>)
 8001900:	785b      	ldrb	r3, [r3, #1]
 8001902:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
		seconds = sTime.Seconds;
 8001906:	4b3a      	ldr	r3, [pc, #232]	; (80019f0 <main+0x1bc>)
 8001908:	789b      	ldrb	r3, [r3, #2]
 800190a:	f8c7 3094 	str.w	r3, [r7, #148]	; 0x94
	}
	if (HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK)
 800190e:	2200      	movs	r2, #0
 8001910:	4939      	ldr	r1, [pc, #228]	; (80019f8 <main+0x1c4>)
 8001912:	4838      	ldr	r0, [pc, #224]	; (80019f4 <main+0x1c0>)
 8001914:	f001 fe1f 	bl	8003556 <HAL_RTC_GetDate>
 8001918:	4603      	mov	r3, r0
 800191a:	2b00      	cmp	r3, #0
 800191c:	d111      	bne.n	8001942 <main+0x10e>
	{
		weekDay = sDate.WeekDay;
 800191e:	4b36      	ldr	r3, [pc, #216]	; (80019f8 <main+0x1c4>)
 8001920:	781b      	ldrb	r3, [r3, #0]
 8001922:	f8c7 30ac 	str.w	r3, [r7, #172]	; 0xac
		month = sDate.Month;
 8001926:	4b34      	ldr	r3, [pc, #208]	; (80019f8 <main+0x1c4>)
 8001928:	785b      	ldrb	r3, [r3, #1]
 800192a:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
		date = sDate.Date;
 800192e:	4b32      	ldr	r3, [pc, #200]	; (80019f8 <main+0x1c4>)
 8001930:	789b      	ldrb	r3, [r3, #2]
 8001932:	f8c7 30a4 	str.w	r3, [r7, #164]	; 0xa4
		year = 2000 + sDate.Year;
 8001936:	4b30      	ldr	r3, [pc, #192]	; (80019f8 <main+0x1c4>)
 8001938:	78db      	ldrb	r3, [r3, #3]
 800193a:	f503 63fa 	add.w	r3, r3, #2000	; 0x7d0
 800193e:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
	}

	// check for leap year
	leap_year = leap_year_check(year);
 8001942:	f8d7 00a0 	ldr.w	r0, [r7, #160]	; 0xa0
 8001946:	f7ff faa3 	bl	8000e90 <leap_year_check>
 800194a:	4603      	mov	r3, r0
 800194c:	2b00      	cmp	r3, #0
 800194e:	bf14      	ite	ne
 8001950:	2301      	movne	r3, #1
 8001952:	2300      	moveq	r3, #0
 8001954:	f887 3083 	strb.w	r3, [r7, #131]	; 0x83
	if (leap_year)
 8001958:	f897 3083 	ldrb.w	r3, [r7, #131]	; 0x83
 800195c:	2b00      	cmp	r3, #0
 800195e:	d00f      	beq.n	8001980 <main+0x14c>
	{
		//Calculate tomorrow's date
		calc_tomorrows_date(date, weekDay, month, year, DaysInMonthLeapYear, tomorrows_date);
 8001960:	f107 0360 	add.w	r3, r7, #96	; 0x60
 8001964:	9301      	str	r3, [sp, #4]
 8001966:	463b      	mov	r3, r7
 8001968:	9300      	str	r3, [sp, #0]
 800196a:	f8d7 30a0 	ldr.w	r3, [r7, #160]	; 0xa0
 800196e:	f8d7 20a8 	ldr.w	r2, [r7, #168]	; 0xa8
 8001972:	f8d7 10ac 	ldr.w	r1, [r7, #172]	; 0xac
 8001976:	f8d7 00a4 	ldr.w	r0, [r7, #164]	; 0xa4
 800197a:	f7ff fec1 	bl	8001700 <calc_tomorrows_date>
 800197e:	e00f      	b.n	80019a0 <main+0x16c>
	} else {
		//Calculate tomorrow's date
		calc_tomorrows_date(date, weekDay, month, year, DaysInMonth, tomorrows_date);
 8001980:	f107 0360 	add.w	r3, r7, #96	; 0x60
 8001984:	9301      	str	r3, [sp, #4]
 8001986:	f107 0330 	add.w	r3, r7, #48	; 0x30
 800198a:	9300      	str	r3, [sp, #0]
 800198c:	f8d7 30a0 	ldr.w	r3, [r7, #160]	; 0xa0
 8001990:	f8d7 20a8 	ldr.w	r2, [r7, #168]	; 0xa8
 8001994:	f8d7 10ac 	ldr.w	r1, [r7, #172]	; 0xac
 8001998:	f8d7 00a4 	ldr.w	r0, [r7, #164]	; 0xa4
 800199c:	f7ff feb0 	bl	8001700 <calc_tomorrows_date>
	}

	//Calculate sunrise and sunset time for tomorrow
	calc_sunrise_sunset(tomorrows_date[0], tomorrows_date[2], tomorrows_date[3], sunrise_time, sunset_time);
 80019a0:	6e38      	ldr	r0, [r7, #96]	; 0x60
 80019a2:	6eb9      	ldr	r1, [r7, #104]	; 0x68
 80019a4:	6efa      	ldr	r2, [r7, #108]	; 0x6c
 80019a6:	f107 0478 	add.w	r4, r7, #120	; 0x78
 80019aa:	f107 0370 	add.w	r3, r7, #112	; 0x70
 80019ae:	9300      	str	r3, [sp, #0]
 80019b0:	4623      	mov	r3, r4
 80019b2:	f7ff fb1d 	bl	8000ff0 <calc_sunrise_sunset>

	set_Alarm(16, 22, 1);
 80019b6:	2201      	movs	r2, #1
 80019b8:	2116      	movs	r1, #22
 80019ba:	2010      	movs	r0, #16
 80019bc:	f7ff fee4 	bl	8001788 <set_Alarm>

	HAL_Delay(5000);
 80019c0:	f241 3088 	movw	r0, #5000	; 0x1388
 80019c4:	f000 fb18 	bl	8001ff8 <HAL_Delay>

	transmit_uart("Ich gehe schlafen!\r\n");
 80019c8:	480c      	ldr	r0, [pc, #48]	; (80019fc <main+0x1c8>)
 80019ca:	f7ff ff1d 	bl	8001808 <transmit_uart>

	// Suspend Tick increment to prevent wake up by Systick interrupt
	HAL_SuspendTick();
 80019ce:	f000 fb35 	bl	800203c <HAL_SuspendTick>

	HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);  //Interrupt for wake up
 80019d2:	2101      	movs	r1, #1
 80019d4:	2000      	movs	r0, #0
 80019d6:	f000 fdff 	bl	80025d8 <HAL_PWR_EnterSLEEPMode>

	HAL_ResumeTick();
 80019da:	f000 fb3f 	bl	800205c <HAL_ResumeTick>

	transmit_uart("Bin wieder wach!\r\n");
 80019de:	4808      	ldr	r0, [pc, #32]	; (8001a00 <main+0x1cc>)
 80019e0:	f7ff ff12 	bl	8001808 <transmit_uart>
	if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK)
 80019e4:	e77f      	b.n	80018e6 <main+0xb2>
 80019e6:	bf00      	nop
 80019e8:	08005fac 	.word	0x08005fac
 80019ec:	08005fdc 	.word	0x08005fdc
 80019f0:	200000a4 	.word	0x200000a4
 80019f4:	200000e4 	.word	0x200000e4
 80019f8:	200000e0 	.word	0x200000e0
 80019fc:	08005f80 	.word	0x08005f80
 8001a00:	08005f98 	.word	0x08005f98

08001a04 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8001a04:	b580      	push	{r7, lr}
 8001a06:	b098      	sub	sp, #96	; 0x60
 8001a08:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 8001a0a:	f107 0330 	add.w	r3, r7, #48	; 0x30
 8001a0e:	2230      	movs	r2, #48	; 0x30
 8001a10:	2100      	movs	r1, #0
 8001a12:	4618      	mov	r0, r3
 8001a14:	f002 fcdc 	bl	80043d0 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8001a18:	f107 031c 	add.w	r3, r7, #28
 8001a1c:	2200      	movs	r2, #0
 8001a1e:	601a      	str	r2, [r3, #0]
 8001a20:	605a      	str	r2, [r3, #4]
 8001a22:	609a      	str	r2, [r3, #8]
 8001a24:	60da      	str	r2, [r3, #12]
 8001a26:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 8001a28:	f107 0308 	add.w	r3, r7, #8
 8001a2c:	2200      	movs	r2, #0
 8001a2e:	601a      	str	r2, [r3, #0]
 8001a30:	605a      	str	r2, [r3, #4]
 8001a32:	609a      	str	r2, [r3, #8]
 8001a34:	60da      	str	r2, [r3, #12]
 8001a36:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  __HAL_RCC_PWR_CLK_ENABLE();
 8001a38:	2300      	movs	r3, #0
 8001a3a:	607b      	str	r3, [r7, #4]
 8001a3c:	4b31      	ldr	r3, [pc, #196]	; (8001b04 <SystemClock_Config+0x100>)
 8001a3e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001a40:	4a30      	ldr	r2, [pc, #192]	; (8001b04 <SystemClock_Config+0x100>)
 8001a42:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001a46:	6413      	str	r3, [r2, #64]	; 0x40
 8001a48:	4b2e      	ldr	r3, [pc, #184]	; (8001b04 <SystemClock_Config+0x100>)
 8001a4a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001a4c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001a50:	607b      	str	r3, [r7, #4]
 8001a52:	687b      	ldr	r3, [r7, #4]
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
 8001a54:	2300      	movs	r3, #0
 8001a56:	603b      	str	r3, [r7, #0]
 8001a58:	4b2b      	ldr	r3, [pc, #172]	; (8001b08 <SystemClock_Config+0x104>)
 8001a5a:	681b      	ldr	r3, [r3, #0]
 8001a5c:	f423 4340 	bic.w	r3, r3, #49152	; 0xc000
 8001a60:	4a29      	ldr	r2, [pc, #164]	; (8001b08 <SystemClock_Config+0x104>)
 8001a62:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 8001a66:	6013      	str	r3, [r2, #0]
 8001a68:	4b27      	ldr	r3, [pc, #156]	; (8001b08 <SystemClock_Config+0x104>)
 8001a6a:	681b      	ldr	r3, [r3, #0]
 8001a6c:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
 8001a70:	603b      	str	r3, [r7, #0]
 8001a72:	683b      	ldr	r3, [r7, #0]
  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI;
 8001a74:	230a      	movs	r3, #10
 8001a76:	633b      	str	r3, [r7, #48]	; 0x30
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8001a78:	2301      	movs	r3, #1
 8001a7a:	63fb      	str	r3, [r7, #60]	; 0x3c
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8001a7c:	2310      	movs	r3, #16
 8001a7e:	643b      	str	r3, [r7, #64]	; 0x40
  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
 8001a80:	2301      	movs	r3, #1
 8001a82:	647b      	str	r3, [r7, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8001a84:	2302      	movs	r3, #2
 8001a86:	64bb      	str	r3, [r7, #72]	; 0x48
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 8001a88:	2300      	movs	r3, #0
 8001a8a:	64fb      	str	r3, [r7, #76]	; 0x4c
  RCC_OscInitStruct.PLL.PLLM = 16;
 8001a8c:	2310      	movs	r3, #16
 8001a8e:	653b      	str	r3, [r7, #80]	; 0x50
  RCC_OscInitStruct.PLL.PLLN = 336;
 8001a90:	f44f 73a8 	mov.w	r3, #336	; 0x150
 8001a94:	657b      	str	r3, [r7, #84]	; 0x54
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
 8001a96:	2304      	movs	r3, #4
 8001a98:	65bb      	str	r3, [r7, #88]	; 0x58
  RCC_OscInitStruct.PLL.PLLQ = 7;
 8001a9a:	2307      	movs	r3, #7
 8001a9c:	65fb      	str	r3, [r7, #92]	; 0x5c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8001a9e:	f107 0330 	add.w	r3, r7, #48	; 0x30
 8001aa2:	4618      	mov	r0, r3
 8001aa4:	f000 fdb4 	bl	8002610 <HAL_RCC_OscConfig>
 8001aa8:	4603      	mov	r3, r0
 8001aaa:	2b00      	cmp	r3, #0
 8001aac:	d001      	beq.n	8001ab2 <SystemClock_Config+0xae>
  {
    Error_Handler();
 8001aae:	f000 f91f 	bl	8001cf0 <Error_Handler>
  }
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8001ab2:	230f      	movs	r3, #15
 8001ab4:	61fb      	str	r3, [r7, #28]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8001ab6:	2302      	movs	r3, #2
 8001ab8:	623b      	str	r3, [r7, #32]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8001aba:	2300      	movs	r3, #0
 8001abc:	627b      	str	r3, [r7, #36]	; 0x24
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 8001abe:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 8001ac2:	62bb      	str	r3, [r7, #40]	; 0x28
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8001ac4:	2300      	movs	r3, #0
 8001ac6:	62fb      	str	r3, [r7, #44]	; 0x2c

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8001ac8:	f107 031c 	add.w	r3, r7, #28
 8001acc:	2102      	movs	r1, #2
 8001ace:	4618      	mov	r0, r3
 8001ad0:	f001 f80e 	bl	8002af0 <HAL_RCC_ClockConfig>
 8001ad4:	4603      	mov	r3, r0
 8001ad6:	2b00      	cmp	r3, #0
 8001ad8:	d001      	beq.n	8001ade <SystemClock_Config+0xda>
  {
    Error_Handler();
 8001ada:	f000 f909 	bl	8001cf0 <Error_Handler>
  }
  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
 8001ade:	2302      	movs	r3, #2
 8001ae0:	60bb      	str	r3, [r7, #8]
  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
 8001ae2:	f44f 7300 	mov.w	r3, #512	; 0x200
 8001ae6:	617b      	str	r3, [r7, #20]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
 8001ae8:	f107 0308 	add.w	r3, r7, #8
 8001aec:	4618      	mov	r0, r3
 8001aee:	f001 f9f1 	bl	8002ed4 <HAL_RCCEx_PeriphCLKConfig>
 8001af2:	4603      	mov	r3, r0
 8001af4:	2b00      	cmp	r3, #0
 8001af6:	d001      	beq.n	8001afc <SystemClock_Config+0xf8>
  {
    Error_Handler();
 8001af8:	f000 f8fa 	bl	8001cf0 <Error_Handler>
  }
}
 8001afc:	bf00      	nop
 8001afe:	3760      	adds	r7, #96	; 0x60
 8001b00:	46bd      	mov	sp, r7
 8001b02:	bd80      	pop	{r7, pc}
 8001b04:	40023800 	.word	0x40023800
 8001b08:	40007000 	.word	0x40007000

08001b0c <MX_RTC_Init>:
  * @brief RTC Initialization Function
  * @param None
  * @retval None
  */
static void MX_RTC_Init(void)
{
 8001b0c:	b580      	push	{r7, lr}
 8001b0e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN RTC_Init 1 */

  /* USER CODE END RTC_Init 1 */
  /** Initialize RTC Only
  */
  hrtc.Instance = RTC;
 8001b10:	4b26      	ldr	r3, [pc, #152]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b12:	4a27      	ldr	r2, [pc, #156]	; (8001bb0 <MX_RTC_Init+0xa4>)
 8001b14:	601a      	str	r2, [r3, #0]
  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
 8001b16:	4b25      	ldr	r3, [pc, #148]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b18:	2200      	movs	r2, #0
 8001b1a:	605a      	str	r2, [r3, #4]
  hrtc.Init.AsynchPrediv = 127;
 8001b1c:	4b23      	ldr	r3, [pc, #140]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b1e:	227f      	movs	r2, #127	; 0x7f
 8001b20:	609a      	str	r2, [r3, #8]
  hrtc.Init.SynchPrediv = 255;
 8001b22:	4b22      	ldr	r3, [pc, #136]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b24:	22ff      	movs	r2, #255	; 0xff
 8001b26:	60da      	str	r2, [r3, #12]
  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
 8001b28:	4b20      	ldr	r3, [pc, #128]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b2a:	2200      	movs	r2, #0
 8001b2c:	611a      	str	r2, [r3, #16]
  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
 8001b2e:	4b1f      	ldr	r3, [pc, #124]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b30:	2200      	movs	r2, #0
 8001b32:	615a      	str	r2, [r3, #20]
  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
 8001b34:	4b1d      	ldr	r3, [pc, #116]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b36:	2200      	movs	r2, #0
 8001b38:	619a      	str	r2, [r3, #24]
  if (HAL_RTC_Init(&hrtc) != HAL_OK)
 8001b3a:	481c      	ldr	r0, [pc, #112]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b3c:	f001 fab8 	bl	80030b0 <HAL_RTC_Init>
 8001b40:	4603      	mov	r3, r0
 8001b42:	2b00      	cmp	r3, #0
 8001b44:	d001      	beq.n	8001b4a <MX_RTC_Init+0x3e>
  {
    Error_Handler();
 8001b46:	f000 f8d3 	bl	8001cf0 <Error_Handler>

  /* USER CODE END Check_RTC_BKUP */

  /** Initialize RTC and set the Time and Date
  */
  sTime.Hours = 16;
 8001b4a:	4b1a      	ldr	r3, [pc, #104]	; (8001bb4 <MX_RTC_Init+0xa8>)
 8001b4c:	2210      	movs	r2, #16
 8001b4e:	701a      	strb	r2, [r3, #0]
  sTime.Minutes = 20;
 8001b50:	4b18      	ldr	r3, [pc, #96]	; (8001bb4 <MX_RTC_Init+0xa8>)
 8001b52:	2214      	movs	r2, #20
 8001b54:	705a      	strb	r2, [r3, #1]
  sTime.Seconds = 30;
 8001b56:	4b17      	ldr	r3, [pc, #92]	; (8001bb4 <MX_RTC_Init+0xa8>)
 8001b58:	221e      	movs	r2, #30
 8001b5a:	709a      	strb	r2, [r3, #2]
  sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
 8001b5c:	4b15      	ldr	r3, [pc, #84]	; (8001bb4 <MX_RTC_Init+0xa8>)
 8001b5e:	2200      	movs	r2, #0
 8001b60:	60da      	str	r2, [r3, #12]
  sTime.StoreOperation = RTC_STOREOPERATION_RESET;
 8001b62:	4b14      	ldr	r3, [pc, #80]	; (8001bb4 <MX_RTC_Init+0xa8>)
 8001b64:	2200      	movs	r2, #0
 8001b66:	611a      	str	r2, [r3, #16]
  if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK)
 8001b68:	2200      	movs	r2, #0
 8001b6a:	4912      	ldr	r1, [pc, #72]	; (8001bb4 <MX_RTC_Init+0xa8>)
 8001b6c:	480f      	ldr	r0, [pc, #60]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b6e:	f001 fb30 	bl	80031d2 <HAL_RTC_SetTime>
 8001b72:	4603      	mov	r3, r0
 8001b74:	2b00      	cmp	r3, #0
 8001b76:	d001      	beq.n	8001b7c <MX_RTC_Init+0x70>
  {
    Error_Handler();
 8001b78:	f000 f8ba 	bl	8001cf0 <Error_Handler>
  }
  sDate.WeekDay = RTC_WEEKDAY_MONDAY;
 8001b7c:	4b0e      	ldr	r3, [pc, #56]	; (8001bb8 <MX_RTC_Init+0xac>)
 8001b7e:	2201      	movs	r2, #1
 8001b80:	701a      	strb	r2, [r3, #0]
  sDate.Month = RTC_MONTH_JANUARY;
 8001b82:	4b0d      	ldr	r3, [pc, #52]	; (8001bb8 <MX_RTC_Init+0xac>)
 8001b84:	2201      	movs	r2, #1
 8001b86:	705a      	strb	r2, [r3, #1]
  sDate.Date = 11;
 8001b88:	4b0b      	ldr	r3, [pc, #44]	; (8001bb8 <MX_RTC_Init+0xac>)
 8001b8a:	220b      	movs	r2, #11
 8001b8c:	709a      	strb	r2, [r3, #2]
  sDate.Year = 21;
 8001b8e:	4b0a      	ldr	r3, [pc, #40]	; (8001bb8 <MX_RTC_Init+0xac>)
 8001b90:	2215      	movs	r2, #21
 8001b92:	70da      	strb	r2, [r3, #3]

  if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK)
 8001b94:	2200      	movs	r2, #0
 8001b96:	4908      	ldr	r1, [pc, #32]	; (8001bb8 <MX_RTC_Init+0xac>)
 8001b98:	4804      	ldr	r0, [pc, #16]	; (8001bac <MX_RTC_Init+0xa0>)
 8001b9a:	f001 fc35 	bl	8003408 <HAL_RTC_SetDate>
 8001b9e:	4603      	mov	r3, r0
 8001ba0:	2b00      	cmp	r3, #0
 8001ba2:	d001      	beq.n	8001ba8 <MX_RTC_Init+0x9c>
  {
    Error_Handler();
 8001ba4:	f000 f8a4 	bl	8001cf0 <Error_Handler>

  /* USER CODE BEGIN RTC_Init 2 */

  /* USER CODE END RTC_Init 2 */

}
 8001ba8:	bf00      	nop
 8001baa:	bd80      	pop	{r7, pc}
 8001bac:	200000e4 	.word	0x200000e4
 8001bb0:	40002800 	.word	0x40002800
 8001bb4:	200000a4 	.word	0x200000a4
 8001bb8:	200000e0 	.word	0x200000e0

08001bbc <MX_USART2_UART_Init>:
  * @brief USART2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART2_UART_Init(void)
{
 8001bbc:	b580      	push	{r7, lr}
 8001bbe:	af00      	add	r7, sp, #0
  /* USER CODE END USART2_Init 0 */

  /* USER CODE BEGIN USART2_Init 1 */

  /* USER CODE END USART2_Init 1 */
  huart2.Instance = USART2;
 8001bc0:	4b11      	ldr	r3, [pc, #68]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bc2:	4a12      	ldr	r2, [pc, #72]	; (8001c0c <MX_USART2_UART_Init+0x50>)
 8001bc4:	601a      	str	r2, [r3, #0]
  huart2.Init.BaudRate = 115200;
 8001bc6:	4b10      	ldr	r3, [pc, #64]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bc8:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 8001bcc:	605a      	str	r2, [r3, #4]
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 8001bce:	4b0e      	ldr	r3, [pc, #56]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bd0:	2200      	movs	r2, #0
 8001bd2:	609a      	str	r2, [r3, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 8001bd4:	4b0c      	ldr	r3, [pc, #48]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bd6:	2200      	movs	r2, #0
 8001bd8:	60da      	str	r2, [r3, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 8001bda:	4b0b      	ldr	r3, [pc, #44]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bdc:	2200      	movs	r2, #0
 8001bde:	611a      	str	r2, [r3, #16]
  huart2.Init.Mode = UART_MODE_TX_RX;
 8001be0:	4b09      	ldr	r3, [pc, #36]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001be2:	220c      	movs	r2, #12
 8001be4:	615a      	str	r2, [r3, #20]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 8001be6:	4b08      	ldr	r3, [pc, #32]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001be8:	2200      	movs	r2, #0
 8001bea:	619a      	str	r2, [r3, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8001bec:	4b06      	ldr	r3, [pc, #24]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bee:	2200      	movs	r2, #0
 8001bf0:	61da      	str	r2, [r3, #28]
  if (HAL_UART_Init(&huart2) != HAL_OK)
 8001bf2:	4805      	ldr	r0, [pc, #20]	; (8001c08 <MX_USART2_UART_Init+0x4c>)
 8001bf4:	f001 ff16 	bl	8003a24 <HAL_UART_Init>
 8001bf8:	4603      	mov	r3, r0
 8001bfa:	2b00      	cmp	r3, #0
 8001bfc:	d001      	beq.n	8001c02 <MX_USART2_UART_Init+0x46>
  {
    Error_Handler();
 8001bfe:	f000 f877 	bl	8001cf0 <Error_Handler>
  }
  /* USER CODE BEGIN USART2_Init 2 */

  /* USER CODE END USART2_Init 2 */

}
 8001c02:	bf00      	nop
 8001c04:	bd80      	pop	{r7, pc}
 8001c06:	bf00      	nop
 8001c08:	20000104 	.word	0x20000104
 8001c0c:	40004400 	.word	0x40004400

08001c10 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8001c10:	b580      	push	{r7, lr}
 8001c12:	b08a      	sub	sp, #40	; 0x28
 8001c14:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001c16:	f107 0314 	add.w	r3, r7, #20
 8001c1a:	2200      	movs	r2, #0
 8001c1c:	601a      	str	r2, [r3, #0]
 8001c1e:	605a      	str	r2, [r3, #4]
 8001c20:	609a      	str	r2, [r3, #8]
 8001c22:	60da      	str	r2, [r3, #12]
 8001c24:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 8001c26:	2300      	movs	r3, #0
 8001c28:	613b      	str	r3, [r7, #16]
 8001c2a:	4b2d      	ldr	r3, [pc, #180]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c2c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c2e:	4a2c      	ldr	r2, [pc, #176]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c30:	f043 0304 	orr.w	r3, r3, #4
 8001c34:	6313      	str	r3, [r2, #48]	; 0x30
 8001c36:	4b2a      	ldr	r3, [pc, #168]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c38:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c3a:	f003 0304 	and.w	r3, r3, #4
 8001c3e:	613b      	str	r3, [r7, #16]
 8001c40:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOH_CLK_ENABLE();
 8001c42:	2300      	movs	r3, #0
 8001c44:	60fb      	str	r3, [r7, #12]
 8001c46:	4b26      	ldr	r3, [pc, #152]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c48:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c4a:	4a25      	ldr	r2, [pc, #148]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c4c:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8001c50:	6313      	str	r3, [r2, #48]	; 0x30
 8001c52:	4b23      	ldr	r3, [pc, #140]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c54:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c56:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8001c5a:	60fb      	str	r3, [r7, #12]
 8001c5c:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8001c5e:	2300      	movs	r3, #0
 8001c60:	60bb      	str	r3, [r7, #8]
 8001c62:	4b1f      	ldr	r3, [pc, #124]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c64:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c66:	4a1e      	ldr	r2, [pc, #120]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c68:	f043 0301 	orr.w	r3, r3, #1
 8001c6c:	6313      	str	r3, [r2, #48]	; 0x30
 8001c6e:	4b1c      	ldr	r3, [pc, #112]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c70:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c72:	f003 0301 	and.w	r3, r3, #1
 8001c76:	60bb      	str	r3, [r7, #8]
 8001c78:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 8001c7a:	2300      	movs	r3, #0
 8001c7c:	607b      	str	r3, [r7, #4]
 8001c7e:	4b18      	ldr	r3, [pc, #96]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c80:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c82:	4a17      	ldr	r2, [pc, #92]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c84:	f043 0302 	orr.w	r3, r3, #2
 8001c88:	6313      	str	r3, [r2, #48]	; 0x30
 8001c8a:	4b15      	ldr	r3, [pc, #84]	; (8001ce0 <MX_GPIO_Init+0xd0>)
 8001c8c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001c8e:	f003 0302 	and.w	r3, r3, #2
 8001c92:	607b      	str	r3, [r7, #4]
 8001c94:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
 8001c96:	2200      	movs	r2, #0
 8001c98:	2120      	movs	r1, #32
 8001c9a:	4812      	ldr	r0, [pc, #72]	; (8001ce4 <MX_GPIO_Init+0xd4>)
 8001c9c:	f000 fc82 	bl	80025a4 <HAL_GPIO_WritePin>

  /*Configure GPIO pin : B1_Pin */
  GPIO_InitStruct.Pin = B1_Pin;
 8001ca0:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8001ca4:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 8001ca6:	4b10      	ldr	r3, [pc, #64]	; (8001ce8 <MX_GPIO_Init+0xd8>)
 8001ca8:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001caa:	2300      	movs	r3, #0
 8001cac:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
 8001cae:	f107 0314 	add.w	r3, r7, #20
 8001cb2:	4619      	mov	r1, r3
 8001cb4:	480d      	ldr	r0, [pc, #52]	; (8001cec <MX_GPIO_Init+0xdc>)
 8001cb6:	f000 faf3 	bl	80022a0 <HAL_GPIO_Init>

  /*Configure GPIO pin : LD2_Pin */
  GPIO_InitStruct.Pin = LD2_Pin;
 8001cba:	2320      	movs	r3, #32
 8001cbc:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8001cbe:	2301      	movs	r3, #1
 8001cc0:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001cc2:	2300      	movs	r3, #0
 8001cc4:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001cc6:	2300      	movs	r3, #0
 8001cc8:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
 8001cca:	f107 0314 	add.w	r3, r7, #20
 8001cce:	4619      	mov	r1, r3
 8001cd0:	4804      	ldr	r0, [pc, #16]	; (8001ce4 <MX_GPIO_Init+0xd4>)
 8001cd2:	f000 fae5 	bl	80022a0 <HAL_GPIO_Init>

}
 8001cd6:	bf00      	nop
 8001cd8:	3728      	adds	r7, #40	; 0x28
 8001cda:	46bd      	mov	sp, r7
 8001cdc:	bd80      	pop	{r7, pc}
 8001cde:	bf00      	nop
 8001ce0:	40023800 	.word	0x40023800
 8001ce4:	40020000 	.word	0x40020000
 8001ce8:	10210000 	.word	0x10210000
 8001cec:	40020800 	.word	0x40020800

08001cf0 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8001cf0:	b480      	push	{r7}
 8001cf2:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8001cf4:	b672      	cpsid	i
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8001cf6:	e7fe      	b.n	8001cf6 <Error_Handler+0x6>

08001cf8 <HAL_RTC_AlarmAEventCallback>:
  * @brief  Alarm callback
  * @param  hrtc: RTC handle
  * @retval None
  */
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
 8001cf8:	b580      	push	{r7, lr}
 8001cfa:	b082      	sub	sp, #8
 8001cfc:	af00      	add	r7, sp, #0
 8001cfe:	6078      	str	r0, [r7, #4]
  /* Alarm generation */
  transmit_uart("Alarm!!!!\r\n");
 8001d00:	4803      	ldr	r0, [pc, #12]	; (8001d10 <HAL_RTC_AlarmAEventCallback+0x18>)
 8001d02:	f7ff fd81 	bl	8001808 <transmit_uart>
}
 8001d06:	bf00      	nop
 8001d08:	3708      	adds	r7, #8
 8001d0a:	46bd      	mov	sp, r7
 8001d0c:	bd80      	pop	{r7, pc}
 8001d0e:	bf00      	nop
 8001d10:	0800600c 	.word	0x0800600c

08001d14 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8001d14:	b580      	push	{r7, lr}
 8001d16:	b082      	sub	sp, #8
 8001d18:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001d1a:	2300      	movs	r3, #0
 8001d1c:	607b      	str	r3, [r7, #4]
 8001d1e:	4b10      	ldr	r3, [pc, #64]	; (8001d60 <HAL_MspInit+0x4c>)
 8001d20:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8001d22:	4a0f      	ldr	r2, [pc, #60]	; (8001d60 <HAL_MspInit+0x4c>)
 8001d24:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8001d28:	6453      	str	r3, [r2, #68]	; 0x44
 8001d2a:	4b0d      	ldr	r3, [pc, #52]	; (8001d60 <HAL_MspInit+0x4c>)
 8001d2c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8001d2e:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8001d32:	607b      	str	r3, [r7, #4]
 8001d34:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8001d36:	2300      	movs	r3, #0
 8001d38:	603b      	str	r3, [r7, #0]
 8001d3a:	4b09      	ldr	r3, [pc, #36]	; (8001d60 <HAL_MspInit+0x4c>)
 8001d3c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001d3e:	4a08      	ldr	r2, [pc, #32]	; (8001d60 <HAL_MspInit+0x4c>)
 8001d40:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001d44:	6413      	str	r3, [r2, #64]	; 0x40
 8001d46:	4b06      	ldr	r3, [pc, #24]	; (8001d60 <HAL_MspInit+0x4c>)
 8001d48:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001d4a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001d4e:	603b      	str	r3, [r7, #0]
 8001d50:	683b      	ldr	r3, [r7, #0]

  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
 8001d52:	2007      	movs	r0, #7
 8001d54:	f000 fa62 	bl	800221c <HAL_NVIC_SetPriorityGrouping>
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8001d58:	bf00      	nop
 8001d5a:	3708      	adds	r7, #8
 8001d5c:	46bd      	mov	sp, r7
 8001d5e:	bd80      	pop	{r7, pc}
 8001d60:	40023800 	.word	0x40023800

08001d64 <HAL_RTC_MspInit>:
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
 8001d64:	b580      	push	{r7, lr}
 8001d66:	b082      	sub	sp, #8
 8001d68:	af00      	add	r7, sp, #0
 8001d6a:	6078      	str	r0, [r7, #4]
  if(hrtc->Instance==RTC)
 8001d6c:	687b      	ldr	r3, [r7, #4]
 8001d6e:	681b      	ldr	r3, [r3, #0]
 8001d70:	4a08      	ldr	r2, [pc, #32]	; (8001d94 <HAL_RTC_MspInit+0x30>)
 8001d72:	4293      	cmp	r3, r2
 8001d74:	d10a      	bne.n	8001d8c <HAL_RTC_MspInit+0x28>
  {
  /* USER CODE BEGIN RTC_MspInit 0 */

  /* USER CODE END RTC_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_RTC_ENABLE();
 8001d76:	4b08      	ldr	r3, [pc, #32]	; (8001d98 <HAL_RTC_MspInit+0x34>)
 8001d78:	2201      	movs	r2, #1
 8001d7a:	601a      	str	r2, [r3, #0]
    /* RTC interrupt Init */
    HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0);
 8001d7c:	2200      	movs	r2, #0
 8001d7e:	2100      	movs	r1, #0
 8001d80:	2029      	movs	r0, #41	; 0x29
 8001d82:	f000 fa56 	bl	8002232 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
 8001d86:	2029      	movs	r0, #41	; 0x29
 8001d88:	f000 fa6f 	bl	800226a <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN RTC_MspInit 1 */

  /* USER CODE END RTC_MspInit 1 */
  }

}
 8001d8c:	bf00      	nop
 8001d8e:	3708      	adds	r7, #8
 8001d90:	46bd      	mov	sp, r7
 8001d92:	bd80      	pop	{r7, pc}
 8001d94:	40002800 	.word	0x40002800
 8001d98:	42470e3c 	.word	0x42470e3c

08001d9c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8001d9c:	b580      	push	{r7, lr}
 8001d9e:	b08a      	sub	sp, #40	; 0x28
 8001da0:	af00      	add	r7, sp, #0
 8001da2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8001da4:	f107 0314 	add.w	r3, r7, #20
 8001da8:	2200      	movs	r2, #0
 8001daa:	601a      	str	r2, [r3, #0]
 8001dac:	605a      	str	r2, [r3, #4]
 8001dae:	609a      	str	r2, [r3, #8]
 8001db0:	60da      	str	r2, [r3, #12]
 8001db2:	611a      	str	r2, [r3, #16]
  if(huart->Instance==USART2)
 8001db4:	687b      	ldr	r3, [r7, #4]
 8001db6:	681b      	ldr	r3, [r3, #0]
 8001db8:	4a19      	ldr	r2, [pc, #100]	; (8001e20 <HAL_UART_MspInit+0x84>)
 8001dba:	4293      	cmp	r3, r2
 8001dbc:	d12b      	bne.n	8001e16 <HAL_UART_MspInit+0x7a>
  {
  /* USER CODE BEGIN USART2_MspInit 0 */

  /* USER CODE END USART2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART2_CLK_ENABLE();
 8001dbe:	2300      	movs	r3, #0
 8001dc0:	613b      	str	r3, [r7, #16]
 8001dc2:	4b18      	ldr	r3, [pc, #96]	; (8001e24 <HAL_UART_MspInit+0x88>)
 8001dc4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001dc6:	4a17      	ldr	r2, [pc, #92]	; (8001e24 <HAL_UART_MspInit+0x88>)
 8001dc8:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8001dcc:	6413      	str	r3, [r2, #64]	; 0x40
 8001dce:	4b15      	ldr	r3, [pc, #84]	; (8001e24 <HAL_UART_MspInit+0x88>)
 8001dd0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001dd2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001dd6:	613b      	str	r3, [r7, #16]
 8001dd8:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8001dda:	2300      	movs	r3, #0
 8001ddc:	60fb      	str	r3, [r7, #12]
 8001dde:	4b11      	ldr	r3, [pc, #68]	; (8001e24 <HAL_UART_MspInit+0x88>)
 8001de0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001de2:	4a10      	ldr	r2, [pc, #64]	; (8001e24 <HAL_UART_MspInit+0x88>)
 8001de4:	f043 0301 	orr.w	r3, r3, #1
 8001de8:	6313      	str	r3, [r2, #48]	; 0x30
 8001dea:	4b0e      	ldr	r3, [pc, #56]	; (8001e24 <HAL_UART_MspInit+0x88>)
 8001dec:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001dee:	f003 0301 	and.w	r3, r3, #1
 8001df2:	60fb      	str	r3, [r7, #12]
 8001df4:	68fb      	ldr	r3, [r7, #12]
    /**USART2 GPIO Configuration
    PA2     ------> USART2_TX
    PA3     ------> USART2_RX
    */
    GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
 8001df6:	230c      	movs	r3, #12
 8001df8:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8001dfa:	2302      	movs	r3, #2
 8001dfc:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8001dfe:	2300      	movs	r3, #0
 8001e00:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8001e02:	2300      	movs	r3, #0
 8001e04:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 8001e06:	2307      	movs	r3, #7
 8001e08:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8001e0a:	f107 0314 	add.w	r3, r7, #20
 8001e0e:	4619      	mov	r1, r3
 8001e10:	4805      	ldr	r0, [pc, #20]	; (8001e28 <HAL_UART_MspInit+0x8c>)
 8001e12:	f000 fa45 	bl	80022a0 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 8001e16:	bf00      	nop
 8001e18:	3728      	adds	r7, #40	; 0x28
 8001e1a:	46bd      	mov	sp, r7
 8001e1c:	bd80      	pop	{r7, pc}
 8001e1e:	bf00      	nop
 8001e20:	40004400 	.word	0x40004400
 8001e24:	40023800 	.word	0x40023800
 8001e28:	40020000 	.word	0x40020000

08001e2c <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8001e2c:	b480      	push	{r7}
 8001e2e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 8001e30:	e7fe      	b.n	8001e30 <NMI_Handler+0x4>

08001e32 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8001e32:	b480      	push	{r7}
 8001e34:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8001e36:	e7fe      	b.n	8001e36 <HardFault_Handler+0x4>

08001e38 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8001e38:	b480      	push	{r7}
 8001e3a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8001e3c:	e7fe      	b.n	8001e3c <MemManage_Handler+0x4>

08001e3e <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8001e3e:	b480      	push	{r7}
 8001e40:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8001e42:	e7fe      	b.n	8001e42 <BusFault_Handler+0x4>

08001e44 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8001e44:	b480      	push	{r7}
 8001e46:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8001e48:	e7fe      	b.n	8001e48 <UsageFault_Handler+0x4>

08001e4a <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8001e4a:	b480      	push	{r7}
 8001e4c:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8001e4e:	bf00      	nop
 8001e50:	46bd      	mov	sp, r7
 8001e52:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001e56:	4770      	bx	lr

08001e58 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8001e58:	b480      	push	{r7}
 8001e5a:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8001e5c:	bf00      	nop
 8001e5e:	46bd      	mov	sp, r7
 8001e60:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001e64:	4770      	bx	lr

08001e66 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8001e66:	b480      	push	{r7}
 8001e68:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8001e6a:	bf00      	nop
 8001e6c:	46bd      	mov	sp, r7
 8001e6e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001e72:	4770      	bx	lr

08001e74 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8001e74:	b580      	push	{r7, lr}
 8001e76:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8001e78:	f000 f89e 	bl	8001fb8 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8001e7c:	bf00      	nop
 8001e7e:	bd80      	pop	{r7, pc}

08001e80 <RTC_Alarm_IRQHandler>:

/**
  * @brief This function handles RTC alarms A and B interrupt through EXTI line 17.
  */
void RTC_Alarm_IRQHandler(void)
{
 8001e80:	b580      	push	{r7, lr}
 8001e82:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN RTC_Alarm_IRQn 0 */

  /* USER CODE END RTC_Alarm_IRQn 0 */
  HAL_RTC_AlarmIRQHandler(&hrtc);
 8001e84:	4802      	ldr	r0, [pc, #8]	; (8001e90 <RTC_Alarm_IRQHandler+0x10>)
 8001e86:	f001 fced 	bl	8003864 <HAL_RTC_AlarmIRQHandler>
  /* USER CODE BEGIN RTC_Alarm_IRQn 1 */

  /* USER CODE END RTC_Alarm_IRQn 1 */
}
 8001e8a:	bf00      	nop
 8001e8c:	bd80      	pop	{r7, pc}
 8001e8e:	bf00      	nop
 8001e90:	200000e4 	.word	0x200000e4

08001e94 <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 8001e94:	b480      	push	{r7}
 8001e96:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 8001e98:	4b08      	ldr	r3, [pc, #32]	; (8001ebc <SystemInit+0x28>)
 8001e9a:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8001e9e:	4a07      	ldr	r2, [pc, #28]	; (8001ebc <SystemInit+0x28>)
 8001ea0:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8001ea4:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88

  /* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 8001ea8:	4b04      	ldr	r3, [pc, #16]	; (8001ebc <SystemInit+0x28>)
 8001eaa:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 8001eae:	609a      	str	r2, [r3, #8]
#endif
}
 8001eb0:	bf00      	nop
 8001eb2:	46bd      	mov	sp, r7
 8001eb4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001eb8:	4770      	bx	lr
 8001eba:	bf00      	nop
 8001ebc:	e000ed00 	.word	0xe000ed00

08001ec0 <Reset_Handler>:
 8001ec0:	f8df d034 	ldr.w	sp, [pc, #52]	; 8001ef8 <LoopFillZerobss+0x14>
 8001ec4:	2100      	movs	r1, #0
 8001ec6:	e003      	b.n	8001ed0 <LoopCopyDataInit>

08001ec8 <CopyDataInit>:
 8001ec8:	4b0c      	ldr	r3, [pc, #48]	; (8001efc <LoopFillZerobss+0x18>)
 8001eca:	585b      	ldr	r3, [r3, r1]
 8001ecc:	5043      	str	r3, [r0, r1]
 8001ece:	3104      	adds	r1, #4

08001ed0 <LoopCopyDataInit>:
 8001ed0:	480b      	ldr	r0, [pc, #44]	; (8001f00 <LoopFillZerobss+0x1c>)
 8001ed2:	4b0c      	ldr	r3, [pc, #48]	; (8001f04 <LoopFillZerobss+0x20>)
 8001ed4:	1842      	adds	r2, r0, r1
 8001ed6:	429a      	cmp	r2, r3
 8001ed8:	d3f6      	bcc.n	8001ec8 <CopyDataInit>
 8001eda:	4a0b      	ldr	r2, [pc, #44]	; (8001f08 <LoopFillZerobss+0x24>)
 8001edc:	e002      	b.n	8001ee4 <LoopFillZerobss>

08001ede <FillZerobss>:
 8001ede:	2300      	movs	r3, #0
 8001ee0:	f842 3b04 	str.w	r3, [r2], #4

08001ee4 <LoopFillZerobss>:
 8001ee4:	4b09      	ldr	r3, [pc, #36]	; (8001f0c <LoopFillZerobss+0x28>)
 8001ee6:	429a      	cmp	r2, r3
 8001ee8:	d3f9      	bcc.n	8001ede <FillZerobss>
 8001eea:	f7ff ffd3 	bl	8001e94 <SystemInit>
 8001eee:	f002 fa4b 	bl	8004388 <__libc_init_array>
 8001ef2:	f7ff fc9f 	bl	8001834 <main>
 8001ef6:	4770      	bx	lr
 8001ef8:	20018000 	.word	0x20018000
 8001efc:	08006220 	.word	0x08006220
 8001f00:	20000000 	.word	0x20000000
 8001f04:	20000088 	.word	0x20000088
 8001f08:	20000088 	.word	0x20000088
 8001f0c:	20000148 	.word	0x20000148

08001f10 <ADC_IRQHandler>:
 8001f10:	e7fe      	b.n	8001f10 <ADC_IRQHandler>
	...

08001f14 <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8001f14:	b580      	push	{r7, lr}
 8001f16:	af00      	add	r7, sp, #0
  /* Configure Flash prefetch, Instruction cache, Data cache */ 
#if (INSTRUCTION_CACHE_ENABLE != 0U)
  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 8001f18:	4b0e      	ldr	r3, [pc, #56]	; (8001f54 <HAL_Init+0x40>)
 8001f1a:	681b      	ldr	r3, [r3, #0]
 8001f1c:	4a0d      	ldr	r2, [pc, #52]	; (8001f54 <HAL_Init+0x40>)
 8001f1e:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 8001f22:	6013      	str	r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */

#if (DATA_CACHE_ENABLE != 0U)
  __HAL_FLASH_DATA_CACHE_ENABLE();
 8001f24:	4b0b      	ldr	r3, [pc, #44]	; (8001f54 <HAL_Init+0x40>)
 8001f26:	681b      	ldr	r3, [r3, #0]
 8001f28:	4a0a      	ldr	r2, [pc, #40]	; (8001f54 <HAL_Init+0x40>)
 8001f2a:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 8001f2e:	6013      	str	r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0U)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8001f30:	4b08      	ldr	r3, [pc, #32]	; (8001f54 <HAL_Init+0x40>)
 8001f32:	681b      	ldr	r3, [r3, #0]
 8001f34:	4a07      	ldr	r2, [pc, #28]	; (8001f54 <HAL_Init+0x40>)
 8001f36:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001f3a:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8001f3c:	2003      	movs	r0, #3
 8001f3e:	f000 f96d 	bl	800221c <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 8001f42:	2000      	movs	r0, #0
 8001f44:	f000 f808 	bl	8001f58 <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 8001f48:	f7ff fee4 	bl	8001d14 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8001f4c:	2300      	movs	r3, #0
}
 8001f4e:	4618      	mov	r0, r3
 8001f50:	bd80      	pop	{r7, pc}
 8001f52:	bf00      	nop
 8001f54:	40023c00 	.word	0x40023c00

08001f58 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8001f58:	b580      	push	{r7, lr}
 8001f5a:	b082      	sub	sp, #8
 8001f5c:	af00      	add	r7, sp, #0
 8001f5e:	6078      	str	r0, [r7, #4]
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8001f60:	4b12      	ldr	r3, [pc, #72]	; (8001fac <HAL_InitTick+0x54>)
 8001f62:	681a      	ldr	r2, [r3, #0]
 8001f64:	4b12      	ldr	r3, [pc, #72]	; (8001fb0 <HAL_InitTick+0x58>)
 8001f66:	781b      	ldrb	r3, [r3, #0]
 8001f68:	4619      	mov	r1, r3
 8001f6a:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8001f6e:	fbb3 f3f1 	udiv	r3, r3, r1
 8001f72:	fbb2 f3f3 	udiv	r3, r2, r3
 8001f76:	4618      	mov	r0, r3
 8001f78:	f000 f985 	bl	8002286 <HAL_SYSTICK_Config>
 8001f7c:	4603      	mov	r3, r0
 8001f7e:	2b00      	cmp	r3, #0
 8001f80:	d001      	beq.n	8001f86 <HAL_InitTick+0x2e>
  {
    return HAL_ERROR;
 8001f82:	2301      	movs	r3, #1
 8001f84:	e00e      	b.n	8001fa4 <HAL_InitTick+0x4c>
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8001f86:	687b      	ldr	r3, [r7, #4]
 8001f88:	2b0f      	cmp	r3, #15
 8001f8a:	d80a      	bhi.n	8001fa2 <HAL_InitTick+0x4a>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8001f8c:	2200      	movs	r2, #0
 8001f8e:	6879      	ldr	r1, [r7, #4]
 8001f90:	f04f 30ff 	mov.w	r0, #4294967295
 8001f94:	f000 f94d 	bl	8002232 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8001f98:	4a06      	ldr	r2, [pc, #24]	; (8001fb4 <HAL_InitTick+0x5c>)
 8001f9a:	687b      	ldr	r3, [r7, #4]
 8001f9c:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 8001f9e:	2300      	movs	r3, #0
 8001fa0:	e000      	b.n	8001fa4 <HAL_InitTick+0x4c>
    return HAL_ERROR;
 8001fa2:	2301      	movs	r3, #1
}
 8001fa4:	4618      	mov	r0, r3
 8001fa6:	3708      	adds	r7, #8
 8001fa8:	46bd      	mov	sp, r7
 8001faa:	bd80      	pop	{r7, pc}
 8001fac:	20000014 	.word	0x20000014
 8001fb0:	2000001c 	.word	0x2000001c
 8001fb4:	20000018 	.word	0x20000018

08001fb8 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other 
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8001fb8:	b480      	push	{r7}
 8001fba:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8001fbc:	4b06      	ldr	r3, [pc, #24]	; (8001fd8 <HAL_IncTick+0x20>)
 8001fbe:	781b      	ldrb	r3, [r3, #0]
 8001fc0:	461a      	mov	r2, r3
 8001fc2:	4b06      	ldr	r3, [pc, #24]	; (8001fdc <HAL_IncTick+0x24>)
 8001fc4:	681b      	ldr	r3, [r3, #0]
 8001fc6:	4413      	add	r3, r2
 8001fc8:	4a04      	ldr	r2, [pc, #16]	; (8001fdc <HAL_IncTick+0x24>)
 8001fca:	6013      	str	r3, [r2, #0]
}
 8001fcc:	bf00      	nop
 8001fce:	46bd      	mov	sp, r7
 8001fd0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001fd4:	4770      	bx	lr
 8001fd6:	bf00      	nop
 8001fd8:	2000001c 	.word	0x2000001c
 8001fdc:	20000144 	.word	0x20000144

08001fe0 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other 
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8001fe0:	b480      	push	{r7}
 8001fe2:	af00      	add	r7, sp, #0
  return uwTick;
 8001fe4:	4b03      	ldr	r3, [pc, #12]	; (8001ff4 <HAL_GetTick+0x14>)
 8001fe6:	681b      	ldr	r3, [r3, #0]
}
 8001fe8:	4618      	mov	r0, r3
 8001fea:	46bd      	mov	sp, r7
 8001fec:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001ff0:	4770      	bx	lr
 8001ff2:	bf00      	nop
 8001ff4:	20000144 	.word	0x20000144

08001ff8 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 8001ff8:	b580      	push	{r7, lr}
 8001ffa:	b084      	sub	sp, #16
 8001ffc:	af00      	add	r7, sp, #0
 8001ffe:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8002000:	f7ff ffee 	bl	8001fe0 <HAL_GetTick>
 8002004:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 8002006:	687b      	ldr	r3, [r7, #4]
 8002008:	60fb      	str	r3, [r7, #12]

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 800200a:	68fb      	ldr	r3, [r7, #12]
 800200c:	f1b3 3fff 	cmp.w	r3, #4294967295
 8002010:	d005      	beq.n	800201e <HAL_Delay+0x26>
  {
    wait += (uint32_t)(uwTickFreq);
 8002012:	4b09      	ldr	r3, [pc, #36]	; (8002038 <HAL_Delay+0x40>)
 8002014:	781b      	ldrb	r3, [r3, #0]
 8002016:	461a      	mov	r2, r3
 8002018:	68fb      	ldr	r3, [r7, #12]
 800201a:	4413      	add	r3, r2
 800201c:	60fb      	str	r3, [r7, #12]
  }

  while((HAL_GetTick() - tickstart) < wait)
 800201e:	bf00      	nop
 8002020:	f7ff ffde 	bl	8001fe0 <HAL_GetTick>
 8002024:	4602      	mov	r2, r0
 8002026:	68bb      	ldr	r3, [r7, #8]
 8002028:	1ad3      	subs	r3, r2, r3
 800202a:	68fa      	ldr	r2, [r7, #12]
 800202c:	429a      	cmp	r2, r3
 800202e:	d8f7      	bhi.n	8002020 <HAL_Delay+0x28>
  {
  }
}
 8002030:	bf00      	nop
 8002032:	3710      	adds	r7, #16
 8002034:	46bd      	mov	sp, r7
 8002036:	bd80      	pop	{r7, pc}
 8002038:	2000001c 	.word	0x2000001c

0800203c <HAL_SuspendTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval None
  */
__weak void HAL_SuspendTick(void)
{
 800203c:	b480      	push	{r7}
 800203e:	af00      	add	r7, sp, #0
  /* Disable SysTick Interrupt */
  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
 8002040:	4b05      	ldr	r3, [pc, #20]	; (8002058 <HAL_SuspendTick+0x1c>)
 8002042:	681b      	ldr	r3, [r3, #0]
 8002044:	4a04      	ldr	r2, [pc, #16]	; (8002058 <HAL_SuspendTick+0x1c>)
 8002046:	f023 0302 	bic.w	r3, r3, #2
 800204a:	6013      	str	r3, [r2, #0]
}
 800204c:	bf00      	nop
 800204e:	46bd      	mov	sp, r7
 8002050:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002054:	4770      	bx	lr
 8002056:	bf00      	nop
 8002058:	e000e010 	.word	0xe000e010

0800205c <HAL_ResumeTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval None
  */
__weak void HAL_ResumeTick(void)
{
 800205c:	b480      	push	{r7}
 800205e:	af00      	add	r7, sp, #0
  /* Enable SysTick Interrupt */
  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
 8002060:	4b05      	ldr	r3, [pc, #20]	; (8002078 <HAL_ResumeTick+0x1c>)
 8002062:	681b      	ldr	r3, [r3, #0]
 8002064:	4a04      	ldr	r2, [pc, #16]	; (8002078 <HAL_ResumeTick+0x1c>)
 8002066:	f043 0302 	orr.w	r3, r3, #2
 800206a:	6013      	str	r3, [r2, #0]
}
 800206c:	bf00      	nop
 800206e:	46bd      	mov	sp, r7
 8002070:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002074:	4770      	bx	lr
 8002076:	bf00      	nop
 8002078:	e000e010 	.word	0xe000e010

0800207c <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 800207c:	b480      	push	{r7}
 800207e:	b085      	sub	sp, #20
 8002080:	af00      	add	r7, sp, #0
 8002082:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8002084:	687b      	ldr	r3, [r7, #4]
 8002086:	f003 0307 	and.w	r3, r3, #7
 800208a:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 800208c:	4b0c      	ldr	r3, [pc, #48]	; (80020c0 <__NVIC_SetPriorityGrouping+0x44>)
 800208e:	68db      	ldr	r3, [r3, #12]
 8002090:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8002092:	68ba      	ldr	r2, [r7, #8]
 8002094:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 8002098:	4013      	ands	r3, r2
 800209a:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 800209c:	68fb      	ldr	r3, [r7, #12]
 800209e:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 80020a0:	68bb      	ldr	r3, [r7, #8]
 80020a2:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 80020a4:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 80020a8:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 80020ac:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80020ae:	4a04      	ldr	r2, [pc, #16]	; (80020c0 <__NVIC_SetPriorityGrouping+0x44>)
 80020b0:	68bb      	ldr	r3, [r7, #8]
 80020b2:	60d3      	str	r3, [r2, #12]
}
 80020b4:	bf00      	nop
 80020b6:	3714      	adds	r7, #20
 80020b8:	46bd      	mov	sp, r7
 80020ba:	f85d 7b04 	ldr.w	r7, [sp], #4
 80020be:	4770      	bx	lr
 80020c0:	e000ed00 	.word	0xe000ed00

080020c4 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80020c4:	b480      	push	{r7}
 80020c6:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80020c8:	4b04      	ldr	r3, [pc, #16]	; (80020dc <__NVIC_GetPriorityGrouping+0x18>)
 80020ca:	68db      	ldr	r3, [r3, #12]
 80020cc:	0a1b      	lsrs	r3, r3, #8
 80020ce:	f003 0307 	and.w	r3, r3, #7
}
 80020d2:	4618      	mov	r0, r3
 80020d4:	46bd      	mov	sp, r7
 80020d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80020da:	4770      	bx	lr
 80020dc:	e000ed00 	.word	0xe000ed00

080020e0 <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80020e0:	b480      	push	{r7}
 80020e2:	b083      	sub	sp, #12
 80020e4:	af00      	add	r7, sp, #0
 80020e6:	4603      	mov	r3, r0
 80020e8:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80020ea:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80020ee:	2b00      	cmp	r3, #0
 80020f0:	db0b      	blt.n	800210a <__NVIC_EnableIRQ+0x2a>
  {
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80020f2:	79fb      	ldrb	r3, [r7, #7]
 80020f4:	f003 021f 	and.w	r2, r3, #31
 80020f8:	4907      	ldr	r1, [pc, #28]	; (8002118 <__NVIC_EnableIRQ+0x38>)
 80020fa:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80020fe:	095b      	lsrs	r3, r3, #5
 8002100:	2001      	movs	r0, #1
 8002102:	fa00 f202 	lsl.w	r2, r0, r2
 8002106:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  }
}
 800210a:	bf00      	nop
 800210c:	370c      	adds	r7, #12
 800210e:	46bd      	mov	sp, r7
 8002110:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002114:	4770      	bx	lr
 8002116:	bf00      	nop
 8002118:	e000e100 	.word	0xe000e100

0800211c <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 800211c:	b480      	push	{r7}
 800211e:	b083      	sub	sp, #12
 8002120:	af00      	add	r7, sp, #0
 8002122:	4603      	mov	r3, r0
 8002124:	6039      	str	r1, [r7, #0]
 8002126:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8002128:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800212c:	2b00      	cmp	r3, #0
 800212e:	db0a      	blt.n	8002146 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8002130:	683b      	ldr	r3, [r7, #0]
 8002132:	b2da      	uxtb	r2, r3
 8002134:	490c      	ldr	r1, [pc, #48]	; (8002168 <__NVIC_SetPriority+0x4c>)
 8002136:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800213a:	0112      	lsls	r2, r2, #4
 800213c:	b2d2      	uxtb	r2, r2
 800213e:	440b      	add	r3, r1
 8002140:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8002144:	e00a      	b.n	800215c <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8002146:	683b      	ldr	r3, [r7, #0]
 8002148:	b2da      	uxtb	r2, r3
 800214a:	4908      	ldr	r1, [pc, #32]	; (800216c <__NVIC_SetPriority+0x50>)
 800214c:	79fb      	ldrb	r3, [r7, #7]
 800214e:	f003 030f 	and.w	r3, r3, #15
 8002152:	3b04      	subs	r3, #4
 8002154:	0112      	lsls	r2, r2, #4
 8002156:	b2d2      	uxtb	r2, r2
 8002158:	440b      	add	r3, r1
 800215a:	761a      	strb	r2, [r3, #24]
}
 800215c:	bf00      	nop
 800215e:	370c      	adds	r7, #12
 8002160:	46bd      	mov	sp, r7
 8002162:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002166:	4770      	bx	lr
 8002168:	e000e100 	.word	0xe000e100
 800216c:	e000ed00 	.word	0xe000ed00

08002170 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8002170:	b480      	push	{r7}
 8002172:	b089      	sub	sp, #36	; 0x24
 8002174:	af00      	add	r7, sp, #0
 8002176:	60f8      	str	r0, [r7, #12]
 8002178:	60b9      	str	r1, [r7, #8]
 800217a:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 800217c:	68fb      	ldr	r3, [r7, #12]
 800217e:	f003 0307 	and.w	r3, r3, #7
 8002182:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8002184:	69fb      	ldr	r3, [r7, #28]
 8002186:	f1c3 0307 	rsb	r3, r3, #7
 800218a:	2b04      	cmp	r3, #4
 800218c:	bf28      	it	cs
 800218e:	2304      	movcs	r3, #4
 8002190:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8002192:	69fb      	ldr	r3, [r7, #28]
 8002194:	3304      	adds	r3, #4
 8002196:	2b06      	cmp	r3, #6
 8002198:	d902      	bls.n	80021a0 <NVIC_EncodePriority+0x30>
 800219a:	69fb      	ldr	r3, [r7, #28]
 800219c:	3b03      	subs	r3, #3
 800219e:	e000      	b.n	80021a2 <NVIC_EncodePriority+0x32>
 80021a0:	2300      	movs	r3, #0
 80021a2:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80021a4:	f04f 32ff 	mov.w	r2, #4294967295
 80021a8:	69bb      	ldr	r3, [r7, #24]
 80021aa:	fa02 f303 	lsl.w	r3, r2, r3
 80021ae:	43da      	mvns	r2, r3
 80021b0:	68bb      	ldr	r3, [r7, #8]
 80021b2:	401a      	ands	r2, r3
 80021b4:	697b      	ldr	r3, [r7, #20]
 80021b6:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 80021b8:	f04f 31ff 	mov.w	r1, #4294967295
 80021bc:	697b      	ldr	r3, [r7, #20]
 80021be:	fa01 f303 	lsl.w	r3, r1, r3
 80021c2:	43d9      	mvns	r1, r3
 80021c4:	687b      	ldr	r3, [r7, #4]
 80021c6:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80021c8:	4313      	orrs	r3, r2
         );
}
 80021ca:	4618      	mov	r0, r3
 80021cc:	3724      	adds	r7, #36	; 0x24
 80021ce:	46bd      	mov	sp, r7
 80021d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80021d4:	4770      	bx	lr
	...

080021d8 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 80021d8:	b580      	push	{r7, lr}
 80021da:	b082      	sub	sp, #8
 80021dc:	af00      	add	r7, sp, #0
 80021de:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80021e0:	687b      	ldr	r3, [r7, #4]
 80021e2:	3b01      	subs	r3, #1
 80021e4:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 80021e8:	d301      	bcc.n	80021ee <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 80021ea:	2301      	movs	r3, #1
 80021ec:	e00f      	b.n	800220e <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80021ee:	4a0a      	ldr	r2, [pc, #40]	; (8002218 <SysTick_Config+0x40>)
 80021f0:	687b      	ldr	r3, [r7, #4]
 80021f2:	3b01      	subs	r3, #1
 80021f4:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 80021f6:	210f      	movs	r1, #15
 80021f8:	f04f 30ff 	mov.w	r0, #4294967295
 80021fc:	f7ff ff8e 	bl	800211c <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8002200:	4b05      	ldr	r3, [pc, #20]	; (8002218 <SysTick_Config+0x40>)
 8002202:	2200      	movs	r2, #0
 8002204:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8002206:	4b04      	ldr	r3, [pc, #16]	; (8002218 <SysTick_Config+0x40>)
 8002208:	2207      	movs	r2, #7
 800220a:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 800220c:	2300      	movs	r3, #0
}
 800220e:	4618      	mov	r0, r3
 8002210:	3708      	adds	r7, #8
 8002212:	46bd      	mov	sp, r7
 8002214:	bd80      	pop	{r7, pc}
 8002216:	bf00      	nop
 8002218:	e000e010 	.word	0xe000e010

0800221c <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 800221c:	b580      	push	{r7, lr}
 800221e:	b082      	sub	sp, #8
 8002220:	af00      	add	r7, sp, #0
 8002222:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8002224:	6878      	ldr	r0, [r7, #4]
 8002226:	f7ff ff29 	bl	800207c <__NVIC_SetPriorityGrouping>
}
 800222a:	bf00      	nop
 800222c:	3708      	adds	r7, #8
 800222e:	46bd      	mov	sp, r7
 8002230:	bd80      	pop	{r7, pc}

08002232 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 8002232:	b580      	push	{r7, lr}
 8002234:	b086      	sub	sp, #24
 8002236:	af00      	add	r7, sp, #0
 8002238:	4603      	mov	r3, r0
 800223a:	60b9      	str	r1, [r7, #8]
 800223c:	607a      	str	r2, [r7, #4]
 800223e:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 8002240:	2300      	movs	r3, #0
 8002242:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 8002244:	f7ff ff3e 	bl	80020c4 <__NVIC_GetPriorityGrouping>
 8002248:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 800224a:	687a      	ldr	r2, [r7, #4]
 800224c:	68b9      	ldr	r1, [r7, #8]
 800224e:	6978      	ldr	r0, [r7, #20]
 8002250:	f7ff ff8e 	bl	8002170 <NVIC_EncodePriority>
 8002254:	4602      	mov	r2, r0
 8002256:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800225a:	4611      	mov	r1, r2
 800225c:	4618      	mov	r0, r3
 800225e:	f7ff ff5d 	bl	800211c <__NVIC_SetPriority>
}
 8002262:	bf00      	nop
 8002264:	3718      	adds	r7, #24
 8002266:	46bd      	mov	sp, r7
 8002268:	bd80      	pop	{r7, pc}

0800226a <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 800226a:	b580      	push	{r7, lr}
 800226c:	b082      	sub	sp, #8
 800226e:	af00      	add	r7, sp, #0
 8002270:	4603      	mov	r3, r0
 8002272:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8002274:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8002278:	4618      	mov	r0, r3
 800227a:	f7ff ff31 	bl	80020e0 <__NVIC_EnableIRQ>
}
 800227e:	bf00      	nop
 8002280:	3708      	adds	r7, #8
 8002282:	46bd      	mov	sp, r7
 8002284:	bd80      	pop	{r7, pc}

08002286 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8002286:	b580      	push	{r7, lr}
 8002288:	b082      	sub	sp, #8
 800228a:	af00      	add	r7, sp, #0
 800228c:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 800228e:	6878      	ldr	r0, [r7, #4]
 8002290:	f7ff ffa2 	bl	80021d8 <SysTick_Config>
 8002294:	4603      	mov	r3, r0
}
 8002296:	4618      	mov	r0, r3
 8002298:	3708      	adds	r7, #8
 800229a:	46bd      	mov	sp, r7
 800229c:	bd80      	pop	{r7, pc}
	...

080022a0 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 80022a0:	b480      	push	{r7}
 80022a2:	b089      	sub	sp, #36	; 0x24
 80022a4:	af00      	add	r7, sp, #0
 80022a6:	6078      	str	r0, [r7, #4]
 80022a8:	6039      	str	r1, [r7, #0]
  uint32_t position;
  uint32_t ioposition = 0x00U;
 80022aa:	2300      	movs	r3, #0
 80022ac:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00U;
 80022ae:	2300      	movs	r3, #0
 80022b0:	613b      	str	r3, [r7, #16]
  uint32_t temp = 0x00U;
 80022b2:	2300      	movs	r3, #0
 80022b4:	61bb      	str	r3, [r7, #24]
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

  /* Configure the port pins */
  for(position = 0U; position < GPIO_NUMBER; position++)
 80022b6:	2300      	movs	r3, #0
 80022b8:	61fb      	str	r3, [r7, #28]
 80022ba:	e159      	b.n	8002570 <HAL_GPIO_Init+0x2d0>
  {
    /* Get the IO position */
    ioposition = 0x01U << position;
 80022bc:	2201      	movs	r2, #1
 80022be:	69fb      	ldr	r3, [r7, #28]
 80022c0:	fa02 f303 	lsl.w	r3, r2, r3
 80022c4:	617b      	str	r3, [r7, #20]
    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80022c6:	683b      	ldr	r3, [r7, #0]
 80022c8:	681b      	ldr	r3, [r3, #0]
 80022ca:	697a      	ldr	r2, [r7, #20]
 80022cc:	4013      	ands	r3, r2
 80022ce:	613b      	str	r3, [r7, #16]

    if(iocurrent == ioposition)
 80022d0:	693a      	ldr	r2, [r7, #16]
 80022d2:	697b      	ldr	r3, [r7, #20]
 80022d4:	429a      	cmp	r2, r3
 80022d6:	f040 8148 	bne.w	800256a <HAL_GPIO_Init+0x2ca>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
 80022da:	683b      	ldr	r3, [r7, #0]
 80022dc:	685b      	ldr	r3, [r3, #4]
 80022de:	2b01      	cmp	r3, #1
 80022e0:	d00b      	beq.n	80022fa <HAL_GPIO_Init+0x5a>
 80022e2:	683b      	ldr	r3, [r7, #0]
 80022e4:	685b      	ldr	r3, [r3, #4]
 80022e6:	2b02      	cmp	r3, #2
 80022e8:	d007      	beq.n	80022fa <HAL_GPIO_Init+0x5a>
         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
 80022ea:	683b      	ldr	r3, [r7, #0]
 80022ec:	685b      	ldr	r3, [r3, #4]
      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
 80022ee:	2b11      	cmp	r3, #17
 80022f0:	d003      	beq.n	80022fa <HAL_GPIO_Init+0x5a>
         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
 80022f2:	683b      	ldr	r3, [r7, #0]
 80022f4:	685b      	ldr	r3, [r3, #4]
 80022f6:	2b12      	cmp	r3, #18
 80022f8:	d130      	bne.n	800235c <HAL_GPIO_Init+0xbc>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR; 
 80022fa:	687b      	ldr	r3, [r7, #4]
 80022fc:	689b      	ldr	r3, [r3, #8]
 80022fe:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
 8002300:	69fb      	ldr	r3, [r7, #28]
 8002302:	005b      	lsls	r3, r3, #1
 8002304:	2203      	movs	r2, #3
 8002306:	fa02 f303 	lsl.w	r3, r2, r3
 800230a:	43db      	mvns	r3, r3
 800230c:	69ba      	ldr	r2, [r7, #24]
 800230e:	4013      	ands	r3, r2
 8002310:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 8002312:	683b      	ldr	r3, [r7, #0]
 8002314:	68da      	ldr	r2, [r3, #12]
 8002316:	69fb      	ldr	r3, [r7, #28]
 8002318:	005b      	lsls	r3, r3, #1
 800231a:	fa02 f303 	lsl.w	r3, r2, r3
 800231e:	69ba      	ldr	r2, [r7, #24]
 8002320:	4313      	orrs	r3, r2
 8002322:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 8002324:	687b      	ldr	r3, [r7, #4]
 8002326:	69ba      	ldr	r2, [r7, #24]
 8002328:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 800232a:	687b      	ldr	r3, [r7, #4]
 800232c:	685b      	ldr	r3, [r3, #4]
 800232e:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
 8002330:	2201      	movs	r2, #1
 8002332:	69fb      	ldr	r3, [r7, #28]
 8002334:	fa02 f303 	lsl.w	r3, r2, r3
 8002338:	43db      	mvns	r3, r3
 800233a:	69ba      	ldr	r2, [r7, #24]
 800233c:	4013      	ands	r3, r2
 800233e:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
 8002340:	683b      	ldr	r3, [r7, #0]
 8002342:	685b      	ldr	r3, [r3, #4]
 8002344:	091b      	lsrs	r3, r3, #4
 8002346:	f003 0201 	and.w	r2, r3, #1
 800234a:	69fb      	ldr	r3, [r7, #28]
 800234c:	fa02 f303 	lsl.w	r3, r2, r3
 8002350:	69ba      	ldr	r2, [r7, #24]
 8002352:	4313      	orrs	r3, r2
 8002354:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 8002356:	687b      	ldr	r3, [r7, #4]
 8002358:	69ba      	ldr	r2, [r7, #24]
 800235a:	605a      	str	r2, [r3, #4]
       }

      /* Activate the Pull-up or Pull down resistor for the current IO */
      temp = GPIOx->PUPDR;
 800235c:	687b      	ldr	r3, [r7, #4]
 800235e:	68db      	ldr	r3, [r3, #12]
 8002360:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
 8002362:	69fb      	ldr	r3, [r7, #28]
 8002364:	005b      	lsls	r3, r3, #1
 8002366:	2203      	movs	r2, #3
 8002368:	fa02 f303 	lsl.w	r3, r2, r3
 800236c:	43db      	mvns	r3, r3
 800236e:	69ba      	ldr	r2, [r7, #24]
 8002370:	4013      	ands	r3, r2
 8002372:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Pull) << (position * 2U));
 8002374:	683b      	ldr	r3, [r7, #0]
 8002376:	689a      	ldr	r2, [r3, #8]
 8002378:	69fb      	ldr	r3, [r7, #28]
 800237a:	005b      	lsls	r3, r3, #1
 800237c:	fa02 f303 	lsl.w	r3, r2, r3
 8002380:	69ba      	ldr	r2, [r7, #24]
 8002382:	4313      	orrs	r3, r2
 8002384:	61bb      	str	r3, [r7, #24]
      GPIOx->PUPDR = temp;
 8002386:	687b      	ldr	r3, [r7, #4]
 8002388:	69ba      	ldr	r2, [r7, #24]
 800238a:	60da      	str	r2, [r3, #12]

      /* In case of Alternate function mode selection */
      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
 800238c:	683b      	ldr	r3, [r7, #0]
 800238e:	685b      	ldr	r3, [r3, #4]
 8002390:	2b02      	cmp	r3, #2
 8002392:	d003      	beq.n	800239c <HAL_GPIO_Init+0xfc>
 8002394:	683b      	ldr	r3, [r7, #0]
 8002396:	685b      	ldr	r3, [r3, #4]
 8002398:	2b12      	cmp	r3, #18
 800239a:	d123      	bne.n	80023e4 <HAL_GPIO_Init+0x144>
      {
        /* Check the Alternate function parameter */
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 800239c:	69fb      	ldr	r3, [r7, #28]
 800239e:	08da      	lsrs	r2, r3, #3
 80023a0:	687b      	ldr	r3, [r7, #4]
 80023a2:	3208      	adds	r2, #8
 80023a4:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 80023a8:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
 80023aa:	69fb      	ldr	r3, [r7, #28]
 80023ac:	f003 0307 	and.w	r3, r3, #7
 80023b0:	009b      	lsls	r3, r3, #2
 80023b2:	220f      	movs	r2, #15
 80023b4:	fa02 f303 	lsl.w	r3, r2, r3
 80023b8:	43db      	mvns	r3, r3
 80023ba:	69ba      	ldr	r2, [r7, #24]
 80023bc:	4013      	ands	r3, r2
 80023be:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
 80023c0:	683b      	ldr	r3, [r7, #0]
 80023c2:	691a      	ldr	r2, [r3, #16]
 80023c4:	69fb      	ldr	r3, [r7, #28]
 80023c6:	f003 0307 	and.w	r3, r3, #7
 80023ca:	009b      	lsls	r3, r3, #2
 80023cc:	fa02 f303 	lsl.w	r3, r2, r3
 80023d0:	69ba      	ldr	r2, [r7, #24]
 80023d2:	4313      	orrs	r3, r2
 80023d4:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 80023d6:	69fb      	ldr	r3, [r7, #28]
 80023d8:	08da      	lsrs	r2, r3, #3
 80023da:	687b      	ldr	r3, [r7, #4]
 80023dc:	3208      	adds	r2, #8
 80023de:	69b9      	ldr	r1, [r7, #24]
 80023e0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 80023e4:	687b      	ldr	r3, [r7, #4]
 80023e6:	681b      	ldr	r3, [r3, #0]
 80023e8:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
 80023ea:	69fb      	ldr	r3, [r7, #28]
 80023ec:	005b      	lsls	r3, r3, #1
 80023ee:	2203      	movs	r2, #3
 80023f0:	fa02 f303 	lsl.w	r3, r2, r3
 80023f4:	43db      	mvns	r3, r3
 80023f6:	69ba      	ldr	r2, [r7, #24]
 80023f8:	4013      	ands	r3, r2
 80023fa:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 80023fc:	683b      	ldr	r3, [r7, #0]
 80023fe:	685b      	ldr	r3, [r3, #4]
 8002400:	f003 0203 	and.w	r2, r3, #3
 8002404:	69fb      	ldr	r3, [r7, #28]
 8002406:	005b      	lsls	r3, r3, #1
 8002408:	fa02 f303 	lsl.w	r3, r2, r3
 800240c:	69ba      	ldr	r2, [r7, #24]
 800240e:	4313      	orrs	r3, r2
 8002410:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 8002412:	687b      	ldr	r3, [r7, #4]
 8002414:	69ba      	ldr	r2, [r7, #24]
 8002416:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8002418:	683b      	ldr	r3, [r7, #0]
 800241a:	685b      	ldr	r3, [r3, #4]
 800241c:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002420:	2b00      	cmp	r3, #0
 8002422:	f000 80a2 	beq.w	800256a <HAL_GPIO_Init+0x2ca>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8002426:	2300      	movs	r3, #0
 8002428:	60fb      	str	r3, [r7, #12]
 800242a:	4b56      	ldr	r3, [pc, #344]	; (8002584 <HAL_GPIO_Init+0x2e4>)
 800242c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800242e:	4a55      	ldr	r2, [pc, #340]	; (8002584 <HAL_GPIO_Init+0x2e4>)
 8002430:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8002434:	6453      	str	r3, [r2, #68]	; 0x44
 8002436:	4b53      	ldr	r3, [pc, #332]	; (8002584 <HAL_GPIO_Init+0x2e4>)
 8002438:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800243a:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 800243e:	60fb      	str	r3, [r7, #12]
 8002440:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 8002442:	4a51      	ldr	r2, [pc, #324]	; (8002588 <HAL_GPIO_Init+0x2e8>)
 8002444:	69fb      	ldr	r3, [r7, #28]
 8002446:	089b      	lsrs	r3, r3, #2
 8002448:	3302      	adds	r3, #2
 800244a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 800244e:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FU << (4U * (position & 0x03U)));
 8002450:	69fb      	ldr	r3, [r7, #28]
 8002452:	f003 0303 	and.w	r3, r3, #3
 8002456:	009b      	lsls	r3, r3, #2
 8002458:	220f      	movs	r2, #15
 800245a:	fa02 f303 	lsl.w	r3, r2, r3
 800245e:	43db      	mvns	r3, r3
 8002460:	69ba      	ldr	r2, [r7, #24]
 8002462:	4013      	ands	r3, r2
 8002464:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8002466:	687b      	ldr	r3, [r7, #4]
 8002468:	4a48      	ldr	r2, [pc, #288]	; (800258c <HAL_GPIO_Init+0x2ec>)
 800246a:	4293      	cmp	r3, r2
 800246c:	d019      	beq.n	80024a2 <HAL_GPIO_Init+0x202>
 800246e:	687b      	ldr	r3, [r7, #4]
 8002470:	4a47      	ldr	r2, [pc, #284]	; (8002590 <HAL_GPIO_Init+0x2f0>)
 8002472:	4293      	cmp	r3, r2
 8002474:	d013      	beq.n	800249e <HAL_GPIO_Init+0x1fe>
 8002476:	687b      	ldr	r3, [r7, #4]
 8002478:	4a46      	ldr	r2, [pc, #280]	; (8002594 <HAL_GPIO_Init+0x2f4>)
 800247a:	4293      	cmp	r3, r2
 800247c:	d00d      	beq.n	800249a <HAL_GPIO_Init+0x1fa>
 800247e:	687b      	ldr	r3, [r7, #4]
 8002480:	4a45      	ldr	r2, [pc, #276]	; (8002598 <HAL_GPIO_Init+0x2f8>)
 8002482:	4293      	cmp	r3, r2
 8002484:	d007      	beq.n	8002496 <HAL_GPIO_Init+0x1f6>
 8002486:	687b      	ldr	r3, [r7, #4]
 8002488:	4a44      	ldr	r2, [pc, #272]	; (800259c <HAL_GPIO_Init+0x2fc>)
 800248a:	4293      	cmp	r3, r2
 800248c:	d101      	bne.n	8002492 <HAL_GPIO_Init+0x1f2>
 800248e:	2304      	movs	r3, #4
 8002490:	e008      	b.n	80024a4 <HAL_GPIO_Init+0x204>
 8002492:	2307      	movs	r3, #7
 8002494:	e006      	b.n	80024a4 <HAL_GPIO_Init+0x204>
 8002496:	2303      	movs	r3, #3
 8002498:	e004      	b.n	80024a4 <HAL_GPIO_Init+0x204>
 800249a:	2302      	movs	r3, #2
 800249c:	e002      	b.n	80024a4 <HAL_GPIO_Init+0x204>
 800249e:	2301      	movs	r3, #1
 80024a0:	e000      	b.n	80024a4 <HAL_GPIO_Init+0x204>
 80024a2:	2300      	movs	r3, #0
 80024a4:	69fa      	ldr	r2, [r7, #28]
 80024a6:	f002 0203 	and.w	r2, r2, #3
 80024aa:	0092      	lsls	r2, r2, #2
 80024ac:	4093      	lsls	r3, r2
 80024ae:	69ba      	ldr	r2, [r7, #24]
 80024b0:	4313      	orrs	r3, r2
 80024b2:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 80024b4:	4934      	ldr	r1, [pc, #208]	; (8002588 <HAL_GPIO_Init+0x2e8>)
 80024b6:	69fb      	ldr	r3, [r7, #28]
 80024b8:	089b      	lsrs	r3, r3, #2
 80024ba:	3302      	adds	r3, #2
 80024bc:	69ba      	ldr	r2, [r7, #24]
 80024be:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 80024c2:	4b37      	ldr	r3, [pc, #220]	; (80025a0 <HAL_GPIO_Init+0x300>)
 80024c4:	681b      	ldr	r3, [r3, #0]
 80024c6:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 80024c8:	693b      	ldr	r3, [r7, #16]
 80024ca:	43db      	mvns	r3, r3
 80024cc:	69ba      	ldr	r2, [r7, #24]
 80024ce:	4013      	ands	r3, r2
 80024d0:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 80024d2:	683b      	ldr	r3, [r7, #0]
 80024d4:	685b      	ldr	r3, [r3, #4]
 80024d6:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 80024da:	2b00      	cmp	r3, #0
 80024dc:	d003      	beq.n	80024e6 <HAL_GPIO_Init+0x246>
        {
          temp |= iocurrent;
 80024de:	69ba      	ldr	r2, [r7, #24]
 80024e0:	693b      	ldr	r3, [r7, #16]
 80024e2:	4313      	orrs	r3, r2
 80024e4:	61bb      	str	r3, [r7, #24]
        }
        EXTI->IMR = temp;
 80024e6:	4a2e      	ldr	r2, [pc, #184]	; (80025a0 <HAL_GPIO_Init+0x300>)
 80024e8:	69bb      	ldr	r3, [r7, #24]
 80024ea:	6013      	str	r3, [r2, #0]

        temp = EXTI->EMR;
 80024ec:	4b2c      	ldr	r3, [pc, #176]	; (80025a0 <HAL_GPIO_Init+0x300>)
 80024ee:	685b      	ldr	r3, [r3, #4]
 80024f0:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 80024f2:	693b      	ldr	r3, [r7, #16]
 80024f4:	43db      	mvns	r3, r3
 80024f6:	69ba      	ldr	r2, [r7, #24]
 80024f8:	4013      	ands	r3, r2
 80024fa:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 80024fc:	683b      	ldr	r3, [r7, #0]
 80024fe:	685b      	ldr	r3, [r3, #4]
 8002500:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002504:	2b00      	cmp	r3, #0
 8002506:	d003      	beq.n	8002510 <HAL_GPIO_Init+0x270>
        {
          temp |= iocurrent;
 8002508:	69ba      	ldr	r2, [r7, #24]
 800250a:	693b      	ldr	r3, [r7, #16]
 800250c:	4313      	orrs	r3, r2
 800250e:	61bb      	str	r3, [r7, #24]
        }
        EXTI->EMR = temp;
 8002510:	4a23      	ldr	r2, [pc, #140]	; (80025a0 <HAL_GPIO_Init+0x300>)
 8002512:	69bb      	ldr	r3, [r7, #24]
 8002514:	6053      	str	r3, [r2, #4]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 8002516:	4b22      	ldr	r3, [pc, #136]	; (80025a0 <HAL_GPIO_Init+0x300>)
 8002518:	689b      	ldr	r3, [r3, #8]
 800251a:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 800251c:	693b      	ldr	r3, [r7, #16]
 800251e:	43db      	mvns	r3, r3
 8002520:	69ba      	ldr	r2, [r7, #24]
 8002522:	4013      	ands	r3, r2
 8002524:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8002526:	683b      	ldr	r3, [r7, #0]
 8002528:	685b      	ldr	r3, [r3, #4]
 800252a:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 800252e:	2b00      	cmp	r3, #0
 8002530:	d003      	beq.n	800253a <HAL_GPIO_Init+0x29a>
        {
          temp |= iocurrent;
 8002532:	69ba      	ldr	r2, [r7, #24]
 8002534:	693b      	ldr	r3, [r7, #16]
 8002536:	4313      	orrs	r3, r2
 8002538:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR = temp;
 800253a:	4a19      	ldr	r2, [pc, #100]	; (80025a0 <HAL_GPIO_Init+0x300>)
 800253c:	69bb      	ldr	r3, [r7, #24]
 800253e:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR;
 8002540:	4b17      	ldr	r3, [pc, #92]	; (80025a0 <HAL_GPIO_Init+0x300>)
 8002542:	68db      	ldr	r3, [r3, #12]
 8002544:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8002546:	693b      	ldr	r3, [r7, #16]
 8002548:	43db      	mvns	r3, r3
 800254a:	69ba      	ldr	r2, [r7, #24]
 800254c:	4013      	ands	r3, r2
 800254e:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8002550:	683b      	ldr	r3, [r7, #0]
 8002552:	685b      	ldr	r3, [r3, #4]
 8002554:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8002558:	2b00      	cmp	r3, #0
 800255a:	d003      	beq.n	8002564 <HAL_GPIO_Init+0x2c4>
        {
          temp |= iocurrent;
 800255c:	69ba      	ldr	r2, [r7, #24]
 800255e:	693b      	ldr	r3, [r7, #16]
 8002560:	4313      	orrs	r3, r2
 8002562:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR = temp;
 8002564:	4a0e      	ldr	r2, [pc, #56]	; (80025a0 <HAL_GPIO_Init+0x300>)
 8002566:	69bb      	ldr	r3, [r7, #24]
 8002568:	60d3      	str	r3, [r2, #12]
  for(position = 0U; position < GPIO_NUMBER; position++)
 800256a:	69fb      	ldr	r3, [r7, #28]
 800256c:	3301      	adds	r3, #1
 800256e:	61fb      	str	r3, [r7, #28]
 8002570:	69fb      	ldr	r3, [r7, #28]
 8002572:	2b0f      	cmp	r3, #15
 8002574:	f67f aea2 	bls.w	80022bc <HAL_GPIO_Init+0x1c>
      }
    }
  }
}
 8002578:	bf00      	nop
 800257a:	3724      	adds	r7, #36	; 0x24
 800257c:	46bd      	mov	sp, r7
 800257e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002582:	4770      	bx	lr
 8002584:	40023800 	.word	0x40023800
 8002588:	40013800 	.word	0x40013800
 800258c:	40020000 	.word	0x40020000
 8002590:	40020400 	.word	0x40020400
 8002594:	40020800 	.word	0x40020800
 8002598:	40020c00 	.word	0x40020c00
 800259c:	40021000 	.word	0x40021000
 80025a0:	40013c00 	.word	0x40013c00

080025a4 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 80025a4:	b480      	push	{r7}
 80025a6:	b083      	sub	sp, #12
 80025a8:	af00      	add	r7, sp, #0
 80025aa:	6078      	str	r0, [r7, #4]
 80025ac:	460b      	mov	r3, r1
 80025ae:	807b      	strh	r3, [r7, #2]
 80025b0:	4613      	mov	r3, r2
 80025b2:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 80025b4:	787b      	ldrb	r3, [r7, #1]
 80025b6:	2b00      	cmp	r3, #0
 80025b8:	d003      	beq.n	80025c2 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = GPIO_Pin;
 80025ba:	887a      	ldrh	r2, [r7, #2]
 80025bc:	687b      	ldr	r3, [r7, #4]
 80025be:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
  }
}
 80025c0:	e003      	b.n	80025ca <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 80025c2:	887b      	ldrh	r3, [r7, #2]
 80025c4:	041a      	lsls	r2, r3, #16
 80025c6:	687b      	ldr	r3, [r7, #4]
 80025c8:	619a      	str	r2, [r3, #24]
}
 80025ca:	bf00      	nop
 80025cc:	370c      	adds	r7, #12
 80025ce:	46bd      	mov	sp, r7
 80025d0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80025d4:	4770      	bx	lr
	...

080025d8 <HAL_PWR_EnterSLEEPMode>:
  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  * @retval None
  */
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
 80025d8:	b480      	push	{r7}
 80025da:	b083      	sub	sp, #12
 80025dc:	af00      	add	r7, sp, #0
 80025de:	6078      	str	r0, [r7, #4]
 80025e0:	460b      	mov	r3, r1
 80025e2:	70fb      	strb	r3, [r7, #3]
  /* Check the parameters */
  assert_param(IS_PWR_REGULATOR(Regulator));
  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));

  /* Clear SLEEPDEEP bit of Cortex System Control Register */
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 80025e4:	4b09      	ldr	r3, [pc, #36]	; (800260c <HAL_PWR_EnterSLEEPMode+0x34>)
 80025e6:	691b      	ldr	r3, [r3, #16]
 80025e8:	4a08      	ldr	r2, [pc, #32]	; (800260c <HAL_PWR_EnterSLEEPMode+0x34>)
 80025ea:	f023 0304 	bic.w	r3, r3, #4
 80025ee:	6113      	str	r3, [r2, #16]

  /* Select SLEEP mode entry -------------------------------------------------*/
  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
 80025f0:	78fb      	ldrb	r3, [r7, #3]
 80025f2:	2b01      	cmp	r3, #1
 80025f4:	d101      	bne.n	80025fa <HAL_PWR_EnterSLEEPMode+0x22>
  {   
    /* Request Wait For Interrupt */
    __WFI();
 80025f6:	bf30      	wfi
    /* Request Wait For Event */
    __SEV();
    __WFE();
    __WFE();
  }
}
 80025f8:	e002      	b.n	8002600 <HAL_PWR_EnterSLEEPMode+0x28>
    __SEV();
 80025fa:	bf40      	sev
    __WFE();
 80025fc:	bf20      	wfe
    __WFE();
 80025fe:	bf20      	wfe
}
 8002600:	bf00      	nop
 8002602:	370c      	adds	r7, #12
 8002604:	46bd      	mov	sp, r7
 8002606:	f85d 7b04 	ldr.w	r7, [sp], #4
 800260a:	4770      	bx	lr
 800260c:	e000ed00 	.word	0xe000ed00

08002610 <HAL_RCC_OscConfig>:
  *         supported by this API. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8002610:	b580      	push	{r7, lr}
 8002612:	b086      	sub	sp, #24
 8002614:	af00      	add	r7, sp, #0
 8002616:	6078      	str	r0, [r7, #4]
  uint32_t tickstart, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 8002618:	687b      	ldr	r3, [r7, #4]
 800261a:	2b00      	cmp	r3, #0
 800261c:	d101      	bne.n	8002622 <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 800261e:	2301      	movs	r3, #1
 8002620:	e25b      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8002622:	687b      	ldr	r3, [r7, #4]
 8002624:	681b      	ldr	r3, [r3, #0]
 8002626:	f003 0301 	and.w	r3, r3, #1
 800262a:	2b00      	cmp	r3, #0
 800262c:	d075      	beq.n	800271a <HAL_RCC_OscConfig+0x10a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 800262e:	4ba3      	ldr	r3, [pc, #652]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002630:	689b      	ldr	r3, [r3, #8]
 8002632:	f003 030c 	and.w	r3, r3, #12
 8002636:	2b04      	cmp	r3, #4
 8002638:	d00c      	beq.n	8002654 <HAL_RCC_OscConfig+0x44>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 800263a:	4ba0      	ldr	r3, [pc, #640]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 800263c:	689b      	ldr	r3, [r3, #8]
 800263e:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 8002642:	2b08      	cmp	r3, #8
 8002644:	d112      	bne.n	800266c <HAL_RCC_OscConfig+0x5c>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 8002646:	4b9d      	ldr	r3, [pc, #628]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002648:	685b      	ldr	r3, [r3, #4]
 800264a:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 800264e:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
 8002652:	d10b      	bne.n	800266c <HAL_RCC_OscConfig+0x5c>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8002654:	4b99      	ldr	r3, [pc, #612]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002656:	681b      	ldr	r3, [r3, #0]
 8002658:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800265c:	2b00      	cmp	r3, #0
 800265e:	d05b      	beq.n	8002718 <HAL_RCC_OscConfig+0x108>
 8002660:	687b      	ldr	r3, [r7, #4]
 8002662:	685b      	ldr	r3, [r3, #4]
 8002664:	2b00      	cmp	r3, #0
 8002666:	d157      	bne.n	8002718 <HAL_RCC_OscConfig+0x108>
      {
        return HAL_ERROR;
 8002668:	2301      	movs	r3, #1
 800266a:	e236      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800266c:	687b      	ldr	r3, [r7, #4]
 800266e:	685b      	ldr	r3, [r3, #4]
 8002670:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8002674:	d106      	bne.n	8002684 <HAL_RCC_OscConfig+0x74>
 8002676:	4b91      	ldr	r3, [pc, #580]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002678:	681b      	ldr	r3, [r3, #0]
 800267a:	4a90      	ldr	r2, [pc, #576]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 800267c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8002680:	6013      	str	r3, [r2, #0]
 8002682:	e01d      	b.n	80026c0 <HAL_RCC_OscConfig+0xb0>
 8002684:	687b      	ldr	r3, [r7, #4]
 8002686:	685b      	ldr	r3, [r3, #4]
 8002688:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 800268c:	d10c      	bne.n	80026a8 <HAL_RCC_OscConfig+0x98>
 800268e:	4b8b      	ldr	r3, [pc, #556]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002690:	681b      	ldr	r3, [r3, #0]
 8002692:	4a8a      	ldr	r2, [pc, #552]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002694:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8002698:	6013      	str	r3, [r2, #0]
 800269a:	4b88      	ldr	r3, [pc, #544]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 800269c:	681b      	ldr	r3, [r3, #0]
 800269e:	4a87      	ldr	r2, [pc, #540]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80026a0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80026a4:	6013      	str	r3, [r2, #0]
 80026a6:	e00b      	b.n	80026c0 <HAL_RCC_OscConfig+0xb0>
 80026a8:	4b84      	ldr	r3, [pc, #528]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80026aa:	681b      	ldr	r3, [r3, #0]
 80026ac:	4a83      	ldr	r2, [pc, #524]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80026ae:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 80026b2:	6013      	str	r3, [r2, #0]
 80026b4:	4b81      	ldr	r3, [pc, #516]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80026b6:	681b      	ldr	r3, [r3, #0]
 80026b8:	4a80      	ldr	r2, [pc, #512]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80026ba:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 80026be:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
 80026c0:	687b      	ldr	r3, [r7, #4]
 80026c2:	685b      	ldr	r3, [r3, #4]
 80026c4:	2b00      	cmp	r3, #0
 80026c6:	d013      	beq.n	80026f0 <HAL_RCC_OscConfig+0xe0>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80026c8:	f7ff fc8a 	bl	8001fe0 <HAL_GetTick>
 80026cc:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80026ce:	e008      	b.n	80026e2 <HAL_RCC_OscConfig+0xd2>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 80026d0:	f7ff fc86 	bl	8001fe0 <HAL_GetTick>
 80026d4:	4602      	mov	r2, r0
 80026d6:	693b      	ldr	r3, [r7, #16]
 80026d8:	1ad3      	subs	r3, r2, r3
 80026da:	2b64      	cmp	r3, #100	; 0x64
 80026dc:	d901      	bls.n	80026e2 <HAL_RCC_OscConfig+0xd2>
          {
            return HAL_TIMEOUT;
 80026de:	2303      	movs	r3, #3
 80026e0:	e1fb      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80026e2:	4b76      	ldr	r3, [pc, #472]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80026e4:	681b      	ldr	r3, [r3, #0]
 80026e6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80026ea:	2b00      	cmp	r3, #0
 80026ec:	d0f0      	beq.n	80026d0 <HAL_RCC_OscConfig+0xc0>
 80026ee:	e014      	b.n	800271a <HAL_RCC_OscConfig+0x10a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80026f0:	f7ff fc76 	bl	8001fe0 <HAL_GetTick>
 80026f4:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is bypassed or disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 80026f6:	e008      	b.n	800270a <HAL_RCC_OscConfig+0xfa>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 80026f8:	f7ff fc72 	bl	8001fe0 <HAL_GetTick>
 80026fc:	4602      	mov	r2, r0
 80026fe:	693b      	ldr	r3, [r7, #16]
 8002700:	1ad3      	subs	r3, r2, r3
 8002702:	2b64      	cmp	r3, #100	; 0x64
 8002704:	d901      	bls.n	800270a <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 8002706:	2303      	movs	r3, #3
 8002708:	e1e7      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 800270a:	4b6c      	ldr	r3, [pc, #432]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 800270c:	681b      	ldr	r3, [r3, #0]
 800270e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002712:	2b00      	cmp	r3, #0
 8002714:	d1f0      	bne.n	80026f8 <HAL_RCC_OscConfig+0xe8>
 8002716:	e000      	b.n	800271a <HAL_RCC_OscConfig+0x10a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8002718:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 800271a:	687b      	ldr	r3, [r7, #4]
 800271c:	681b      	ldr	r3, [r3, #0]
 800271e:	f003 0302 	and.w	r3, r3, #2
 8002722:	2b00      	cmp	r3, #0
 8002724:	d063      	beq.n	80027ee <HAL_RCC_OscConfig+0x1de>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8002726:	4b65      	ldr	r3, [pc, #404]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002728:	689b      	ldr	r3, [r3, #8]
 800272a:	f003 030c 	and.w	r3, r3, #12
 800272e:	2b00      	cmp	r3, #0
 8002730:	d00b      	beq.n	800274a <HAL_RCC_OscConfig+0x13a>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8002732:	4b62      	ldr	r3, [pc, #392]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002734:	689b      	ldr	r3, [r3, #8]
 8002736:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 800273a:	2b08      	cmp	r3, #8
 800273c:	d11c      	bne.n	8002778 <HAL_RCC_OscConfig+0x168>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 800273e:	4b5f      	ldr	r3, [pc, #380]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002740:	685b      	ldr	r3, [r3, #4]
 8002742:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8002746:	2b00      	cmp	r3, #0
 8002748:	d116      	bne.n	8002778 <HAL_RCC_OscConfig+0x168>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 800274a:	4b5c      	ldr	r3, [pc, #368]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 800274c:	681b      	ldr	r3, [r3, #0]
 800274e:	f003 0302 	and.w	r3, r3, #2
 8002752:	2b00      	cmp	r3, #0
 8002754:	d005      	beq.n	8002762 <HAL_RCC_OscConfig+0x152>
 8002756:	687b      	ldr	r3, [r7, #4]
 8002758:	68db      	ldr	r3, [r3, #12]
 800275a:	2b01      	cmp	r3, #1
 800275c:	d001      	beq.n	8002762 <HAL_RCC_OscConfig+0x152>
      {
        return HAL_ERROR;
 800275e:	2301      	movs	r3, #1
 8002760:	e1bb      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8002762:	4b56      	ldr	r3, [pc, #344]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002764:	681b      	ldr	r3, [r3, #0]
 8002766:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 800276a:	687b      	ldr	r3, [r7, #4]
 800276c:	691b      	ldr	r3, [r3, #16]
 800276e:	00db      	lsls	r3, r3, #3
 8002770:	4952      	ldr	r1, [pc, #328]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002772:	4313      	orrs	r3, r2
 8002774:	600b      	str	r3, [r1, #0]
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8002776:	e03a      	b.n	80027ee <HAL_RCC_OscConfig+0x1de>
      }
    }
    else
    {
      /* Check the HSI State */
      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
 8002778:	687b      	ldr	r3, [r7, #4]
 800277a:	68db      	ldr	r3, [r3, #12]
 800277c:	2b00      	cmp	r3, #0
 800277e:	d020      	beq.n	80027c2 <HAL_RCC_OscConfig+0x1b2>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8002780:	4b4f      	ldr	r3, [pc, #316]	; (80028c0 <HAL_RCC_OscConfig+0x2b0>)
 8002782:	2201      	movs	r2, #1
 8002784:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8002786:	f7ff fc2b 	bl	8001fe0 <HAL_GetTick>
 800278a:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 800278c:	e008      	b.n	80027a0 <HAL_RCC_OscConfig+0x190>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 800278e:	f7ff fc27 	bl	8001fe0 <HAL_GetTick>
 8002792:	4602      	mov	r2, r0
 8002794:	693b      	ldr	r3, [r7, #16]
 8002796:	1ad3      	subs	r3, r2, r3
 8002798:	2b02      	cmp	r3, #2
 800279a:	d901      	bls.n	80027a0 <HAL_RCC_OscConfig+0x190>
          {
            return HAL_TIMEOUT;
 800279c:	2303      	movs	r3, #3
 800279e:	e19c      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80027a0:	4b46      	ldr	r3, [pc, #280]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80027a2:	681b      	ldr	r3, [r3, #0]
 80027a4:	f003 0302 	and.w	r3, r3, #2
 80027a8:	2b00      	cmp	r3, #0
 80027aa:	d0f0      	beq.n	800278e <HAL_RCC_OscConfig+0x17e>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80027ac:	4b43      	ldr	r3, [pc, #268]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80027ae:	681b      	ldr	r3, [r3, #0]
 80027b0:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 80027b4:	687b      	ldr	r3, [r7, #4]
 80027b6:	691b      	ldr	r3, [r3, #16]
 80027b8:	00db      	lsls	r3, r3, #3
 80027ba:	4940      	ldr	r1, [pc, #256]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80027bc:	4313      	orrs	r3, r2
 80027be:	600b      	str	r3, [r1, #0]
 80027c0:	e015      	b.n	80027ee <HAL_RCC_OscConfig+0x1de>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 80027c2:	4b3f      	ldr	r3, [pc, #252]	; (80028c0 <HAL_RCC_OscConfig+0x2b0>)
 80027c4:	2200      	movs	r2, #0
 80027c6:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 80027c8:	f7ff fc0a 	bl	8001fe0 <HAL_GetTick>
 80027cc:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 80027ce:	e008      	b.n	80027e2 <HAL_RCC_OscConfig+0x1d2>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 80027d0:	f7ff fc06 	bl	8001fe0 <HAL_GetTick>
 80027d4:	4602      	mov	r2, r0
 80027d6:	693b      	ldr	r3, [r7, #16]
 80027d8:	1ad3      	subs	r3, r2, r3
 80027da:	2b02      	cmp	r3, #2
 80027dc:	d901      	bls.n	80027e2 <HAL_RCC_OscConfig+0x1d2>
          {
            return HAL_TIMEOUT;
 80027de:	2303      	movs	r3, #3
 80027e0:	e17b      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 80027e2:	4b36      	ldr	r3, [pc, #216]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 80027e4:	681b      	ldr	r3, [r3, #0]
 80027e6:	f003 0302 	and.w	r3, r3, #2
 80027ea:	2b00      	cmp	r3, #0
 80027ec:	d1f0      	bne.n	80027d0 <HAL_RCC_OscConfig+0x1c0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 80027ee:	687b      	ldr	r3, [r7, #4]
 80027f0:	681b      	ldr	r3, [r3, #0]
 80027f2:	f003 0308 	and.w	r3, r3, #8
 80027f6:	2b00      	cmp	r3, #0
 80027f8:	d030      	beq.n	800285c <HAL_RCC_OscConfig+0x24c>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
 80027fa:	687b      	ldr	r3, [r7, #4]
 80027fc:	695b      	ldr	r3, [r3, #20]
 80027fe:	2b00      	cmp	r3, #0
 8002800:	d016      	beq.n	8002830 <HAL_RCC_OscConfig+0x220>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8002802:	4b30      	ldr	r3, [pc, #192]	; (80028c4 <HAL_RCC_OscConfig+0x2b4>)
 8002804:	2201      	movs	r2, #1
 8002806:	601a      	str	r2, [r3, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002808:	f7ff fbea 	bl	8001fe0 <HAL_GetTick>
 800280c:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 800280e:	e008      	b.n	8002822 <HAL_RCC_OscConfig+0x212>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8002810:	f7ff fbe6 	bl	8001fe0 <HAL_GetTick>
 8002814:	4602      	mov	r2, r0
 8002816:	693b      	ldr	r3, [r7, #16]
 8002818:	1ad3      	subs	r3, r2, r3
 800281a:	2b02      	cmp	r3, #2
 800281c:	d901      	bls.n	8002822 <HAL_RCC_OscConfig+0x212>
        {
          return HAL_TIMEOUT;
 800281e:	2303      	movs	r3, #3
 8002820:	e15b      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8002822:	4b26      	ldr	r3, [pc, #152]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002824:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 8002826:	f003 0302 	and.w	r3, r3, #2
 800282a:	2b00      	cmp	r3, #0
 800282c:	d0f0      	beq.n	8002810 <HAL_RCC_OscConfig+0x200>
 800282e:	e015      	b.n	800285c <HAL_RCC_OscConfig+0x24c>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8002830:	4b24      	ldr	r3, [pc, #144]	; (80028c4 <HAL_RCC_OscConfig+0x2b4>)
 8002832:	2200      	movs	r2, #0
 8002834:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8002836:	f7ff fbd3 	bl	8001fe0 <HAL_GetTick>
 800283a:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 800283c:	e008      	b.n	8002850 <HAL_RCC_OscConfig+0x240>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 800283e:	f7ff fbcf 	bl	8001fe0 <HAL_GetTick>
 8002842:	4602      	mov	r2, r0
 8002844:	693b      	ldr	r3, [r7, #16]
 8002846:	1ad3      	subs	r3, r2, r3
 8002848:	2b02      	cmp	r3, #2
 800284a:	d901      	bls.n	8002850 <HAL_RCC_OscConfig+0x240>
        {
          return HAL_TIMEOUT;
 800284c:	2303      	movs	r3, #3
 800284e:	e144      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8002850:	4b1a      	ldr	r3, [pc, #104]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002852:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 8002854:	f003 0302 	and.w	r3, r3, #2
 8002858:	2b00      	cmp	r3, #0
 800285a:	d1f0      	bne.n	800283e <HAL_RCC_OscConfig+0x22e>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 800285c:	687b      	ldr	r3, [r7, #4]
 800285e:	681b      	ldr	r3, [r3, #0]
 8002860:	f003 0304 	and.w	r3, r3, #4
 8002864:	2b00      	cmp	r3, #0
 8002866:	f000 80a0 	beq.w	80029aa <HAL_RCC_OscConfig+0x39a>
  {
    FlagStatus       pwrclkchanged = RESET;
 800286a:	2300      	movs	r3, #0
 800286c:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 800286e:	4b13      	ldr	r3, [pc, #76]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002870:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002872:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002876:	2b00      	cmp	r3, #0
 8002878:	d10f      	bne.n	800289a <HAL_RCC_OscConfig+0x28a>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 800287a:	2300      	movs	r3, #0
 800287c:	60bb      	str	r3, [r7, #8]
 800287e:	4b0f      	ldr	r3, [pc, #60]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002880:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002882:	4a0e      	ldr	r2, [pc, #56]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 8002884:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8002888:	6413      	str	r3, [r2, #64]	; 0x40
 800288a:	4b0c      	ldr	r3, [pc, #48]	; (80028bc <HAL_RCC_OscConfig+0x2ac>)
 800288c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800288e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002892:	60bb      	str	r3, [r7, #8]
 8002894:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8002896:	2301      	movs	r3, #1
 8002898:	75fb      	strb	r3, [r7, #23]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800289a:	4b0b      	ldr	r3, [pc, #44]	; (80028c8 <HAL_RCC_OscConfig+0x2b8>)
 800289c:	681b      	ldr	r3, [r3, #0]
 800289e:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80028a2:	2b00      	cmp	r3, #0
 80028a4:	d121      	bne.n	80028ea <HAL_RCC_OscConfig+0x2da>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 80028a6:	4b08      	ldr	r3, [pc, #32]	; (80028c8 <HAL_RCC_OscConfig+0x2b8>)
 80028a8:	681b      	ldr	r3, [r3, #0]
 80028aa:	4a07      	ldr	r2, [pc, #28]	; (80028c8 <HAL_RCC_OscConfig+0x2b8>)
 80028ac:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80028b0:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 80028b2:	f7ff fb95 	bl	8001fe0 <HAL_GetTick>
 80028b6:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80028b8:	e011      	b.n	80028de <HAL_RCC_OscConfig+0x2ce>
 80028ba:	bf00      	nop
 80028bc:	40023800 	.word	0x40023800
 80028c0:	42470000 	.word	0x42470000
 80028c4:	42470e80 	.word	0x42470e80
 80028c8:	40007000 	.word	0x40007000
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80028cc:	f7ff fb88 	bl	8001fe0 <HAL_GetTick>
 80028d0:	4602      	mov	r2, r0
 80028d2:	693b      	ldr	r3, [r7, #16]
 80028d4:	1ad3      	subs	r3, r2, r3
 80028d6:	2b02      	cmp	r3, #2
 80028d8:	d901      	bls.n	80028de <HAL_RCC_OscConfig+0x2ce>
        {
          return HAL_TIMEOUT;
 80028da:	2303      	movs	r3, #3
 80028dc:	e0fd      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80028de:	4b81      	ldr	r3, [pc, #516]	; (8002ae4 <HAL_RCC_OscConfig+0x4d4>)
 80028e0:	681b      	ldr	r3, [r3, #0]
 80028e2:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80028e6:	2b00      	cmp	r3, #0
 80028e8:	d0f0      	beq.n	80028cc <HAL_RCC_OscConfig+0x2bc>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 80028ea:	687b      	ldr	r3, [r7, #4]
 80028ec:	689b      	ldr	r3, [r3, #8]
 80028ee:	2b01      	cmp	r3, #1
 80028f0:	d106      	bne.n	8002900 <HAL_RCC_OscConfig+0x2f0>
 80028f2:	4b7d      	ldr	r3, [pc, #500]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 80028f4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80028f6:	4a7c      	ldr	r2, [pc, #496]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 80028f8:	f043 0301 	orr.w	r3, r3, #1
 80028fc:	6713      	str	r3, [r2, #112]	; 0x70
 80028fe:	e01c      	b.n	800293a <HAL_RCC_OscConfig+0x32a>
 8002900:	687b      	ldr	r3, [r7, #4]
 8002902:	689b      	ldr	r3, [r3, #8]
 8002904:	2b05      	cmp	r3, #5
 8002906:	d10c      	bne.n	8002922 <HAL_RCC_OscConfig+0x312>
 8002908:	4b77      	ldr	r3, [pc, #476]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 800290a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 800290c:	4a76      	ldr	r2, [pc, #472]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 800290e:	f043 0304 	orr.w	r3, r3, #4
 8002912:	6713      	str	r3, [r2, #112]	; 0x70
 8002914:	4b74      	ldr	r3, [pc, #464]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002916:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002918:	4a73      	ldr	r2, [pc, #460]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 800291a:	f043 0301 	orr.w	r3, r3, #1
 800291e:	6713      	str	r3, [r2, #112]	; 0x70
 8002920:	e00b      	b.n	800293a <HAL_RCC_OscConfig+0x32a>
 8002922:	4b71      	ldr	r3, [pc, #452]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002924:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002926:	4a70      	ldr	r2, [pc, #448]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002928:	f023 0301 	bic.w	r3, r3, #1
 800292c:	6713      	str	r3, [r2, #112]	; 0x70
 800292e:	4b6e      	ldr	r3, [pc, #440]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002930:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002932:	4a6d      	ldr	r2, [pc, #436]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002934:	f023 0304 	bic.w	r3, r3, #4
 8002938:	6713      	str	r3, [r2, #112]	; 0x70
    /* Check the LSE State */
    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 800293a:	687b      	ldr	r3, [r7, #4]
 800293c:	689b      	ldr	r3, [r3, #8]
 800293e:	2b00      	cmp	r3, #0
 8002940:	d015      	beq.n	800296e <HAL_RCC_OscConfig+0x35e>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8002942:	f7ff fb4d 	bl	8001fe0 <HAL_GetTick>
 8002946:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8002948:	e00a      	b.n	8002960 <HAL_RCC_OscConfig+0x350>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 800294a:	f7ff fb49 	bl	8001fe0 <HAL_GetTick>
 800294e:	4602      	mov	r2, r0
 8002950:	693b      	ldr	r3, [r7, #16]
 8002952:	1ad3      	subs	r3, r2, r3
 8002954:	f241 3288 	movw	r2, #5000	; 0x1388
 8002958:	4293      	cmp	r3, r2
 800295a:	d901      	bls.n	8002960 <HAL_RCC_OscConfig+0x350>
        {
          return HAL_TIMEOUT;
 800295c:	2303      	movs	r3, #3
 800295e:	e0bc      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8002960:	4b61      	ldr	r3, [pc, #388]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002962:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002964:	f003 0302 	and.w	r3, r3, #2
 8002968:	2b00      	cmp	r3, #0
 800296a:	d0ee      	beq.n	800294a <HAL_RCC_OscConfig+0x33a>
 800296c:	e014      	b.n	8002998 <HAL_RCC_OscConfig+0x388>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 800296e:	f7ff fb37 	bl	8001fe0 <HAL_GetTick>
 8002972:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8002974:	e00a      	b.n	800298c <HAL_RCC_OscConfig+0x37c>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8002976:	f7ff fb33 	bl	8001fe0 <HAL_GetTick>
 800297a:	4602      	mov	r2, r0
 800297c:	693b      	ldr	r3, [r7, #16]
 800297e:	1ad3      	subs	r3, r2, r3
 8002980:	f241 3288 	movw	r2, #5000	; 0x1388
 8002984:	4293      	cmp	r3, r2
 8002986:	d901      	bls.n	800298c <HAL_RCC_OscConfig+0x37c>
        {
          return HAL_TIMEOUT;
 8002988:	2303      	movs	r3, #3
 800298a:	e0a6      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 800298c:	4b56      	ldr	r3, [pc, #344]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 800298e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002990:	f003 0302 	and.w	r3, r3, #2
 8002994:	2b00      	cmp	r3, #0
 8002996:	d1ee      	bne.n	8002976 <HAL_RCC_OscConfig+0x366>
        }
      }
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8002998:	7dfb      	ldrb	r3, [r7, #23]
 800299a:	2b01      	cmp	r3, #1
 800299c:	d105      	bne.n	80029aa <HAL_RCC_OscConfig+0x39a>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 800299e:	4b52      	ldr	r3, [pc, #328]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 80029a0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80029a2:	4a51      	ldr	r2, [pc, #324]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 80029a4:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 80029a8:	6413      	str	r3, [r2, #64]	; 0x40
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 80029aa:	687b      	ldr	r3, [r7, #4]
 80029ac:	699b      	ldr	r3, [r3, #24]
 80029ae:	2b00      	cmp	r3, #0
 80029b0:	f000 8092 	beq.w	8002ad8 <HAL_RCC_OscConfig+0x4c8>
  {
    /* Check if the PLL is used as system clock or not */
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
 80029b4:	4b4c      	ldr	r3, [pc, #304]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 80029b6:	689b      	ldr	r3, [r3, #8]
 80029b8:	f003 030c 	and.w	r3, r3, #12
 80029bc:	2b08      	cmp	r3, #8
 80029be:	d05c      	beq.n	8002a7a <HAL_RCC_OscConfig+0x46a>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 80029c0:	687b      	ldr	r3, [r7, #4]
 80029c2:	699b      	ldr	r3, [r3, #24]
 80029c4:	2b02      	cmp	r3, #2
 80029c6:	d141      	bne.n	8002a4c <HAL_RCC_OscConfig+0x43c>
        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 80029c8:	4b48      	ldr	r3, [pc, #288]	; (8002aec <HAL_RCC_OscConfig+0x4dc>)
 80029ca:	2200      	movs	r2, #0
 80029cc:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80029ce:	f7ff fb07 	bl	8001fe0 <HAL_GetTick>
 80029d2:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 80029d4:	e008      	b.n	80029e8 <HAL_RCC_OscConfig+0x3d8>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 80029d6:	f7ff fb03 	bl	8001fe0 <HAL_GetTick>
 80029da:	4602      	mov	r2, r0
 80029dc:	693b      	ldr	r3, [r7, #16]
 80029de:	1ad3      	subs	r3, r2, r3
 80029e0:	2b02      	cmp	r3, #2
 80029e2:	d901      	bls.n	80029e8 <HAL_RCC_OscConfig+0x3d8>
          {
            return HAL_TIMEOUT;
 80029e4:	2303      	movs	r3, #3
 80029e6:	e078      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 80029e8:	4b3f      	ldr	r3, [pc, #252]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 80029ea:	681b      	ldr	r3, [r3, #0]
 80029ec:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80029f0:	2b00      	cmp	r3, #0
 80029f2:	d1f0      	bne.n	80029d6 <HAL_RCC_OscConfig+0x3c6>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
 80029f4:	687b      	ldr	r3, [r7, #4]
 80029f6:	69da      	ldr	r2, [r3, #28]
 80029f8:	687b      	ldr	r3, [r7, #4]
 80029fa:	6a1b      	ldr	r3, [r3, #32]
 80029fc:	431a      	orrs	r2, r3
 80029fe:	687b      	ldr	r3, [r7, #4]
 8002a00:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8002a02:	019b      	lsls	r3, r3, #6
 8002a04:	431a      	orrs	r2, r3
 8002a06:	687b      	ldr	r3, [r7, #4]
 8002a08:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8002a0a:	085b      	lsrs	r3, r3, #1
 8002a0c:	3b01      	subs	r3, #1
 8002a0e:	041b      	lsls	r3, r3, #16
 8002a10:	431a      	orrs	r2, r3
 8002a12:	687b      	ldr	r3, [r7, #4]
 8002a14:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8002a16:	061b      	lsls	r3, r3, #24
 8002a18:	4933      	ldr	r1, [pc, #204]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002a1a:	4313      	orrs	r3, r2
 8002a1c:	604b      	str	r3, [r1, #4]
                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8002a1e:	4b33      	ldr	r3, [pc, #204]	; (8002aec <HAL_RCC_OscConfig+0x4dc>)
 8002a20:	2201      	movs	r2, #1
 8002a22:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8002a24:	f7ff fadc 	bl	8001fe0 <HAL_GetTick>
 8002a28:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8002a2a:	e008      	b.n	8002a3e <HAL_RCC_OscConfig+0x42e>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8002a2c:	f7ff fad8 	bl	8001fe0 <HAL_GetTick>
 8002a30:	4602      	mov	r2, r0
 8002a32:	693b      	ldr	r3, [r7, #16]
 8002a34:	1ad3      	subs	r3, r2, r3
 8002a36:	2b02      	cmp	r3, #2
 8002a38:	d901      	bls.n	8002a3e <HAL_RCC_OscConfig+0x42e>
          {
            return HAL_TIMEOUT;
 8002a3a:	2303      	movs	r3, #3
 8002a3c:	e04d      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8002a3e:	4b2a      	ldr	r3, [pc, #168]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002a40:	681b      	ldr	r3, [r3, #0]
 8002a42:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8002a46:	2b00      	cmp	r3, #0
 8002a48:	d0f0      	beq.n	8002a2c <HAL_RCC_OscConfig+0x41c>
 8002a4a:	e045      	b.n	8002ad8 <HAL_RCC_OscConfig+0x4c8>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8002a4c:	4b27      	ldr	r3, [pc, #156]	; (8002aec <HAL_RCC_OscConfig+0x4dc>)
 8002a4e:	2200      	movs	r2, #0
 8002a50:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8002a52:	f7ff fac5 	bl	8001fe0 <HAL_GetTick>
 8002a56:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8002a58:	e008      	b.n	8002a6c <HAL_RCC_OscConfig+0x45c>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8002a5a:	f7ff fac1 	bl	8001fe0 <HAL_GetTick>
 8002a5e:	4602      	mov	r2, r0
 8002a60:	693b      	ldr	r3, [r7, #16]
 8002a62:	1ad3      	subs	r3, r2, r3
 8002a64:	2b02      	cmp	r3, #2
 8002a66:	d901      	bls.n	8002a6c <HAL_RCC_OscConfig+0x45c>
          {
            return HAL_TIMEOUT;
 8002a68:	2303      	movs	r3, #3
 8002a6a:	e036      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8002a6c:	4b1e      	ldr	r3, [pc, #120]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002a6e:	681b      	ldr	r3, [r3, #0]
 8002a70:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8002a74:	2b00      	cmp	r3, #0
 8002a76:	d1f0      	bne.n	8002a5a <HAL_RCC_OscConfig+0x44a>
 8002a78:	e02e      	b.n	8002ad8 <HAL_RCC_OscConfig+0x4c8>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8002a7a:	687b      	ldr	r3, [r7, #4]
 8002a7c:	699b      	ldr	r3, [r3, #24]
 8002a7e:	2b01      	cmp	r3, #1
 8002a80:	d101      	bne.n	8002a86 <HAL_RCC_OscConfig+0x476>
      {
        return HAL_ERROR;
 8002a82:	2301      	movs	r3, #1
 8002a84:	e029      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->PLLCFGR;
 8002a86:	4b18      	ldr	r3, [pc, #96]	; (8002ae8 <HAL_RCC_OscConfig+0x4d8>)
 8002a88:	685b      	ldr	r3, [r3, #4]
 8002a8a:	60fb      	str	r3, [r7, #12]
        if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8002a8c:	68fb      	ldr	r3, [r7, #12]
 8002a8e:	f403 0280 	and.w	r2, r3, #4194304	; 0x400000
 8002a92:	687b      	ldr	r3, [r7, #4]
 8002a94:	69db      	ldr	r3, [r3, #28]
 8002a96:	429a      	cmp	r2, r3
 8002a98:	d11c      	bne.n	8002ad4 <HAL_RCC_OscConfig+0x4c4>
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
 8002a9a:	68fb      	ldr	r3, [r7, #12]
 8002a9c:	f003 023f 	and.w	r2, r3, #63	; 0x3f
 8002aa0:	687b      	ldr	r3, [r7, #4]
 8002aa2:	6a1b      	ldr	r3, [r3, #32]
        if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8002aa4:	429a      	cmp	r2, r3
 8002aa6:	d115      	bne.n	8002ad4 <HAL_RCC_OscConfig+0x4c4>
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
 8002aa8:	68fa      	ldr	r2, [r7, #12]
 8002aaa:	f647 73c0 	movw	r3, #32704	; 0x7fc0
 8002aae:	4013      	ands	r3, r2
 8002ab0:	687a      	ldr	r2, [r7, #4]
 8002ab2:	6a52      	ldr	r2, [r2, #36]	; 0x24
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
 8002ab4:	4293      	cmp	r3, r2
 8002ab6:	d10d      	bne.n	8002ad4 <HAL_RCC_OscConfig+0x4c4>
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
 8002ab8:	68fb      	ldr	r3, [r7, #12]
 8002aba:	f403 3240 	and.w	r2, r3, #196608	; 0x30000
 8002abe:	687b      	ldr	r3, [r7, #4]
 8002ac0:	6a9b      	ldr	r3, [r3, #40]	; 0x28
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
 8002ac2:	429a      	cmp	r2, r3
 8002ac4:	d106      	bne.n	8002ad4 <HAL_RCC_OscConfig+0x4c4>
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
 8002ac6:	68fb      	ldr	r3, [r7, #12]
 8002ac8:	f003 6270 	and.w	r2, r3, #251658240	; 0xf000000
 8002acc:	687b      	ldr	r3, [r7, #4]
 8002ace:	6adb      	ldr	r3, [r3, #44]	; 0x2c
           (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
 8002ad0:	429a      	cmp	r2, r3
 8002ad2:	d001      	beq.n	8002ad8 <HAL_RCC_OscConfig+0x4c8>
        {
          return HAL_ERROR;
 8002ad4:	2301      	movs	r3, #1
 8002ad6:	e000      	b.n	8002ada <HAL_RCC_OscConfig+0x4ca>
        }
      }
    }
  }
  return HAL_OK;
 8002ad8:	2300      	movs	r3, #0
}
 8002ada:	4618      	mov	r0, r3
 8002adc:	3718      	adds	r7, #24
 8002ade:	46bd      	mov	sp, r7
 8002ae0:	bd80      	pop	{r7, pc}
 8002ae2:	bf00      	nop
 8002ae4:	40007000 	.word	0x40007000
 8002ae8:	40023800 	.word	0x40023800
 8002aec:	42470060 	.word	0x42470060

08002af0 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8002af0:	b580      	push	{r7, lr}
 8002af2:	b084      	sub	sp, #16
 8002af4:	af00      	add	r7, sp, #0
 8002af6:	6078      	str	r0, [r7, #4]
 8002af8:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 8002afa:	687b      	ldr	r3, [r7, #4]
 8002afc:	2b00      	cmp	r3, #0
 8002afe:	d101      	bne.n	8002b04 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8002b00:	2301      	movs	r3, #1
 8002b02:	e0cc      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8002b04:	4b68      	ldr	r3, [pc, #416]	; (8002ca8 <HAL_RCC_ClockConfig+0x1b8>)
 8002b06:	681b      	ldr	r3, [r3, #0]
 8002b08:	f003 030f 	and.w	r3, r3, #15
 8002b0c:	683a      	ldr	r2, [r7, #0]
 8002b0e:	429a      	cmp	r2, r3
 8002b10:	d90c      	bls.n	8002b2c <HAL_RCC_ClockConfig+0x3c>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8002b12:	4b65      	ldr	r3, [pc, #404]	; (8002ca8 <HAL_RCC_ClockConfig+0x1b8>)
 8002b14:	683a      	ldr	r2, [r7, #0]
 8002b16:	b2d2      	uxtb	r2, r2
 8002b18:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8002b1a:	4b63      	ldr	r3, [pc, #396]	; (8002ca8 <HAL_RCC_ClockConfig+0x1b8>)
 8002b1c:	681b      	ldr	r3, [r3, #0]
 8002b1e:	f003 030f 	and.w	r3, r3, #15
 8002b22:	683a      	ldr	r2, [r7, #0]
 8002b24:	429a      	cmp	r2, r3
 8002b26:	d001      	beq.n	8002b2c <HAL_RCC_ClockConfig+0x3c>
    {
      return HAL_ERROR;
 8002b28:	2301      	movs	r3, #1
 8002b2a:	e0b8      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8002b2c:	687b      	ldr	r3, [r7, #4]
 8002b2e:	681b      	ldr	r3, [r3, #0]
 8002b30:	f003 0302 	and.w	r3, r3, #2
 8002b34:	2b00      	cmp	r3, #0
 8002b36:	d020      	beq.n	8002b7a <HAL_RCC_ClockConfig+0x8a>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
       a non-spec phase whatever we decrease or increase HCLK. */
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8002b38:	687b      	ldr	r3, [r7, #4]
 8002b3a:	681b      	ldr	r3, [r3, #0]
 8002b3c:	f003 0304 	and.w	r3, r3, #4
 8002b40:	2b00      	cmp	r3, #0
 8002b42:	d005      	beq.n	8002b50 <HAL_RCC_ClockConfig+0x60>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8002b44:	4b59      	ldr	r3, [pc, #356]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b46:	689b      	ldr	r3, [r3, #8]
 8002b48:	4a58      	ldr	r2, [pc, #352]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b4a:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
 8002b4e:	6093      	str	r3, [r2, #8]
    }

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8002b50:	687b      	ldr	r3, [r7, #4]
 8002b52:	681b      	ldr	r3, [r3, #0]
 8002b54:	f003 0308 	and.w	r3, r3, #8
 8002b58:	2b00      	cmp	r3, #0
 8002b5a:	d005      	beq.n	8002b68 <HAL_RCC_ClockConfig+0x78>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8002b5c:	4b53      	ldr	r3, [pc, #332]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b5e:	689b      	ldr	r3, [r3, #8]
 8002b60:	4a52      	ldr	r2, [pc, #328]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b62:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
 8002b66:	6093      	str	r3, [r2, #8]
    }

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8002b68:	4b50      	ldr	r3, [pc, #320]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b6a:	689b      	ldr	r3, [r3, #8]
 8002b6c:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8002b70:	687b      	ldr	r3, [r7, #4]
 8002b72:	689b      	ldr	r3, [r3, #8]
 8002b74:	494d      	ldr	r1, [pc, #308]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b76:	4313      	orrs	r3, r2
 8002b78:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8002b7a:	687b      	ldr	r3, [r7, #4]
 8002b7c:	681b      	ldr	r3, [r3, #0]
 8002b7e:	f003 0301 	and.w	r3, r3, #1
 8002b82:	2b00      	cmp	r3, #0
 8002b84:	d044      	beq.n	8002c10 <HAL_RCC_ClockConfig+0x120>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8002b86:	687b      	ldr	r3, [r7, #4]
 8002b88:	685b      	ldr	r3, [r3, #4]
 8002b8a:	2b01      	cmp	r3, #1
 8002b8c:	d107      	bne.n	8002b9e <HAL_RCC_ClockConfig+0xae>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8002b8e:	4b47      	ldr	r3, [pc, #284]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002b90:	681b      	ldr	r3, [r3, #0]
 8002b92:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002b96:	2b00      	cmp	r3, #0
 8002b98:	d119      	bne.n	8002bce <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002b9a:	2301      	movs	r3, #1
 8002b9c:	e07f      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
      }
    }
    /* PLL is selected as System Clock Source */
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8002b9e:	687b      	ldr	r3, [r7, #4]
 8002ba0:	685b      	ldr	r3, [r3, #4]
 8002ba2:	2b02      	cmp	r3, #2
 8002ba4:	d003      	beq.n	8002bae <HAL_RCC_ClockConfig+0xbe>
            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
 8002ba6:	687b      	ldr	r3, [r7, #4]
 8002ba8:	685b      	ldr	r3, [r3, #4]
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8002baa:	2b03      	cmp	r3, #3
 8002bac:	d107      	bne.n	8002bbe <HAL_RCC_ClockConfig+0xce>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8002bae:	4b3f      	ldr	r3, [pc, #252]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002bb0:	681b      	ldr	r3, [r3, #0]
 8002bb2:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8002bb6:	2b00      	cmp	r3, #0
 8002bb8:	d109      	bne.n	8002bce <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002bba:	2301      	movs	r3, #1
 8002bbc:	e06f      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8002bbe:	4b3b      	ldr	r3, [pc, #236]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002bc0:	681b      	ldr	r3, [r3, #0]
 8002bc2:	f003 0302 	and.w	r3, r3, #2
 8002bc6:	2b00      	cmp	r3, #0
 8002bc8:	d101      	bne.n	8002bce <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002bca:	2301      	movs	r3, #1
 8002bcc:	e067      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
      }
    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8002bce:	4b37      	ldr	r3, [pc, #220]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002bd0:	689b      	ldr	r3, [r3, #8]
 8002bd2:	f023 0203 	bic.w	r2, r3, #3
 8002bd6:	687b      	ldr	r3, [r7, #4]
 8002bd8:	685b      	ldr	r3, [r3, #4]
 8002bda:	4934      	ldr	r1, [pc, #208]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002bdc:	4313      	orrs	r3, r2
 8002bde:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8002be0:	f7ff f9fe 	bl	8001fe0 <HAL_GetTick>
 8002be4:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002be6:	e00a      	b.n	8002bfe <HAL_RCC_ClockConfig+0x10e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8002be8:	f7ff f9fa 	bl	8001fe0 <HAL_GetTick>
 8002bec:	4602      	mov	r2, r0
 8002bee:	68fb      	ldr	r3, [r7, #12]
 8002bf0:	1ad3      	subs	r3, r2, r3
 8002bf2:	f241 3288 	movw	r2, #5000	; 0x1388
 8002bf6:	4293      	cmp	r3, r2
 8002bf8:	d901      	bls.n	8002bfe <HAL_RCC_ClockConfig+0x10e>
      {
        return HAL_TIMEOUT;
 8002bfa:	2303      	movs	r3, #3
 8002bfc:	e04f      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002bfe:	4b2b      	ldr	r3, [pc, #172]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002c00:	689b      	ldr	r3, [r3, #8]
 8002c02:	f003 020c 	and.w	r2, r3, #12
 8002c06:	687b      	ldr	r3, [r7, #4]
 8002c08:	685b      	ldr	r3, [r3, #4]
 8002c0a:	009b      	lsls	r3, r3, #2
 8002c0c:	429a      	cmp	r2, r3
 8002c0e:	d1eb      	bne.n	8002be8 <HAL_RCC_ClockConfig+0xf8>
      }
    }
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8002c10:	4b25      	ldr	r3, [pc, #148]	; (8002ca8 <HAL_RCC_ClockConfig+0x1b8>)
 8002c12:	681b      	ldr	r3, [r3, #0]
 8002c14:	f003 030f 	and.w	r3, r3, #15
 8002c18:	683a      	ldr	r2, [r7, #0]
 8002c1a:	429a      	cmp	r2, r3
 8002c1c:	d20c      	bcs.n	8002c38 <HAL_RCC_ClockConfig+0x148>
  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8002c1e:	4b22      	ldr	r3, [pc, #136]	; (8002ca8 <HAL_RCC_ClockConfig+0x1b8>)
 8002c20:	683a      	ldr	r2, [r7, #0]
 8002c22:	b2d2      	uxtb	r2, r2
 8002c24:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8002c26:	4b20      	ldr	r3, [pc, #128]	; (8002ca8 <HAL_RCC_ClockConfig+0x1b8>)
 8002c28:	681b      	ldr	r3, [r3, #0]
 8002c2a:	f003 030f 	and.w	r3, r3, #15
 8002c2e:	683a      	ldr	r2, [r7, #0]
 8002c30:	429a      	cmp	r2, r3
 8002c32:	d001      	beq.n	8002c38 <HAL_RCC_ClockConfig+0x148>
    {
      return HAL_ERROR;
 8002c34:	2301      	movs	r3, #1
 8002c36:	e032      	b.n	8002c9e <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8002c38:	687b      	ldr	r3, [r7, #4]
 8002c3a:	681b      	ldr	r3, [r3, #0]
 8002c3c:	f003 0304 	and.w	r3, r3, #4
 8002c40:	2b00      	cmp	r3, #0
 8002c42:	d008      	beq.n	8002c56 <HAL_RCC_ClockConfig+0x166>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8002c44:	4b19      	ldr	r3, [pc, #100]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002c46:	689b      	ldr	r3, [r3, #8]
 8002c48:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
 8002c4c:	687b      	ldr	r3, [r7, #4]
 8002c4e:	68db      	ldr	r3, [r3, #12]
 8002c50:	4916      	ldr	r1, [pc, #88]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002c52:	4313      	orrs	r3, r2
 8002c54:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8002c56:	687b      	ldr	r3, [r7, #4]
 8002c58:	681b      	ldr	r3, [r3, #0]
 8002c5a:	f003 0308 	and.w	r3, r3, #8
 8002c5e:	2b00      	cmp	r3, #0
 8002c60:	d009      	beq.n	8002c76 <HAL_RCC_ClockConfig+0x186>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8002c62:	4b12      	ldr	r3, [pc, #72]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002c64:	689b      	ldr	r3, [r3, #8]
 8002c66:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8002c6a:	687b      	ldr	r3, [r7, #4]
 8002c6c:	691b      	ldr	r3, [r3, #16]
 8002c6e:	00db      	lsls	r3, r3, #3
 8002c70:	490e      	ldr	r1, [pc, #56]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002c72:	4313      	orrs	r3, r2
 8002c74:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8002c76:	f000 f821 	bl	8002cbc <HAL_RCC_GetSysClockFreq>
 8002c7a:	4601      	mov	r1, r0
 8002c7c:	4b0b      	ldr	r3, [pc, #44]	; (8002cac <HAL_RCC_ClockConfig+0x1bc>)
 8002c7e:	689b      	ldr	r3, [r3, #8]
 8002c80:	091b      	lsrs	r3, r3, #4
 8002c82:	f003 030f 	and.w	r3, r3, #15
 8002c86:	4a0a      	ldr	r2, [pc, #40]	; (8002cb0 <HAL_RCC_ClockConfig+0x1c0>)
 8002c88:	5cd3      	ldrb	r3, [r2, r3]
 8002c8a:	fa21 f303 	lsr.w	r3, r1, r3
 8002c8e:	4a09      	ldr	r2, [pc, #36]	; (8002cb4 <HAL_RCC_ClockConfig+0x1c4>)
 8002c90:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings */
  HAL_InitTick (uwTickPrio);
 8002c92:	4b09      	ldr	r3, [pc, #36]	; (8002cb8 <HAL_RCC_ClockConfig+0x1c8>)
 8002c94:	681b      	ldr	r3, [r3, #0]
 8002c96:	4618      	mov	r0, r3
 8002c98:	f7ff f95e 	bl	8001f58 <HAL_InitTick>

  return HAL_OK;
 8002c9c:	2300      	movs	r3, #0
}
 8002c9e:	4618      	mov	r0, r3
 8002ca0:	3710      	adds	r7, #16
 8002ca2:	46bd      	mov	sp, r7
 8002ca4:	bd80      	pop	{r7, pc}
 8002ca6:	bf00      	nop
 8002ca8:	40023c00 	.word	0x40023c00
 8002cac:	40023800 	.word	0x40023800
 8002cb0:	08006018 	.word	0x08006018
 8002cb4:	20000014 	.word	0x20000014
 8002cb8:	20000018 	.word	0x20000018

08002cbc <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8002cbc:	b5f0      	push	{r4, r5, r6, r7, lr}
 8002cbe:	b085      	sub	sp, #20
 8002cc0:	af00      	add	r7, sp, #0
  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
 8002cc2:	2300      	movs	r3, #0
 8002cc4:	607b      	str	r3, [r7, #4]
 8002cc6:	2300      	movs	r3, #0
 8002cc8:	60fb      	str	r3, [r7, #12]
 8002cca:	2300      	movs	r3, #0
 8002ccc:	603b      	str	r3, [r7, #0]
  uint32_t sysclockfreq = 0U;
 8002cce:	2300      	movs	r3, #0
 8002cd0:	60bb      	str	r3, [r7, #8]

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (RCC->CFGR & RCC_CFGR_SWS)
 8002cd2:	4b63      	ldr	r3, [pc, #396]	; (8002e60 <HAL_RCC_GetSysClockFreq+0x1a4>)
 8002cd4:	689b      	ldr	r3, [r3, #8]
 8002cd6:	f003 030c 	and.w	r3, r3, #12
 8002cda:	2b04      	cmp	r3, #4
 8002cdc:	d007      	beq.n	8002cee <HAL_RCC_GetSysClockFreq+0x32>
 8002cde:	2b08      	cmp	r3, #8
 8002ce0:	d008      	beq.n	8002cf4 <HAL_RCC_GetSysClockFreq+0x38>
 8002ce2:	2b00      	cmp	r3, #0
 8002ce4:	f040 80b4 	bne.w	8002e50 <HAL_RCC_GetSysClockFreq+0x194>
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 8002ce8:	4b5e      	ldr	r3, [pc, #376]	; (8002e64 <HAL_RCC_GetSysClockFreq+0x1a8>)
 8002cea:	60bb      	str	r3, [r7, #8]
       break;
 8002cec:	e0b3      	b.n	8002e56 <HAL_RCC_GetSysClockFreq+0x19a>
    }
    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
    {
      sysclockfreq = HSE_VALUE;
 8002cee:	4b5e      	ldr	r3, [pc, #376]	; (8002e68 <HAL_RCC_GetSysClockFreq+0x1ac>)
 8002cf0:	60bb      	str	r3, [r7, #8]
      break;
 8002cf2:	e0b0      	b.n	8002e56 <HAL_RCC_GetSysClockFreq+0x19a>
    }
    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
    {
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLP */
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 8002cf4:	4b5a      	ldr	r3, [pc, #360]	; (8002e60 <HAL_RCC_GetSysClockFreq+0x1a4>)
 8002cf6:	685b      	ldr	r3, [r3, #4]
 8002cf8:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 8002cfc:	607b      	str	r3, [r7, #4]
      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 8002cfe:	4b58      	ldr	r3, [pc, #352]	; (8002e60 <HAL_RCC_GetSysClockFreq+0x1a4>)
 8002d00:	685b      	ldr	r3, [r3, #4]
 8002d02:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8002d06:	2b00      	cmp	r3, #0
 8002d08:	d04a      	beq.n	8002da0 <HAL_RCC_GetSysClockFreq+0xe4>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 8002d0a:	4b55      	ldr	r3, [pc, #340]	; (8002e60 <HAL_RCC_GetSysClockFreq+0x1a4>)
 8002d0c:	685b      	ldr	r3, [r3, #4]
 8002d0e:	099b      	lsrs	r3, r3, #6
 8002d10:	f04f 0400 	mov.w	r4, #0
 8002d14:	f240 11ff 	movw	r1, #511	; 0x1ff
 8002d18:	f04f 0200 	mov.w	r2, #0
 8002d1c:	ea03 0501 	and.w	r5, r3, r1
 8002d20:	ea04 0602 	and.w	r6, r4, r2
 8002d24:	4629      	mov	r1, r5
 8002d26:	4632      	mov	r2, r6
 8002d28:	f04f 0300 	mov.w	r3, #0
 8002d2c:	f04f 0400 	mov.w	r4, #0
 8002d30:	0154      	lsls	r4, r2, #5
 8002d32:	ea44 64d1 	orr.w	r4, r4, r1, lsr #27
 8002d36:	014b      	lsls	r3, r1, #5
 8002d38:	4619      	mov	r1, r3
 8002d3a:	4622      	mov	r2, r4
 8002d3c:	1b49      	subs	r1, r1, r5
 8002d3e:	eb62 0206 	sbc.w	r2, r2, r6
 8002d42:	f04f 0300 	mov.w	r3, #0
 8002d46:	f04f 0400 	mov.w	r4, #0
 8002d4a:	0194      	lsls	r4, r2, #6
 8002d4c:	ea44 6491 	orr.w	r4, r4, r1, lsr #26
 8002d50:	018b      	lsls	r3, r1, #6
 8002d52:	1a5b      	subs	r3, r3, r1
 8002d54:	eb64 0402 	sbc.w	r4, r4, r2
 8002d58:	f04f 0100 	mov.w	r1, #0
 8002d5c:	f04f 0200 	mov.w	r2, #0
 8002d60:	00e2      	lsls	r2, r4, #3
 8002d62:	ea42 7253 	orr.w	r2, r2, r3, lsr #29
 8002d66:	00d9      	lsls	r1, r3, #3
 8002d68:	460b      	mov	r3, r1
 8002d6a:	4614      	mov	r4, r2
 8002d6c:	195b      	adds	r3, r3, r5
 8002d6e:	eb44 0406 	adc.w	r4, r4, r6
 8002d72:	f04f 0100 	mov.w	r1, #0
 8002d76:	f04f 0200 	mov.w	r2, #0
 8002d7a:	0262      	lsls	r2, r4, #9
 8002d7c:	ea42 52d3 	orr.w	r2, r2, r3, lsr #23
 8002d80:	0259      	lsls	r1, r3, #9
 8002d82:	460b      	mov	r3, r1
 8002d84:	4614      	mov	r4, r2
 8002d86:	4618      	mov	r0, r3
 8002d88:	4621      	mov	r1, r4
 8002d8a:	687b      	ldr	r3, [r7, #4]
 8002d8c:	f04f 0400 	mov.w	r4, #0
 8002d90:	461a      	mov	r2, r3
 8002d92:	4623      	mov	r3, r4
 8002d94:	f7fd febc 	bl	8000b10 <__aeabi_uldivmod>
 8002d98:	4603      	mov	r3, r0
 8002d9a:	460c      	mov	r4, r1
 8002d9c:	60fb      	str	r3, [r7, #12]
 8002d9e:	e049      	b.n	8002e34 <HAL_RCC_GetSysClockFreq+0x178>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 8002da0:	4b2f      	ldr	r3, [pc, #188]	; (8002e60 <HAL_RCC_GetSysClockFreq+0x1a4>)
 8002da2:	685b      	ldr	r3, [r3, #4]
 8002da4:	099b      	lsrs	r3, r3, #6
 8002da6:	f04f 0400 	mov.w	r4, #0
 8002daa:	f240 11ff 	movw	r1, #511	; 0x1ff
 8002dae:	f04f 0200 	mov.w	r2, #0
 8002db2:	ea03 0501 	and.w	r5, r3, r1
 8002db6:	ea04 0602 	and.w	r6, r4, r2
 8002dba:	4629      	mov	r1, r5
 8002dbc:	4632      	mov	r2, r6
 8002dbe:	f04f 0300 	mov.w	r3, #0
 8002dc2:	f04f 0400 	mov.w	r4, #0
 8002dc6:	0154      	lsls	r4, r2, #5
 8002dc8:	ea44 64d1 	orr.w	r4, r4, r1, lsr #27
 8002dcc:	014b      	lsls	r3, r1, #5
 8002dce:	4619      	mov	r1, r3
 8002dd0:	4622      	mov	r2, r4
 8002dd2:	1b49      	subs	r1, r1, r5
 8002dd4:	eb62 0206 	sbc.w	r2, r2, r6
 8002dd8:	f04f 0300 	mov.w	r3, #0
 8002ddc:	f04f 0400 	mov.w	r4, #0
 8002de0:	0194      	lsls	r4, r2, #6
 8002de2:	ea44 6491 	orr.w	r4, r4, r1, lsr #26
 8002de6:	018b      	lsls	r3, r1, #6
 8002de8:	1a5b      	subs	r3, r3, r1
 8002dea:	eb64 0402 	sbc.w	r4, r4, r2
 8002dee:	f04f 0100 	mov.w	r1, #0
 8002df2:	f04f 0200 	mov.w	r2, #0
 8002df6:	00e2      	lsls	r2, r4, #3
 8002df8:	ea42 7253 	orr.w	r2, r2, r3, lsr #29
 8002dfc:	00d9      	lsls	r1, r3, #3
 8002dfe:	460b      	mov	r3, r1
 8002e00:	4614      	mov	r4, r2
 8002e02:	195b      	adds	r3, r3, r5
 8002e04:	eb44 0406 	adc.w	r4, r4, r6
 8002e08:	f04f 0100 	mov.w	r1, #0
 8002e0c:	f04f 0200 	mov.w	r2, #0
 8002e10:	02a2      	lsls	r2, r4, #10
 8002e12:	ea42 5293 	orr.w	r2, r2, r3, lsr #22
 8002e16:	0299      	lsls	r1, r3, #10
 8002e18:	460b      	mov	r3, r1
 8002e1a:	4614      	mov	r4, r2
 8002e1c:	4618      	mov	r0, r3
 8002e1e:	4621      	mov	r1, r4
 8002e20:	687b      	ldr	r3, [r7, #4]
 8002e22:	f04f 0400 	mov.w	r4, #0
 8002e26:	461a      	mov	r2, r3
 8002e28:	4623      	mov	r3, r4
 8002e2a:	f7fd fe71 	bl	8000b10 <__aeabi_uldivmod>
 8002e2e:	4603      	mov	r3, r0
 8002e30:	460c      	mov	r4, r1
 8002e32:	60fb      	str	r3, [r7, #12]
      }
      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
 8002e34:	4b0a      	ldr	r3, [pc, #40]	; (8002e60 <HAL_RCC_GetSysClockFreq+0x1a4>)
 8002e36:	685b      	ldr	r3, [r3, #4]
 8002e38:	0c1b      	lsrs	r3, r3, #16
 8002e3a:	f003 0303 	and.w	r3, r3, #3
 8002e3e:	3301      	adds	r3, #1
 8002e40:	005b      	lsls	r3, r3, #1
 8002e42:	603b      	str	r3, [r7, #0]

      sysclockfreq = pllvco/pllp;
 8002e44:	68fa      	ldr	r2, [r7, #12]
 8002e46:	683b      	ldr	r3, [r7, #0]
 8002e48:	fbb2 f3f3 	udiv	r3, r2, r3
 8002e4c:	60bb      	str	r3, [r7, #8]
      break;
 8002e4e:	e002      	b.n	8002e56 <HAL_RCC_GetSysClockFreq+0x19a>
    }
    default:
    {
      sysclockfreq = HSI_VALUE;
 8002e50:	4b04      	ldr	r3, [pc, #16]	; (8002e64 <HAL_RCC_GetSysClockFreq+0x1a8>)
 8002e52:	60bb      	str	r3, [r7, #8]
      break;
 8002e54:	bf00      	nop
    }
  }
  return sysclockfreq;
 8002e56:	68bb      	ldr	r3, [r7, #8]
}
 8002e58:	4618      	mov	r0, r3
 8002e5a:	3714      	adds	r7, #20
 8002e5c:	46bd      	mov	sp, r7
 8002e5e:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8002e60:	40023800 	.word	0x40023800
 8002e64:	00f42400 	.word	0x00f42400
 8002e68:	007a1200 	.word	0x007a1200

08002e6c <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8002e6c:	b480      	push	{r7}
 8002e6e:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8002e70:	4b03      	ldr	r3, [pc, #12]	; (8002e80 <HAL_RCC_GetHCLKFreq+0x14>)
 8002e72:	681b      	ldr	r3, [r3, #0]
}
 8002e74:	4618      	mov	r0, r3
 8002e76:	46bd      	mov	sp, r7
 8002e78:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002e7c:	4770      	bx	lr
 8002e7e:	bf00      	nop
 8002e80:	20000014 	.word	0x20000014

08002e84 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8002e84:	b580      	push	{r7, lr}
 8002e86:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
 8002e88:	f7ff fff0 	bl	8002e6c <HAL_RCC_GetHCLKFreq>
 8002e8c:	4601      	mov	r1, r0
 8002e8e:	4b05      	ldr	r3, [pc, #20]	; (8002ea4 <HAL_RCC_GetPCLK1Freq+0x20>)
 8002e90:	689b      	ldr	r3, [r3, #8]
 8002e92:	0a9b      	lsrs	r3, r3, #10
 8002e94:	f003 0307 	and.w	r3, r3, #7
 8002e98:	4a03      	ldr	r2, [pc, #12]	; (8002ea8 <HAL_RCC_GetPCLK1Freq+0x24>)
 8002e9a:	5cd3      	ldrb	r3, [r2, r3]
 8002e9c:	fa21 f303 	lsr.w	r3, r1, r3
}
 8002ea0:	4618      	mov	r0, r3
 8002ea2:	bd80      	pop	{r7, pc}
 8002ea4:	40023800 	.word	0x40023800
 8002ea8:	08006028 	.word	0x08006028

08002eac <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 8002eac:	b580      	push	{r7, lr}
 8002eae:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
 8002eb0:	f7ff ffdc 	bl	8002e6c <HAL_RCC_GetHCLKFreq>
 8002eb4:	4601      	mov	r1, r0
 8002eb6:	4b05      	ldr	r3, [pc, #20]	; (8002ecc <HAL_RCC_GetPCLK2Freq+0x20>)
 8002eb8:	689b      	ldr	r3, [r3, #8]
 8002eba:	0b5b      	lsrs	r3, r3, #13
 8002ebc:	f003 0307 	and.w	r3, r3, #7
 8002ec0:	4a03      	ldr	r2, [pc, #12]	; (8002ed0 <HAL_RCC_GetPCLK2Freq+0x24>)
 8002ec2:	5cd3      	ldrb	r3, [r2, r3]
 8002ec4:	fa21 f303 	lsr.w	r3, r1, r3
}
 8002ec8:	4618      	mov	r0, r3
 8002eca:	bd80      	pop	{r7, pc}
 8002ecc:	40023800 	.word	0x40023800
 8002ed0:	08006028 	.word	0x08006028

08002ed4 <HAL_RCCEx_PeriphCLKConfig>:
  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 8002ed4:	b580      	push	{r7, lr}
 8002ed6:	b086      	sub	sp, #24
 8002ed8:	af00      	add	r7, sp, #0
 8002eda:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U;
 8002edc:	2300      	movs	r3, #0
 8002ede:	617b      	str	r3, [r7, #20]
  uint32_t tmpreg1 = 0U;
 8002ee0:	2300      	movs	r3, #0
 8002ee2:	613b      	str	r3, [r7, #16]

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*---------------------------- I2S configuration ---------------------------*/
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
 8002ee4:	687b      	ldr	r3, [r7, #4]
 8002ee6:	681b      	ldr	r3, [r3, #0]
 8002ee8:	f003 0301 	and.w	r3, r3, #1
 8002eec:	2b00      	cmp	r3, #0
 8002eee:	d105      	bne.n	8002efc <HAL_RCCEx_PeriphCLKConfig+0x28>
     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
 8002ef0:	687b      	ldr	r3, [r7, #4]
 8002ef2:	681b      	ldr	r3, [r3, #0]
 8002ef4:	f003 0304 	and.w	r3, r3, #4
  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
 8002ef8:	2b00      	cmp	r3, #0
 8002efa:	d035      	beq.n	8002f68 <HAL_RCCEx_PeriphCLKConfig+0x94>
    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
#if defined(STM32F411xE)
    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
#endif /* STM32F411xE */
    /* Disable the PLLI2S */
    __HAL_RCC_PLLI2S_DISABLE();
 8002efc:	4b67      	ldr	r3, [pc, #412]	; (800309c <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
 8002efe:	2200      	movs	r2, #0
 8002f00:	601a      	str	r2, [r3, #0]
    /* Get tick */
    tickstart = HAL_GetTick();
 8002f02:	f7ff f86d 	bl	8001fe0 <HAL_GetTick>
 8002f06:	6178      	str	r0, [r7, #20]
    /* Wait till PLLI2S is disabled */
    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
 8002f08:	e008      	b.n	8002f1c <HAL_RCCEx_PeriphCLKConfig+0x48>
    {
      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
 8002f0a:	f7ff f869 	bl	8001fe0 <HAL_GetTick>
 8002f0e:	4602      	mov	r2, r0
 8002f10:	697b      	ldr	r3, [r7, #20]
 8002f12:	1ad3      	subs	r3, r2, r3
 8002f14:	2b02      	cmp	r3, #2
 8002f16:	d901      	bls.n	8002f1c <HAL_RCCEx_PeriphCLKConfig+0x48>
      {
        /* return in case of Timeout detected */
        return HAL_TIMEOUT;
 8002f18:	2303      	movs	r3, #3
 8002f1a:	e0ba      	b.n	8003092 <HAL_RCCEx_PeriphCLKConfig+0x1be>
    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
 8002f1c:	4b60      	ldr	r3, [pc, #384]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002f1e:	681b      	ldr	r3, [r3, #0]
 8002f20:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
 8002f24:	2b00      	cmp	r3, #0
 8002f26:	d1f0      	bne.n	8002f0a <HAL_RCCEx_PeriphCLKConfig+0x36>
    __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
#else
    /* Configure the PLLI2S division factors */
    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
 8002f28:	687b      	ldr	r3, [r7, #4]
 8002f2a:	685b      	ldr	r3, [r3, #4]
 8002f2c:	019a      	lsls	r2, r3, #6
 8002f2e:	687b      	ldr	r3, [r7, #4]
 8002f30:	689b      	ldr	r3, [r3, #8]
 8002f32:	071b      	lsls	r3, r3, #28
 8002f34:	495a      	ldr	r1, [pc, #360]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002f36:	4313      	orrs	r3, r2
 8002f38:	f8c1 3084 	str.w	r3, [r1, #132]	; 0x84
#endif /* STM32F411xE */

    /* Enable the PLLI2S */
    __HAL_RCC_PLLI2S_ENABLE();
 8002f3c:	4b57      	ldr	r3, [pc, #348]	; (800309c <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
 8002f3e:	2201      	movs	r2, #1
 8002f40:	601a      	str	r2, [r3, #0]
    /* Get tick */
    tickstart = HAL_GetTick();
 8002f42:	f7ff f84d 	bl	8001fe0 <HAL_GetTick>
 8002f46:	6178      	str	r0, [r7, #20]
    /* Wait till PLLI2S is ready */
    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
 8002f48:	e008      	b.n	8002f5c <HAL_RCCEx_PeriphCLKConfig+0x88>
    {
      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
 8002f4a:	f7ff f849 	bl	8001fe0 <HAL_GetTick>
 8002f4e:	4602      	mov	r2, r0
 8002f50:	697b      	ldr	r3, [r7, #20]
 8002f52:	1ad3      	subs	r3, r2, r3
 8002f54:	2b02      	cmp	r3, #2
 8002f56:	d901      	bls.n	8002f5c <HAL_RCCEx_PeriphCLKConfig+0x88>
      {
        /* return in case of Timeout detected */
        return HAL_TIMEOUT;
 8002f58:	2303      	movs	r3, #3
 8002f5a:	e09a      	b.n	8003092 <HAL_RCCEx_PeriphCLKConfig+0x1be>
    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
 8002f5c:	4b50      	ldr	r3, [pc, #320]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002f5e:	681b      	ldr	r3, [r3, #0]
 8002f60:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
 8002f64:	2b00      	cmp	r3, #0
 8002f66:	d0f0      	beq.n	8002f4a <HAL_RCCEx_PeriphCLKConfig+0x76>
      }
    }
  }

  /*---------------------------- RTC configuration ---------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
 8002f68:	687b      	ldr	r3, [r7, #4]
 8002f6a:	681b      	ldr	r3, [r3, #0]
 8002f6c:	f003 0302 	and.w	r3, r3, #2
 8002f70:	2b00      	cmp	r3, #0
 8002f72:	f000 8083 	beq.w	800307c <HAL_RCCEx_PeriphCLKConfig+0x1a8>
  {
    /* Check for RTC Parameters used to output RTCCLK */
    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));

    /* Enable Power Clock*/
    __HAL_RCC_PWR_CLK_ENABLE();
 8002f76:	2300      	movs	r3, #0
 8002f78:	60fb      	str	r3, [r7, #12]
 8002f7a:	4b49      	ldr	r3, [pc, #292]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002f7c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002f7e:	4a48      	ldr	r2, [pc, #288]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002f80:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8002f84:	6413      	str	r3, [r2, #64]	; 0x40
 8002f86:	4b46      	ldr	r3, [pc, #280]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002f88:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002f8a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002f8e:	60fb      	str	r3, [r7, #12]
 8002f90:	68fb      	ldr	r3, [r7, #12]

    /* Enable write access to Backup domain */
    PWR->CR |= PWR_CR_DBP;
 8002f92:	4b44      	ldr	r3, [pc, #272]	; (80030a4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
 8002f94:	681b      	ldr	r3, [r3, #0]
 8002f96:	4a43      	ldr	r2, [pc, #268]	; (80030a4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
 8002f98:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8002f9c:	6013      	str	r3, [r2, #0]

    /* Get tick */
    tickstart = HAL_GetTick();
 8002f9e:	f7ff f81f 	bl	8001fe0 <HAL_GetTick>
 8002fa2:	6178      	str	r0, [r7, #20]

    while((PWR->CR & PWR_CR_DBP) == RESET)
 8002fa4:	e008      	b.n	8002fb8 <HAL_RCCEx_PeriphCLKConfig+0xe4>
    {
      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
 8002fa6:	f7ff f81b 	bl	8001fe0 <HAL_GetTick>
 8002faa:	4602      	mov	r2, r0
 8002fac:	697b      	ldr	r3, [r7, #20]
 8002fae:	1ad3      	subs	r3, r2, r3
 8002fb0:	2b02      	cmp	r3, #2
 8002fb2:	d901      	bls.n	8002fb8 <HAL_RCCEx_PeriphCLKConfig+0xe4>
      {
        return HAL_TIMEOUT;
 8002fb4:	2303      	movs	r3, #3
 8002fb6:	e06c      	b.n	8003092 <HAL_RCCEx_PeriphCLKConfig+0x1be>
    while((PWR->CR & PWR_CR_DBP) == RESET)
 8002fb8:	4b3a      	ldr	r3, [pc, #232]	; (80030a4 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
 8002fba:	681b      	ldr	r3, [r3, #0]
 8002fbc:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8002fc0:	2b00      	cmp	r3, #0
 8002fc2:	d0f0      	beq.n	8002fa6 <HAL_RCCEx_PeriphCLKConfig+0xd2>
      }
    }
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
 8002fc4:	4b36      	ldr	r3, [pc, #216]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002fc6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002fc8:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8002fcc:	613b      	str	r3, [r7, #16]
    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8002fce:	693b      	ldr	r3, [r7, #16]
 8002fd0:	2b00      	cmp	r3, #0
 8002fd2:	d02f      	beq.n	8003034 <HAL_RCCEx_PeriphCLKConfig+0x160>
 8002fd4:	687b      	ldr	r3, [r7, #4]
 8002fd6:	68db      	ldr	r3, [r3, #12]
 8002fd8:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8002fdc:	693a      	ldr	r2, [r7, #16]
 8002fde:	429a      	cmp	r2, r3
 8002fe0:	d028      	beq.n	8003034 <HAL_RCCEx_PeriphCLKConfig+0x160>
    {
      /* Store the content of BDCR register before the reset of Backup Domain */
      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8002fe2:	4b2f      	ldr	r3, [pc, #188]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002fe4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002fe6:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8002fea:	613b      	str	r3, [r7, #16]
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
 8002fec:	4b2e      	ldr	r3, [pc, #184]	; (80030a8 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
 8002fee:	2201      	movs	r2, #1
 8002ff0:	601a      	str	r2, [r3, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8002ff2:	4b2d      	ldr	r3, [pc, #180]	; (80030a8 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
 8002ff4:	2200      	movs	r2, #0
 8002ff6:	601a      	str	r2, [r3, #0]
      /* Restore the Content of BDCR register */
      RCC->BDCR = tmpreg1;
 8002ff8:	4a29      	ldr	r2, [pc, #164]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8002ffa:	693b      	ldr	r3, [r7, #16]
 8002ffc:	6713      	str	r3, [r2, #112]	; 0x70

      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
 8002ffe:	4b28      	ldr	r3, [pc, #160]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8003000:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8003002:	f003 0301 	and.w	r3, r3, #1
 8003006:	2b01      	cmp	r3, #1
 8003008:	d114      	bne.n	8003034 <HAL_RCCEx_PeriphCLKConfig+0x160>
      {
        /* Get tick */
        tickstart = HAL_GetTick();
 800300a:	f7fe ffe9 	bl	8001fe0 <HAL_GetTick>
 800300e:	6178      	str	r0, [r7, #20]

        /* Wait till LSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8003010:	e00a      	b.n	8003028 <HAL_RCCEx_PeriphCLKConfig+0x154>
        {
          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8003012:	f7fe ffe5 	bl	8001fe0 <HAL_GetTick>
 8003016:	4602      	mov	r2, r0
 8003018:	697b      	ldr	r3, [r7, #20]
 800301a:	1ad3      	subs	r3, r2, r3
 800301c:	f241 3288 	movw	r2, #5000	; 0x1388
 8003020:	4293      	cmp	r3, r2
 8003022:	d901      	bls.n	8003028 <HAL_RCCEx_PeriphCLKConfig+0x154>
          {
            return HAL_TIMEOUT;
 8003024:	2303      	movs	r3, #3
 8003026:	e034      	b.n	8003092 <HAL_RCCEx_PeriphCLKConfig+0x1be>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8003028:	4b1d      	ldr	r3, [pc, #116]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 800302a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 800302c:	f003 0302 	and.w	r3, r3, #2
 8003030:	2b00      	cmp	r3, #0
 8003032:	d0ee      	beq.n	8003012 <HAL_RCCEx_PeriphCLKConfig+0x13e>
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8003034:	687b      	ldr	r3, [r7, #4]
 8003036:	68db      	ldr	r3, [r3, #12]
 8003038:	f403 7340 	and.w	r3, r3, #768	; 0x300
 800303c:	f5b3 7f40 	cmp.w	r3, #768	; 0x300
 8003040:	d10d      	bne.n	800305e <HAL_RCCEx_PeriphCLKConfig+0x18a>
 8003042:	4b17      	ldr	r3, [pc, #92]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8003044:	689b      	ldr	r3, [r3, #8]
 8003046:	f423 12f8 	bic.w	r2, r3, #2031616	; 0x1f0000
 800304a:	687b      	ldr	r3, [r7, #4]
 800304c:	68db      	ldr	r3, [r3, #12]
 800304e:	f023 4370 	bic.w	r3, r3, #4026531840	; 0xf0000000
 8003052:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8003056:	4912      	ldr	r1, [pc, #72]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8003058:	4313      	orrs	r3, r2
 800305a:	608b      	str	r3, [r1, #8]
 800305c:	e005      	b.n	800306a <HAL_RCCEx_PeriphCLKConfig+0x196>
 800305e:	4b10      	ldr	r3, [pc, #64]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8003060:	689b      	ldr	r3, [r3, #8]
 8003062:	4a0f      	ldr	r2, [pc, #60]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8003064:	f423 13f8 	bic.w	r3, r3, #2031616	; 0x1f0000
 8003068:	6093      	str	r3, [r2, #8]
 800306a:	4b0d      	ldr	r3, [pc, #52]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 800306c:	6f1a      	ldr	r2, [r3, #112]	; 0x70
 800306e:	687b      	ldr	r3, [r7, #4]
 8003070:	68db      	ldr	r3, [r3, #12]
 8003072:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8003076:	490a      	ldr	r1, [pc, #40]	; (80030a0 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
 8003078:	4313      	orrs	r3, r2
 800307a:	670b      	str	r3, [r1, #112]	; 0x70
  }
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
  /*---------------------------- TIM configuration ---------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
 800307c:	687b      	ldr	r3, [r7, #4]
 800307e:	681b      	ldr	r3, [r3, #0]
 8003080:	f003 0308 	and.w	r3, r3, #8
 8003084:	2b00      	cmp	r3, #0
 8003086:	d003      	beq.n	8003090 <HAL_RCCEx_PeriphCLKConfig+0x1bc>
  {
    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
 8003088:	687b      	ldr	r3, [r7, #4]
 800308a:	7c1a      	ldrb	r2, [r3, #16]
 800308c:	4b07      	ldr	r3, [pc, #28]	; (80030ac <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
 800308e:	601a      	str	r2, [r3, #0]
  }
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
  return HAL_OK;
 8003090:	2300      	movs	r3, #0
}
 8003092:	4618      	mov	r0, r3
 8003094:	3718      	adds	r7, #24
 8003096:	46bd      	mov	sp, r7
 8003098:	bd80      	pop	{r7, pc}
 800309a:	bf00      	nop
 800309c:	42470068 	.word	0x42470068
 80030a0:	40023800 	.word	0x40023800
 80030a4:	40007000 	.word	0x40007000
 80030a8:	42470e40 	.word	0x42470e40
 80030ac:	424711e0 	.word	0x424711e0

080030b0 <HAL_RTC_Init>:
  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
 80030b0:	b580      	push	{r7, lr}
 80030b2:	b082      	sub	sp, #8
 80030b4:	af00      	add	r7, sp, #0
 80030b6:	6078      	str	r0, [r7, #4]
  /* Check the RTC peripheral state */
  if(hrtc == NULL)
 80030b8:	687b      	ldr	r3, [r7, #4]
 80030ba:	2b00      	cmp	r3, #0
 80030bc:	d101      	bne.n	80030c2 <HAL_RTC_Init+0x12>
  {
     return HAL_ERROR;
 80030be:	2301      	movs	r3, #1
 80030c0:	e083      	b.n	80031ca <HAL_RTC_Init+0x11a>
    {
      hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
    }
  }
#else
  if(hrtc->State == HAL_RTC_STATE_RESET)
 80030c2:	687b      	ldr	r3, [r7, #4]
 80030c4:	7f5b      	ldrb	r3, [r3, #29]
 80030c6:	b2db      	uxtb	r3, r3
 80030c8:	2b00      	cmp	r3, #0
 80030ca:	d105      	bne.n	80030d8 <HAL_RTC_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hrtc->Lock = HAL_UNLOCKED;
 80030cc:	687b      	ldr	r3, [r7, #4]
 80030ce:	2200      	movs	r2, #0
 80030d0:	771a      	strb	r2, [r3, #28]

    /* Initialize RTC MSP */
    HAL_RTC_MspInit(hrtc);
 80030d2:	6878      	ldr	r0, [r7, #4]
 80030d4:	f7fe fe46 	bl	8001d64 <HAL_RTC_MspInit>
  }
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */

  /* Set RTC state */
  hrtc->State = HAL_RTC_STATE_BUSY;
 80030d8:	687b      	ldr	r3, [r7, #4]
 80030da:	2202      	movs	r2, #2
 80030dc:	775a      	strb	r2, [r3, #29]

  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 80030de:	687b      	ldr	r3, [r7, #4]
 80030e0:	681b      	ldr	r3, [r3, #0]
 80030e2:	22ca      	movs	r2, #202	; 0xca
 80030e4:	625a      	str	r2, [r3, #36]	; 0x24
 80030e6:	687b      	ldr	r3, [r7, #4]
 80030e8:	681b      	ldr	r3, [r3, #0]
 80030ea:	2253      	movs	r2, #83	; 0x53
 80030ec:	625a      	str	r2, [r3, #36]	; 0x24

  /* Set Initialization mode */
  if(RTC_EnterInitMode(hrtc) != HAL_OK)
 80030ee:	6878      	ldr	r0, [r7, #4]
 80030f0:	f000 fc26 	bl	8003940 <RTC_EnterInitMode>
 80030f4:	4603      	mov	r3, r0
 80030f6:	2b00      	cmp	r3, #0
 80030f8:	d008      	beq.n	800310c <HAL_RTC_Init+0x5c>
  {
    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 80030fa:	687b      	ldr	r3, [r7, #4]
 80030fc:	681b      	ldr	r3, [r3, #0]
 80030fe:	22ff      	movs	r2, #255	; 0xff
 8003100:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_ERROR;
 8003102:	687b      	ldr	r3, [r7, #4]
 8003104:	2204      	movs	r2, #4
 8003106:	775a      	strb	r2, [r3, #29]

    return HAL_ERROR;
 8003108:	2301      	movs	r3, #1
 800310a:	e05e      	b.n	80031ca <HAL_RTC_Init+0x11a>
  }
  else
  {
    /* Clear RTC_CR FMT, OSEL and POL Bits */
    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
 800310c:	687b      	ldr	r3, [r7, #4]
 800310e:	681b      	ldr	r3, [r3, #0]
 8003110:	689b      	ldr	r3, [r3, #8]
 8003112:	687a      	ldr	r2, [r7, #4]
 8003114:	6812      	ldr	r2, [r2, #0]
 8003116:	f423 03e0 	bic.w	r3, r3, #7340032	; 0x700000
 800311a:	f023 0340 	bic.w	r3, r3, #64	; 0x40
 800311e:	6093      	str	r3, [r2, #8]
    /* Set RTC_CR register */
    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
 8003120:	687b      	ldr	r3, [r7, #4]
 8003122:	681b      	ldr	r3, [r3, #0]
 8003124:	6899      	ldr	r1, [r3, #8]
 8003126:	687b      	ldr	r3, [r7, #4]
 8003128:	685a      	ldr	r2, [r3, #4]
 800312a:	687b      	ldr	r3, [r7, #4]
 800312c:	691b      	ldr	r3, [r3, #16]
 800312e:	431a      	orrs	r2, r3
 8003130:	687b      	ldr	r3, [r7, #4]
 8003132:	695b      	ldr	r3, [r3, #20]
 8003134:	431a      	orrs	r2, r3
 8003136:	687b      	ldr	r3, [r7, #4]
 8003138:	681b      	ldr	r3, [r3, #0]
 800313a:	430a      	orrs	r2, r1
 800313c:	609a      	str	r2, [r3, #8]

    /* Configure the RTC PRER */
    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
 800313e:	687b      	ldr	r3, [r7, #4]
 8003140:	681b      	ldr	r3, [r3, #0]
 8003142:	687a      	ldr	r2, [r7, #4]
 8003144:	68d2      	ldr	r2, [r2, #12]
 8003146:	611a      	str	r2, [r3, #16]
    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
 8003148:	687b      	ldr	r3, [r7, #4]
 800314a:	681b      	ldr	r3, [r3, #0]
 800314c:	6919      	ldr	r1, [r3, #16]
 800314e:	687b      	ldr	r3, [r7, #4]
 8003150:	689b      	ldr	r3, [r3, #8]
 8003152:	041a      	lsls	r2, r3, #16
 8003154:	687b      	ldr	r3, [r7, #4]
 8003156:	681b      	ldr	r3, [r3, #0]
 8003158:	430a      	orrs	r2, r1
 800315a:	611a      	str	r2, [r3, #16]

    /* Exit Initialization mode */
    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
 800315c:	687b      	ldr	r3, [r7, #4]
 800315e:	681b      	ldr	r3, [r3, #0]
 8003160:	68da      	ldr	r2, [r3, #12]
 8003162:	687b      	ldr	r3, [r7, #4]
 8003164:	681b      	ldr	r3, [r3, #0]
 8003166:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800316a:	60da      	str	r2, [r3, #12]

    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
 800316c:	687b      	ldr	r3, [r7, #4]
 800316e:	681b      	ldr	r3, [r3, #0]
 8003170:	689b      	ldr	r3, [r3, #8]
 8003172:	f003 0320 	and.w	r3, r3, #32
 8003176:	2b00      	cmp	r3, #0
 8003178:	d10e      	bne.n	8003198 <HAL_RTC_Init+0xe8>
    {
      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 800317a:	6878      	ldr	r0, [r7, #4]
 800317c:	f000 fbb8 	bl	80038f0 <HAL_RTC_WaitForSynchro>
 8003180:	4603      	mov	r3, r0
 8003182:	2b00      	cmp	r3, #0
 8003184:	d008      	beq.n	8003198 <HAL_RTC_Init+0xe8>
      {
        /* Enable the write protection for RTC registers */
        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8003186:	687b      	ldr	r3, [r7, #4]
 8003188:	681b      	ldr	r3, [r3, #0]
 800318a:	22ff      	movs	r2, #255	; 0xff
 800318c:	625a      	str	r2, [r3, #36]	; 0x24

        hrtc->State = HAL_RTC_STATE_ERROR;
 800318e:	687b      	ldr	r3, [r7, #4]
 8003190:	2204      	movs	r2, #4
 8003192:	775a      	strb	r2, [r3, #29]

        return HAL_ERROR;
 8003194:	2301      	movs	r3, #1
 8003196:	e018      	b.n	80031ca <HAL_RTC_Init+0x11a>
      }
    }

    hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
 8003198:	687b      	ldr	r3, [r7, #4]
 800319a:	681b      	ldr	r3, [r3, #0]
 800319c:	6c1a      	ldr	r2, [r3, #64]	; 0x40
 800319e:	687b      	ldr	r3, [r7, #4]
 80031a0:	681b      	ldr	r3, [r3, #0]
 80031a2:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 80031a6:	641a      	str	r2, [r3, #64]	; 0x40
    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
 80031a8:	687b      	ldr	r3, [r7, #4]
 80031aa:	681b      	ldr	r3, [r3, #0]
 80031ac:	6c19      	ldr	r1, [r3, #64]	; 0x40
 80031ae:	687b      	ldr	r3, [r7, #4]
 80031b0:	699a      	ldr	r2, [r3, #24]
 80031b2:	687b      	ldr	r3, [r7, #4]
 80031b4:	681b      	ldr	r3, [r3, #0]
 80031b6:	430a      	orrs	r2, r1
 80031b8:	641a      	str	r2, [r3, #64]	; 0x40

    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 80031ba:	687b      	ldr	r3, [r7, #4]
 80031bc:	681b      	ldr	r3, [r3, #0]
 80031be:	22ff      	movs	r2, #255	; 0xff
 80031c0:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_READY;
 80031c2:	687b      	ldr	r3, [r7, #4]
 80031c4:	2201      	movs	r2, #1
 80031c6:	775a      	strb	r2, [r3, #29]

    return HAL_OK;
 80031c8:	2300      	movs	r3, #0
  }
}
 80031ca:	4618      	mov	r0, r3
 80031cc:	3708      	adds	r7, #8
 80031ce:	46bd      	mov	sp, r7
 80031d0:	bd80      	pop	{r7, pc}

080031d2 <HAL_RTC_SetTime>:
  *            @arg RTC_FORMAT_BIN: Binary data format
  *            @arg RTC_FORMAT_BCD: BCD data format
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
 80031d2:	b590      	push	{r4, r7, lr}
 80031d4:	b087      	sub	sp, #28
 80031d6:	af00      	add	r7, sp, #0
 80031d8:	60f8      	str	r0, [r7, #12]
 80031da:	60b9      	str	r1, [r7, #8]
 80031dc:	607a      	str	r2, [r7, #4]
  uint32_t tmpreg = 0U;
 80031de:	2300      	movs	r3, #0
 80031e0:	617b      	str	r3, [r7, #20]
  assert_param(IS_RTC_FORMAT(Format));
  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));

  /* Process Locked */
  __HAL_LOCK(hrtc);
 80031e2:	68fb      	ldr	r3, [r7, #12]
 80031e4:	7f1b      	ldrb	r3, [r3, #28]
 80031e6:	2b01      	cmp	r3, #1
 80031e8:	d101      	bne.n	80031ee <HAL_RTC_SetTime+0x1c>
 80031ea:	2302      	movs	r3, #2
 80031ec:	e0aa      	b.n	8003344 <HAL_RTC_SetTime+0x172>
 80031ee:	68fb      	ldr	r3, [r7, #12]
 80031f0:	2201      	movs	r2, #1
 80031f2:	771a      	strb	r2, [r3, #28]

  hrtc->State = HAL_RTC_STATE_BUSY;
 80031f4:	68fb      	ldr	r3, [r7, #12]
 80031f6:	2202      	movs	r2, #2
 80031f8:	775a      	strb	r2, [r3, #29]

  if(Format == RTC_FORMAT_BIN)
 80031fa:	687b      	ldr	r3, [r7, #4]
 80031fc:	2b00      	cmp	r3, #0
 80031fe:	d126      	bne.n	800324e <HAL_RTC_SetTime+0x7c>
  {
    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
 8003200:	68fb      	ldr	r3, [r7, #12]
 8003202:	681b      	ldr	r3, [r3, #0]
 8003204:	689b      	ldr	r3, [r3, #8]
 8003206:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800320a:	2b00      	cmp	r3, #0
 800320c:	d102      	bne.n	8003214 <HAL_RTC_SetTime+0x42>
      assert_param(IS_RTC_HOUR12(sTime->Hours));
      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
    }
    else
    {
      sTime->TimeFormat = 0x00U;
 800320e:	68bb      	ldr	r3, [r7, #8]
 8003210:	2200      	movs	r2, #0
 8003212:	70da      	strb	r2, [r3, #3]
      assert_param(IS_RTC_HOUR24(sTime->Hours));
    }
    assert_param(IS_RTC_MINUTES(sTime->Minutes));
    assert_param(IS_RTC_SECONDS(sTime->Seconds));

    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
 8003214:	68bb      	ldr	r3, [r7, #8]
 8003216:	781b      	ldrb	r3, [r3, #0]
 8003218:	4618      	mov	r0, r3
 800321a:	f000 fbbd 	bl	8003998 <RTC_ByteToBcd2>
 800321e:	4603      	mov	r3, r0
 8003220:	041c      	lsls	r4, r3, #16
                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
 8003222:	68bb      	ldr	r3, [r7, #8]
 8003224:	785b      	ldrb	r3, [r3, #1]
 8003226:	4618      	mov	r0, r3
 8003228:	f000 fbb6 	bl	8003998 <RTC_ByteToBcd2>
 800322c:	4603      	mov	r3, r0
 800322e:	021b      	lsls	r3, r3, #8
    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
 8003230:	431c      	orrs	r4, r3
                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
 8003232:	68bb      	ldr	r3, [r7, #8]
 8003234:	789b      	ldrb	r3, [r3, #2]
 8003236:	4618      	mov	r0, r3
 8003238:	f000 fbae 	bl	8003998 <RTC_ByteToBcd2>
 800323c:	4603      	mov	r3, r0
                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
 800323e:	ea44 0203 	orr.w	r2, r4, r3
                        (((uint32_t)sTime->TimeFormat) << 16U));
 8003242:	68bb      	ldr	r3, [r7, #8]
 8003244:	78db      	ldrb	r3, [r3, #3]
 8003246:	041b      	lsls	r3, r3, #16
    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
 8003248:	4313      	orrs	r3, r2
 800324a:	617b      	str	r3, [r7, #20]
 800324c:	e018      	b.n	8003280 <HAL_RTC_SetTime+0xae>
  }
  else
  {
    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
 800324e:	68fb      	ldr	r3, [r7, #12]
 8003250:	681b      	ldr	r3, [r3, #0]
 8003252:	689b      	ldr	r3, [r3, #8]
 8003254:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8003258:	2b00      	cmp	r3, #0
 800325a:	d102      	bne.n	8003262 <HAL_RTC_SetTime+0x90>
      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
    }
    else
    {
      sTime->TimeFormat = 0x00U;
 800325c:	68bb      	ldr	r3, [r7, #8]
 800325e:	2200      	movs	r2, #0
 8003260:	70da      	strb	r2, [r3, #3]
      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
    }
    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
 8003262:	68bb      	ldr	r3, [r7, #8]
 8003264:	781b      	ldrb	r3, [r3, #0]
 8003266:	041a      	lsls	r2, r3, #16
              ((uint32_t)(sTime->Minutes) << 8U) | \
 8003268:	68bb      	ldr	r3, [r7, #8]
 800326a:	785b      	ldrb	r3, [r3, #1]
 800326c:	021b      	lsls	r3, r3, #8
    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
 800326e:	4313      	orrs	r3, r2
              ((uint32_t)sTime->Seconds) | \
 8003270:	68ba      	ldr	r2, [r7, #8]
 8003272:	7892      	ldrb	r2, [r2, #2]
              ((uint32_t)(sTime->Minutes) << 8U) | \
 8003274:	431a      	orrs	r2, r3
              ((uint32_t)(sTime->TimeFormat) << 16U));
 8003276:	68bb      	ldr	r3, [r7, #8]
 8003278:	78db      	ldrb	r3, [r3, #3]
 800327a:	041b      	lsls	r3, r3, #16
    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
 800327c:	4313      	orrs	r3, r2
 800327e:	617b      	str	r3, [r7, #20]
  }

  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 8003280:	68fb      	ldr	r3, [r7, #12]
 8003282:	681b      	ldr	r3, [r3, #0]
 8003284:	22ca      	movs	r2, #202	; 0xca
 8003286:	625a      	str	r2, [r3, #36]	; 0x24
 8003288:	68fb      	ldr	r3, [r7, #12]
 800328a:	681b      	ldr	r3, [r3, #0]
 800328c:	2253      	movs	r2, #83	; 0x53
 800328e:	625a      	str	r2, [r3, #36]	; 0x24

  /* Set Initialization mode */
  if(RTC_EnterInitMode(hrtc) != HAL_OK)
 8003290:	68f8      	ldr	r0, [r7, #12]
 8003292:	f000 fb55 	bl	8003940 <RTC_EnterInitMode>
 8003296:	4603      	mov	r3, r0
 8003298:	2b00      	cmp	r3, #0
 800329a:	d00b      	beq.n	80032b4 <HAL_RTC_SetTime+0xe2>
  {
    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 800329c:	68fb      	ldr	r3, [r7, #12]
 800329e:	681b      	ldr	r3, [r3, #0]
 80032a0:	22ff      	movs	r2, #255	; 0xff
 80032a2:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_ERROR;
 80032a4:	68fb      	ldr	r3, [r7, #12]
 80032a6:	2204      	movs	r2, #4
 80032a8:	775a      	strb	r2, [r3, #29]

    /* Process Unlocked */
    __HAL_UNLOCK(hrtc);
 80032aa:	68fb      	ldr	r3, [r7, #12]
 80032ac:	2200      	movs	r2, #0
 80032ae:	771a      	strb	r2, [r3, #28]

    return HAL_ERROR;
 80032b0:	2301      	movs	r3, #1
 80032b2:	e047      	b.n	8003344 <HAL_RTC_SetTime+0x172>
  }
  else
  {
    /* Set the RTC_TR register */
    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
 80032b4:	68fb      	ldr	r3, [r7, #12]
 80032b6:	681a      	ldr	r2, [r3, #0]
 80032b8:	697b      	ldr	r3, [r7, #20]
 80032ba:	f003 337f 	and.w	r3, r3, #2139062143	; 0x7f7f7f7f
 80032be:	f023 43fe 	bic.w	r3, r3, #2130706432	; 0x7f000000
 80032c2:	6013      	str	r3, [r2, #0]

    /* Clear the bits to be configured */
    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
 80032c4:	68fb      	ldr	r3, [r7, #12]
 80032c6:	681b      	ldr	r3, [r3, #0]
 80032c8:	689a      	ldr	r2, [r3, #8]
 80032ca:	68fb      	ldr	r3, [r7, #12]
 80032cc:	681b      	ldr	r3, [r3, #0]
 80032ce:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 80032d2:	609a      	str	r2, [r3, #8]

    /* Configure the RTC_CR register */
    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
 80032d4:	68fb      	ldr	r3, [r7, #12]
 80032d6:	681b      	ldr	r3, [r3, #0]
 80032d8:	6899      	ldr	r1, [r3, #8]
 80032da:	68bb      	ldr	r3, [r7, #8]
 80032dc:	68da      	ldr	r2, [r3, #12]
 80032de:	68bb      	ldr	r3, [r7, #8]
 80032e0:	691b      	ldr	r3, [r3, #16]
 80032e2:	431a      	orrs	r2, r3
 80032e4:	68fb      	ldr	r3, [r7, #12]
 80032e6:	681b      	ldr	r3, [r3, #0]
 80032e8:	430a      	orrs	r2, r1
 80032ea:	609a      	str	r2, [r3, #8]

    /* Exit Initialization mode */
    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
 80032ec:	68fb      	ldr	r3, [r7, #12]
 80032ee:	681b      	ldr	r3, [r3, #0]
 80032f0:	68da      	ldr	r2, [r3, #12]
 80032f2:	68fb      	ldr	r3, [r7, #12]
 80032f4:	681b      	ldr	r3, [r3, #0]
 80032f6:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 80032fa:	60da      	str	r2, [r3, #12]

    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
 80032fc:	68fb      	ldr	r3, [r7, #12]
 80032fe:	681b      	ldr	r3, [r3, #0]
 8003300:	689b      	ldr	r3, [r3, #8]
 8003302:	f003 0320 	and.w	r3, r3, #32
 8003306:	2b00      	cmp	r3, #0
 8003308:	d111      	bne.n	800332e <HAL_RTC_SetTime+0x15c>
    {
      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 800330a:	68f8      	ldr	r0, [r7, #12]
 800330c:	f000 faf0 	bl	80038f0 <HAL_RTC_WaitForSynchro>
 8003310:	4603      	mov	r3, r0
 8003312:	2b00      	cmp	r3, #0
 8003314:	d00b      	beq.n	800332e <HAL_RTC_SetTime+0x15c>
      {
        /* Enable the write protection for RTC registers */
        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8003316:	68fb      	ldr	r3, [r7, #12]
 8003318:	681b      	ldr	r3, [r3, #0]
 800331a:	22ff      	movs	r2, #255	; 0xff
 800331c:	625a      	str	r2, [r3, #36]	; 0x24

        hrtc->State = HAL_RTC_STATE_ERROR;
 800331e:	68fb      	ldr	r3, [r7, #12]
 8003320:	2204      	movs	r2, #4
 8003322:	775a      	strb	r2, [r3, #29]

        /* Process Unlocked */
        __HAL_UNLOCK(hrtc);
 8003324:	68fb      	ldr	r3, [r7, #12]
 8003326:	2200      	movs	r2, #0
 8003328:	771a      	strb	r2, [r3, #28]

        return HAL_ERROR;
 800332a:	2301      	movs	r3, #1
 800332c:	e00a      	b.n	8003344 <HAL_RTC_SetTime+0x172>
      }
    }

    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 800332e:	68fb      	ldr	r3, [r7, #12]
 8003330:	681b      	ldr	r3, [r3, #0]
 8003332:	22ff      	movs	r2, #255	; 0xff
 8003334:	625a      	str	r2, [r3, #36]	; 0x24

   hrtc->State = HAL_RTC_STATE_READY;
 8003336:	68fb      	ldr	r3, [r7, #12]
 8003338:	2201      	movs	r2, #1
 800333a:	775a      	strb	r2, [r3, #29]

   __HAL_UNLOCK(hrtc);
 800333c:	68fb      	ldr	r3, [r7, #12]
 800333e:	2200      	movs	r2, #0
 8003340:	771a      	strb	r2, [r3, #28]

   return HAL_OK;
 8003342:	2300      	movs	r3, #0
  }
}
 8003344:	4618      	mov	r0, r3
 8003346:	371c      	adds	r7, #28
 8003348:	46bd      	mov	sp, r7
 800334a:	bd90      	pop	{r4, r7, pc}

0800334c <HAL_RTC_GetTime>:
  *        in the higher-order calendar shadow registers to ensure consistency between the time and date values.
  *        Reading RTC current time locks the values in calendar shadow registers until current date is read.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
 800334c:	b580      	push	{r7, lr}
 800334e:	b086      	sub	sp, #24
 8003350:	af00      	add	r7, sp, #0
 8003352:	60f8      	str	r0, [r7, #12]
 8003354:	60b9      	str	r1, [r7, #8]
 8003356:	607a      	str	r2, [r7, #4]
  uint32_t tmpreg = 0U;
 8003358:	2300      	movs	r3, #0
 800335a:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_RTC_FORMAT(Format));

  /* Get subseconds structure field from the corresponding register */
  sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
 800335c:	68fb      	ldr	r3, [r7, #12]
 800335e:	681b      	ldr	r3, [r3, #0]
 8003360:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 8003362:	68bb      	ldr	r3, [r7, #8]
 8003364:	605a      	str	r2, [r3, #4]

  /* Get SecondFraction structure field from the corresponding register field*/
  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
 8003366:	68fb      	ldr	r3, [r7, #12]
 8003368:	681b      	ldr	r3, [r3, #0]
 800336a:	691b      	ldr	r3, [r3, #16]
 800336c:	f3c3 020e 	ubfx	r2, r3, #0, #15
 8003370:	68bb      	ldr	r3, [r7, #8]
 8003372:	609a      	str	r2, [r3, #8]

  /* Get the TR register */
  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
 8003374:	68fb      	ldr	r3, [r7, #12]
 8003376:	681b      	ldr	r3, [r3, #0]
 8003378:	681b      	ldr	r3, [r3, #0]
 800337a:	f003 337f 	and.w	r3, r3, #2139062143	; 0x7f7f7f7f
 800337e:	f023 43fe 	bic.w	r3, r3, #2130706432	; 0x7f000000
 8003382:	617b      	str	r3, [r7, #20]

  /* Fill the structure fields with the read parameters */
  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
 8003384:	697b      	ldr	r3, [r7, #20]
 8003386:	0c1b      	lsrs	r3, r3, #16
 8003388:	b2db      	uxtb	r3, r3
 800338a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 800338e:	b2da      	uxtb	r2, r3
 8003390:	68bb      	ldr	r3, [r7, #8]
 8003392:	701a      	strb	r2, [r3, #0]
  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
 8003394:	697b      	ldr	r3, [r7, #20]
 8003396:	0a1b      	lsrs	r3, r3, #8
 8003398:	b2db      	uxtb	r3, r3
 800339a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
 800339e:	b2da      	uxtb	r2, r3
 80033a0:	68bb      	ldr	r3, [r7, #8]
 80033a2:	705a      	strb	r2, [r3, #1]
  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
 80033a4:	697b      	ldr	r3, [r7, #20]
 80033a6:	b2db      	uxtb	r3, r3
 80033a8:	f003 037f 	and.w	r3, r3, #127	; 0x7f
 80033ac:	b2da      	uxtb	r2, r3
 80033ae:	68bb      	ldr	r3, [r7, #8]
 80033b0:	709a      	strb	r2, [r3, #2]
  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
 80033b2:	697b      	ldr	r3, [r7, #20]
 80033b4:	0c1b      	lsrs	r3, r3, #16
 80033b6:	b2db      	uxtb	r3, r3
 80033b8:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80033bc:	b2da      	uxtb	r2, r3
 80033be:	68bb      	ldr	r3, [r7, #8]
 80033c0:	70da      	strb	r2, [r3, #3]

  /* Check the input parameters format */
  if(Format == RTC_FORMAT_BIN)
 80033c2:	687b      	ldr	r3, [r7, #4]
 80033c4:	2b00      	cmp	r3, #0
 80033c6:	d11a      	bne.n	80033fe <HAL_RTC_GetTime+0xb2>
  {
    /* Convert the time structure parameters to Binary format */
    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
 80033c8:	68bb      	ldr	r3, [r7, #8]
 80033ca:	781b      	ldrb	r3, [r3, #0]
 80033cc:	4618      	mov	r0, r3
 80033ce:	f000 fb01 	bl	80039d4 <RTC_Bcd2ToByte>
 80033d2:	4603      	mov	r3, r0
 80033d4:	461a      	mov	r2, r3
 80033d6:	68bb      	ldr	r3, [r7, #8]
 80033d8:	701a      	strb	r2, [r3, #0]
    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
 80033da:	68bb      	ldr	r3, [r7, #8]
 80033dc:	785b      	ldrb	r3, [r3, #1]
 80033de:	4618      	mov	r0, r3
 80033e0:	f000 faf8 	bl	80039d4 <RTC_Bcd2ToByte>
 80033e4:	4603      	mov	r3, r0
 80033e6:	461a      	mov	r2, r3
 80033e8:	68bb      	ldr	r3, [r7, #8]
 80033ea:	705a      	strb	r2, [r3, #1]
    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
 80033ec:	68bb      	ldr	r3, [r7, #8]
 80033ee:	789b      	ldrb	r3, [r3, #2]
 80033f0:	4618      	mov	r0, r3
 80033f2:	f000 faef 	bl	80039d4 <RTC_Bcd2ToByte>
 80033f6:	4603      	mov	r3, r0
 80033f8:	461a      	mov	r2, r3
 80033fa:	68bb      	ldr	r3, [r7, #8]
 80033fc:	709a      	strb	r2, [r3, #2]
  }

  return HAL_OK;
 80033fe:	2300      	movs	r3, #0
}
 8003400:	4618      	mov	r0, r3
 8003402:	3718      	adds	r7, #24
 8003404:	46bd      	mov	sp, r7
 8003406:	bd80      	pop	{r7, pc}

08003408 <HAL_RTC_SetDate>:
  *            @arg RTC_FORMAT_BIN: Binary data format
  *            @arg RTC_FORMAT_BCD: BCD data format
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
 8003408:	b590      	push	{r4, r7, lr}
 800340a:	b087      	sub	sp, #28
 800340c:	af00      	add	r7, sp, #0
 800340e:	60f8      	str	r0, [r7, #12]
 8003410:	60b9      	str	r1, [r7, #8]
 8003412:	607a      	str	r2, [r7, #4]
  uint32_t datetmpreg = 0U;
 8003414:	2300      	movs	r3, #0
 8003416:	617b      	str	r3, [r7, #20]

 /* Check the parameters */
  assert_param(IS_RTC_FORMAT(Format));

 /* Process Locked */
 __HAL_LOCK(hrtc);
 8003418:	68fb      	ldr	r3, [r7, #12]
 800341a:	7f1b      	ldrb	r3, [r3, #28]
 800341c:	2b01      	cmp	r3, #1
 800341e:	d101      	bne.n	8003424 <HAL_RTC_SetDate+0x1c>
 8003420:	2302      	movs	r3, #2
 8003422:	e094      	b.n	800354e <HAL_RTC_SetDate+0x146>
 8003424:	68fb      	ldr	r3, [r7, #12]
 8003426:	2201      	movs	r2, #1
 8003428:	771a      	strb	r2, [r3, #28]

  hrtc->State = HAL_RTC_STATE_BUSY;
 800342a:	68fb      	ldr	r3, [r7, #12]
 800342c:	2202      	movs	r2, #2
 800342e:	775a      	strb	r2, [r3, #29]

  if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
 8003430:	687b      	ldr	r3, [r7, #4]
 8003432:	2b00      	cmp	r3, #0
 8003434:	d10e      	bne.n	8003454 <HAL_RTC_SetDate+0x4c>
 8003436:	68bb      	ldr	r3, [r7, #8]
 8003438:	785b      	ldrb	r3, [r3, #1]
 800343a:	f003 0310 	and.w	r3, r3, #16
 800343e:	2b00      	cmp	r3, #0
 8003440:	d008      	beq.n	8003454 <HAL_RTC_SetDate+0x4c>
  {
    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
 8003442:	68bb      	ldr	r3, [r7, #8]
 8003444:	785b      	ldrb	r3, [r3, #1]
 8003446:	f023 0310 	bic.w	r3, r3, #16
 800344a:	b2db      	uxtb	r3, r3
 800344c:	330a      	adds	r3, #10
 800344e:	b2da      	uxtb	r2, r3
 8003450:	68bb      	ldr	r3, [r7, #8]
 8003452:	705a      	strb	r2, [r3, #1]
  }

  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));

  if(Format == RTC_FORMAT_BIN)
 8003454:	687b      	ldr	r3, [r7, #4]
 8003456:	2b00      	cmp	r3, #0
 8003458:	d11c      	bne.n	8003494 <HAL_RTC_SetDate+0x8c>
  {
    assert_param(IS_RTC_YEAR(sDate->Year));
    assert_param(IS_RTC_MONTH(sDate->Month));
    assert_param(IS_RTC_DATE(sDate->Date));

   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
 800345a:	68bb      	ldr	r3, [r7, #8]
 800345c:	78db      	ldrb	r3, [r3, #3]
 800345e:	4618      	mov	r0, r3
 8003460:	f000 fa9a 	bl	8003998 <RTC_ByteToBcd2>
 8003464:	4603      	mov	r3, r0
 8003466:	041c      	lsls	r4, r3, #16
                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
 8003468:	68bb      	ldr	r3, [r7, #8]
 800346a:	785b      	ldrb	r3, [r3, #1]
 800346c:	4618      	mov	r0, r3
 800346e:	f000 fa93 	bl	8003998 <RTC_ByteToBcd2>
 8003472:	4603      	mov	r3, r0
 8003474:	021b      	lsls	r3, r3, #8
   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
 8003476:	431c      	orrs	r4, r3
                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
 8003478:	68bb      	ldr	r3, [r7, #8]
 800347a:	789b      	ldrb	r3, [r3, #2]
 800347c:	4618      	mov	r0, r3
 800347e:	f000 fa8b 	bl	8003998 <RTC_ByteToBcd2>
 8003482:	4603      	mov	r3, r0
                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
 8003484:	ea44 0203 	orr.w	r2, r4, r3
                 ((uint32_t)sDate->WeekDay << 13U));
 8003488:	68bb      	ldr	r3, [r7, #8]
 800348a:	781b      	ldrb	r3, [r3, #0]
 800348c:	035b      	lsls	r3, r3, #13
   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
 800348e:	4313      	orrs	r3, r2
 8003490:	617b      	str	r3, [r7, #20]
 8003492:	e00e      	b.n	80034b2 <HAL_RTC_SetDate+0xaa>
  {
    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
    assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
    assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));

    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
 8003494:	68bb      	ldr	r3, [r7, #8]
 8003496:	78db      	ldrb	r3, [r3, #3]
 8003498:	041a      	lsls	r2, r3, #16
                  (((uint32_t)sDate->Month) << 8U) | \
 800349a:	68bb      	ldr	r3, [r7, #8]
 800349c:	785b      	ldrb	r3, [r3, #1]
 800349e:	021b      	lsls	r3, r3, #8
    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
 80034a0:	4313      	orrs	r3, r2
                  ((uint32_t)sDate->Date) | \
 80034a2:	68ba      	ldr	r2, [r7, #8]
 80034a4:	7892      	ldrb	r2, [r2, #2]
                  (((uint32_t)sDate->Month) << 8U) | \
 80034a6:	431a      	orrs	r2, r3
                  (((uint32_t)sDate->WeekDay) << 13U));
 80034a8:	68bb      	ldr	r3, [r7, #8]
 80034aa:	781b      	ldrb	r3, [r3, #0]
 80034ac:	035b      	lsls	r3, r3, #13
    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
 80034ae:	4313      	orrs	r3, r2
 80034b0:	617b      	str	r3, [r7, #20]
  }

  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 80034b2:	68fb      	ldr	r3, [r7, #12]
 80034b4:	681b      	ldr	r3, [r3, #0]
 80034b6:	22ca      	movs	r2, #202	; 0xca
 80034b8:	625a      	str	r2, [r3, #36]	; 0x24
 80034ba:	68fb      	ldr	r3, [r7, #12]
 80034bc:	681b      	ldr	r3, [r3, #0]
 80034be:	2253      	movs	r2, #83	; 0x53
 80034c0:	625a      	str	r2, [r3, #36]	; 0x24

  /* Set Initialization mode */
  if(RTC_EnterInitMode(hrtc) != HAL_OK)
 80034c2:	68f8      	ldr	r0, [r7, #12]
 80034c4:	f000 fa3c 	bl	8003940 <RTC_EnterInitMode>
 80034c8:	4603      	mov	r3, r0
 80034ca:	2b00      	cmp	r3, #0
 80034cc:	d00b      	beq.n	80034e6 <HAL_RTC_SetDate+0xde>
  {
    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 80034ce:	68fb      	ldr	r3, [r7, #12]
 80034d0:	681b      	ldr	r3, [r3, #0]
 80034d2:	22ff      	movs	r2, #255	; 0xff
 80034d4:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state*/
    hrtc->State = HAL_RTC_STATE_ERROR;
 80034d6:	68fb      	ldr	r3, [r7, #12]
 80034d8:	2204      	movs	r2, #4
 80034da:	775a      	strb	r2, [r3, #29]

    /* Process Unlocked */
    __HAL_UNLOCK(hrtc);
 80034dc:	68fb      	ldr	r3, [r7, #12]
 80034de:	2200      	movs	r2, #0
 80034e0:	771a      	strb	r2, [r3, #28]

    return HAL_ERROR;
 80034e2:	2301      	movs	r3, #1
 80034e4:	e033      	b.n	800354e <HAL_RTC_SetDate+0x146>
  }
  else
  {
    /* Set the RTC_DR register */
    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
 80034e6:	68fb      	ldr	r3, [r7, #12]
 80034e8:	681a      	ldr	r2, [r3, #0]
 80034ea:	697b      	ldr	r3, [r7, #20]
 80034ec:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
 80034f0:	f023 03c0 	bic.w	r3, r3, #192	; 0xc0
 80034f4:	6053      	str	r3, [r2, #4]

    /* Exit Initialization mode */
    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
 80034f6:	68fb      	ldr	r3, [r7, #12]
 80034f8:	681b      	ldr	r3, [r3, #0]
 80034fa:	68da      	ldr	r2, [r3, #12]
 80034fc:	68fb      	ldr	r3, [r7, #12]
 80034fe:	681b      	ldr	r3, [r3, #0]
 8003500:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8003504:	60da      	str	r2, [r3, #12]

    /* If  CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
    if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
 8003506:	68fb      	ldr	r3, [r7, #12]
 8003508:	681b      	ldr	r3, [r3, #0]
 800350a:	689b      	ldr	r3, [r3, #8]
 800350c:	f003 0320 	and.w	r3, r3, #32
 8003510:	2b00      	cmp	r3, #0
 8003512:	d111      	bne.n	8003538 <HAL_RTC_SetDate+0x130>
    {
      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 8003514:	68f8      	ldr	r0, [r7, #12]
 8003516:	f000 f9eb 	bl	80038f0 <HAL_RTC_WaitForSynchro>
 800351a:	4603      	mov	r3, r0
 800351c:	2b00      	cmp	r3, #0
 800351e:	d00b      	beq.n	8003538 <HAL_RTC_SetDate+0x130>
      {
        /* Enable the write protection for RTC registers */
        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8003520:	68fb      	ldr	r3, [r7, #12]
 8003522:	681b      	ldr	r3, [r3, #0]
 8003524:	22ff      	movs	r2, #255	; 0xff
 8003526:	625a      	str	r2, [r3, #36]	; 0x24

        hrtc->State = HAL_RTC_STATE_ERROR;
 8003528:	68fb      	ldr	r3, [r7, #12]
 800352a:	2204      	movs	r2, #4
 800352c:	775a      	strb	r2, [r3, #29]

        /* Process Unlocked */
        __HAL_UNLOCK(hrtc);
 800352e:	68fb      	ldr	r3, [r7, #12]
 8003530:	2200      	movs	r2, #0
 8003532:	771a      	strb	r2, [r3, #28]

        return HAL_ERROR;
 8003534:	2301      	movs	r3, #1
 8003536:	e00a      	b.n	800354e <HAL_RTC_SetDate+0x146>
      }
    }

    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8003538:	68fb      	ldr	r3, [r7, #12]
 800353a:	681b      	ldr	r3, [r3, #0]
 800353c:	22ff      	movs	r2, #255	; 0xff
 800353e:	625a      	str	r2, [r3, #36]	; 0x24

    hrtc->State = HAL_RTC_STATE_READY ;
 8003540:	68fb      	ldr	r3, [r7, #12]
 8003542:	2201      	movs	r2, #1
 8003544:	775a      	strb	r2, [r3, #29]

    /* Process Unlocked */
    __HAL_UNLOCK(hrtc);
 8003546:	68fb      	ldr	r3, [r7, #12]
 8003548:	2200      	movs	r2, #0
 800354a:	771a      	strb	r2, [r3, #28]

    return HAL_OK;
 800354c:	2300      	movs	r3, #0
  }
}
 800354e:	4618      	mov	r0, r3
 8003550:	371c      	adds	r7, #28
 8003552:	46bd      	mov	sp, r7
 8003554:	bd90      	pop	{r4, r7, pc}

08003556 <HAL_RTC_GetDate>:
  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
 8003556:	b580      	push	{r7, lr}
 8003558:	b086      	sub	sp, #24
 800355a:	af00      	add	r7, sp, #0
 800355c:	60f8      	str	r0, [r7, #12]
 800355e:	60b9      	str	r1, [r7, #8]
 8003560:	607a      	str	r2, [r7, #4]
  uint32_t datetmpreg = 0U;
 8003562:	2300      	movs	r3, #0
 8003564:	617b      	str	r3, [r7, #20]

  /* Check the parameters */
  assert_param(IS_RTC_FORMAT(Format));

  /* Get the DR register */
  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
 8003566:	68fb      	ldr	r3, [r7, #12]
 8003568:	681b      	ldr	r3, [r3, #0]
 800356a:	685b      	ldr	r3, [r3, #4]
 800356c:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
 8003570:	f023 03c0 	bic.w	r3, r3, #192	; 0xc0
 8003574:	617b      	str	r3, [r7, #20]

  /* Fill the structure fields with the read parameters */
  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
 8003576:	697b      	ldr	r3, [r7, #20]
 8003578:	0c1b      	lsrs	r3, r3, #16
 800357a:	b2da      	uxtb	r2, r3
 800357c:	68bb      	ldr	r3, [r7, #8]
 800357e:	70da      	strb	r2, [r3, #3]
  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
 8003580:	697b      	ldr	r3, [r7, #20]
 8003582:	0a1b      	lsrs	r3, r3, #8
 8003584:	b2db      	uxtb	r3, r3
 8003586:	f003 031f 	and.w	r3, r3, #31
 800358a:	b2da      	uxtb	r2, r3
 800358c:	68bb      	ldr	r3, [r7, #8]
 800358e:	705a      	strb	r2, [r3, #1]
  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
 8003590:	697b      	ldr	r3, [r7, #20]
 8003592:	b2db      	uxtb	r3, r3
 8003594:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 8003598:	b2da      	uxtb	r2, r3
 800359a:	68bb      	ldr	r3, [r7, #8]
 800359c:	709a      	strb	r2, [r3, #2]
  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
 800359e:	697b      	ldr	r3, [r7, #20]
 80035a0:	0b5b      	lsrs	r3, r3, #13
 80035a2:	b2db      	uxtb	r3, r3
 80035a4:	f003 0307 	and.w	r3, r3, #7
 80035a8:	b2da      	uxtb	r2, r3
 80035aa:	68bb      	ldr	r3, [r7, #8]
 80035ac:	701a      	strb	r2, [r3, #0]

  /* Check the input parameters format */
  if(Format == RTC_FORMAT_BIN)
 80035ae:	687b      	ldr	r3, [r7, #4]
 80035b0:	2b00      	cmp	r3, #0
 80035b2:	d11a      	bne.n	80035ea <HAL_RTC_GetDate+0x94>
  {
    /* Convert the date structure parameters to Binary format */
    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
 80035b4:	68bb      	ldr	r3, [r7, #8]
 80035b6:	78db      	ldrb	r3, [r3, #3]
 80035b8:	4618      	mov	r0, r3
 80035ba:	f000 fa0b 	bl	80039d4 <RTC_Bcd2ToByte>
 80035be:	4603      	mov	r3, r0
 80035c0:	461a      	mov	r2, r3
 80035c2:	68bb      	ldr	r3, [r7, #8]
 80035c4:	70da      	strb	r2, [r3, #3]
    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
 80035c6:	68bb      	ldr	r3, [r7, #8]
 80035c8:	785b      	ldrb	r3, [r3, #1]
 80035ca:	4618      	mov	r0, r3
 80035cc:	f000 fa02 	bl	80039d4 <RTC_Bcd2ToByte>
 80035d0:	4603      	mov	r3, r0
 80035d2:	461a      	mov	r2, r3
 80035d4:	68bb      	ldr	r3, [r7, #8]
 80035d6:	705a      	strb	r2, [r3, #1]
    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
 80035d8:	68bb      	ldr	r3, [r7, #8]
 80035da:	789b      	ldrb	r3, [r3, #2]
 80035dc:	4618      	mov	r0, r3
 80035de:	f000 f9f9 	bl	80039d4 <RTC_Bcd2ToByte>
 80035e2:	4603      	mov	r3, r0
 80035e4:	461a      	mov	r2, r3
 80035e6:	68bb      	ldr	r3, [r7, #8]
 80035e8:	709a      	strb	r2, [r3, #2]
  }
  return HAL_OK;
 80035ea:	2300      	movs	r3, #0
}
 80035ec:	4618      	mov	r0, r3
 80035ee:	3718      	adds	r7, #24
 80035f0:	46bd      	mov	sp, r7
 80035f2:	bd80      	pop	{r7, pc}

080035f4 <HAL_RTC_SetAlarm_IT>:
  *             @arg RTC_FORMAT_BIN: Binary data format
  *             @arg RTC_FORMAT_BCD: BCD data format
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
 80035f4:	b590      	push	{r4, r7, lr}
 80035f6:	b089      	sub	sp, #36	; 0x24
 80035f8:	af00      	add	r7, sp, #0
 80035fa:	60f8      	str	r0, [r7, #12]
 80035fc:	60b9      	str	r1, [r7, #8]
 80035fe:	607a      	str	r2, [r7, #4]
  uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
 8003600:	2300      	movs	r3, #0
 8003602:	61fb      	str	r3, [r7, #28]
 8003604:	2300      	movs	r3, #0
 8003606:	61bb      	str	r3, [r7, #24]
  __IO uint32_t count = RTC_TIMEOUT_VALUE  * (SystemCoreClock / 32U / 1000U) ;
 8003608:	4b93      	ldr	r3, [pc, #588]	; (8003858 <HAL_RTC_SetAlarm_IT+0x264>)
 800360a:	681b      	ldr	r3, [r3, #0]
 800360c:	4a93      	ldr	r2, [pc, #588]	; (800385c <HAL_RTC_SetAlarm_IT+0x268>)
 800360e:	fba2 2303 	umull	r2, r3, r2, r3
 8003612:	0adb      	lsrs	r3, r3, #11
 8003614:	f44f 727a 	mov.w	r2, #1000	; 0x3e8
 8003618:	fb02 f303 	mul.w	r3, r2, r3
 800361c:	617b      	str	r3, [r7, #20]
  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));

  /* Process Locked */
  __HAL_LOCK(hrtc);
 800361e:	68fb      	ldr	r3, [r7, #12]
 8003620:	7f1b      	ldrb	r3, [r3, #28]
 8003622:	2b01      	cmp	r3, #1
 8003624:	d101      	bne.n	800362a <HAL_RTC_SetAlarm_IT+0x36>
 8003626:	2302      	movs	r3, #2
 8003628:	e111      	b.n	800384e <HAL_RTC_SetAlarm_IT+0x25a>
 800362a:	68fb      	ldr	r3, [r7, #12]
 800362c:	2201      	movs	r2, #1
 800362e:	771a      	strb	r2, [r3, #28]

  hrtc->State = HAL_RTC_STATE_BUSY;
 8003630:	68fb      	ldr	r3, [r7, #12]
 8003632:	2202      	movs	r2, #2
 8003634:	775a      	strb	r2, [r3, #29]

  if(Format == RTC_FORMAT_BIN)
 8003636:	687b      	ldr	r3, [r7, #4]
 8003638:	2b00      	cmp	r3, #0
 800363a:	d137      	bne.n	80036ac <HAL_RTC_SetAlarm_IT+0xb8>
  {
    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
 800363c:	68fb      	ldr	r3, [r7, #12]
 800363e:	681b      	ldr	r3, [r3, #0]
 8003640:	689b      	ldr	r3, [r3, #8]
 8003642:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8003646:	2b00      	cmp	r3, #0
 8003648:	d102      	bne.n	8003650 <HAL_RTC_SetAlarm_IT+0x5c>
      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
    }
    else
    {
      sAlarm->AlarmTime.TimeFormat = 0x00U;
 800364a:	68bb      	ldr	r3, [r7, #8]
 800364c:	2200      	movs	r2, #0
 800364e:	70da      	strb	r2, [r3, #3]
    }
    else
    {
      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
    }
    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
 8003650:	68bb      	ldr	r3, [r7, #8]
 8003652:	781b      	ldrb	r3, [r3, #0]
 8003654:	4618      	mov	r0, r3
 8003656:	f000 f99f 	bl	8003998 <RTC_ByteToBcd2>
 800365a:	4603      	mov	r3, r0
 800365c:	041c      	lsls	r4, r3, #16
              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
 800365e:	68bb      	ldr	r3, [r7, #8]
 8003660:	785b      	ldrb	r3, [r3, #1]
 8003662:	4618      	mov	r0, r3
 8003664:	f000 f998 	bl	8003998 <RTC_ByteToBcd2>
 8003668:	4603      	mov	r3, r0
 800366a:	021b      	lsls	r3, r3, #8
    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
 800366c:	431c      	orrs	r4, r3
              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
 800366e:	68bb      	ldr	r3, [r7, #8]
 8003670:	789b      	ldrb	r3, [r3, #2]
 8003672:	4618      	mov	r0, r3
 8003674:	f000 f990 	bl	8003998 <RTC_ByteToBcd2>
 8003678:	4603      	mov	r3, r0
              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
 800367a:	ea44 0203 	orr.w	r2, r4, r3
              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
 800367e:	68bb      	ldr	r3, [r7, #8]
 8003680:	78db      	ldrb	r3, [r3, #3]
 8003682:	041b      	lsls	r3, r3, #16
              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
 8003684:	ea42 0403 	orr.w	r4, r2, r3
              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
 8003688:	68bb      	ldr	r3, [r7, #8]
 800368a:	f893 3020 	ldrb.w	r3, [r3, #32]
 800368e:	4618      	mov	r0, r3
 8003690:	f000 f982 	bl	8003998 <RTC_ByteToBcd2>
 8003694:	4603      	mov	r3, r0
 8003696:	061b      	lsls	r3, r3, #24
              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
 8003698:	ea44 0203 	orr.w	r2, r4, r3
              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
 800369c:	68bb      	ldr	r3, [r7, #8]
 800369e:	69db      	ldr	r3, [r3, #28]
              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
 80036a0:	431a      	orrs	r2, r3
              ((uint32_t)sAlarm->AlarmMask));
 80036a2:	68bb      	ldr	r3, [r7, #8]
 80036a4:	695b      	ldr	r3, [r3, #20]
    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
 80036a6:	4313      	orrs	r3, r2
 80036a8:	61fb      	str	r3, [r7, #28]
 80036aa:	e023      	b.n	80036f4 <HAL_RTC_SetAlarm_IT+0x100>
  }
  else
  {
    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
 80036ac:	68fb      	ldr	r3, [r7, #12]
 80036ae:	681b      	ldr	r3, [r3, #0]
 80036b0:	689b      	ldr	r3, [r3, #8]
 80036b2:	f003 0340 	and.w	r3, r3, #64	; 0x40
 80036b6:	2b00      	cmp	r3, #0
 80036b8:	d102      	bne.n	80036c0 <HAL_RTC_SetAlarm_IT+0xcc>
      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
    }
    else
    {
      sAlarm->AlarmTime.TimeFormat = 0x00U;
 80036ba:	68bb      	ldr	r3, [r7, #8]
 80036bc:	2200      	movs	r2, #0
 80036be:	70da      	strb	r2, [r3, #3]
    }
    else
    {
      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
    }
    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
 80036c0:	68bb      	ldr	r3, [r7, #8]
 80036c2:	781b      	ldrb	r3, [r3, #0]
 80036c4:	041a      	lsls	r2, r3, #16
              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
 80036c6:	68bb      	ldr	r3, [r7, #8]
 80036c8:	785b      	ldrb	r3, [r3, #1]
 80036ca:	021b      	lsls	r3, r3, #8
    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
 80036cc:	4313      	orrs	r3, r2
              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
 80036ce:	68ba      	ldr	r2, [r7, #8]
 80036d0:	7892      	ldrb	r2, [r2, #2]
              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
 80036d2:	431a      	orrs	r2, r3
              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
 80036d4:	68bb      	ldr	r3, [r7, #8]
 80036d6:	78db      	ldrb	r3, [r3, #3]
 80036d8:	041b      	lsls	r3, r3, #16
              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
 80036da:	431a      	orrs	r2, r3
              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
 80036dc:	68bb      	ldr	r3, [r7, #8]
 80036de:	f893 3020 	ldrb.w	r3, [r3, #32]
 80036e2:	061b      	lsls	r3, r3, #24
              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
 80036e4:	431a      	orrs	r2, r3
              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
 80036e6:	68bb      	ldr	r3, [r7, #8]
 80036e8:	69db      	ldr	r3, [r3, #28]
              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
 80036ea:	431a      	orrs	r2, r3
              ((uint32_t)sAlarm->AlarmMask));
 80036ec:	68bb      	ldr	r3, [r7, #8]
 80036ee:	695b      	ldr	r3, [r3, #20]
    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
 80036f0:	4313      	orrs	r3, r2
 80036f2:	61fb      	str	r3, [r7, #28]
  }
  /* Configure the Alarm A or Alarm B Sub Second registers */
  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
 80036f4:	68bb      	ldr	r3, [r7, #8]
 80036f6:	685a      	ldr	r2, [r3, #4]
 80036f8:	68bb      	ldr	r3, [r7, #8]
 80036fa:	699b      	ldr	r3, [r3, #24]
 80036fc:	4313      	orrs	r3, r2
 80036fe:	61bb      	str	r3, [r7, #24]

  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 8003700:	68fb      	ldr	r3, [r7, #12]
 8003702:	681b      	ldr	r3, [r3, #0]
 8003704:	22ca      	movs	r2, #202	; 0xca
 8003706:	625a      	str	r2, [r3, #36]	; 0x24
 8003708:	68fb      	ldr	r3, [r7, #12]
 800370a:	681b      	ldr	r3, [r3, #0]
 800370c:	2253      	movs	r2, #83	; 0x53
 800370e:	625a      	str	r2, [r3, #36]	; 0x24

  /* Configure the Alarm register */
  if(sAlarm->Alarm == RTC_ALARM_A)
 8003710:	68bb      	ldr	r3, [r7, #8]
 8003712:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003714:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 8003718:	d141      	bne.n	800379e <HAL_RTC_SetAlarm_IT+0x1aa>
  {
    /* Disable the Alarm A interrupt */
    __HAL_RTC_ALARMA_DISABLE(hrtc);
 800371a:	68fb      	ldr	r3, [r7, #12]
 800371c:	681b      	ldr	r3, [r3, #0]
 800371e:	689a      	ldr	r2, [r3, #8]
 8003720:	68fb      	ldr	r3, [r7, #12]
 8003722:	681b      	ldr	r3, [r3, #0]
 8003724:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 8003728:	609a      	str	r2, [r3, #8]

    /* Clear flag alarm A */
    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
 800372a:	68fb      	ldr	r3, [r7, #12]
 800372c:	681b      	ldr	r3, [r3, #0]
 800372e:	68db      	ldr	r3, [r3, #12]
 8003730:	b2da      	uxtb	r2, r3
 8003732:	68fb      	ldr	r3, [r7, #12]
 8003734:	681b      	ldr	r3, [r3, #0]
 8003736:	f462 72c0 	orn	r2, r2, #384	; 0x180
 800373a:	60da      	str	r2, [r3, #12]

    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
    do
    {
      if (count-- == 0U)
 800373c:	697b      	ldr	r3, [r7, #20]
 800373e:	1e5a      	subs	r2, r3, #1
 8003740:	617a      	str	r2, [r7, #20]
 8003742:	2b00      	cmp	r3, #0
 8003744:	d10b      	bne.n	800375e <HAL_RTC_SetAlarm_IT+0x16a>
      {
        /* Enable the write protection for RTC registers */
        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8003746:	68fb      	ldr	r3, [r7, #12]
 8003748:	681b      	ldr	r3, [r3, #0]
 800374a:	22ff      	movs	r2, #255	; 0xff
 800374c:	625a      	str	r2, [r3, #36]	; 0x24

        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 800374e:	68fb      	ldr	r3, [r7, #12]
 8003750:	2203      	movs	r2, #3
 8003752:	775a      	strb	r2, [r3, #29]

        /* Process Unlocked */
        __HAL_UNLOCK(hrtc);
 8003754:	68fb      	ldr	r3, [r7, #12]
 8003756:	2200      	movs	r2, #0
 8003758:	771a      	strb	r2, [r3, #28]

        return HAL_TIMEOUT;
 800375a:	2303      	movs	r3, #3
 800375c:	e077      	b.n	800384e <HAL_RTC_SetAlarm_IT+0x25a>
      }
    }
    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);
 800375e:	68fb      	ldr	r3, [r7, #12]
 8003760:	681b      	ldr	r3, [r3, #0]
 8003762:	68db      	ldr	r3, [r3, #12]
 8003764:	f003 0301 	and.w	r3, r3, #1
 8003768:	2b00      	cmp	r3, #0
 800376a:	d0e7      	beq.n	800373c <HAL_RTC_SetAlarm_IT+0x148>

    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
 800376c:	68fb      	ldr	r3, [r7, #12]
 800376e:	681b      	ldr	r3, [r3, #0]
 8003770:	69fa      	ldr	r2, [r7, #28]
 8003772:	61da      	str	r2, [r3, #28]
    /* Configure the Alarm A Sub Second register */
    hrtc->Instance->ALRMASSR = subsecondtmpreg;
 8003774:	68fb      	ldr	r3, [r7, #12]
 8003776:	681b      	ldr	r3, [r3, #0]
 8003778:	69ba      	ldr	r2, [r7, #24]
 800377a:	645a      	str	r2, [r3, #68]	; 0x44
    /* Configure the Alarm state: Enable Alarm */
    __HAL_RTC_ALARMA_ENABLE(hrtc);
 800377c:	68fb      	ldr	r3, [r7, #12]
 800377e:	681b      	ldr	r3, [r3, #0]
 8003780:	689a      	ldr	r2, [r3, #8]
 8003782:	68fb      	ldr	r3, [r7, #12]
 8003784:	681b      	ldr	r3, [r3, #0]
 8003786:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 800378a:	609a      	str	r2, [r3, #8]
    /* Configure the Alarm interrupt */
    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
 800378c:	68fb      	ldr	r3, [r7, #12]
 800378e:	681b      	ldr	r3, [r3, #0]
 8003790:	689a      	ldr	r2, [r3, #8]
 8003792:	68fb      	ldr	r3, [r7, #12]
 8003794:	681b      	ldr	r3, [r3, #0]
 8003796:	f442 5280 	orr.w	r2, r2, #4096	; 0x1000
 800379a:	609a      	str	r2, [r3, #8]
 800379c:	e040      	b.n	8003820 <HAL_RTC_SetAlarm_IT+0x22c>
  }
  else
  {
    /* Disable the Alarm B interrupt */
    __HAL_RTC_ALARMB_DISABLE(hrtc);
 800379e:	68fb      	ldr	r3, [r7, #12]
 80037a0:	681b      	ldr	r3, [r3, #0]
 80037a2:	689a      	ldr	r2, [r3, #8]
 80037a4:	68fb      	ldr	r3, [r7, #12]
 80037a6:	681b      	ldr	r3, [r3, #0]
 80037a8:	f422 7200 	bic.w	r2, r2, #512	; 0x200
 80037ac:	609a      	str	r2, [r3, #8]

    /* Clear flag alarm B */
    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
 80037ae:	68fb      	ldr	r3, [r7, #12]
 80037b0:	681b      	ldr	r3, [r3, #0]
 80037b2:	68db      	ldr	r3, [r3, #12]
 80037b4:	b2da      	uxtb	r2, r3
 80037b6:	68fb      	ldr	r3, [r7, #12]
 80037b8:	681b      	ldr	r3, [r3, #0]
 80037ba:	f462 7220 	orn	r2, r2, #640	; 0x280
 80037be:	60da      	str	r2, [r3, #12]

    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
    do
    {
      if (count-- == 0U)
 80037c0:	697b      	ldr	r3, [r7, #20]
 80037c2:	1e5a      	subs	r2, r3, #1
 80037c4:	617a      	str	r2, [r7, #20]
 80037c6:	2b00      	cmp	r3, #0
 80037c8:	d10b      	bne.n	80037e2 <HAL_RTC_SetAlarm_IT+0x1ee>
      {
        /* Enable the write protection for RTC registers */
        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 80037ca:	68fb      	ldr	r3, [r7, #12]
 80037cc:	681b      	ldr	r3, [r3, #0]
 80037ce:	22ff      	movs	r2, #255	; 0xff
 80037d0:	625a      	str	r2, [r3, #36]	; 0x24

        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 80037d2:	68fb      	ldr	r3, [r7, #12]
 80037d4:	2203      	movs	r2, #3
 80037d6:	775a      	strb	r2, [r3, #29]

        /* Process Unlocked */
        __HAL_UNLOCK(hrtc);
 80037d8:	68fb      	ldr	r3, [r7, #12]
 80037da:	2200      	movs	r2, #0
 80037dc:	771a      	strb	r2, [r3, #28]

        return HAL_TIMEOUT;
 80037de:	2303      	movs	r3, #3
 80037e0:	e035      	b.n	800384e <HAL_RTC_SetAlarm_IT+0x25a>
      }
    }
    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);
 80037e2:	68fb      	ldr	r3, [r7, #12]
 80037e4:	681b      	ldr	r3, [r3, #0]
 80037e6:	68db      	ldr	r3, [r3, #12]
 80037e8:	f003 0302 	and.w	r3, r3, #2
 80037ec:	2b00      	cmp	r3, #0
 80037ee:	d0e7      	beq.n	80037c0 <HAL_RTC_SetAlarm_IT+0x1cc>

    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
 80037f0:	68fb      	ldr	r3, [r7, #12]
 80037f2:	681b      	ldr	r3, [r3, #0]
 80037f4:	69fa      	ldr	r2, [r7, #28]
 80037f6:	621a      	str	r2, [r3, #32]
    /* Configure the Alarm B Sub Second register */
    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
 80037f8:	68fb      	ldr	r3, [r7, #12]
 80037fa:	681b      	ldr	r3, [r3, #0]
 80037fc:	69ba      	ldr	r2, [r7, #24]
 80037fe:	649a      	str	r2, [r3, #72]	; 0x48
    /* Configure the Alarm state: Enable Alarm */
    __HAL_RTC_ALARMB_ENABLE(hrtc);
 8003800:	68fb      	ldr	r3, [r7, #12]
 8003802:	681b      	ldr	r3, [r3, #0]
 8003804:	689a      	ldr	r2, [r3, #8]
 8003806:	68fb      	ldr	r3, [r7, #12]
 8003808:	681b      	ldr	r3, [r3, #0]
 800380a:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 800380e:	609a      	str	r2, [r3, #8]
    /* Configure the Alarm interrupt */
    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
 8003810:	68fb      	ldr	r3, [r7, #12]
 8003812:	681b      	ldr	r3, [r3, #0]
 8003814:	689a      	ldr	r2, [r3, #8]
 8003816:	68fb      	ldr	r3, [r7, #12]
 8003818:	681b      	ldr	r3, [r3, #0]
 800381a:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 800381e:	609a      	str	r2, [r3, #8]
  }

  /* RTC Alarm Interrupt Configuration: EXTI configuration */
  __HAL_RTC_ALARM_EXTI_ENABLE_IT();
 8003820:	4b0f      	ldr	r3, [pc, #60]	; (8003860 <HAL_RTC_SetAlarm_IT+0x26c>)
 8003822:	681b      	ldr	r3, [r3, #0]
 8003824:	4a0e      	ldr	r2, [pc, #56]	; (8003860 <HAL_RTC_SetAlarm_IT+0x26c>)
 8003826:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 800382a:	6013      	str	r3, [r2, #0]

  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
 800382c:	4b0c      	ldr	r3, [pc, #48]	; (8003860 <HAL_RTC_SetAlarm_IT+0x26c>)
 800382e:	689b      	ldr	r3, [r3, #8]
 8003830:	4a0b      	ldr	r2, [pc, #44]	; (8003860 <HAL_RTC_SetAlarm_IT+0x26c>)
 8003832:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8003836:	6093      	str	r3, [r2, #8]

  /* Enable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8003838:	68fb      	ldr	r3, [r7, #12]
 800383a:	681b      	ldr	r3, [r3, #0]
 800383c:	22ff      	movs	r2, #255	; 0xff
 800383e:	625a      	str	r2, [r3, #36]	; 0x24

  hrtc->State = HAL_RTC_STATE_READY;
 8003840:	68fb      	ldr	r3, [r7, #12]
 8003842:	2201      	movs	r2, #1
 8003844:	775a      	strb	r2, [r3, #29]

  /* Process Unlocked */
  __HAL_UNLOCK(hrtc);
 8003846:	68fb      	ldr	r3, [r7, #12]
 8003848:	2200      	movs	r2, #0
 800384a:	771a      	strb	r2, [r3, #28]

  return HAL_OK;
 800384c:	2300      	movs	r3, #0
}
 800384e:	4618      	mov	r0, r3
 8003850:	3724      	adds	r7, #36	; 0x24
 8003852:	46bd      	mov	sp, r7
 8003854:	bd90      	pop	{r4, r7, pc}
 8003856:	bf00      	nop
 8003858:	20000014 	.word	0x20000014
 800385c:	10624dd3 	.word	0x10624dd3
 8003860:	40013c00 	.word	0x40013c00

08003864 <HAL_RTC_AlarmIRQHandler>:
  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval None
  */
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
 8003864:	b580      	push	{r7, lr}
 8003866:	b082      	sub	sp, #8
 8003868:	af00      	add	r7, sp, #0
 800386a:	6078      	str	r0, [r7, #4]
  /* Get the AlarmA interrupt source enable status */
  if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET)
 800386c:	687b      	ldr	r3, [r7, #4]
 800386e:	681b      	ldr	r3, [r3, #0]
 8003870:	689b      	ldr	r3, [r3, #8]
 8003872:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 8003876:	2b00      	cmp	r3, #0
 8003878:	d012      	beq.n	80038a0 <HAL_RTC_AlarmIRQHandler+0x3c>
  {
    /* Get the pending status of the AlarmA Interrupt */
    if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
 800387a:	687b      	ldr	r3, [r7, #4]
 800387c:	681b      	ldr	r3, [r3, #0]
 800387e:	68db      	ldr	r3, [r3, #12]
 8003880:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8003884:	2b00      	cmp	r3, #0
 8003886:	d00b      	beq.n	80038a0 <HAL_RTC_AlarmIRQHandler+0x3c>
    {
      /* AlarmA callback */
    #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
      hrtc->AlarmAEventCallback(hrtc);
    #else
      HAL_RTC_AlarmAEventCallback(hrtc);
 8003888:	6878      	ldr	r0, [r7, #4]
 800388a:	f7fe fa35 	bl	8001cf8 <HAL_RTC_AlarmAEventCallback>
    #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */

      /* Clear the AlarmA interrupt pending bit */
      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
 800388e:	687b      	ldr	r3, [r7, #4]
 8003890:	681b      	ldr	r3, [r3, #0]
 8003892:	68db      	ldr	r3, [r3, #12]
 8003894:	b2da      	uxtb	r2, r3
 8003896:	687b      	ldr	r3, [r7, #4]
 8003898:	681b      	ldr	r3, [r3, #0]
 800389a:	f462 72c0 	orn	r2, r2, #384	; 0x180
 800389e:	60da      	str	r2, [r3, #12]
    }
  }

  /* Get the AlarmB interrupt source enable status */
  if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET)
 80038a0:	687b      	ldr	r3, [r7, #4]
 80038a2:	681b      	ldr	r3, [r3, #0]
 80038a4:	689b      	ldr	r3, [r3, #8]
 80038a6:	f403 5300 	and.w	r3, r3, #8192	; 0x2000
 80038aa:	2b00      	cmp	r3, #0
 80038ac:	d012      	beq.n	80038d4 <HAL_RTC_AlarmIRQHandler+0x70>
  {
    /* Get the pending status of the AlarmB Interrupt */
    if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET)
 80038ae:	687b      	ldr	r3, [r7, #4]
 80038b0:	681b      	ldr	r3, [r3, #0]
 80038b2:	68db      	ldr	r3, [r3, #12]
 80038b4:	f403 7300 	and.w	r3, r3, #512	; 0x200
 80038b8:	2b00      	cmp	r3, #0
 80038ba:	d00b      	beq.n	80038d4 <HAL_RTC_AlarmIRQHandler+0x70>
    {
      /* AlarmB callback */
    #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
      hrtc->AlarmBEventCallback(hrtc);
    #else
      HAL_RTCEx_AlarmBEventCallback(hrtc);
 80038bc:	6878      	ldr	r0, [r7, #4]
 80038be:	f000 f8a7 	bl	8003a10 <HAL_RTCEx_AlarmBEventCallback>
    #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */

      /* Clear the AlarmB interrupt pending bit */
      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
 80038c2:	687b      	ldr	r3, [r7, #4]
 80038c4:	681b      	ldr	r3, [r3, #0]
 80038c6:	68db      	ldr	r3, [r3, #12]
 80038c8:	b2da      	uxtb	r2, r3
 80038ca:	687b      	ldr	r3, [r7, #4]
 80038cc:	681b      	ldr	r3, [r3, #0]
 80038ce:	f462 7220 	orn	r2, r2, #640	; 0x280
 80038d2:	60da      	str	r2, [r3, #12]
    }
  }

  /* Clear the EXTI's line Flag for RTC Alarm */
  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
 80038d4:	4b05      	ldr	r3, [pc, #20]	; (80038ec <HAL_RTC_AlarmIRQHandler+0x88>)
 80038d6:	f44f 3200 	mov.w	r2, #131072	; 0x20000
 80038da:	615a      	str	r2, [r3, #20]

  /* Change RTC state */
  hrtc->State = HAL_RTC_STATE_READY;
 80038dc:	687b      	ldr	r3, [r7, #4]
 80038de:	2201      	movs	r2, #1
 80038e0:	775a      	strb	r2, [r3, #29]
}
 80038e2:	bf00      	nop
 80038e4:	3708      	adds	r7, #8
 80038e6:	46bd      	mov	sp, r7
 80038e8:	bd80      	pop	{r7, pc}
 80038ea:	bf00      	nop
 80038ec:	40013c00 	.word	0x40013c00

080038f0 <HAL_RTC_WaitForSynchro>:
  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
 80038f0:	b580      	push	{r7, lr}
 80038f2:	b084      	sub	sp, #16
 80038f4:	af00      	add	r7, sp, #0
 80038f6:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U;
 80038f8:	2300      	movs	r3, #0
 80038fa:	60fb      	str	r3, [r7, #12]

  /* Clear RSF flag */
  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
 80038fc:	687b      	ldr	r3, [r7, #4]
 80038fe:	681b      	ldr	r3, [r3, #0]
 8003900:	68da      	ldr	r2, [r3, #12]
 8003902:	687b      	ldr	r3, [r7, #4]
 8003904:	681b      	ldr	r3, [r3, #0]
 8003906:	f022 02a0 	bic.w	r2, r2, #160	; 0xa0
 800390a:	60da      	str	r2, [r3, #12]

    /* Get tick */
    tickstart = HAL_GetTick();
 800390c:	f7fe fb68 	bl	8001fe0 <HAL_GetTick>
 8003910:	60f8      	str	r0, [r7, #12]

  /* Wait the registers to be synchronised */
  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
 8003912:	e009      	b.n	8003928 <HAL_RTC_WaitForSynchro+0x38>
  {
    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
 8003914:	f7fe fb64 	bl	8001fe0 <HAL_GetTick>
 8003918:	4602      	mov	r2, r0
 800391a:	68fb      	ldr	r3, [r7, #12]
 800391c:	1ad3      	subs	r3, r2, r3
 800391e:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 8003922:	d901      	bls.n	8003928 <HAL_RTC_WaitForSynchro+0x38>
    {
      return HAL_TIMEOUT;
 8003924:	2303      	movs	r3, #3
 8003926:	e007      	b.n	8003938 <HAL_RTC_WaitForSynchro+0x48>
  while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
 8003928:	687b      	ldr	r3, [r7, #4]
 800392a:	681b      	ldr	r3, [r3, #0]
 800392c:	68db      	ldr	r3, [r3, #12]
 800392e:	f003 0320 	and.w	r3, r3, #32
 8003932:	2b00      	cmp	r3, #0
 8003934:	d0ee      	beq.n	8003914 <HAL_RTC_WaitForSynchro+0x24>
    }
  }

  return HAL_OK;
 8003936:	2300      	movs	r3, #0
}
 8003938:	4618      	mov	r0, r3
 800393a:	3710      	adds	r7, #16
 800393c:	46bd      	mov	sp, r7
 800393e:	bd80      	pop	{r7, pc}

08003940 <RTC_EnterInitMode>:
  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval HAL status
  */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
 8003940:	b580      	push	{r7, lr}
 8003942:	b084      	sub	sp, #16
 8003944:	af00      	add	r7, sp, #0
 8003946:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = 0U;
 8003948:	2300      	movs	r3, #0
 800394a:	60fb      	str	r3, [r7, #12]

  /* Check if the Initialization mode is set */
  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
 800394c:	687b      	ldr	r3, [r7, #4]
 800394e:	681b      	ldr	r3, [r3, #0]
 8003950:	68db      	ldr	r3, [r3, #12]
 8003952:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8003956:	2b00      	cmp	r3, #0
 8003958:	d119      	bne.n	800398e <RTC_EnterInitMode+0x4e>
  {
    /* Set the Initialization mode */
    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
 800395a:	687b      	ldr	r3, [r7, #4]
 800395c:	681b      	ldr	r3, [r3, #0]
 800395e:	f04f 32ff 	mov.w	r2, #4294967295
 8003962:	60da      	str	r2, [r3, #12]

    /* Get tick */
    tickstart = HAL_GetTick();
 8003964:	f7fe fb3c 	bl	8001fe0 <HAL_GetTick>
 8003968:	60f8      	str	r0, [r7, #12]

    /* Wait till RTC is in INIT state and if Time out is reached exit */
    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
 800396a:	e009      	b.n	8003980 <RTC_EnterInitMode+0x40>
    {
      if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
 800396c:	f7fe fb38 	bl	8001fe0 <HAL_GetTick>
 8003970:	4602      	mov	r2, r0
 8003972:	68fb      	ldr	r3, [r7, #12]
 8003974:	1ad3      	subs	r3, r2, r3
 8003976:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 800397a:	d901      	bls.n	8003980 <RTC_EnterInitMode+0x40>
      {
        return HAL_TIMEOUT;
 800397c:	2303      	movs	r3, #3
 800397e:	e007      	b.n	8003990 <RTC_EnterInitMode+0x50>
    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
 8003980:	687b      	ldr	r3, [r7, #4]
 8003982:	681b      	ldr	r3, [r3, #0]
 8003984:	68db      	ldr	r3, [r3, #12]
 8003986:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800398a:	2b00      	cmp	r3, #0
 800398c:	d0ee      	beq.n	800396c <RTC_EnterInitMode+0x2c>
      }
    }
  }

  return HAL_OK;
 800398e:	2300      	movs	r3, #0
}
 8003990:	4618      	mov	r0, r3
 8003992:	3710      	adds	r7, #16
 8003994:	46bd      	mov	sp, r7
 8003996:	bd80      	pop	{r7, pc}

08003998 <RTC_ByteToBcd2>:
  * @brief  Converts a 2 digit decimal to BCD format.
  * @param  Value Byte to be converted
  * @retval Converted byte
  */
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
 8003998:	b480      	push	{r7}
 800399a:	b085      	sub	sp, #20
 800399c:	af00      	add	r7, sp, #0
 800399e:	4603      	mov	r3, r0
 80039a0:	71fb      	strb	r3, [r7, #7]
  uint32_t bcdhigh = 0U;
 80039a2:	2300      	movs	r3, #0
 80039a4:	60fb      	str	r3, [r7, #12]

  while(Value >= 10U)
 80039a6:	e005      	b.n	80039b4 <RTC_ByteToBcd2+0x1c>
  {
    bcdhigh++;
 80039a8:	68fb      	ldr	r3, [r7, #12]
 80039aa:	3301      	adds	r3, #1
 80039ac:	60fb      	str	r3, [r7, #12]
    Value -= 10U;
 80039ae:	79fb      	ldrb	r3, [r7, #7]
 80039b0:	3b0a      	subs	r3, #10
 80039b2:	71fb      	strb	r3, [r7, #7]
  while(Value >= 10U)
 80039b4:	79fb      	ldrb	r3, [r7, #7]
 80039b6:	2b09      	cmp	r3, #9
 80039b8:	d8f6      	bhi.n	80039a8 <RTC_ByteToBcd2+0x10>
  }

  return  ((uint8_t)(bcdhigh << 4U) | Value);
 80039ba:	68fb      	ldr	r3, [r7, #12]
 80039bc:	b2db      	uxtb	r3, r3
 80039be:	011b      	lsls	r3, r3, #4
 80039c0:	b2da      	uxtb	r2, r3
 80039c2:	79fb      	ldrb	r3, [r7, #7]
 80039c4:	4313      	orrs	r3, r2
 80039c6:	b2db      	uxtb	r3, r3
}
 80039c8:	4618      	mov	r0, r3
 80039ca:	3714      	adds	r7, #20
 80039cc:	46bd      	mov	sp, r7
 80039ce:	f85d 7b04 	ldr.w	r7, [sp], #4
 80039d2:	4770      	bx	lr

080039d4 <RTC_Bcd2ToByte>:
  * @brief  Converts from 2 digit BCD to Binary.
  * @param  Value BCD value to be converted
  * @retval Converted word
  */
uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
 80039d4:	b480      	push	{r7}
 80039d6:	b085      	sub	sp, #20
 80039d8:	af00      	add	r7, sp, #0
 80039da:	4603      	mov	r3, r0
 80039dc:	71fb      	strb	r3, [r7, #7]
  uint32_t tmp = 0U;
 80039de:	2300      	movs	r3, #0
 80039e0:	60fb      	str	r3, [r7, #12]
  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
 80039e2:	79fb      	ldrb	r3, [r7, #7]
 80039e4:	091b      	lsrs	r3, r3, #4
 80039e6:	b2db      	uxtb	r3, r3
 80039e8:	461a      	mov	r2, r3
 80039ea:	4613      	mov	r3, r2
 80039ec:	009b      	lsls	r3, r3, #2
 80039ee:	4413      	add	r3, r2
 80039f0:	005b      	lsls	r3, r3, #1
 80039f2:	60fb      	str	r3, [r7, #12]
  return (tmp + (Value & (uint8_t)0x0F));
 80039f4:	79fb      	ldrb	r3, [r7, #7]
 80039f6:	f003 030f 	and.w	r3, r3, #15
 80039fa:	b2da      	uxtb	r2, r3
 80039fc:	68fb      	ldr	r3, [r7, #12]
 80039fe:	b2db      	uxtb	r3, r3
 8003a00:	4413      	add	r3, r2
 8003a02:	b2db      	uxtb	r3, r3
}
 8003a04:	4618      	mov	r0, r3
 8003a06:	3714      	adds	r7, #20
 8003a08:	46bd      	mov	sp, r7
 8003a0a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003a0e:	4770      	bx	lr

08003a10 <HAL_RTCEx_AlarmBEventCallback>:
  * @param  hrtc pointer to a RTC_HandleTypeDef structure that contains
  *                the configuration information for RTC.
  * @retval None
  */
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
{
 8003a10:	b480      	push	{r7}
 8003a12:	b083      	sub	sp, #12
 8003a14:	af00      	add	r7, sp, #0
 8003a16:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hrtc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_RTC_AlarmBEventCallback could be implemented in the user file
   */
}
 8003a18:	bf00      	nop
 8003a1a:	370c      	adds	r7, #12
 8003a1c:	46bd      	mov	sp, r7
 8003a1e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003a22:	4770      	bx	lr

08003a24 <HAL_UART_Init>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8003a24:	b580      	push	{r7, lr}
 8003a26:	b082      	sub	sp, #8
 8003a28:	af00      	add	r7, sp, #0
 8003a2a:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8003a2c:	687b      	ldr	r3, [r7, #4]
 8003a2e:	2b00      	cmp	r3, #0
 8003a30:	d101      	bne.n	8003a36 <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 8003a32:	2301      	movs	r3, #1
 8003a34:	e03f      	b.n	8003ab6 <HAL_UART_Init+0x92>
    assert_param(IS_UART_INSTANCE(huart->Instance));
  }
  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));

  if (huart->gState == HAL_UART_STATE_RESET)
 8003a36:	687b      	ldr	r3, [r7, #4]
 8003a38:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8003a3c:	b2db      	uxtb	r3, r3
 8003a3e:	2b00      	cmp	r3, #0
 8003a40:	d106      	bne.n	8003a50 <HAL_UART_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 8003a42:	687b      	ldr	r3, [r7, #4]
 8003a44:	2200      	movs	r2, #0
 8003a46:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8003a4a:	6878      	ldr	r0, [r7, #4]
 8003a4c:	f7fe f9a6 	bl	8001d9c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8003a50:	687b      	ldr	r3, [r7, #4]
 8003a52:	2224      	movs	r2, #36	; 0x24
 8003a54:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Disable the peripheral */
  __HAL_UART_DISABLE(huart);
 8003a58:	687b      	ldr	r3, [r7, #4]
 8003a5a:	681b      	ldr	r3, [r3, #0]
 8003a5c:	68da      	ldr	r2, [r3, #12]
 8003a5e:	687b      	ldr	r3, [r7, #4]
 8003a60:	681b      	ldr	r3, [r3, #0]
 8003a62:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 8003a66:	60da      	str	r2, [r3, #12]

  /* Set the UART Communication parameters */
  UART_SetConfig(huart);
 8003a68:	6878      	ldr	r0, [r7, #4]
 8003a6a:	f000 f90b 	bl	8003c84 <UART_SetConfig>

  /* In asynchronous mode, the following bits must be kept cleared:
     - LINEN and CLKEN bits in the USART_CR2 register,
     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8003a6e:	687b      	ldr	r3, [r7, #4]
 8003a70:	681b      	ldr	r3, [r3, #0]
 8003a72:	691a      	ldr	r2, [r3, #16]
 8003a74:	687b      	ldr	r3, [r7, #4]
 8003a76:	681b      	ldr	r3, [r3, #0]
 8003a78:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8003a7c:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8003a7e:	687b      	ldr	r3, [r7, #4]
 8003a80:	681b      	ldr	r3, [r3, #0]
 8003a82:	695a      	ldr	r2, [r3, #20]
 8003a84:	687b      	ldr	r3, [r7, #4]
 8003a86:	681b      	ldr	r3, [r3, #0]
 8003a88:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8003a8c:	615a      	str	r2, [r3, #20]

  /* Enable the peripheral */
  __HAL_UART_ENABLE(huart);
 8003a8e:	687b      	ldr	r3, [r7, #4]
 8003a90:	681b      	ldr	r3, [r3, #0]
 8003a92:	68da      	ldr	r2, [r3, #12]
 8003a94:	687b      	ldr	r3, [r7, #4]
 8003a96:	681b      	ldr	r3, [r3, #0]
 8003a98:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8003a9c:	60da      	str	r2, [r3, #12]

  /* Initialize the UART state */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8003a9e:	687b      	ldr	r3, [r7, #4]
 8003aa0:	2200      	movs	r2, #0
 8003aa2:	63da      	str	r2, [r3, #60]	; 0x3c
  huart->gState = HAL_UART_STATE_READY;
 8003aa4:	687b      	ldr	r3, [r7, #4]
 8003aa6:	2220      	movs	r2, #32
 8003aa8:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
  huart->RxState = HAL_UART_STATE_READY;
 8003aac:	687b      	ldr	r3, [r7, #4]
 8003aae:	2220      	movs	r2, #32
 8003ab0:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

  return HAL_OK;
 8003ab4:	2300      	movs	r3, #0
}
 8003ab6:	4618      	mov	r0, r3
 8003ab8:	3708      	adds	r7, #8
 8003aba:	46bd      	mov	sp, r7
 8003abc:	bd80      	pop	{r7, pc}

08003abe <HAL_UART_Transmit>:
  * @param  Size  Amount of data elements (u8 or u16) to be sent
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8003abe:	b580      	push	{r7, lr}
 8003ac0:	b088      	sub	sp, #32
 8003ac2:	af02      	add	r7, sp, #8
 8003ac4:	60f8      	str	r0, [r7, #12]
 8003ac6:	60b9      	str	r1, [r7, #8]
 8003ac8:	603b      	str	r3, [r7, #0]
 8003aca:	4613      	mov	r3, r2
 8003acc:	80fb      	strh	r3, [r7, #6]
  uint16_t *tmp;
  uint32_t tickstart = 0U;
 8003ace:	2300      	movs	r3, #0
 8003ad0:	617b      	str	r3, [r7, #20]

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 8003ad2:	68fb      	ldr	r3, [r7, #12]
 8003ad4:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8003ad8:	b2db      	uxtb	r3, r3
 8003ada:	2b20      	cmp	r3, #32
 8003adc:	f040 8083 	bne.w	8003be6 <HAL_UART_Transmit+0x128>
  {
    if ((pData == NULL) || (Size == 0U))
 8003ae0:	68bb      	ldr	r3, [r7, #8]
 8003ae2:	2b00      	cmp	r3, #0
 8003ae4:	d002      	beq.n	8003aec <HAL_UART_Transmit+0x2e>
 8003ae6:	88fb      	ldrh	r3, [r7, #6]
 8003ae8:	2b00      	cmp	r3, #0
 8003aea:	d101      	bne.n	8003af0 <HAL_UART_Transmit+0x32>
    {
      return  HAL_ERROR;
 8003aec:	2301      	movs	r3, #1
 8003aee:	e07b      	b.n	8003be8 <HAL_UART_Transmit+0x12a>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 8003af0:	68fb      	ldr	r3, [r7, #12]
 8003af2:	f893 3038 	ldrb.w	r3, [r3, #56]	; 0x38
 8003af6:	2b01      	cmp	r3, #1
 8003af8:	d101      	bne.n	8003afe <HAL_UART_Transmit+0x40>
 8003afa:	2302      	movs	r3, #2
 8003afc:	e074      	b.n	8003be8 <HAL_UART_Transmit+0x12a>
 8003afe:	68fb      	ldr	r3, [r7, #12]
 8003b00:	2201      	movs	r2, #1
 8003b02:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8003b06:	68fb      	ldr	r3, [r7, #12]
 8003b08:	2200      	movs	r2, #0
 8003b0a:	63da      	str	r2, [r3, #60]	; 0x3c
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8003b0c:	68fb      	ldr	r3, [r7, #12]
 8003b0e:	2221      	movs	r2, #33	; 0x21
 8003b10:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

    /* Init tickstart for timeout managment */
    tickstart = HAL_GetTick();
 8003b14:	f7fe fa64 	bl	8001fe0 <HAL_GetTick>
 8003b18:	6178      	str	r0, [r7, #20]

    huart->TxXferSize = Size;
 8003b1a:	68fb      	ldr	r3, [r7, #12]
 8003b1c:	88fa      	ldrh	r2, [r7, #6]
 8003b1e:	849a      	strh	r2, [r3, #36]	; 0x24
    huart->TxXferCount = Size;
 8003b20:	68fb      	ldr	r3, [r7, #12]
 8003b22:	88fa      	ldrh	r2, [r7, #6]
 8003b24:	84da      	strh	r2, [r3, #38]	; 0x26

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 8003b26:	68fb      	ldr	r3, [r7, #12]
 8003b28:	2200      	movs	r2, #0
 8003b2a:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    while (huart->TxXferCount > 0U)
 8003b2e:	e042      	b.n	8003bb6 <HAL_UART_Transmit+0xf8>
    {
      huart->TxXferCount--;
 8003b30:	68fb      	ldr	r3, [r7, #12]
 8003b32:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8003b34:	b29b      	uxth	r3, r3
 8003b36:	3b01      	subs	r3, #1
 8003b38:	b29a      	uxth	r2, r3
 8003b3a:	68fb      	ldr	r3, [r7, #12]
 8003b3c:	84da      	strh	r2, [r3, #38]	; 0x26
      if (huart->Init.WordLength == UART_WORDLENGTH_9B)
 8003b3e:	68fb      	ldr	r3, [r7, #12]
 8003b40:	689b      	ldr	r3, [r3, #8]
 8003b42:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8003b46:	d122      	bne.n	8003b8e <HAL_UART_Transmit+0xd0>
      {
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8003b48:	683b      	ldr	r3, [r7, #0]
 8003b4a:	9300      	str	r3, [sp, #0]
 8003b4c:	697b      	ldr	r3, [r7, #20]
 8003b4e:	2200      	movs	r2, #0
 8003b50:	2180      	movs	r1, #128	; 0x80
 8003b52:	68f8      	ldr	r0, [r7, #12]
 8003b54:	f000 f84c 	bl	8003bf0 <UART_WaitOnFlagUntilTimeout>
 8003b58:	4603      	mov	r3, r0
 8003b5a:	2b00      	cmp	r3, #0
 8003b5c:	d001      	beq.n	8003b62 <HAL_UART_Transmit+0xa4>
        {
          return HAL_TIMEOUT;
 8003b5e:	2303      	movs	r3, #3
 8003b60:	e042      	b.n	8003be8 <HAL_UART_Transmit+0x12a>
        }
        tmp = (uint16_t *) pData;
 8003b62:	68bb      	ldr	r3, [r7, #8]
 8003b64:	613b      	str	r3, [r7, #16]
        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
 8003b66:	693b      	ldr	r3, [r7, #16]
 8003b68:	881b      	ldrh	r3, [r3, #0]
 8003b6a:	461a      	mov	r2, r3
 8003b6c:	68fb      	ldr	r3, [r7, #12]
 8003b6e:	681b      	ldr	r3, [r3, #0]
 8003b70:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8003b74:	605a      	str	r2, [r3, #4]
        if (huart->Init.Parity == UART_PARITY_NONE)
 8003b76:	68fb      	ldr	r3, [r7, #12]
 8003b78:	691b      	ldr	r3, [r3, #16]
 8003b7a:	2b00      	cmp	r3, #0
 8003b7c:	d103      	bne.n	8003b86 <HAL_UART_Transmit+0xc8>
        {
          pData += 2U;
 8003b7e:	68bb      	ldr	r3, [r7, #8]
 8003b80:	3302      	adds	r3, #2
 8003b82:	60bb      	str	r3, [r7, #8]
 8003b84:	e017      	b.n	8003bb6 <HAL_UART_Transmit+0xf8>
        }
        else
        {
          pData += 1U;
 8003b86:	68bb      	ldr	r3, [r7, #8]
 8003b88:	3301      	adds	r3, #1
 8003b8a:	60bb      	str	r3, [r7, #8]
 8003b8c:	e013      	b.n	8003bb6 <HAL_UART_Transmit+0xf8>
        }
      }
      else
      {
        if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8003b8e:	683b      	ldr	r3, [r7, #0]
 8003b90:	9300      	str	r3, [sp, #0]
 8003b92:	697b      	ldr	r3, [r7, #20]
 8003b94:	2200      	movs	r2, #0
 8003b96:	2180      	movs	r1, #128	; 0x80
 8003b98:	68f8      	ldr	r0, [r7, #12]
 8003b9a:	f000 f829 	bl	8003bf0 <UART_WaitOnFlagUntilTimeout>
 8003b9e:	4603      	mov	r3, r0
 8003ba0:	2b00      	cmp	r3, #0
 8003ba2:	d001      	beq.n	8003ba8 <HAL_UART_Transmit+0xea>
        {
          return HAL_TIMEOUT;
 8003ba4:	2303      	movs	r3, #3
 8003ba6:	e01f      	b.n	8003be8 <HAL_UART_Transmit+0x12a>
        }
        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
 8003ba8:	68bb      	ldr	r3, [r7, #8]
 8003baa:	1c5a      	adds	r2, r3, #1
 8003bac:	60ba      	str	r2, [r7, #8]
 8003bae:	781a      	ldrb	r2, [r3, #0]
 8003bb0:	68fb      	ldr	r3, [r7, #12]
 8003bb2:	681b      	ldr	r3, [r3, #0]
 8003bb4:	605a      	str	r2, [r3, #4]
    while (huart->TxXferCount > 0U)
 8003bb6:	68fb      	ldr	r3, [r7, #12]
 8003bb8:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8003bba:	b29b      	uxth	r3, r3
 8003bbc:	2b00      	cmp	r3, #0
 8003bbe:	d1b7      	bne.n	8003b30 <HAL_UART_Transmit+0x72>
      }
    }

    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8003bc0:	683b      	ldr	r3, [r7, #0]
 8003bc2:	9300      	str	r3, [sp, #0]
 8003bc4:	697b      	ldr	r3, [r7, #20]
 8003bc6:	2200      	movs	r2, #0
 8003bc8:	2140      	movs	r1, #64	; 0x40
 8003bca:	68f8      	ldr	r0, [r7, #12]
 8003bcc:	f000 f810 	bl	8003bf0 <UART_WaitOnFlagUntilTimeout>
 8003bd0:	4603      	mov	r3, r0
 8003bd2:	2b00      	cmp	r3, #0
 8003bd4:	d001      	beq.n	8003bda <HAL_UART_Transmit+0x11c>
    {
      return HAL_TIMEOUT;
 8003bd6:	2303      	movs	r3, #3
 8003bd8:	e006      	b.n	8003be8 <HAL_UART_Transmit+0x12a>
    }

    /* At end of Tx process, restore huart->gState to Ready */
    huart->gState = HAL_UART_STATE_READY;
 8003bda:	68fb      	ldr	r3, [r7, #12]
 8003bdc:	2220      	movs	r2, #32
 8003bde:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

    return HAL_OK;
 8003be2:	2300      	movs	r3, #0
 8003be4:	e000      	b.n	8003be8 <HAL_UART_Transmit+0x12a>
  }
  else
  {
    return HAL_BUSY;
 8003be6:	2302      	movs	r3, #2
  }
}
 8003be8:	4618      	mov	r0, r3
 8003bea:	3718      	adds	r7, #24
 8003bec:	46bd      	mov	sp, r7
 8003bee:	bd80      	pop	{r7, pc}

08003bf0 <UART_WaitOnFlagUntilTimeout>:
  * @param  Tickstart Tick start value
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
 8003bf0:	b580      	push	{r7, lr}
 8003bf2:	b084      	sub	sp, #16
 8003bf4:	af00      	add	r7, sp, #0
 8003bf6:	60f8      	str	r0, [r7, #12]
 8003bf8:	60b9      	str	r1, [r7, #8]
 8003bfa:	603b      	str	r3, [r7, #0]
 8003bfc:	4613      	mov	r3, r2
 8003bfe:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8003c00:	e02c      	b.n	8003c5c <UART_WaitOnFlagUntilTimeout+0x6c>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8003c02:	69bb      	ldr	r3, [r7, #24]
 8003c04:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003c08:	d028      	beq.n	8003c5c <UART_WaitOnFlagUntilTimeout+0x6c>
    {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 8003c0a:	69bb      	ldr	r3, [r7, #24]
 8003c0c:	2b00      	cmp	r3, #0
 8003c0e:	d007      	beq.n	8003c20 <UART_WaitOnFlagUntilTimeout+0x30>
 8003c10:	f7fe f9e6 	bl	8001fe0 <HAL_GetTick>
 8003c14:	4602      	mov	r2, r0
 8003c16:	683b      	ldr	r3, [r7, #0]
 8003c18:	1ad3      	subs	r3, r2, r3
 8003c1a:	69ba      	ldr	r2, [r7, #24]
 8003c1c:	429a      	cmp	r2, r3
 8003c1e:	d21d      	bcs.n	8003c5c <UART_WaitOnFlagUntilTimeout+0x6c>
      {
        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 8003c20:	68fb      	ldr	r3, [r7, #12]
 8003c22:	681b      	ldr	r3, [r3, #0]
 8003c24:	68da      	ldr	r2, [r3, #12]
 8003c26:	68fb      	ldr	r3, [r7, #12]
 8003c28:	681b      	ldr	r3, [r3, #0]
 8003c2a:	f422 72d0 	bic.w	r2, r2, #416	; 0x1a0
 8003c2e:	60da      	str	r2, [r3, #12]
        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8003c30:	68fb      	ldr	r3, [r7, #12]
 8003c32:	681b      	ldr	r3, [r3, #0]
 8003c34:	695a      	ldr	r2, [r3, #20]
 8003c36:	68fb      	ldr	r3, [r7, #12]
 8003c38:	681b      	ldr	r3, [r3, #0]
 8003c3a:	f022 0201 	bic.w	r2, r2, #1
 8003c3e:	615a      	str	r2, [r3, #20]

        huart->gState  = HAL_UART_STATE_READY;
 8003c40:	68fb      	ldr	r3, [r7, #12]
 8003c42:	2220      	movs	r2, #32
 8003c44:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
        huart->RxState = HAL_UART_STATE_READY;
 8003c48:	68fb      	ldr	r3, [r7, #12]
 8003c4a:	2220      	movs	r2, #32
 8003c4c:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

        /* Process Unlocked */
        __HAL_UNLOCK(huart);
 8003c50:	68fb      	ldr	r3, [r7, #12]
 8003c52:	2200      	movs	r2, #0
 8003c54:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

        return HAL_TIMEOUT;
 8003c58:	2303      	movs	r3, #3
 8003c5a:	e00f      	b.n	8003c7c <UART_WaitOnFlagUntilTimeout+0x8c>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8003c5c:	68fb      	ldr	r3, [r7, #12]
 8003c5e:	681b      	ldr	r3, [r3, #0]
 8003c60:	681a      	ldr	r2, [r3, #0]
 8003c62:	68bb      	ldr	r3, [r7, #8]
 8003c64:	4013      	ands	r3, r2
 8003c66:	68ba      	ldr	r2, [r7, #8]
 8003c68:	429a      	cmp	r2, r3
 8003c6a:	bf0c      	ite	eq
 8003c6c:	2301      	moveq	r3, #1
 8003c6e:	2300      	movne	r3, #0
 8003c70:	b2db      	uxtb	r3, r3
 8003c72:	461a      	mov	r2, r3
 8003c74:	79fb      	ldrb	r3, [r7, #7]
 8003c76:	429a      	cmp	r2, r3
 8003c78:	d0c3      	beq.n	8003c02 <UART_WaitOnFlagUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8003c7a:	2300      	movs	r3, #0
}
 8003c7c:	4618      	mov	r0, r3
 8003c7e:	3710      	adds	r7, #16
 8003c80:	46bd      	mov	sp, r7
 8003c82:	bd80      	pop	{r7, pc}

08003c84 <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8003c84:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8003c88:	b085      	sub	sp, #20
 8003c8a:	af00      	add	r7, sp, #0
 8003c8c:	6078      	str	r0, [r7, #4]
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8003c8e:	687b      	ldr	r3, [r7, #4]
 8003c90:	681b      	ldr	r3, [r3, #0]
 8003c92:	691b      	ldr	r3, [r3, #16]
 8003c94:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
 8003c98:	687b      	ldr	r3, [r7, #4]
 8003c9a:	68da      	ldr	r2, [r3, #12]
 8003c9c:	687b      	ldr	r3, [r7, #4]
 8003c9e:	681b      	ldr	r3, [r3, #0]
 8003ca0:	430a      	orrs	r2, r1
 8003ca2:	611a      	str	r2, [r3, #16]
     Set the M bits according to huart->Init.WordLength value
     Set PCE and PS bits according to huart->Init.Parity value
     Set TE and RE bits according to huart->Init.Mode value
     Set OVER8 bit according to huart->Init.OverSampling value */

  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
 8003ca4:	687b      	ldr	r3, [r7, #4]
 8003ca6:	689a      	ldr	r2, [r3, #8]
 8003ca8:	687b      	ldr	r3, [r7, #4]
 8003caa:	691b      	ldr	r3, [r3, #16]
 8003cac:	431a      	orrs	r2, r3
 8003cae:	687b      	ldr	r3, [r7, #4]
 8003cb0:	695b      	ldr	r3, [r3, #20]
 8003cb2:	431a      	orrs	r2, r3
 8003cb4:	687b      	ldr	r3, [r7, #4]
 8003cb6:	69db      	ldr	r3, [r3, #28]
 8003cb8:	4313      	orrs	r3, r2
 8003cba:	60fb      	str	r3, [r7, #12]
  MODIFY_REG(huart->Instance->CR1,
 8003cbc:	687b      	ldr	r3, [r7, #4]
 8003cbe:	681b      	ldr	r3, [r3, #0]
 8003cc0:	68db      	ldr	r3, [r3, #12]
 8003cc2:	f423 4316 	bic.w	r3, r3, #38400	; 0x9600
 8003cc6:	f023 030c 	bic.w	r3, r3, #12
 8003cca:	687a      	ldr	r2, [r7, #4]
 8003ccc:	6812      	ldr	r2, [r2, #0]
 8003cce:	68f9      	ldr	r1, [r7, #12]
 8003cd0:	430b      	orrs	r3, r1
 8003cd2:	60d3      	str	r3, [r2, #12]
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 8003cd4:	687b      	ldr	r3, [r7, #4]
 8003cd6:	681b      	ldr	r3, [r3, #0]
 8003cd8:	695b      	ldr	r3, [r3, #20]
 8003cda:	f423 7140 	bic.w	r1, r3, #768	; 0x300
 8003cde:	687b      	ldr	r3, [r7, #4]
 8003ce0:	699a      	ldr	r2, [r3, #24]
 8003ce2:	687b      	ldr	r3, [r7, #4]
 8003ce4:	681b      	ldr	r3, [r3, #0]
 8003ce6:	430a      	orrs	r2, r1
 8003ce8:	615a      	str	r2, [r3, #20]

  /* Check the Over Sampling */
  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8003cea:	687b      	ldr	r3, [r7, #4]
 8003cec:	69db      	ldr	r3, [r3, #28]
 8003cee:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 8003cf2:	f040 818b 	bne.w	800400c <UART_SetConfig+0x388>
    {
      pclk = HAL_RCC_GetPCLK2Freq();
      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
    }
#elif defined(USART6)
    if ((huart->Instance == USART1) || (huart->Instance == USART6))
 8003cf6:	687b      	ldr	r3, [r7, #4]
 8003cf8:	681b      	ldr	r3, [r3, #0]
 8003cfa:	4ac1      	ldr	r2, [pc, #772]	; (8004000 <UART_SetConfig+0x37c>)
 8003cfc:	4293      	cmp	r3, r2
 8003cfe:	d005      	beq.n	8003d0c <UART_SetConfig+0x88>
 8003d00:	687b      	ldr	r3, [r7, #4]
 8003d02:	681b      	ldr	r3, [r3, #0]
 8003d04:	4abf      	ldr	r2, [pc, #764]	; (8004004 <UART_SetConfig+0x380>)
 8003d06:	4293      	cmp	r3, r2
 8003d08:	f040 80bd 	bne.w	8003e86 <UART_SetConfig+0x202>
    {
      pclk = HAL_RCC_GetPCLK2Freq();
 8003d0c:	f7ff f8ce 	bl	8002eac <HAL_RCC_GetPCLK2Freq>
 8003d10:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8003d12:	68bb      	ldr	r3, [r7, #8]
 8003d14:	461d      	mov	r5, r3
 8003d16:	f04f 0600 	mov.w	r6, #0
 8003d1a:	46a8      	mov	r8, r5
 8003d1c:	46b1      	mov	r9, r6
 8003d1e:	eb18 0308 	adds.w	r3, r8, r8
 8003d22:	eb49 0409 	adc.w	r4, r9, r9
 8003d26:	4698      	mov	r8, r3
 8003d28:	46a1      	mov	r9, r4
 8003d2a:	eb18 0805 	adds.w	r8, r8, r5
 8003d2e:	eb49 0906 	adc.w	r9, r9, r6
 8003d32:	f04f 0100 	mov.w	r1, #0
 8003d36:	f04f 0200 	mov.w	r2, #0
 8003d3a:	ea4f 02c9 	mov.w	r2, r9, lsl #3
 8003d3e:	ea42 7258 	orr.w	r2, r2, r8, lsr #29
 8003d42:	ea4f 01c8 	mov.w	r1, r8, lsl #3
 8003d46:	4688      	mov	r8, r1
 8003d48:	4691      	mov	r9, r2
 8003d4a:	eb18 0005 	adds.w	r0, r8, r5
 8003d4e:	eb49 0106 	adc.w	r1, r9, r6
 8003d52:	687b      	ldr	r3, [r7, #4]
 8003d54:	685b      	ldr	r3, [r3, #4]
 8003d56:	461d      	mov	r5, r3
 8003d58:	f04f 0600 	mov.w	r6, #0
 8003d5c:	196b      	adds	r3, r5, r5
 8003d5e:	eb46 0406 	adc.w	r4, r6, r6
 8003d62:	461a      	mov	r2, r3
 8003d64:	4623      	mov	r3, r4
 8003d66:	f7fc fed3 	bl	8000b10 <__aeabi_uldivmod>
 8003d6a:	4603      	mov	r3, r0
 8003d6c:	460c      	mov	r4, r1
 8003d6e:	461a      	mov	r2, r3
 8003d70:	4ba5      	ldr	r3, [pc, #660]	; (8004008 <UART_SetConfig+0x384>)
 8003d72:	fba3 2302 	umull	r2, r3, r3, r2
 8003d76:	095b      	lsrs	r3, r3, #5
 8003d78:	ea4f 1803 	mov.w	r8, r3, lsl #4
 8003d7c:	68bb      	ldr	r3, [r7, #8]
 8003d7e:	461d      	mov	r5, r3
 8003d80:	f04f 0600 	mov.w	r6, #0
 8003d84:	46a9      	mov	r9, r5
 8003d86:	46b2      	mov	sl, r6
 8003d88:	eb19 0309 	adds.w	r3, r9, r9
 8003d8c:	eb4a 040a 	adc.w	r4, sl, sl
 8003d90:	4699      	mov	r9, r3
 8003d92:	46a2      	mov	sl, r4
 8003d94:	eb19 0905 	adds.w	r9, r9, r5
 8003d98:	eb4a 0a06 	adc.w	sl, sl, r6
 8003d9c:	f04f 0100 	mov.w	r1, #0
 8003da0:	f04f 0200 	mov.w	r2, #0
 8003da4:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 8003da8:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 8003dac:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8003db0:	4689      	mov	r9, r1
 8003db2:	4692      	mov	sl, r2
 8003db4:	eb19 0005 	adds.w	r0, r9, r5
 8003db8:	eb4a 0106 	adc.w	r1, sl, r6
 8003dbc:	687b      	ldr	r3, [r7, #4]
 8003dbe:	685b      	ldr	r3, [r3, #4]
 8003dc0:	461d      	mov	r5, r3
 8003dc2:	f04f 0600 	mov.w	r6, #0
 8003dc6:	196b      	adds	r3, r5, r5
 8003dc8:	eb46 0406 	adc.w	r4, r6, r6
 8003dcc:	461a      	mov	r2, r3
 8003dce:	4623      	mov	r3, r4
 8003dd0:	f7fc fe9e 	bl	8000b10 <__aeabi_uldivmod>
 8003dd4:	4603      	mov	r3, r0
 8003dd6:	460c      	mov	r4, r1
 8003dd8:	461a      	mov	r2, r3
 8003dda:	4b8b      	ldr	r3, [pc, #556]	; (8004008 <UART_SetConfig+0x384>)
 8003ddc:	fba3 1302 	umull	r1, r3, r3, r2
 8003de0:	095b      	lsrs	r3, r3, #5
 8003de2:	2164      	movs	r1, #100	; 0x64
 8003de4:	fb01 f303 	mul.w	r3, r1, r3
 8003de8:	1ad3      	subs	r3, r2, r3
 8003dea:	00db      	lsls	r3, r3, #3
 8003dec:	3332      	adds	r3, #50	; 0x32
 8003dee:	4a86      	ldr	r2, [pc, #536]	; (8004008 <UART_SetConfig+0x384>)
 8003df0:	fba2 2303 	umull	r2, r3, r2, r3
 8003df4:	095b      	lsrs	r3, r3, #5
 8003df6:	005b      	lsls	r3, r3, #1
 8003df8:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 8003dfc:	4498      	add	r8, r3
 8003dfe:	68bb      	ldr	r3, [r7, #8]
 8003e00:	461d      	mov	r5, r3
 8003e02:	f04f 0600 	mov.w	r6, #0
 8003e06:	46a9      	mov	r9, r5
 8003e08:	46b2      	mov	sl, r6
 8003e0a:	eb19 0309 	adds.w	r3, r9, r9
 8003e0e:	eb4a 040a 	adc.w	r4, sl, sl
 8003e12:	4699      	mov	r9, r3
 8003e14:	46a2      	mov	sl, r4
 8003e16:	eb19 0905 	adds.w	r9, r9, r5
 8003e1a:	eb4a 0a06 	adc.w	sl, sl, r6
 8003e1e:	f04f 0100 	mov.w	r1, #0
 8003e22:	f04f 0200 	mov.w	r2, #0
 8003e26:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 8003e2a:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 8003e2e:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8003e32:	4689      	mov	r9, r1
 8003e34:	4692      	mov	sl, r2
 8003e36:	eb19 0005 	adds.w	r0, r9, r5
 8003e3a:	eb4a 0106 	adc.w	r1, sl, r6
 8003e3e:	687b      	ldr	r3, [r7, #4]
 8003e40:	685b      	ldr	r3, [r3, #4]
 8003e42:	461d      	mov	r5, r3
 8003e44:	f04f 0600 	mov.w	r6, #0
 8003e48:	196b      	adds	r3, r5, r5
 8003e4a:	eb46 0406 	adc.w	r4, r6, r6
 8003e4e:	461a      	mov	r2, r3
 8003e50:	4623      	mov	r3, r4
 8003e52:	f7fc fe5d 	bl	8000b10 <__aeabi_uldivmod>
 8003e56:	4603      	mov	r3, r0
 8003e58:	460c      	mov	r4, r1
 8003e5a:	461a      	mov	r2, r3
 8003e5c:	4b6a      	ldr	r3, [pc, #424]	; (8004008 <UART_SetConfig+0x384>)
 8003e5e:	fba3 1302 	umull	r1, r3, r3, r2
 8003e62:	095b      	lsrs	r3, r3, #5
 8003e64:	2164      	movs	r1, #100	; 0x64
 8003e66:	fb01 f303 	mul.w	r3, r1, r3
 8003e6a:	1ad3      	subs	r3, r2, r3
 8003e6c:	00db      	lsls	r3, r3, #3
 8003e6e:	3332      	adds	r3, #50	; 0x32
 8003e70:	4a65      	ldr	r2, [pc, #404]	; (8004008 <UART_SetConfig+0x384>)
 8003e72:	fba2 2303 	umull	r2, r3, r2, r3
 8003e76:	095b      	lsrs	r3, r3, #5
 8003e78:	f003 0207 	and.w	r2, r3, #7
 8003e7c:	687b      	ldr	r3, [r7, #4]
 8003e7e:	681b      	ldr	r3, [r3, #0]
 8003e80:	4442      	add	r2, r8
 8003e82:	609a      	str	r2, [r3, #8]
 8003e84:	e26f      	b.n	8004366 <UART_SetConfig+0x6e2>
      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
    }
#endif /* USART6 */
    else
    {
      pclk = HAL_RCC_GetPCLK1Freq();
 8003e86:	f7fe fffd 	bl	8002e84 <HAL_RCC_GetPCLK1Freq>
 8003e8a:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8003e8c:	68bb      	ldr	r3, [r7, #8]
 8003e8e:	461d      	mov	r5, r3
 8003e90:	f04f 0600 	mov.w	r6, #0
 8003e94:	46a8      	mov	r8, r5
 8003e96:	46b1      	mov	r9, r6
 8003e98:	eb18 0308 	adds.w	r3, r8, r8
 8003e9c:	eb49 0409 	adc.w	r4, r9, r9
 8003ea0:	4698      	mov	r8, r3
 8003ea2:	46a1      	mov	r9, r4
 8003ea4:	eb18 0805 	adds.w	r8, r8, r5
 8003ea8:	eb49 0906 	adc.w	r9, r9, r6
 8003eac:	f04f 0100 	mov.w	r1, #0
 8003eb0:	f04f 0200 	mov.w	r2, #0
 8003eb4:	ea4f 02c9 	mov.w	r2, r9, lsl #3
 8003eb8:	ea42 7258 	orr.w	r2, r2, r8, lsr #29
 8003ebc:	ea4f 01c8 	mov.w	r1, r8, lsl #3
 8003ec0:	4688      	mov	r8, r1
 8003ec2:	4691      	mov	r9, r2
 8003ec4:	eb18 0005 	adds.w	r0, r8, r5
 8003ec8:	eb49 0106 	adc.w	r1, r9, r6
 8003ecc:	687b      	ldr	r3, [r7, #4]
 8003ece:	685b      	ldr	r3, [r3, #4]
 8003ed0:	461d      	mov	r5, r3
 8003ed2:	f04f 0600 	mov.w	r6, #0
 8003ed6:	196b      	adds	r3, r5, r5
 8003ed8:	eb46 0406 	adc.w	r4, r6, r6
 8003edc:	461a      	mov	r2, r3
 8003ede:	4623      	mov	r3, r4
 8003ee0:	f7fc fe16 	bl	8000b10 <__aeabi_uldivmod>
 8003ee4:	4603      	mov	r3, r0
 8003ee6:	460c      	mov	r4, r1
 8003ee8:	461a      	mov	r2, r3
 8003eea:	4b47      	ldr	r3, [pc, #284]	; (8004008 <UART_SetConfig+0x384>)
 8003eec:	fba3 2302 	umull	r2, r3, r3, r2
 8003ef0:	095b      	lsrs	r3, r3, #5
 8003ef2:	ea4f 1803 	mov.w	r8, r3, lsl #4
 8003ef6:	68bb      	ldr	r3, [r7, #8]
 8003ef8:	461d      	mov	r5, r3
 8003efa:	f04f 0600 	mov.w	r6, #0
 8003efe:	46a9      	mov	r9, r5
 8003f00:	46b2      	mov	sl, r6
 8003f02:	eb19 0309 	adds.w	r3, r9, r9
 8003f06:	eb4a 040a 	adc.w	r4, sl, sl
 8003f0a:	4699      	mov	r9, r3
 8003f0c:	46a2      	mov	sl, r4
 8003f0e:	eb19 0905 	adds.w	r9, r9, r5
 8003f12:	eb4a 0a06 	adc.w	sl, sl, r6
 8003f16:	f04f 0100 	mov.w	r1, #0
 8003f1a:	f04f 0200 	mov.w	r2, #0
 8003f1e:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 8003f22:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 8003f26:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8003f2a:	4689      	mov	r9, r1
 8003f2c:	4692      	mov	sl, r2
 8003f2e:	eb19 0005 	adds.w	r0, r9, r5
 8003f32:	eb4a 0106 	adc.w	r1, sl, r6
 8003f36:	687b      	ldr	r3, [r7, #4]
 8003f38:	685b      	ldr	r3, [r3, #4]
 8003f3a:	461d      	mov	r5, r3
 8003f3c:	f04f 0600 	mov.w	r6, #0
 8003f40:	196b      	adds	r3, r5, r5
 8003f42:	eb46 0406 	adc.w	r4, r6, r6
 8003f46:	461a      	mov	r2, r3
 8003f48:	4623      	mov	r3, r4
 8003f4a:	f7fc fde1 	bl	8000b10 <__aeabi_uldivmod>
 8003f4e:	4603      	mov	r3, r0
 8003f50:	460c      	mov	r4, r1
 8003f52:	461a      	mov	r2, r3
 8003f54:	4b2c      	ldr	r3, [pc, #176]	; (8004008 <UART_SetConfig+0x384>)
 8003f56:	fba3 1302 	umull	r1, r3, r3, r2
 8003f5a:	095b      	lsrs	r3, r3, #5
 8003f5c:	2164      	movs	r1, #100	; 0x64
 8003f5e:	fb01 f303 	mul.w	r3, r1, r3
 8003f62:	1ad3      	subs	r3, r2, r3
 8003f64:	00db      	lsls	r3, r3, #3
 8003f66:	3332      	adds	r3, #50	; 0x32
 8003f68:	4a27      	ldr	r2, [pc, #156]	; (8004008 <UART_SetConfig+0x384>)
 8003f6a:	fba2 2303 	umull	r2, r3, r2, r3
 8003f6e:	095b      	lsrs	r3, r3, #5
 8003f70:	005b      	lsls	r3, r3, #1
 8003f72:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 8003f76:	4498      	add	r8, r3
 8003f78:	68bb      	ldr	r3, [r7, #8]
 8003f7a:	461d      	mov	r5, r3
 8003f7c:	f04f 0600 	mov.w	r6, #0
 8003f80:	46a9      	mov	r9, r5
 8003f82:	46b2      	mov	sl, r6
 8003f84:	eb19 0309 	adds.w	r3, r9, r9
 8003f88:	eb4a 040a 	adc.w	r4, sl, sl
 8003f8c:	4699      	mov	r9, r3
 8003f8e:	46a2      	mov	sl, r4
 8003f90:	eb19 0905 	adds.w	r9, r9, r5
 8003f94:	eb4a 0a06 	adc.w	sl, sl, r6
 8003f98:	f04f 0100 	mov.w	r1, #0
 8003f9c:	f04f 0200 	mov.w	r2, #0
 8003fa0:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 8003fa4:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 8003fa8:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8003fac:	4689      	mov	r9, r1
 8003fae:	4692      	mov	sl, r2
 8003fb0:	eb19 0005 	adds.w	r0, r9, r5
 8003fb4:	eb4a 0106 	adc.w	r1, sl, r6
 8003fb8:	687b      	ldr	r3, [r7, #4]
 8003fba:	685b      	ldr	r3, [r3, #4]
 8003fbc:	461d      	mov	r5, r3
 8003fbe:	f04f 0600 	mov.w	r6, #0
 8003fc2:	196b      	adds	r3, r5, r5
 8003fc4:	eb46 0406 	adc.w	r4, r6, r6
 8003fc8:	461a      	mov	r2, r3
 8003fca:	4623      	mov	r3, r4
 8003fcc:	f7fc fda0 	bl	8000b10 <__aeabi_uldivmod>
 8003fd0:	4603      	mov	r3, r0
 8003fd2:	460c      	mov	r4, r1
 8003fd4:	461a      	mov	r2, r3
 8003fd6:	4b0c      	ldr	r3, [pc, #48]	; (8004008 <UART_SetConfig+0x384>)
 8003fd8:	fba3 1302 	umull	r1, r3, r3, r2
 8003fdc:	095b      	lsrs	r3, r3, #5
 8003fde:	2164      	movs	r1, #100	; 0x64
 8003fe0:	fb01 f303 	mul.w	r3, r1, r3
 8003fe4:	1ad3      	subs	r3, r2, r3
 8003fe6:	00db      	lsls	r3, r3, #3
 8003fe8:	3332      	adds	r3, #50	; 0x32
 8003fea:	4a07      	ldr	r2, [pc, #28]	; (8004008 <UART_SetConfig+0x384>)
 8003fec:	fba2 2303 	umull	r2, r3, r2, r3
 8003ff0:	095b      	lsrs	r3, r3, #5
 8003ff2:	f003 0207 	and.w	r2, r3, #7
 8003ff6:	687b      	ldr	r3, [r7, #4]
 8003ff8:	681b      	ldr	r3, [r3, #0]
 8003ffa:	4442      	add	r2, r8
 8003ffc:	609a      	str	r2, [r3, #8]
    {
      pclk = HAL_RCC_GetPCLK1Freq();
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
    }
  }
}
 8003ffe:	e1b2      	b.n	8004366 <UART_SetConfig+0x6e2>
 8004000:	40011000 	.word	0x40011000
 8004004:	40011400 	.word	0x40011400
 8004008:	51eb851f 	.word	0x51eb851f
    if ((huart->Instance == USART1) || (huart->Instance == USART6))
 800400c:	687b      	ldr	r3, [r7, #4]
 800400e:	681b      	ldr	r3, [r3, #0]
 8004010:	4ad7      	ldr	r2, [pc, #860]	; (8004370 <UART_SetConfig+0x6ec>)
 8004012:	4293      	cmp	r3, r2
 8004014:	d005      	beq.n	8004022 <UART_SetConfig+0x39e>
 8004016:	687b      	ldr	r3, [r7, #4]
 8004018:	681b      	ldr	r3, [r3, #0]
 800401a:	4ad6      	ldr	r2, [pc, #856]	; (8004374 <UART_SetConfig+0x6f0>)
 800401c:	4293      	cmp	r3, r2
 800401e:	f040 80d1 	bne.w	80041c4 <UART_SetConfig+0x540>
      pclk = HAL_RCC_GetPCLK2Freq();
 8004022:	f7fe ff43 	bl	8002eac <HAL_RCC_GetPCLK2Freq>
 8004026:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8004028:	68bb      	ldr	r3, [r7, #8]
 800402a:	469a      	mov	sl, r3
 800402c:	f04f 0b00 	mov.w	fp, #0
 8004030:	46d0      	mov	r8, sl
 8004032:	46d9      	mov	r9, fp
 8004034:	eb18 0308 	adds.w	r3, r8, r8
 8004038:	eb49 0409 	adc.w	r4, r9, r9
 800403c:	4698      	mov	r8, r3
 800403e:	46a1      	mov	r9, r4
 8004040:	eb18 080a 	adds.w	r8, r8, sl
 8004044:	eb49 090b 	adc.w	r9, r9, fp
 8004048:	f04f 0100 	mov.w	r1, #0
 800404c:	f04f 0200 	mov.w	r2, #0
 8004050:	ea4f 02c9 	mov.w	r2, r9, lsl #3
 8004054:	ea42 7258 	orr.w	r2, r2, r8, lsr #29
 8004058:	ea4f 01c8 	mov.w	r1, r8, lsl #3
 800405c:	4688      	mov	r8, r1
 800405e:	4691      	mov	r9, r2
 8004060:	eb1a 0508 	adds.w	r5, sl, r8
 8004064:	eb4b 0609 	adc.w	r6, fp, r9
 8004068:	687b      	ldr	r3, [r7, #4]
 800406a:	685b      	ldr	r3, [r3, #4]
 800406c:	4619      	mov	r1, r3
 800406e:	f04f 0200 	mov.w	r2, #0
 8004072:	f04f 0300 	mov.w	r3, #0
 8004076:	f04f 0400 	mov.w	r4, #0
 800407a:	0094      	lsls	r4, r2, #2
 800407c:	ea44 7491 	orr.w	r4, r4, r1, lsr #30
 8004080:	008b      	lsls	r3, r1, #2
 8004082:	461a      	mov	r2, r3
 8004084:	4623      	mov	r3, r4
 8004086:	4628      	mov	r0, r5
 8004088:	4631      	mov	r1, r6
 800408a:	f7fc fd41 	bl	8000b10 <__aeabi_uldivmod>
 800408e:	4603      	mov	r3, r0
 8004090:	460c      	mov	r4, r1
 8004092:	461a      	mov	r2, r3
 8004094:	4bb8      	ldr	r3, [pc, #736]	; (8004378 <UART_SetConfig+0x6f4>)
 8004096:	fba3 2302 	umull	r2, r3, r3, r2
 800409a:	095b      	lsrs	r3, r3, #5
 800409c:	ea4f 1803 	mov.w	r8, r3, lsl #4
 80040a0:	68bb      	ldr	r3, [r7, #8]
 80040a2:	469b      	mov	fp, r3
 80040a4:	f04f 0c00 	mov.w	ip, #0
 80040a8:	46d9      	mov	r9, fp
 80040aa:	46e2      	mov	sl, ip
 80040ac:	eb19 0309 	adds.w	r3, r9, r9
 80040b0:	eb4a 040a 	adc.w	r4, sl, sl
 80040b4:	4699      	mov	r9, r3
 80040b6:	46a2      	mov	sl, r4
 80040b8:	eb19 090b 	adds.w	r9, r9, fp
 80040bc:	eb4a 0a0c 	adc.w	sl, sl, ip
 80040c0:	f04f 0100 	mov.w	r1, #0
 80040c4:	f04f 0200 	mov.w	r2, #0
 80040c8:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 80040cc:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 80040d0:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 80040d4:	4689      	mov	r9, r1
 80040d6:	4692      	mov	sl, r2
 80040d8:	eb1b 0509 	adds.w	r5, fp, r9
 80040dc:	eb4c 060a 	adc.w	r6, ip, sl
 80040e0:	687b      	ldr	r3, [r7, #4]
 80040e2:	685b      	ldr	r3, [r3, #4]
 80040e4:	4619      	mov	r1, r3
 80040e6:	f04f 0200 	mov.w	r2, #0
 80040ea:	f04f 0300 	mov.w	r3, #0
 80040ee:	f04f 0400 	mov.w	r4, #0
 80040f2:	0094      	lsls	r4, r2, #2
 80040f4:	ea44 7491 	orr.w	r4, r4, r1, lsr #30
 80040f8:	008b      	lsls	r3, r1, #2
 80040fa:	461a      	mov	r2, r3
 80040fc:	4623      	mov	r3, r4
 80040fe:	4628      	mov	r0, r5
 8004100:	4631      	mov	r1, r6
 8004102:	f7fc fd05 	bl	8000b10 <__aeabi_uldivmod>
 8004106:	4603      	mov	r3, r0
 8004108:	460c      	mov	r4, r1
 800410a:	461a      	mov	r2, r3
 800410c:	4b9a      	ldr	r3, [pc, #616]	; (8004378 <UART_SetConfig+0x6f4>)
 800410e:	fba3 1302 	umull	r1, r3, r3, r2
 8004112:	095b      	lsrs	r3, r3, #5
 8004114:	2164      	movs	r1, #100	; 0x64
 8004116:	fb01 f303 	mul.w	r3, r1, r3
 800411a:	1ad3      	subs	r3, r2, r3
 800411c:	011b      	lsls	r3, r3, #4
 800411e:	3332      	adds	r3, #50	; 0x32
 8004120:	4a95      	ldr	r2, [pc, #596]	; (8004378 <UART_SetConfig+0x6f4>)
 8004122:	fba2 2303 	umull	r2, r3, r2, r3
 8004126:	095b      	lsrs	r3, r3, #5
 8004128:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 800412c:	4498      	add	r8, r3
 800412e:	68bb      	ldr	r3, [r7, #8]
 8004130:	469b      	mov	fp, r3
 8004132:	f04f 0c00 	mov.w	ip, #0
 8004136:	46d9      	mov	r9, fp
 8004138:	46e2      	mov	sl, ip
 800413a:	eb19 0309 	adds.w	r3, r9, r9
 800413e:	eb4a 040a 	adc.w	r4, sl, sl
 8004142:	4699      	mov	r9, r3
 8004144:	46a2      	mov	sl, r4
 8004146:	eb19 090b 	adds.w	r9, r9, fp
 800414a:	eb4a 0a0c 	adc.w	sl, sl, ip
 800414e:	f04f 0100 	mov.w	r1, #0
 8004152:	f04f 0200 	mov.w	r2, #0
 8004156:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 800415a:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 800415e:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8004162:	4689      	mov	r9, r1
 8004164:	4692      	mov	sl, r2
 8004166:	eb1b 0509 	adds.w	r5, fp, r9
 800416a:	eb4c 060a 	adc.w	r6, ip, sl
 800416e:	687b      	ldr	r3, [r7, #4]
 8004170:	685b      	ldr	r3, [r3, #4]
 8004172:	4619      	mov	r1, r3
 8004174:	f04f 0200 	mov.w	r2, #0
 8004178:	f04f 0300 	mov.w	r3, #0
 800417c:	f04f 0400 	mov.w	r4, #0
 8004180:	0094      	lsls	r4, r2, #2
 8004182:	ea44 7491 	orr.w	r4, r4, r1, lsr #30
 8004186:	008b      	lsls	r3, r1, #2
 8004188:	461a      	mov	r2, r3
 800418a:	4623      	mov	r3, r4
 800418c:	4628      	mov	r0, r5
 800418e:	4631      	mov	r1, r6
 8004190:	f7fc fcbe 	bl	8000b10 <__aeabi_uldivmod>
 8004194:	4603      	mov	r3, r0
 8004196:	460c      	mov	r4, r1
 8004198:	461a      	mov	r2, r3
 800419a:	4b77      	ldr	r3, [pc, #476]	; (8004378 <UART_SetConfig+0x6f4>)
 800419c:	fba3 1302 	umull	r1, r3, r3, r2
 80041a0:	095b      	lsrs	r3, r3, #5
 80041a2:	2164      	movs	r1, #100	; 0x64
 80041a4:	fb01 f303 	mul.w	r3, r1, r3
 80041a8:	1ad3      	subs	r3, r2, r3
 80041aa:	011b      	lsls	r3, r3, #4
 80041ac:	3332      	adds	r3, #50	; 0x32
 80041ae:	4a72      	ldr	r2, [pc, #456]	; (8004378 <UART_SetConfig+0x6f4>)
 80041b0:	fba2 2303 	umull	r2, r3, r2, r3
 80041b4:	095b      	lsrs	r3, r3, #5
 80041b6:	f003 020f 	and.w	r2, r3, #15
 80041ba:	687b      	ldr	r3, [r7, #4]
 80041bc:	681b      	ldr	r3, [r3, #0]
 80041be:	4442      	add	r2, r8
 80041c0:	609a      	str	r2, [r3, #8]
 80041c2:	e0d0      	b.n	8004366 <UART_SetConfig+0x6e2>
      pclk = HAL_RCC_GetPCLK1Freq();
 80041c4:	f7fe fe5e 	bl	8002e84 <HAL_RCC_GetPCLK1Freq>
 80041c8:	60b8      	str	r0, [r7, #8]
      huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 80041ca:	68bb      	ldr	r3, [r7, #8]
 80041cc:	469a      	mov	sl, r3
 80041ce:	f04f 0b00 	mov.w	fp, #0
 80041d2:	46d0      	mov	r8, sl
 80041d4:	46d9      	mov	r9, fp
 80041d6:	eb18 0308 	adds.w	r3, r8, r8
 80041da:	eb49 0409 	adc.w	r4, r9, r9
 80041de:	4698      	mov	r8, r3
 80041e0:	46a1      	mov	r9, r4
 80041e2:	eb18 080a 	adds.w	r8, r8, sl
 80041e6:	eb49 090b 	adc.w	r9, r9, fp
 80041ea:	f04f 0100 	mov.w	r1, #0
 80041ee:	f04f 0200 	mov.w	r2, #0
 80041f2:	ea4f 02c9 	mov.w	r2, r9, lsl #3
 80041f6:	ea42 7258 	orr.w	r2, r2, r8, lsr #29
 80041fa:	ea4f 01c8 	mov.w	r1, r8, lsl #3
 80041fe:	4688      	mov	r8, r1
 8004200:	4691      	mov	r9, r2
 8004202:	eb1a 0508 	adds.w	r5, sl, r8
 8004206:	eb4b 0609 	adc.w	r6, fp, r9
 800420a:	687b      	ldr	r3, [r7, #4]
 800420c:	685b      	ldr	r3, [r3, #4]
 800420e:	4619      	mov	r1, r3
 8004210:	f04f 0200 	mov.w	r2, #0
 8004214:	f04f 0300 	mov.w	r3, #0
 8004218:	f04f 0400 	mov.w	r4, #0
 800421c:	0094      	lsls	r4, r2, #2
 800421e:	ea44 7491 	orr.w	r4, r4, r1, lsr #30
 8004222:	008b      	lsls	r3, r1, #2
 8004224:	461a      	mov	r2, r3
 8004226:	4623      	mov	r3, r4
 8004228:	4628      	mov	r0, r5
 800422a:	4631      	mov	r1, r6
 800422c:	f7fc fc70 	bl	8000b10 <__aeabi_uldivmod>
 8004230:	4603      	mov	r3, r0
 8004232:	460c      	mov	r4, r1
 8004234:	461a      	mov	r2, r3
 8004236:	4b50      	ldr	r3, [pc, #320]	; (8004378 <UART_SetConfig+0x6f4>)
 8004238:	fba3 2302 	umull	r2, r3, r3, r2
 800423c:	095b      	lsrs	r3, r3, #5
 800423e:	ea4f 1803 	mov.w	r8, r3, lsl #4
 8004242:	68bb      	ldr	r3, [r7, #8]
 8004244:	469b      	mov	fp, r3
 8004246:	f04f 0c00 	mov.w	ip, #0
 800424a:	46d9      	mov	r9, fp
 800424c:	46e2      	mov	sl, ip
 800424e:	eb19 0309 	adds.w	r3, r9, r9
 8004252:	eb4a 040a 	adc.w	r4, sl, sl
 8004256:	4699      	mov	r9, r3
 8004258:	46a2      	mov	sl, r4
 800425a:	eb19 090b 	adds.w	r9, r9, fp
 800425e:	eb4a 0a0c 	adc.w	sl, sl, ip
 8004262:	f04f 0100 	mov.w	r1, #0
 8004266:	f04f 0200 	mov.w	r2, #0
 800426a:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 800426e:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 8004272:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8004276:	4689      	mov	r9, r1
 8004278:	4692      	mov	sl, r2
 800427a:	eb1b 0509 	adds.w	r5, fp, r9
 800427e:	eb4c 060a 	adc.w	r6, ip, sl
 8004282:	687b      	ldr	r3, [r7, #4]
 8004284:	685b      	ldr	r3, [r3, #4]
 8004286:	4619      	mov	r1, r3
 8004288:	f04f 0200 	mov.w	r2, #0
 800428c:	f04f 0300 	mov.w	r3, #0
 8004290:	f04f 0400 	mov.w	r4, #0
 8004294:	0094      	lsls	r4, r2, #2
 8004296:	ea44 7491 	orr.w	r4, r4, r1, lsr #30
 800429a:	008b      	lsls	r3, r1, #2
 800429c:	461a      	mov	r2, r3
 800429e:	4623      	mov	r3, r4
 80042a0:	4628      	mov	r0, r5
 80042a2:	4631      	mov	r1, r6
 80042a4:	f7fc fc34 	bl	8000b10 <__aeabi_uldivmod>
 80042a8:	4603      	mov	r3, r0
 80042aa:	460c      	mov	r4, r1
 80042ac:	461a      	mov	r2, r3
 80042ae:	4b32      	ldr	r3, [pc, #200]	; (8004378 <UART_SetConfig+0x6f4>)
 80042b0:	fba3 1302 	umull	r1, r3, r3, r2
 80042b4:	095b      	lsrs	r3, r3, #5
 80042b6:	2164      	movs	r1, #100	; 0x64
 80042b8:	fb01 f303 	mul.w	r3, r1, r3
 80042bc:	1ad3      	subs	r3, r2, r3
 80042be:	011b      	lsls	r3, r3, #4
 80042c0:	3332      	adds	r3, #50	; 0x32
 80042c2:	4a2d      	ldr	r2, [pc, #180]	; (8004378 <UART_SetConfig+0x6f4>)
 80042c4:	fba2 2303 	umull	r2, r3, r2, r3
 80042c8:	095b      	lsrs	r3, r3, #5
 80042ca:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 80042ce:	4498      	add	r8, r3
 80042d0:	68bb      	ldr	r3, [r7, #8]
 80042d2:	469b      	mov	fp, r3
 80042d4:	f04f 0c00 	mov.w	ip, #0
 80042d8:	46d9      	mov	r9, fp
 80042da:	46e2      	mov	sl, ip
 80042dc:	eb19 0309 	adds.w	r3, r9, r9
 80042e0:	eb4a 040a 	adc.w	r4, sl, sl
 80042e4:	4699      	mov	r9, r3
 80042e6:	46a2      	mov	sl, r4
 80042e8:	eb19 090b 	adds.w	r9, r9, fp
 80042ec:	eb4a 0a0c 	adc.w	sl, sl, ip
 80042f0:	f04f 0100 	mov.w	r1, #0
 80042f4:	f04f 0200 	mov.w	r2, #0
 80042f8:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 80042fc:	ea42 7259 	orr.w	r2, r2, r9, lsr #29
 8004300:	ea4f 01c9 	mov.w	r1, r9, lsl #3
 8004304:	4689      	mov	r9, r1
 8004306:	4692      	mov	sl, r2
 8004308:	eb1b 0509 	adds.w	r5, fp, r9
 800430c:	eb4c 060a 	adc.w	r6, ip, sl
 8004310:	687b      	ldr	r3, [r7, #4]
 8004312:	685b      	ldr	r3, [r3, #4]
 8004314:	4619      	mov	r1, r3
 8004316:	f04f 0200 	mov.w	r2, #0
 800431a:	f04f 0300 	mov.w	r3, #0
 800431e:	f04f 0400 	mov.w	r4, #0
 8004322:	0094      	lsls	r4, r2, #2
 8004324:	ea44 7491 	orr.w	r4, r4, r1, lsr #30
 8004328:	008b      	lsls	r3, r1, #2
 800432a:	461a      	mov	r2, r3
 800432c:	4623      	mov	r3, r4
 800432e:	4628      	mov	r0, r5
 8004330:	4631      	mov	r1, r6
 8004332:	f7fc fbed 	bl	8000b10 <__aeabi_uldivmod>
 8004336:	4603      	mov	r3, r0
 8004338:	460c      	mov	r4, r1
 800433a:	461a      	mov	r2, r3
 800433c:	4b0e      	ldr	r3, [pc, #56]	; (8004378 <UART_SetConfig+0x6f4>)
 800433e:	fba3 1302 	umull	r1, r3, r3, r2
 8004342:	095b      	lsrs	r3, r3, #5
 8004344:	2164      	movs	r1, #100	; 0x64
 8004346:	fb01 f303 	mul.w	r3, r1, r3
 800434a:	1ad3      	subs	r3, r2, r3
 800434c:	011b      	lsls	r3, r3, #4
 800434e:	3332      	adds	r3, #50	; 0x32
 8004350:	4a09      	ldr	r2, [pc, #36]	; (8004378 <UART_SetConfig+0x6f4>)
 8004352:	fba2 2303 	umull	r2, r3, r2, r3
 8004356:	095b      	lsrs	r3, r3, #5
 8004358:	f003 020f 	and.w	r2, r3, #15
 800435c:	687b      	ldr	r3, [r7, #4]
 800435e:	681b      	ldr	r3, [r3, #0]
 8004360:	4442      	add	r2, r8
 8004362:	609a      	str	r2, [r3, #8]
}
 8004364:	e7ff      	b.n	8004366 <UART_SetConfig+0x6e2>
 8004366:	bf00      	nop
 8004368:	3714      	adds	r7, #20
 800436a:	46bd      	mov	sp, r7
 800436c:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8004370:	40011000 	.word	0x40011000
 8004374:	40011400 	.word	0x40011400
 8004378:	51eb851f 	.word	0x51eb851f

0800437c <__errno>:
 800437c:	4b01      	ldr	r3, [pc, #4]	; (8004384 <__errno+0x8>)
 800437e:	6818      	ldr	r0, [r3, #0]
 8004380:	4770      	bx	lr
 8004382:	bf00      	nop
 8004384:	20000020 	.word	0x20000020

08004388 <__libc_init_array>:
 8004388:	b570      	push	{r4, r5, r6, lr}
 800438a:	4e0d      	ldr	r6, [pc, #52]	; (80043c0 <__libc_init_array+0x38>)
 800438c:	4c0d      	ldr	r4, [pc, #52]	; (80043c4 <__libc_init_array+0x3c>)
 800438e:	1ba4      	subs	r4, r4, r6
 8004390:	10a4      	asrs	r4, r4, #2
 8004392:	2500      	movs	r5, #0
 8004394:	42a5      	cmp	r5, r4
 8004396:	d109      	bne.n	80043ac <__libc_init_array+0x24>
 8004398:	4e0b      	ldr	r6, [pc, #44]	; (80043c8 <__libc_init_array+0x40>)
 800439a:	4c0c      	ldr	r4, [pc, #48]	; (80043cc <__libc_init_array+0x44>)
 800439c:	f001 fde2 	bl	8005f64 <_init>
 80043a0:	1ba4      	subs	r4, r4, r6
 80043a2:	10a4      	asrs	r4, r4, #2
 80043a4:	2500      	movs	r5, #0
 80043a6:	42a5      	cmp	r5, r4
 80043a8:	d105      	bne.n	80043b6 <__libc_init_array+0x2e>
 80043aa:	bd70      	pop	{r4, r5, r6, pc}
 80043ac:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80043b0:	4798      	blx	r3
 80043b2:	3501      	adds	r5, #1
 80043b4:	e7ee      	b.n	8004394 <__libc_init_array+0xc>
 80043b6:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80043ba:	4798      	blx	r3
 80043bc:	3501      	adds	r5, #1
 80043be:	e7f2      	b.n	80043a6 <__libc_init_array+0x1e>
 80043c0:	08006218 	.word	0x08006218
 80043c4:	08006218 	.word	0x08006218
 80043c8:	08006218 	.word	0x08006218
 80043cc:	0800621c 	.word	0x0800621c

080043d0 <memset>:
 80043d0:	4402      	add	r2, r0
 80043d2:	4603      	mov	r3, r0
 80043d4:	4293      	cmp	r3, r2
 80043d6:	d100      	bne.n	80043da <memset+0xa>
 80043d8:	4770      	bx	lr
 80043da:	f803 1b01 	strb.w	r1, [r3], #1
 80043de:	e7f9      	b.n	80043d4 <memset+0x4>

080043e0 <cos>:
 80043e0:	b51f      	push	{r0, r1, r2, r3, r4, lr}
 80043e2:	ec51 0b10 	vmov	r0, r1, d0
 80043e6:	4a1e      	ldr	r2, [pc, #120]	; (8004460 <cos+0x80>)
 80043e8:	f021 4300 	bic.w	r3, r1, #2147483648	; 0x80000000
 80043ec:	4293      	cmp	r3, r2
 80043ee:	dc06      	bgt.n	80043fe <cos+0x1e>
 80043f0:	ed9f 1b19 	vldr	d1, [pc, #100]	; 8004458 <cos+0x78>
 80043f4:	f000 fe8c 	bl	8005110 <__kernel_cos>
 80043f8:	ec51 0b10 	vmov	r0, r1, d0
 80043fc:	e007      	b.n	800440e <cos+0x2e>
 80043fe:	4a19      	ldr	r2, [pc, #100]	; (8004464 <cos+0x84>)
 8004400:	4293      	cmp	r3, r2
 8004402:	dd09      	ble.n	8004418 <cos+0x38>
 8004404:	ee10 2a10 	vmov	r2, s0
 8004408:	460b      	mov	r3, r1
 800440a:	f7fb fef1 	bl	80001f0 <__aeabi_dsub>
 800440e:	ec41 0b10 	vmov	d0, r0, r1
 8004412:	b005      	add	sp, #20
 8004414:	f85d fb04 	ldr.w	pc, [sp], #4
 8004418:	4668      	mov	r0, sp
 800441a:	f000 fbd5 	bl	8004bc8 <__ieee754_rem_pio2>
 800441e:	f000 0003 	and.w	r0, r0, #3
 8004422:	2801      	cmp	r0, #1
 8004424:	ed9d 1b02 	vldr	d1, [sp, #8]
 8004428:	ed9d 0b00 	vldr	d0, [sp]
 800442c:	d007      	beq.n	800443e <cos+0x5e>
 800442e:	2802      	cmp	r0, #2
 8004430:	d00e      	beq.n	8004450 <cos+0x70>
 8004432:	2800      	cmp	r0, #0
 8004434:	d0de      	beq.n	80043f4 <cos+0x14>
 8004436:	2001      	movs	r0, #1
 8004438:	f001 fa72 	bl	8005920 <__kernel_sin>
 800443c:	e7dc      	b.n	80043f8 <cos+0x18>
 800443e:	f001 fa6f 	bl	8005920 <__kernel_sin>
 8004442:	ec53 2b10 	vmov	r2, r3, d0
 8004446:	ee10 0a10 	vmov	r0, s0
 800444a:	f103 4100 	add.w	r1, r3, #2147483648	; 0x80000000
 800444e:	e7de      	b.n	800440e <cos+0x2e>
 8004450:	f000 fe5e 	bl	8005110 <__kernel_cos>
 8004454:	e7f5      	b.n	8004442 <cos+0x62>
 8004456:	bf00      	nop
	...
 8004460:	3fe921fb 	.word	0x3fe921fb
 8004464:	7fefffff 	.word	0x7fefffff

08004468 <floor>:
 8004468:	ec51 0b10 	vmov	r0, r1, d0
 800446c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8004470:	f3c1 570a 	ubfx	r7, r1, #20, #11
 8004474:	f2a7 36ff 	subw	r6, r7, #1023	; 0x3ff
 8004478:	2e13      	cmp	r6, #19
 800447a:	460c      	mov	r4, r1
 800447c:	ee10 5a10 	vmov	r5, s0
 8004480:	4680      	mov	r8, r0
 8004482:	dc34      	bgt.n	80044ee <floor+0x86>
 8004484:	2e00      	cmp	r6, #0
 8004486:	da16      	bge.n	80044b6 <floor+0x4e>
 8004488:	a335      	add	r3, pc, #212	; (adr r3, 8004560 <floor+0xf8>)
 800448a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800448e:	f7fb feb1 	bl	80001f4 <__adddf3>
 8004492:	2200      	movs	r2, #0
 8004494:	2300      	movs	r3, #0
 8004496:	f7fc faf3 	bl	8000a80 <__aeabi_dcmpgt>
 800449a:	b148      	cbz	r0, 80044b0 <floor+0x48>
 800449c:	2c00      	cmp	r4, #0
 800449e:	da59      	bge.n	8004554 <floor+0xec>
 80044a0:	f024 4300 	bic.w	r3, r4, #2147483648	; 0x80000000
 80044a4:	4a30      	ldr	r2, [pc, #192]	; (8004568 <floor+0x100>)
 80044a6:	432b      	orrs	r3, r5
 80044a8:	2500      	movs	r5, #0
 80044aa:	42ab      	cmp	r3, r5
 80044ac:	bf18      	it	ne
 80044ae:	4614      	movne	r4, r2
 80044b0:	4621      	mov	r1, r4
 80044b2:	4628      	mov	r0, r5
 80044b4:	e025      	b.n	8004502 <floor+0x9a>
 80044b6:	4f2d      	ldr	r7, [pc, #180]	; (800456c <floor+0x104>)
 80044b8:	4137      	asrs	r7, r6
 80044ba:	ea01 0307 	and.w	r3, r1, r7
 80044be:	4303      	orrs	r3, r0
 80044c0:	d01f      	beq.n	8004502 <floor+0x9a>
 80044c2:	a327      	add	r3, pc, #156	; (adr r3, 8004560 <floor+0xf8>)
 80044c4:	e9d3 2300 	ldrd	r2, r3, [r3]
 80044c8:	f7fb fe94 	bl	80001f4 <__adddf3>
 80044cc:	2200      	movs	r2, #0
 80044ce:	2300      	movs	r3, #0
 80044d0:	f7fc fad6 	bl	8000a80 <__aeabi_dcmpgt>
 80044d4:	2800      	cmp	r0, #0
 80044d6:	d0eb      	beq.n	80044b0 <floor+0x48>
 80044d8:	2c00      	cmp	r4, #0
 80044da:	bfbe      	ittt	lt
 80044dc:	f44f 1380 	movlt.w	r3, #1048576	; 0x100000
 80044e0:	fa43 f606 	asrlt.w	r6, r3, r6
 80044e4:	19a4      	addlt	r4, r4, r6
 80044e6:	ea24 0407 	bic.w	r4, r4, r7
 80044ea:	2500      	movs	r5, #0
 80044ec:	e7e0      	b.n	80044b0 <floor+0x48>
 80044ee:	2e33      	cmp	r6, #51	; 0x33
 80044f0:	dd0b      	ble.n	800450a <floor+0xa2>
 80044f2:	f5b6 6f80 	cmp.w	r6, #1024	; 0x400
 80044f6:	d104      	bne.n	8004502 <floor+0x9a>
 80044f8:	ee10 2a10 	vmov	r2, s0
 80044fc:	460b      	mov	r3, r1
 80044fe:	f7fb fe79 	bl	80001f4 <__adddf3>
 8004502:	ec41 0b10 	vmov	d0, r0, r1
 8004506:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 800450a:	f2a7 4713 	subw	r7, r7, #1043	; 0x413
 800450e:	f04f 33ff 	mov.w	r3, #4294967295
 8004512:	fa23 f707 	lsr.w	r7, r3, r7
 8004516:	4207      	tst	r7, r0
 8004518:	d0f3      	beq.n	8004502 <floor+0x9a>
 800451a:	a311      	add	r3, pc, #68	; (adr r3, 8004560 <floor+0xf8>)
 800451c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004520:	f7fb fe68 	bl	80001f4 <__adddf3>
 8004524:	2200      	movs	r2, #0
 8004526:	2300      	movs	r3, #0
 8004528:	f7fc faaa 	bl	8000a80 <__aeabi_dcmpgt>
 800452c:	2800      	cmp	r0, #0
 800452e:	d0bf      	beq.n	80044b0 <floor+0x48>
 8004530:	2c00      	cmp	r4, #0
 8004532:	da02      	bge.n	800453a <floor+0xd2>
 8004534:	2e14      	cmp	r6, #20
 8004536:	d103      	bne.n	8004540 <floor+0xd8>
 8004538:	3401      	adds	r4, #1
 800453a:	ea25 0507 	bic.w	r5, r5, r7
 800453e:	e7b7      	b.n	80044b0 <floor+0x48>
 8004540:	2301      	movs	r3, #1
 8004542:	f1c6 0634 	rsb	r6, r6, #52	; 0x34
 8004546:	fa03 f606 	lsl.w	r6, r3, r6
 800454a:	4435      	add	r5, r6
 800454c:	4545      	cmp	r5, r8
 800454e:	bf38      	it	cc
 8004550:	18e4      	addcc	r4, r4, r3
 8004552:	e7f2      	b.n	800453a <floor+0xd2>
 8004554:	2500      	movs	r5, #0
 8004556:	462c      	mov	r4, r5
 8004558:	e7aa      	b.n	80044b0 <floor+0x48>
 800455a:	bf00      	nop
 800455c:	f3af 8000 	nop.w
 8004560:	8800759c 	.word	0x8800759c
 8004564:	7e37e43c 	.word	0x7e37e43c
 8004568:	bff00000 	.word	0xbff00000
 800456c:	000fffff 	.word	0x000fffff

08004570 <sin>:
 8004570:	b51f      	push	{r0, r1, r2, r3, r4, lr}
 8004572:	ec51 0b10 	vmov	r0, r1, d0
 8004576:	4a20      	ldr	r2, [pc, #128]	; (80045f8 <sin+0x88>)
 8004578:	f021 4300 	bic.w	r3, r1, #2147483648	; 0x80000000
 800457c:	4293      	cmp	r3, r2
 800457e:	dc07      	bgt.n	8004590 <sin+0x20>
 8004580:	ed9f 1b1b 	vldr	d1, [pc, #108]	; 80045f0 <sin+0x80>
 8004584:	2000      	movs	r0, #0
 8004586:	f001 f9cb 	bl	8005920 <__kernel_sin>
 800458a:	ec51 0b10 	vmov	r0, r1, d0
 800458e:	e007      	b.n	80045a0 <sin+0x30>
 8004590:	4a1a      	ldr	r2, [pc, #104]	; (80045fc <sin+0x8c>)
 8004592:	4293      	cmp	r3, r2
 8004594:	dd09      	ble.n	80045aa <sin+0x3a>
 8004596:	ee10 2a10 	vmov	r2, s0
 800459a:	460b      	mov	r3, r1
 800459c:	f7fb fe28 	bl	80001f0 <__aeabi_dsub>
 80045a0:	ec41 0b10 	vmov	d0, r0, r1
 80045a4:	b005      	add	sp, #20
 80045a6:	f85d fb04 	ldr.w	pc, [sp], #4
 80045aa:	4668      	mov	r0, sp
 80045ac:	f000 fb0c 	bl	8004bc8 <__ieee754_rem_pio2>
 80045b0:	f000 0003 	and.w	r0, r0, #3
 80045b4:	2801      	cmp	r0, #1
 80045b6:	ed9d 1b02 	vldr	d1, [sp, #8]
 80045ba:	ed9d 0b00 	vldr	d0, [sp]
 80045be:	d004      	beq.n	80045ca <sin+0x5a>
 80045c0:	2802      	cmp	r0, #2
 80045c2:	d005      	beq.n	80045d0 <sin+0x60>
 80045c4:	b970      	cbnz	r0, 80045e4 <sin+0x74>
 80045c6:	2001      	movs	r0, #1
 80045c8:	e7dd      	b.n	8004586 <sin+0x16>
 80045ca:	f000 fda1 	bl	8005110 <__kernel_cos>
 80045ce:	e7dc      	b.n	800458a <sin+0x1a>
 80045d0:	2001      	movs	r0, #1
 80045d2:	f001 f9a5 	bl	8005920 <__kernel_sin>
 80045d6:	ec53 2b10 	vmov	r2, r3, d0
 80045da:	ee10 0a10 	vmov	r0, s0
 80045de:	f103 4100 	add.w	r1, r3, #2147483648	; 0x80000000
 80045e2:	e7dd      	b.n	80045a0 <sin+0x30>
 80045e4:	f000 fd94 	bl	8005110 <__kernel_cos>
 80045e8:	e7f5      	b.n	80045d6 <sin+0x66>
 80045ea:	bf00      	nop
 80045ec:	f3af 8000 	nop.w
	...
 80045f8:	3fe921fb 	.word	0x3fe921fb
 80045fc:	7fefffff 	.word	0x7fefffff

08004600 <tan>:
 8004600:	b51f      	push	{r0, r1, r2, r3, r4, lr}
 8004602:	ec51 0b10 	vmov	r0, r1, d0
 8004606:	4a14      	ldr	r2, [pc, #80]	; (8004658 <tan+0x58>)
 8004608:	f021 4300 	bic.w	r3, r1, #2147483648	; 0x80000000
 800460c:	4293      	cmp	r3, r2
 800460e:	dc05      	bgt.n	800461c <tan+0x1c>
 8004610:	ed9f 1b0f 	vldr	d1, [pc, #60]	; 8004650 <tan+0x50>
 8004614:	2001      	movs	r0, #1
 8004616:	f001 fa3f 	bl	8005a98 <__kernel_tan>
 800461a:	e009      	b.n	8004630 <tan+0x30>
 800461c:	4a0f      	ldr	r2, [pc, #60]	; (800465c <tan+0x5c>)
 800461e:	4293      	cmp	r3, r2
 8004620:	dd09      	ble.n	8004636 <tan+0x36>
 8004622:	ee10 2a10 	vmov	r2, s0
 8004626:	460b      	mov	r3, r1
 8004628:	f7fb fde2 	bl	80001f0 <__aeabi_dsub>
 800462c:	ec41 0b10 	vmov	d0, r0, r1
 8004630:	b005      	add	sp, #20
 8004632:	f85d fb04 	ldr.w	pc, [sp], #4
 8004636:	4668      	mov	r0, sp
 8004638:	f000 fac6 	bl	8004bc8 <__ieee754_rem_pio2>
 800463c:	0040      	lsls	r0, r0, #1
 800463e:	f000 0002 	and.w	r0, r0, #2
 8004642:	f1c0 0001 	rsb	r0, r0, #1
 8004646:	ed9d 1b02 	vldr	d1, [sp, #8]
 800464a:	ed9d 0b00 	vldr	d0, [sp]
 800464e:	e7e2      	b.n	8004616 <tan+0x16>
	...
 8004658:	3fe921fb 	.word	0x3fe921fb
 800465c:	7fefffff 	.word	0x7fefffff

08004660 <acos>:
 8004660:	b5f0      	push	{r4, r5, r6, r7, lr}
 8004662:	ed2d 8b02 	vpush	{d8}
 8004666:	4e26      	ldr	r6, [pc, #152]	; (8004700 <acos+0xa0>)
 8004668:	b08b      	sub	sp, #44	; 0x2c
 800466a:	ec55 4b10 	vmov	r4, r5, d0
 800466e:	f000 f84f 	bl	8004710 <__ieee754_acos>
 8004672:	f996 3000 	ldrsb.w	r3, [r6]
 8004676:	eeb0 8a40 	vmov.f32	s16, s0
 800467a:	eef0 8a60 	vmov.f32	s17, s1
 800467e:	3301      	adds	r3, #1
 8004680:	d036      	beq.n	80046f0 <acos+0x90>
 8004682:	4622      	mov	r2, r4
 8004684:	462b      	mov	r3, r5
 8004686:	4620      	mov	r0, r4
 8004688:	4629      	mov	r1, r5
 800468a:	f7fc fa03 	bl	8000a94 <__aeabi_dcmpun>
 800468e:	4607      	mov	r7, r0
 8004690:	bb70      	cbnz	r0, 80046f0 <acos+0x90>
 8004692:	ec45 4b10 	vmov	d0, r4, r5
 8004696:	f001 fbcb 	bl	8005e30 <fabs>
 800469a:	2200      	movs	r2, #0
 800469c:	4b19      	ldr	r3, [pc, #100]	; (8004704 <acos+0xa4>)
 800469e:	ec51 0b10 	vmov	r0, r1, d0
 80046a2:	f7fc f9ed 	bl	8000a80 <__aeabi_dcmpgt>
 80046a6:	b318      	cbz	r0, 80046f0 <acos+0x90>
 80046a8:	2301      	movs	r3, #1
 80046aa:	9300      	str	r3, [sp, #0]
 80046ac:	4816      	ldr	r0, [pc, #88]	; (8004708 <acos+0xa8>)
 80046ae:	4b17      	ldr	r3, [pc, #92]	; (800470c <acos+0xac>)
 80046b0:	9301      	str	r3, [sp, #4]
 80046b2:	9708      	str	r7, [sp, #32]
 80046b4:	e9cd 4504 	strd	r4, r5, [sp, #16]
 80046b8:	e9cd 4502 	strd	r4, r5, [sp, #8]
 80046bc:	f001 fbc4 	bl	8005e48 <nan>
 80046c0:	f996 3000 	ldrsb.w	r3, [r6]
 80046c4:	2b02      	cmp	r3, #2
 80046c6:	ed8d 0b06 	vstr	d0, [sp, #24]
 80046ca:	d104      	bne.n	80046d6 <acos+0x76>
 80046cc:	f7ff fe56 	bl	800437c <__errno>
 80046d0:	2321      	movs	r3, #33	; 0x21
 80046d2:	6003      	str	r3, [r0, #0]
 80046d4:	e004      	b.n	80046e0 <acos+0x80>
 80046d6:	4668      	mov	r0, sp
 80046d8:	f001 fbb3 	bl	8005e42 <matherr>
 80046dc:	2800      	cmp	r0, #0
 80046de:	d0f5      	beq.n	80046cc <acos+0x6c>
 80046e0:	9b08      	ldr	r3, [sp, #32]
 80046e2:	b11b      	cbz	r3, 80046ec <acos+0x8c>
 80046e4:	f7ff fe4a 	bl	800437c <__errno>
 80046e8:	9b08      	ldr	r3, [sp, #32]
 80046ea:	6003      	str	r3, [r0, #0]
 80046ec:	ed9d 8b06 	vldr	d8, [sp, #24]
 80046f0:	eeb0 0a48 	vmov.f32	s0, s16
 80046f4:	eef0 0a68 	vmov.f32	s1, s17
 80046f8:	b00b      	add	sp, #44	; 0x2c
 80046fa:	ecbd 8b02 	vpop	{d8}
 80046fe:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8004700:	20000084 	.word	0x20000084
 8004704:	3ff00000 	.word	0x3ff00000
 8004708:	08006034 	.word	0x08006034
 800470c:	08006030 	.word	0x08006030

08004710 <__ieee754_acos>:
 8004710:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8004714:	ec55 4b10 	vmov	r4, r5, d0
 8004718:	49b7      	ldr	r1, [pc, #732]	; (80049f8 <__ieee754_acos+0x2e8>)
 800471a:	f025 4300 	bic.w	r3, r5, #2147483648	; 0x80000000
 800471e:	428b      	cmp	r3, r1
 8004720:	dd1b      	ble.n	800475a <__ieee754_acos+0x4a>
 8004722:	f103 4340 	add.w	r3, r3, #3221225472	; 0xc0000000
 8004726:	f503 1380 	add.w	r3, r3, #1048576	; 0x100000
 800472a:	4323      	orrs	r3, r4
 800472c:	d109      	bne.n	8004742 <__ieee754_acos+0x32>
 800472e:	2d00      	cmp	r5, #0
 8004730:	f300 8211 	bgt.w	8004b56 <__ieee754_acos+0x446>
 8004734:	a196      	add	r1, pc, #600	; (adr r1, 8004990 <__ieee754_acos+0x280>)
 8004736:	e9d1 0100 	ldrd	r0, r1, [r1]
 800473a:	ec41 0b10 	vmov	d0, r0, r1
 800473e:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8004742:	ee10 2a10 	vmov	r2, s0
 8004746:	462b      	mov	r3, r5
 8004748:	4620      	mov	r0, r4
 800474a:	4629      	mov	r1, r5
 800474c:	f7fb fd50 	bl	80001f0 <__aeabi_dsub>
 8004750:	4602      	mov	r2, r0
 8004752:	460b      	mov	r3, r1
 8004754:	f7fc f82e 	bl	80007b4 <__aeabi_ddiv>
 8004758:	e7ef      	b.n	800473a <__ieee754_acos+0x2a>
 800475a:	49a8      	ldr	r1, [pc, #672]	; (80049fc <__ieee754_acos+0x2ec>)
 800475c:	428b      	cmp	r3, r1
 800475e:	f300 8087 	bgt.w	8004870 <__ieee754_acos+0x160>
 8004762:	4aa7      	ldr	r2, [pc, #668]	; (8004a00 <__ieee754_acos+0x2f0>)
 8004764:	4293      	cmp	r3, r2
 8004766:	f340 81f9 	ble.w	8004b5c <__ieee754_acos+0x44c>
 800476a:	ee10 2a10 	vmov	r2, s0
 800476e:	ee10 0a10 	vmov	r0, s0
 8004772:	462b      	mov	r3, r5
 8004774:	4629      	mov	r1, r5
 8004776:	f7fb fef3 	bl	8000560 <__aeabi_dmul>
 800477a:	a387      	add	r3, pc, #540	; (adr r3, 8004998 <__ieee754_acos+0x288>)
 800477c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004780:	4606      	mov	r6, r0
 8004782:	460f      	mov	r7, r1
 8004784:	f7fb feec 	bl	8000560 <__aeabi_dmul>
 8004788:	a385      	add	r3, pc, #532	; (adr r3, 80049a0 <__ieee754_acos+0x290>)
 800478a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800478e:	f7fb fd31 	bl	80001f4 <__adddf3>
 8004792:	4632      	mov	r2, r6
 8004794:	463b      	mov	r3, r7
 8004796:	f7fb fee3 	bl	8000560 <__aeabi_dmul>
 800479a:	a383      	add	r3, pc, #524	; (adr r3, 80049a8 <__ieee754_acos+0x298>)
 800479c:	e9d3 2300 	ldrd	r2, r3, [r3]
 80047a0:	f7fb fd26 	bl	80001f0 <__aeabi_dsub>
 80047a4:	4632      	mov	r2, r6
 80047a6:	463b      	mov	r3, r7
 80047a8:	f7fb feda 	bl	8000560 <__aeabi_dmul>
 80047ac:	a380      	add	r3, pc, #512	; (adr r3, 80049b0 <__ieee754_acos+0x2a0>)
 80047ae:	e9d3 2300 	ldrd	r2, r3, [r3]
 80047b2:	f7fb fd1f 	bl	80001f4 <__adddf3>
 80047b6:	4632      	mov	r2, r6
 80047b8:	463b      	mov	r3, r7
 80047ba:	f7fb fed1 	bl	8000560 <__aeabi_dmul>
 80047be:	a37e      	add	r3, pc, #504	; (adr r3, 80049b8 <__ieee754_acos+0x2a8>)
 80047c0:	e9d3 2300 	ldrd	r2, r3, [r3]
 80047c4:	f7fb fd14 	bl	80001f0 <__aeabi_dsub>
 80047c8:	4632      	mov	r2, r6
 80047ca:	463b      	mov	r3, r7
 80047cc:	f7fb fec8 	bl	8000560 <__aeabi_dmul>
 80047d0:	a37b      	add	r3, pc, #492	; (adr r3, 80049c0 <__ieee754_acos+0x2b0>)
 80047d2:	e9d3 2300 	ldrd	r2, r3, [r3]
 80047d6:	f7fb fd0d 	bl	80001f4 <__adddf3>
 80047da:	4632      	mov	r2, r6
 80047dc:	463b      	mov	r3, r7
 80047de:	f7fb febf 	bl	8000560 <__aeabi_dmul>
 80047e2:	a379      	add	r3, pc, #484	; (adr r3, 80049c8 <__ieee754_acos+0x2b8>)
 80047e4:	e9d3 2300 	ldrd	r2, r3, [r3]
 80047e8:	4680      	mov	r8, r0
 80047ea:	4689      	mov	r9, r1
 80047ec:	4630      	mov	r0, r6
 80047ee:	4639      	mov	r1, r7
 80047f0:	f7fb feb6 	bl	8000560 <__aeabi_dmul>
 80047f4:	a376      	add	r3, pc, #472	; (adr r3, 80049d0 <__ieee754_acos+0x2c0>)
 80047f6:	e9d3 2300 	ldrd	r2, r3, [r3]
 80047fa:	f7fb fcf9 	bl	80001f0 <__aeabi_dsub>
 80047fe:	4632      	mov	r2, r6
 8004800:	463b      	mov	r3, r7
 8004802:	f7fb fead 	bl	8000560 <__aeabi_dmul>
 8004806:	a374      	add	r3, pc, #464	; (adr r3, 80049d8 <__ieee754_acos+0x2c8>)
 8004808:	e9d3 2300 	ldrd	r2, r3, [r3]
 800480c:	f7fb fcf2 	bl	80001f4 <__adddf3>
 8004810:	4632      	mov	r2, r6
 8004812:	463b      	mov	r3, r7
 8004814:	f7fb fea4 	bl	8000560 <__aeabi_dmul>
 8004818:	a371      	add	r3, pc, #452	; (adr r3, 80049e0 <__ieee754_acos+0x2d0>)
 800481a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800481e:	f7fb fce7 	bl	80001f0 <__aeabi_dsub>
 8004822:	4632      	mov	r2, r6
 8004824:	463b      	mov	r3, r7
 8004826:	f7fb fe9b 	bl	8000560 <__aeabi_dmul>
 800482a:	2200      	movs	r2, #0
 800482c:	4b75      	ldr	r3, [pc, #468]	; (8004a04 <__ieee754_acos+0x2f4>)
 800482e:	f7fb fce1 	bl	80001f4 <__adddf3>
 8004832:	4602      	mov	r2, r0
 8004834:	460b      	mov	r3, r1
 8004836:	4640      	mov	r0, r8
 8004838:	4649      	mov	r1, r9
 800483a:	f7fb ffbb 	bl	80007b4 <__aeabi_ddiv>
 800483e:	4622      	mov	r2, r4
 8004840:	462b      	mov	r3, r5
 8004842:	f7fb fe8d 	bl	8000560 <__aeabi_dmul>
 8004846:	4602      	mov	r2, r0
 8004848:	460b      	mov	r3, r1
 800484a:	a167      	add	r1, pc, #412	; (adr r1, 80049e8 <__ieee754_acos+0x2d8>)
 800484c:	e9d1 0100 	ldrd	r0, r1, [r1]
 8004850:	f7fb fcce 	bl	80001f0 <__aeabi_dsub>
 8004854:	4602      	mov	r2, r0
 8004856:	460b      	mov	r3, r1
 8004858:	4620      	mov	r0, r4
 800485a:	4629      	mov	r1, r5
 800485c:	f7fb fcc8 	bl	80001f0 <__aeabi_dsub>
 8004860:	4602      	mov	r2, r0
 8004862:	460b      	mov	r3, r1
 8004864:	a162      	add	r1, pc, #392	; (adr r1, 80049f0 <__ieee754_acos+0x2e0>)
 8004866:	e9d1 0100 	ldrd	r0, r1, [r1]
 800486a:	f7fb fcc1 	bl	80001f0 <__aeabi_dsub>
 800486e:	e764      	b.n	800473a <__ieee754_acos+0x2a>
 8004870:	2d00      	cmp	r5, #0
 8004872:	f280 80cb 	bge.w	8004a0c <__ieee754_acos+0x2fc>
 8004876:	ee10 0a10 	vmov	r0, s0
 800487a:	2200      	movs	r2, #0
 800487c:	4b61      	ldr	r3, [pc, #388]	; (8004a04 <__ieee754_acos+0x2f4>)
 800487e:	4629      	mov	r1, r5
 8004880:	f7fb fcb8 	bl	80001f4 <__adddf3>
 8004884:	2200      	movs	r2, #0
 8004886:	4b60      	ldr	r3, [pc, #384]	; (8004a08 <__ieee754_acos+0x2f8>)
 8004888:	f7fb fe6a 	bl	8000560 <__aeabi_dmul>
 800488c:	a342      	add	r3, pc, #264	; (adr r3, 8004998 <__ieee754_acos+0x288>)
 800488e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004892:	4604      	mov	r4, r0
 8004894:	460d      	mov	r5, r1
 8004896:	f7fb fe63 	bl	8000560 <__aeabi_dmul>
 800489a:	a341      	add	r3, pc, #260	; (adr r3, 80049a0 <__ieee754_acos+0x290>)
 800489c:	e9d3 2300 	ldrd	r2, r3, [r3]
 80048a0:	f7fb fca8 	bl	80001f4 <__adddf3>
 80048a4:	4622      	mov	r2, r4
 80048a6:	462b      	mov	r3, r5
 80048a8:	f7fb fe5a 	bl	8000560 <__aeabi_dmul>
 80048ac:	a33e      	add	r3, pc, #248	; (adr r3, 80049a8 <__ieee754_acos+0x298>)
 80048ae:	e9d3 2300 	ldrd	r2, r3, [r3]
 80048b2:	f7fb fc9d 	bl	80001f0 <__aeabi_dsub>
 80048b6:	4622      	mov	r2, r4
 80048b8:	462b      	mov	r3, r5
 80048ba:	f7fb fe51 	bl	8000560 <__aeabi_dmul>
 80048be:	a33c      	add	r3, pc, #240	; (adr r3, 80049b0 <__ieee754_acos+0x2a0>)
 80048c0:	e9d3 2300 	ldrd	r2, r3, [r3]
 80048c4:	f7fb fc96 	bl	80001f4 <__adddf3>
 80048c8:	4622      	mov	r2, r4
 80048ca:	462b      	mov	r3, r5
 80048cc:	f7fb fe48 	bl	8000560 <__aeabi_dmul>
 80048d0:	a339      	add	r3, pc, #228	; (adr r3, 80049b8 <__ieee754_acos+0x2a8>)
 80048d2:	e9d3 2300 	ldrd	r2, r3, [r3]
 80048d6:	f7fb fc8b 	bl	80001f0 <__aeabi_dsub>
 80048da:	4622      	mov	r2, r4
 80048dc:	462b      	mov	r3, r5
 80048de:	f7fb fe3f 	bl	8000560 <__aeabi_dmul>
 80048e2:	a337      	add	r3, pc, #220	; (adr r3, 80049c0 <__ieee754_acos+0x2b0>)
 80048e4:	e9d3 2300 	ldrd	r2, r3, [r3]
 80048e8:	f7fb fc84 	bl	80001f4 <__adddf3>
 80048ec:	4622      	mov	r2, r4
 80048ee:	462b      	mov	r3, r5
 80048f0:	f7fb fe36 	bl	8000560 <__aeabi_dmul>
 80048f4:	ec45 4b10 	vmov	d0, r4, r5
 80048f8:	4680      	mov	r8, r0
 80048fa:	4689      	mov	r9, r1
 80048fc:	f000 fb56 	bl	8004fac <__ieee754_sqrt>
 8004900:	a331      	add	r3, pc, #196	; (adr r3, 80049c8 <__ieee754_acos+0x2b8>)
 8004902:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004906:	4620      	mov	r0, r4
 8004908:	4629      	mov	r1, r5
 800490a:	ec57 6b10 	vmov	r6, r7, d0
 800490e:	f7fb fe27 	bl	8000560 <__aeabi_dmul>
 8004912:	a32f      	add	r3, pc, #188	; (adr r3, 80049d0 <__ieee754_acos+0x2c0>)
 8004914:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004918:	f7fb fc6a 	bl	80001f0 <__aeabi_dsub>
 800491c:	4622      	mov	r2, r4
 800491e:	462b      	mov	r3, r5
 8004920:	f7fb fe1e 	bl	8000560 <__aeabi_dmul>
 8004924:	a32c      	add	r3, pc, #176	; (adr r3, 80049d8 <__ieee754_acos+0x2c8>)
 8004926:	e9d3 2300 	ldrd	r2, r3, [r3]
 800492a:	f7fb fc63 	bl	80001f4 <__adddf3>
 800492e:	4622      	mov	r2, r4
 8004930:	462b      	mov	r3, r5
 8004932:	f7fb fe15 	bl	8000560 <__aeabi_dmul>
 8004936:	a32a      	add	r3, pc, #168	; (adr r3, 80049e0 <__ieee754_acos+0x2d0>)
 8004938:	e9d3 2300 	ldrd	r2, r3, [r3]
 800493c:	f7fb fc58 	bl	80001f0 <__aeabi_dsub>
 8004940:	4622      	mov	r2, r4
 8004942:	462b      	mov	r3, r5
 8004944:	f7fb fe0c 	bl	8000560 <__aeabi_dmul>
 8004948:	2200      	movs	r2, #0
 800494a:	4b2e      	ldr	r3, [pc, #184]	; (8004a04 <__ieee754_acos+0x2f4>)
 800494c:	f7fb fc52 	bl	80001f4 <__adddf3>
 8004950:	4602      	mov	r2, r0
 8004952:	460b      	mov	r3, r1
 8004954:	4640      	mov	r0, r8
 8004956:	4649      	mov	r1, r9
 8004958:	f7fb ff2c 	bl	80007b4 <__aeabi_ddiv>
 800495c:	4632      	mov	r2, r6
 800495e:	463b      	mov	r3, r7
 8004960:	f7fb fdfe 	bl	8000560 <__aeabi_dmul>
 8004964:	a320      	add	r3, pc, #128	; (adr r3, 80049e8 <__ieee754_acos+0x2d8>)
 8004966:	e9d3 2300 	ldrd	r2, r3, [r3]
 800496a:	f7fb fc41 	bl	80001f0 <__aeabi_dsub>
 800496e:	4632      	mov	r2, r6
 8004970:	463b      	mov	r3, r7
 8004972:	f7fb fc3f 	bl	80001f4 <__adddf3>
 8004976:	4602      	mov	r2, r0
 8004978:	460b      	mov	r3, r1
 800497a:	f7fb fc3b 	bl	80001f4 <__adddf3>
 800497e:	4602      	mov	r2, r0
 8004980:	460b      	mov	r3, r1
 8004982:	a103      	add	r1, pc, #12	; (adr r1, 8004990 <__ieee754_acos+0x280>)
 8004984:	e9d1 0100 	ldrd	r0, r1, [r1]
 8004988:	e76f      	b.n	800486a <__ieee754_acos+0x15a>
 800498a:	bf00      	nop
 800498c:	f3af 8000 	nop.w
 8004990:	54442d18 	.word	0x54442d18
 8004994:	400921fb 	.word	0x400921fb
 8004998:	0dfdf709 	.word	0x0dfdf709
 800499c:	3f023de1 	.word	0x3f023de1
 80049a0:	7501b288 	.word	0x7501b288
 80049a4:	3f49efe0 	.word	0x3f49efe0
 80049a8:	b5688f3b 	.word	0xb5688f3b
 80049ac:	3fa48228 	.word	0x3fa48228
 80049b0:	0e884455 	.word	0x0e884455
 80049b4:	3fc9c155 	.word	0x3fc9c155
 80049b8:	03eb6f7d 	.word	0x03eb6f7d
 80049bc:	3fd4d612 	.word	0x3fd4d612
 80049c0:	55555555 	.word	0x55555555
 80049c4:	3fc55555 	.word	0x3fc55555
 80049c8:	b12e9282 	.word	0xb12e9282
 80049cc:	3fb3b8c5 	.word	0x3fb3b8c5
 80049d0:	1b8d0159 	.word	0x1b8d0159
 80049d4:	3fe6066c 	.word	0x3fe6066c
 80049d8:	9c598ac8 	.word	0x9c598ac8
 80049dc:	40002ae5 	.word	0x40002ae5
 80049e0:	1c8a2d4b 	.word	0x1c8a2d4b
 80049e4:	40033a27 	.word	0x40033a27
 80049e8:	33145c07 	.word	0x33145c07
 80049ec:	3c91a626 	.word	0x3c91a626
 80049f0:	54442d18 	.word	0x54442d18
 80049f4:	3ff921fb 	.word	0x3ff921fb
 80049f8:	3fefffff 	.word	0x3fefffff
 80049fc:	3fdfffff 	.word	0x3fdfffff
 8004a00:	3c600000 	.word	0x3c600000
 8004a04:	3ff00000 	.word	0x3ff00000
 8004a08:	3fe00000 	.word	0x3fe00000
 8004a0c:	ee10 2a10 	vmov	r2, s0
 8004a10:	462b      	mov	r3, r5
 8004a12:	2000      	movs	r0, #0
 8004a14:	496a      	ldr	r1, [pc, #424]	; (8004bc0 <__ieee754_acos+0x4b0>)
 8004a16:	f7fb fbeb 	bl	80001f0 <__aeabi_dsub>
 8004a1a:	2200      	movs	r2, #0
 8004a1c:	4b69      	ldr	r3, [pc, #420]	; (8004bc4 <__ieee754_acos+0x4b4>)
 8004a1e:	f7fb fd9f 	bl	8000560 <__aeabi_dmul>
 8004a22:	4604      	mov	r4, r0
 8004a24:	460d      	mov	r5, r1
 8004a26:	ec45 4b10 	vmov	d0, r4, r5
 8004a2a:	f000 fabf 	bl	8004fac <__ieee754_sqrt>
 8004a2e:	a34e      	add	r3, pc, #312	; (adr r3, 8004b68 <__ieee754_acos+0x458>)
 8004a30:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004a34:	4620      	mov	r0, r4
 8004a36:	4629      	mov	r1, r5
 8004a38:	ec59 8b10 	vmov	r8, r9, d0
 8004a3c:	f7fb fd90 	bl	8000560 <__aeabi_dmul>
 8004a40:	a34b      	add	r3, pc, #300	; (adr r3, 8004b70 <__ieee754_acos+0x460>)
 8004a42:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004a46:	f7fb fbd5 	bl	80001f4 <__adddf3>
 8004a4a:	4622      	mov	r2, r4
 8004a4c:	462b      	mov	r3, r5
 8004a4e:	f7fb fd87 	bl	8000560 <__aeabi_dmul>
 8004a52:	a349      	add	r3, pc, #292	; (adr r3, 8004b78 <__ieee754_acos+0x468>)
 8004a54:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004a58:	f7fb fbca 	bl	80001f0 <__aeabi_dsub>
 8004a5c:	4622      	mov	r2, r4
 8004a5e:	462b      	mov	r3, r5
 8004a60:	f7fb fd7e 	bl	8000560 <__aeabi_dmul>
 8004a64:	a346      	add	r3, pc, #280	; (adr r3, 8004b80 <__ieee754_acos+0x470>)
 8004a66:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004a6a:	f7fb fbc3 	bl	80001f4 <__adddf3>
 8004a6e:	4622      	mov	r2, r4
 8004a70:	462b      	mov	r3, r5
 8004a72:	f7fb fd75 	bl	8000560 <__aeabi_dmul>
 8004a76:	a344      	add	r3, pc, #272	; (adr r3, 8004b88 <__ieee754_acos+0x478>)
 8004a78:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004a7c:	f7fb fbb8 	bl	80001f0 <__aeabi_dsub>
 8004a80:	4622      	mov	r2, r4
 8004a82:	462b      	mov	r3, r5
 8004a84:	f7fb fd6c 	bl	8000560 <__aeabi_dmul>
 8004a88:	a341      	add	r3, pc, #260	; (adr r3, 8004b90 <__ieee754_acos+0x480>)
 8004a8a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004a8e:	f7fb fbb1 	bl	80001f4 <__adddf3>
 8004a92:	4622      	mov	r2, r4
 8004a94:	462b      	mov	r3, r5
 8004a96:	f7fb fd63 	bl	8000560 <__aeabi_dmul>
 8004a9a:	a33f      	add	r3, pc, #252	; (adr r3, 8004b98 <__ieee754_acos+0x488>)
 8004a9c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004aa0:	4682      	mov	sl, r0
 8004aa2:	468b      	mov	fp, r1
 8004aa4:	4620      	mov	r0, r4
 8004aa6:	4629      	mov	r1, r5
 8004aa8:	f7fb fd5a 	bl	8000560 <__aeabi_dmul>
 8004aac:	a33c      	add	r3, pc, #240	; (adr r3, 8004ba0 <__ieee754_acos+0x490>)
 8004aae:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004ab2:	f7fb fb9d 	bl	80001f0 <__aeabi_dsub>
 8004ab6:	4622      	mov	r2, r4
 8004ab8:	462b      	mov	r3, r5
 8004aba:	f7fb fd51 	bl	8000560 <__aeabi_dmul>
 8004abe:	a33a      	add	r3, pc, #232	; (adr r3, 8004ba8 <__ieee754_acos+0x498>)
 8004ac0:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004ac4:	f7fb fb96 	bl	80001f4 <__adddf3>
 8004ac8:	4622      	mov	r2, r4
 8004aca:	462b      	mov	r3, r5
 8004acc:	f7fb fd48 	bl	8000560 <__aeabi_dmul>
 8004ad0:	a337      	add	r3, pc, #220	; (adr r3, 8004bb0 <__ieee754_acos+0x4a0>)
 8004ad2:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004ad6:	f7fb fb8b 	bl	80001f0 <__aeabi_dsub>
 8004ada:	4622      	mov	r2, r4
 8004adc:	462b      	mov	r3, r5
 8004ade:	f7fb fd3f 	bl	8000560 <__aeabi_dmul>
 8004ae2:	2200      	movs	r2, #0
 8004ae4:	4b36      	ldr	r3, [pc, #216]	; (8004bc0 <__ieee754_acos+0x4b0>)
 8004ae6:	f7fb fb85 	bl	80001f4 <__adddf3>
 8004aea:	4602      	mov	r2, r0
 8004aec:	460b      	mov	r3, r1
 8004aee:	4650      	mov	r0, sl
 8004af0:	4659      	mov	r1, fp
 8004af2:	f7fb fe5f 	bl	80007b4 <__aeabi_ddiv>
 8004af6:	4642      	mov	r2, r8
 8004af8:	464b      	mov	r3, r9
 8004afa:	f7fb fd31 	bl	8000560 <__aeabi_dmul>
 8004afe:	2600      	movs	r6, #0
 8004b00:	4682      	mov	sl, r0
 8004b02:	468b      	mov	fp, r1
 8004b04:	4632      	mov	r2, r6
 8004b06:	464b      	mov	r3, r9
 8004b08:	4630      	mov	r0, r6
 8004b0a:	4649      	mov	r1, r9
 8004b0c:	f7fb fd28 	bl	8000560 <__aeabi_dmul>
 8004b10:	4602      	mov	r2, r0
 8004b12:	460b      	mov	r3, r1
 8004b14:	4620      	mov	r0, r4
 8004b16:	4629      	mov	r1, r5
 8004b18:	f7fb fb6a 	bl	80001f0 <__aeabi_dsub>
 8004b1c:	4632      	mov	r2, r6
 8004b1e:	4604      	mov	r4, r0
 8004b20:	460d      	mov	r5, r1
 8004b22:	464b      	mov	r3, r9
 8004b24:	4640      	mov	r0, r8
 8004b26:	4649      	mov	r1, r9
 8004b28:	f7fb fb64 	bl	80001f4 <__adddf3>
 8004b2c:	4602      	mov	r2, r0
 8004b2e:	460b      	mov	r3, r1
 8004b30:	4620      	mov	r0, r4
 8004b32:	4629      	mov	r1, r5
 8004b34:	f7fb fe3e 	bl	80007b4 <__aeabi_ddiv>
 8004b38:	4602      	mov	r2, r0
 8004b3a:	460b      	mov	r3, r1
 8004b3c:	4650      	mov	r0, sl
 8004b3e:	4659      	mov	r1, fp
 8004b40:	f7fb fb58 	bl	80001f4 <__adddf3>
 8004b44:	4632      	mov	r2, r6
 8004b46:	464b      	mov	r3, r9
 8004b48:	f7fb fb54 	bl	80001f4 <__adddf3>
 8004b4c:	4602      	mov	r2, r0
 8004b4e:	460b      	mov	r3, r1
 8004b50:	f7fb fb50 	bl	80001f4 <__adddf3>
 8004b54:	e5f1      	b.n	800473a <__ieee754_acos+0x2a>
 8004b56:	2000      	movs	r0, #0
 8004b58:	2100      	movs	r1, #0
 8004b5a:	e5ee      	b.n	800473a <__ieee754_acos+0x2a>
 8004b5c:	a116      	add	r1, pc, #88	; (adr r1, 8004bb8 <__ieee754_acos+0x4a8>)
 8004b5e:	e9d1 0100 	ldrd	r0, r1, [r1]
 8004b62:	e5ea      	b.n	800473a <__ieee754_acos+0x2a>
 8004b64:	f3af 8000 	nop.w
 8004b68:	0dfdf709 	.word	0x0dfdf709
 8004b6c:	3f023de1 	.word	0x3f023de1
 8004b70:	7501b288 	.word	0x7501b288
 8004b74:	3f49efe0 	.word	0x3f49efe0
 8004b78:	b5688f3b 	.word	0xb5688f3b
 8004b7c:	3fa48228 	.word	0x3fa48228
 8004b80:	0e884455 	.word	0x0e884455
 8004b84:	3fc9c155 	.word	0x3fc9c155
 8004b88:	03eb6f7d 	.word	0x03eb6f7d
 8004b8c:	3fd4d612 	.word	0x3fd4d612
 8004b90:	55555555 	.word	0x55555555
 8004b94:	3fc55555 	.word	0x3fc55555
 8004b98:	b12e9282 	.word	0xb12e9282
 8004b9c:	3fb3b8c5 	.word	0x3fb3b8c5
 8004ba0:	1b8d0159 	.word	0x1b8d0159
 8004ba4:	3fe6066c 	.word	0x3fe6066c
 8004ba8:	9c598ac8 	.word	0x9c598ac8
 8004bac:	40002ae5 	.word	0x40002ae5
 8004bb0:	1c8a2d4b 	.word	0x1c8a2d4b
 8004bb4:	40033a27 	.word	0x40033a27
 8004bb8:	54442d18 	.word	0x54442d18
 8004bbc:	3ff921fb 	.word	0x3ff921fb
 8004bc0:	3ff00000 	.word	0x3ff00000
 8004bc4:	3fe00000 	.word	0x3fe00000

08004bc8 <__ieee754_rem_pio2>:
 8004bc8:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8004bcc:	ec57 6b10 	vmov	r6, r7, d0
 8004bd0:	4bc3      	ldr	r3, [pc, #780]	; (8004ee0 <__ieee754_rem_pio2+0x318>)
 8004bd2:	b08d      	sub	sp, #52	; 0x34
 8004bd4:	f027 4800 	bic.w	r8, r7, #2147483648	; 0x80000000
 8004bd8:	4598      	cmp	r8, r3
 8004bda:	4604      	mov	r4, r0
 8004bdc:	9704      	str	r7, [sp, #16]
 8004bde:	dc07      	bgt.n	8004bf0 <__ieee754_rem_pio2+0x28>
 8004be0:	2200      	movs	r2, #0
 8004be2:	2300      	movs	r3, #0
 8004be4:	ed84 0b00 	vstr	d0, [r4]
 8004be8:	e9c0 2302 	strd	r2, r3, [r0, #8]
 8004bec:	2500      	movs	r5, #0
 8004bee:	e027      	b.n	8004c40 <__ieee754_rem_pio2+0x78>
 8004bf0:	4bbc      	ldr	r3, [pc, #752]	; (8004ee4 <__ieee754_rem_pio2+0x31c>)
 8004bf2:	4598      	cmp	r8, r3
 8004bf4:	dc75      	bgt.n	8004ce2 <__ieee754_rem_pio2+0x11a>
 8004bf6:	9b04      	ldr	r3, [sp, #16]
 8004bf8:	4dbb      	ldr	r5, [pc, #748]	; (8004ee8 <__ieee754_rem_pio2+0x320>)
 8004bfa:	2b00      	cmp	r3, #0
 8004bfc:	ee10 0a10 	vmov	r0, s0
 8004c00:	a3a9      	add	r3, pc, #676	; (adr r3, 8004ea8 <__ieee754_rem_pio2+0x2e0>)
 8004c02:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c06:	4639      	mov	r1, r7
 8004c08:	dd36      	ble.n	8004c78 <__ieee754_rem_pio2+0xb0>
 8004c0a:	f7fb faf1 	bl	80001f0 <__aeabi_dsub>
 8004c0e:	45a8      	cmp	r8, r5
 8004c10:	4606      	mov	r6, r0
 8004c12:	460f      	mov	r7, r1
 8004c14:	d018      	beq.n	8004c48 <__ieee754_rem_pio2+0x80>
 8004c16:	a3a6      	add	r3, pc, #664	; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>)
 8004c18:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c1c:	f7fb fae8 	bl	80001f0 <__aeabi_dsub>
 8004c20:	4602      	mov	r2, r0
 8004c22:	460b      	mov	r3, r1
 8004c24:	e9c4 2300 	strd	r2, r3, [r4]
 8004c28:	4630      	mov	r0, r6
 8004c2a:	4639      	mov	r1, r7
 8004c2c:	f7fb fae0 	bl	80001f0 <__aeabi_dsub>
 8004c30:	a39f      	add	r3, pc, #636	; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>)
 8004c32:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c36:	f7fb fadb 	bl	80001f0 <__aeabi_dsub>
 8004c3a:	e9c4 0102 	strd	r0, r1, [r4, #8]
 8004c3e:	2501      	movs	r5, #1
 8004c40:	4628      	mov	r0, r5
 8004c42:	b00d      	add	sp, #52	; 0x34
 8004c44:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8004c48:	a39b      	add	r3, pc, #620	; (adr r3, 8004eb8 <__ieee754_rem_pio2+0x2f0>)
 8004c4a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c4e:	f7fb facf 	bl	80001f0 <__aeabi_dsub>
 8004c52:	a39b      	add	r3, pc, #620	; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>)
 8004c54:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c58:	4606      	mov	r6, r0
 8004c5a:	460f      	mov	r7, r1
 8004c5c:	f7fb fac8 	bl	80001f0 <__aeabi_dsub>
 8004c60:	4602      	mov	r2, r0
 8004c62:	460b      	mov	r3, r1
 8004c64:	e9c4 2300 	strd	r2, r3, [r4]
 8004c68:	4630      	mov	r0, r6
 8004c6a:	4639      	mov	r1, r7
 8004c6c:	f7fb fac0 	bl	80001f0 <__aeabi_dsub>
 8004c70:	a393      	add	r3, pc, #588	; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>)
 8004c72:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c76:	e7de      	b.n	8004c36 <__ieee754_rem_pio2+0x6e>
 8004c78:	f7fb fabc 	bl	80001f4 <__adddf3>
 8004c7c:	45a8      	cmp	r8, r5
 8004c7e:	4606      	mov	r6, r0
 8004c80:	460f      	mov	r7, r1
 8004c82:	d016      	beq.n	8004cb2 <__ieee754_rem_pio2+0xea>
 8004c84:	a38a      	add	r3, pc, #552	; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>)
 8004c86:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004c8a:	f7fb fab3 	bl	80001f4 <__adddf3>
 8004c8e:	4602      	mov	r2, r0
 8004c90:	460b      	mov	r3, r1
 8004c92:	e9c4 2300 	strd	r2, r3, [r4]
 8004c96:	4630      	mov	r0, r6
 8004c98:	4639      	mov	r1, r7
 8004c9a:	f7fb faa9 	bl	80001f0 <__aeabi_dsub>
 8004c9e:	a384      	add	r3, pc, #528	; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>)
 8004ca0:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004ca4:	f7fb faa6 	bl	80001f4 <__adddf3>
 8004ca8:	f04f 35ff 	mov.w	r5, #4294967295
 8004cac:	e9c4 0102 	strd	r0, r1, [r4, #8]
 8004cb0:	e7c6      	b.n	8004c40 <__ieee754_rem_pio2+0x78>
 8004cb2:	a381      	add	r3, pc, #516	; (adr r3, 8004eb8 <__ieee754_rem_pio2+0x2f0>)
 8004cb4:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004cb8:	f7fb fa9c 	bl	80001f4 <__adddf3>
 8004cbc:	a380      	add	r3, pc, #512	; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>)
 8004cbe:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004cc2:	4606      	mov	r6, r0
 8004cc4:	460f      	mov	r7, r1
 8004cc6:	f7fb fa95 	bl	80001f4 <__adddf3>
 8004cca:	4602      	mov	r2, r0
 8004ccc:	460b      	mov	r3, r1
 8004cce:	e9c4 2300 	strd	r2, r3, [r4]
 8004cd2:	4630      	mov	r0, r6
 8004cd4:	4639      	mov	r1, r7
 8004cd6:	f7fb fa8b 	bl	80001f0 <__aeabi_dsub>
 8004cda:	a379      	add	r3, pc, #484	; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>)
 8004cdc:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004ce0:	e7e0      	b.n	8004ca4 <__ieee754_rem_pio2+0xdc>
 8004ce2:	4b82      	ldr	r3, [pc, #520]	; (8004eec <__ieee754_rem_pio2+0x324>)
 8004ce4:	4598      	cmp	r8, r3
 8004ce6:	f300 80d0 	bgt.w	8004e8a <__ieee754_rem_pio2+0x2c2>
 8004cea:	f001 f8a1 	bl	8005e30 <fabs>
 8004cee:	ec57 6b10 	vmov	r6, r7, d0
 8004cf2:	ee10 0a10 	vmov	r0, s0
 8004cf6:	a374      	add	r3, pc, #464	; (adr r3, 8004ec8 <__ieee754_rem_pio2+0x300>)
 8004cf8:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004cfc:	4639      	mov	r1, r7
 8004cfe:	f7fb fc2f 	bl	8000560 <__aeabi_dmul>
 8004d02:	2200      	movs	r2, #0
 8004d04:	4b7a      	ldr	r3, [pc, #488]	; (8004ef0 <__ieee754_rem_pio2+0x328>)
 8004d06:	f7fb fa75 	bl	80001f4 <__adddf3>
 8004d0a:	f7fb fed9 	bl	8000ac0 <__aeabi_d2iz>
 8004d0e:	4605      	mov	r5, r0
 8004d10:	f7fb fbbc 	bl	800048c <__aeabi_i2d>
 8004d14:	a364      	add	r3, pc, #400	; (adr r3, 8004ea8 <__ieee754_rem_pio2+0x2e0>)
 8004d16:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004d1a:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8004d1e:	f7fb fc1f 	bl	8000560 <__aeabi_dmul>
 8004d22:	4602      	mov	r2, r0
 8004d24:	460b      	mov	r3, r1
 8004d26:	4630      	mov	r0, r6
 8004d28:	4639      	mov	r1, r7
 8004d2a:	f7fb fa61 	bl	80001f0 <__aeabi_dsub>
 8004d2e:	a360      	add	r3, pc, #384	; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>)
 8004d30:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004d34:	4682      	mov	sl, r0
 8004d36:	468b      	mov	fp, r1
 8004d38:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8004d3c:	f7fb fc10 	bl	8000560 <__aeabi_dmul>
 8004d40:	2d1f      	cmp	r5, #31
 8004d42:	4606      	mov	r6, r0
 8004d44:	460f      	mov	r7, r1
 8004d46:	dc0c      	bgt.n	8004d62 <__ieee754_rem_pio2+0x19a>
 8004d48:	1e6a      	subs	r2, r5, #1
 8004d4a:	4b6a      	ldr	r3, [pc, #424]	; (8004ef4 <__ieee754_rem_pio2+0x32c>)
 8004d4c:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8004d50:	4543      	cmp	r3, r8
 8004d52:	d006      	beq.n	8004d62 <__ieee754_rem_pio2+0x19a>
 8004d54:	4632      	mov	r2, r6
 8004d56:	463b      	mov	r3, r7
 8004d58:	4650      	mov	r0, sl
 8004d5a:	4659      	mov	r1, fp
 8004d5c:	f7fb fa48 	bl	80001f0 <__aeabi_dsub>
 8004d60:	e00e      	b.n	8004d80 <__ieee754_rem_pio2+0x1b8>
 8004d62:	4632      	mov	r2, r6
 8004d64:	463b      	mov	r3, r7
 8004d66:	4650      	mov	r0, sl
 8004d68:	4659      	mov	r1, fp
 8004d6a:	f7fb fa41 	bl	80001f0 <__aeabi_dsub>
 8004d6e:	ea4f 5328 	mov.w	r3, r8, asr #20
 8004d72:	9305      	str	r3, [sp, #20]
 8004d74:	9a05      	ldr	r2, [sp, #20]
 8004d76:	f3c1 530a 	ubfx	r3, r1, #20, #11
 8004d7a:	1ad3      	subs	r3, r2, r3
 8004d7c:	2b10      	cmp	r3, #16
 8004d7e:	dc02      	bgt.n	8004d86 <__ieee754_rem_pio2+0x1be>
 8004d80:	e9c4 0100 	strd	r0, r1, [r4]
 8004d84:	e039      	b.n	8004dfa <__ieee754_rem_pio2+0x232>
 8004d86:	a34c      	add	r3, pc, #304	; (adr r3, 8004eb8 <__ieee754_rem_pio2+0x2f0>)
 8004d88:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004d8c:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8004d90:	f7fb fbe6 	bl	8000560 <__aeabi_dmul>
 8004d94:	4606      	mov	r6, r0
 8004d96:	460f      	mov	r7, r1
 8004d98:	4602      	mov	r2, r0
 8004d9a:	460b      	mov	r3, r1
 8004d9c:	4650      	mov	r0, sl
 8004d9e:	4659      	mov	r1, fp
 8004da0:	f7fb fa26 	bl	80001f0 <__aeabi_dsub>
 8004da4:	4602      	mov	r2, r0
 8004da6:	460b      	mov	r3, r1
 8004da8:	4680      	mov	r8, r0
 8004daa:	4689      	mov	r9, r1
 8004dac:	4650      	mov	r0, sl
 8004dae:	4659      	mov	r1, fp
 8004db0:	f7fb fa1e 	bl	80001f0 <__aeabi_dsub>
 8004db4:	4632      	mov	r2, r6
 8004db6:	463b      	mov	r3, r7
 8004db8:	f7fb fa1a 	bl	80001f0 <__aeabi_dsub>
 8004dbc:	a340      	add	r3, pc, #256	; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>)
 8004dbe:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004dc2:	4606      	mov	r6, r0
 8004dc4:	460f      	mov	r7, r1
 8004dc6:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8004dca:	f7fb fbc9 	bl	8000560 <__aeabi_dmul>
 8004dce:	4632      	mov	r2, r6
 8004dd0:	463b      	mov	r3, r7
 8004dd2:	f7fb fa0d 	bl	80001f0 <__aeabi_dsub>
 8004dd6:	4602      	mov	r2, r0
 8004dd8:	460b      	mov	r3, r1
 8004dda:	4606      	mov	r6, r0
 8004ddc:	460f      	mov	r7, r1
 8004dde:	4640      	mov	r0, r8
 8004de0:	4649      	mov	r1, r9
 8004de2:	f7fb fa05 	bl	80001f0 <__aeabi_dsub>
 8004de6:	9a05      	ldr	r2, [sp, #20]
 8004de8:	f3c1 530a 	ubfx	r3, r1, #20, #11
 8004dec:	1ad3      	subs	r3, r2, r3
 8004dee:	2b31      	cmp	r3, #49	; 0x31
 8004df0:	dc20      	bgt.n	8004e34 <__ieee754_rem_pio2+0x26c>
 8004df2:	e9c4 0100 	strd	r0, r1, [r4]
 8004df6:	46c2      	mov	sl, r8
 8004df8:	46cb      	mov	fp, r9
 8004dfa:	e9d4 8900 	ldrd	r8, r9, [r4]
 8004dfe:	4650      	mov	r0, sl
 8004e00:	4642      	mov	r2, r8
 8004e02:	464b      	mov	r3, r9
 8004e04:	4659      	mov	r1, fp
 8004e06:	f7fb f9f3 	bl	80001f0 <__aeabi_dsub>
 8004e0a:	463b      	mov	r3, r7
 8004e0c:	4632      	mov	r2, r6
 8004e0e:	f7fb f9ef 	bl	80001f0 <__aeabi_dsub>
 8004e12:	9b04      	ldr	r3, [sp, #16]
 8004e14:	2b00      	cmp	r3, #0
 8004e16:	e9c4 0102 	strd	r0, r1, [r4, #8]
 8004e1a:	f6bf af11 	bge.w	8004c40 <__ieee754_rem_pio2+0x78>
 8004e1e:	f109 4300 	add.w	r3, r9, #2147483648	; 0x80000000
 8004e22:	6063      	str	r3, [r4, #4]
 8004e24:	f8c4 8000 	str.w	r8, [r4]
 8004e28:	60a0      	str	r0, [r4, #8]
 8004e2a:	f101 4300 	add.w	r3, r1, #2147483648	; 0x80000000
 8004e2e:	60e3      	str	r3, [r4, #12]
 8004e30:	426d      	negs	r5, r5
 8004e32:	e705      	b.n	8004c40 <__ieee754_rem_pio2+0x78>
 8004e34:	a326      	add	r3, pc, #152	; (adr r3, 8004ed0 <__ieee754_rem_pio2+0x308>)
 8004e36:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004e3a:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8004e3e:	f7fb fb8f 	bl	8000560 <__aeabi_dmul>
 8004e42:	4606      	mov	r6, r0
 8004e44:	460f      	mov	r7, r1
 8004e46:	4602      	mov	r2, r0
 8004e48:	460b      	mov	r3, r1
 8004e4a:	4640      	mov	r0, r8
 8004e4c:	4649      	mov	r1, r9
 8004e4e:	f7fb f9cf 	bl	80001f0 <__aeabi_dsub>
 8004e52:	4602      	mov	r2, r0
 8004e54:	460b      	mov	r3, r1
 8004e56:	4682      	mov	sl, r0
 8004e58:	468b      	mov	fp, r1
 8004e5a:	4640      	mov	r0, r8
 8004e5c:	4649      	mov	r1, r9
 8004e5e:	f7fb f9c7 	bl	80001f0 <__aeabi_dsub>
 8004e62:	4632      	mov	r2, r6
 8004e64:	463b      	mov	r3, r7
 8004e66:	f7fb f9c3 	bl	80001f0 <__aeabi_dsub>
 8004e6a:	a31b      	add	r3, pc, #108	; (adr r3, 8004ed8 <__ieee754_rem_pio2+0x310>)
 8004e6c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8004e70:	4606      	mov	r6, r0
 8004e72:	460f      	mov	r7, r1
 8004e74:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8004e78:	f7fb fb72 	bl	8000560 <__aeabi_dmul>
 8004e7c:	4632      	mov	r2, r6
 8004e7e:	463b      	mov	r3, r7
 8004e80:	f7fb f9b6 	bl	80001f0 <__aeabi_dsub>
 8004e84:	4606      	mov	r6, r0
 8004e86:	460f      	mov	r7, r1
 8004e88:	e764      	b.n	8004d54 <__ieee754_rem_pio2+0x18c>
 8004e8a:	4b1b      	ldr	r3, [pc, #108]	; (8004ef8 <__ieee754_rem_pio2+0x330>)
 8004e8c:	4598      	cmp	r8, r3
 8004e8e:	dd35      	ble.n	8004efc <__ieee754_rem_pio2+0x334>
 8004e90:	ee10 2a10 	vmov	r2, s0
 8004e94:	463b      	mov	r3, r7
 8004e96:	4630      	mov	r0, r6
 8004e98:	4639      	mov	r1, r7
 8004e9a:	f7fb f9a9 	bl	80001f0 <__aeabi_dsub>
 8004e9e:	e9c4 0102 	strd	r0, r1, [r4, #8]
 8004ea2:	e9c4 0100 	strd	r0, r1, [r4]
 8004ea6:	e6a1      	b.n	8004bec <__ieee754_rem_pio2+0x24>
 8004ea8:	54400000 	.word	0x54400000
 8004eac:	3ff921fb 	.word	0x3ff921fb
 8004eb0:	1a626331 	.word	0x1a626331
 8004eb4:	3dd0b461 	.word	0x3dd0b461
 8004eb8:	1a600000 	.word	0x1a600000
 8004ebc:	3dd0b461 	.word	0x3dd0b461
 8004ec0:	2e037073 	.word	0x2e037073
 8004ec4:	3ba3198a 	.word	0x3ba3198a
 8004ec8:	6dc9c883 	.word	0x6dc9c883
 8004ecc:	3fe45f30 	.word	0x3fe45f30
 8004ed0:	2e000000 	.word	0x2e000000
 8004ed4:	3ba3198a 	.word	0x3ba3198a
 8004ed8:	252049c1 	.word	0x252049c1
 8004edc:	397b839a 	.word	0x397b839a
 8004ee0:	3fe921fb 	.word	0x3fe921fb
 8004ee4:	4002d97b 	.word	0x4002d97b
 8004ee8:	3ff921fb 	.word	0x3ff921fb
 8004eec:	413921fb 	.word	0x413921fb
 8004ef0:	3fe00000 	.word	0x3fe00000
 8004ef4:	08006038 	.word	0x08006038
 8004ef8:	7fefffff 	.word	0x7fefffff
 8004efc:	ea4f 5528 	mov.w	r5, r8, asr #20
 8004f00:	f2a5 4516 	subw	r5, r5, #1046	; 0x416
 8004f04:	eba8 5105 	sub.w	r1, r8, r5, lsl #20
 8004f08:	4630      	mov	r0, r6
 8004f0a:	460f      	mov	r7, r1
 8004f0c:	f7fb fdd8 	bl	8000ac0 <__aeabi_d2iz>
 8004f10:	f7fb fabc 	bl	800048c <__aeabi_i2d>
 8004f14:	4602      	mov	r2, r0
 8004f16:	460b      	mov	r3, r1
 8004f18:	4630      	mov	r0, r6
 8004f1a:	4639      	mov	r1, r7
 8004f1c:	e9cd 2306 	strd	r2, r3, [sp, #24]
 8004f20:	f7fb f966 	bl	80001f0 <__aeabi_dsub>
 8004f24:	2200      	movs	r2, #0
 8004f26:	4b1f      	ldr	r3, [pc, #124]	; (8004fa4 <__ieee754_rem_pio2+0x3dc>)
 8004f28:	f7fb fb1a 	bl	8000560 <__aeabi_dmul>
 8004f2c:	460f      	mov	r7, r1
 8004f2e:	4606      	mov	r6, r0
 8004f30:	f7fb fdc6 	bl	8000ac0 <__aeabi_d2iz>
 8004f34:	f7fb faaa 	bl	800048c <__aeabi_i2d>
 8004f38:	4602      	mov	r2, r0
 8004f3a:	460b      	mov	r3, r1
 8004f3c:	4630      	mov	r0, r6
 8004f3e:	4639      	mov	r1, r7
 8004f40:	e9cd 2308 	strd	r2, r3, [sp, #32]
 8004f44:	f7fb f954 	bl	80001f0 <__aeabi_dsub>
 8004f48:	2200      	movs	r2, #0
 8004f4a:	4b16      	ldr	r3, [pc, #88]	; (8004fa4 <__ieee754_rem_pio2+0x3dc>)
 8004f4c:	f7fb fb08 	bl	8000560 <__aeabi_dmul>
 8004f50:	e9cd 010a 	strd	r0, r1, [sp, #40]	; 0x28
 8004f54:	f10d 0930 	add.w	r9, sp, #48	; 0x30
 8004f58:	f04f 0803 	mov.w	r8, #3
 8004f5c:	2600      	movs	r6, #0
 8004f5e:	2700      	movs	r7, #0
 8004f60:	4632      	mov	r2, r6
 8004f62:	463b      	mov	r3, r7
 8004f64:	e979 0102 	ldrd	r0, r1, [r9, #-8]!
 8004f68:	f108 3aff 	add.w	sl, r8, #4294967295
 8004f6c:	f7fb fd60 	bl	8000a30 <__aeabi_dcmpeq>
 8004f70:	b9b0      	cbnz	r0, 8004fa0 <__ieee754_rem_pio2+0x3d8>
 8004f72:	4b0d      	ldr	r3, [pc, #52]	; (8004fa8 <__ieee754_rem_pio2+0x3e0>)
 8004f74:	9301      	str	r3, [sp, #4]
 8004f76:	2302      	movs	r3, #2
 8004f78:	9300      	str	r3, [sp, #0]
 8004f7a:	462a      	mov	r2, r5
 8004f7c:	4643      	mov	r3, r8
 8004f7e:	4621      	mov	r1, r4
 8004f80:	a806      	add	r0, sp, #24
 8004f82:	f000 f98d 	bl	80052a0 <__kernel_rem_pio2>
 8004f86:	9b04      	ldr	r3, [sp, #16]
 8004f88:	2b00      	cmp	r3, #0
 8004f8a:	4605      	mov	r5, r0
 8004f8c:	f6bf ae58 	bge.w	8004c40 <__ieee754_rem_pio2+0x78>
 8004f90:	6863      	ldr	r3, [r4, #4]
 8004f92:	f103 4300 	add.w	r3, r3, #2147483648	; 0x80000000
 8004f96:	6063      	str	r3, [r4, #4]
 8004f98:	68e3      	ldr	r3, [r4, #12]
 8004f9a:	f103 4300 	add.w	r3, r3, #2147483648	; 0x80000000
 8004f9e:	e746      	b.n	8004e2e <__ieee754_rem_pio2+0x266>
 8004fa0:	46d0      	mov	r8, sl
 8004fa2:	e7dd      	b.n	8004f60 <__ieee754_rem_pio2+0x398>
 8004fa4:	41700000 	.word	0x41700000
 8004fa8:	080060b8 	.word	0x080060b8

08004fac <__ieee754_sqrt>:
 8004fac:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
 8004fb0:	4955      	ldr	r1, [pc, #340]	; (8005108 <__ieee754_sqrt+0x15c>)
 8004fb2:	ec55 4b10 	vmov	r4, r5, d0
 8004fb6:	43a9      	bics	r1, r5
 8004fb8:	462b      	mov	r3, r5
 8004fba:	462a      	mov	r2, r5
 8004fbc:	d112      	bne.n	8004fe4 <__ieee754_sqrt+0x38>
 8004fbe:	ee10 2a10 	vmov	r2, s0
 8004fc2:	ee10 0a10 	vmov	r0, s0
 8004fc6:	4629      	mov	r1, r5
 8004fc8:	f7fb faca 	bl	8000560 <__aeabi_dmul>
 8004fcc:	4602      	mov	r2, r0
 8004fce:	460b      	mov	r3, r1
 8004fd0:	4620      	mov	r0, r4
 8004fd2:	4629      	mov	r1, r5
 8004fd4:	f7fb f90e 	bl	80001f4 <__adddf3>
 8004fd8:	4604      	mov	r4, r0
 8004fda:	460d      	mov	r5, r1
 8004fdc:	ec45 4b10 	vmov	d0, r4, r5
 8004fe0:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
 8004fe4:	2d00      	cmp	r5, #0
 8004fe6:	ee10 0a10 	vmov	r0, s0
 8004fea:	4621      	mov	r1, r4
 8004fec:	dc0f      	bgt.n	800500e <__ieee754_sqrt+0x62>
 8004fee:	f025 4600 	bic.w	r6, r5, #2147483648	; 0x80000000
 8004ff2:	4330      	orrs	r0, r6
 8004ff4:	d0f2      	beq.n	8004fdc <__ieee754_sqrt+0x30>
 8004ff6:	b155      	cbz	r5, 800500e <__ieee754_sqrt+0x62>
 8004ff8:	ee10 2a10 	vmov	r2, s0
 8004ffc:	4620      	mov	r0, r4
 8004ffe:	4629      	mov	r1, r5
 8005000:	f7fb f8f6 	bl	80001f0 <__aeabi_dsub>
 8005004:	4602      	mov	r2, r0
 8005006:	460b      	mov	r3, r1
 8005008:	f7fb fbd4 	bl	80007b4 <__aeabi_ddiv>
 800500c:	e7e4      	b.n	8004fd8 <__ieee754_sqrt+0x2c>
 800500e:	151b      	asrs	r3, r3, #20
 8005010:	d073      	beq.n	80050fa <__ieee754_sqrt+0x14e>
 8005012:	f2a3 33ff 	subw	r3, r3, #1023	; 0x3ff
 8005016:	07dd      	lsls	r5, r3, #31
 8005018:	f3c2 0213 	ubfx	r2, r2, #0, #20
 800501c:	bf48      	it	mi
 800501e:	0fc8      	lsrmi	r0, r1, #31
 8005020:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
 8005024:	bf44      	itt	mi
 8005026:	0049      	lslmi	r1, r1, #1
 8005028:	eb00 0242 	addmi.w	r2, r0, r2, lsl #1
 800502c:	2500      	movs	r5, #0
 800502e:	1058      	asrs	r0, r3, #1
 8005030:	0fcb      	lsrs	r3, r1, #31
 8005032:	eb03 0242 	add.w	r2, r3, r2, lsl #1
 8005036:	0049      	lsls	r1, r1, #1
 8005038:	2316      	movs	r3, #22
 800503a:	462c      	mov	r4, r5
 800503c:	f44f 1600 	mov.w	r6, #2097152	; 0x200000
 8005040:	19a7      	adds	r7, r4, r6
 8005042:	4297      	cmp	r7, r2
 8005044:	bfde      	ittt	le
 8005046:	19bc      	addle	r4, r7, r6
 8005048:	1bd2      	suble	r2, r2, r7
 800504a:	19ad      	addle	r5, r5, r6
 800504c:	0fcf      	lsrs	r7, r1, #31
 800504e:	3b01      	subs	r3, #1
 8005050:	eb07 0242 	add.w	r2, r7, r2, lsl #1
 8005054:	ea4f 0141 	mov.w	r1, r1, lsl #1
 8005058:	ea4f 0656 	mov.w	r6, r6, lsr #1
 800505c:	d1f0      	bne.n	8005040 <__ieee754_sqrt+0x94>
 800505e:	f04f 0c20 	mov.w	ip, #32
 8005062:	469e      	mov	lr, r3
 8005064:	f04f 4600 	mov.w	r6, #2147483648	; 0x80000000
 8005068:	42a2      	cmp	r2, r4
 800506a:	eb06 070e 	add.w	r7, r6, lr
 800506e:	dc02      	bgt.n	8005076 <__ieee754_sqrt+0xca>
 8005070:	d112      	bne.n	8005098 <__ieee754_sqrt+0xec>
 8005072:	428f      	cmp	r7, r1
 8005074:	d810      	bhi.n	8005098 <__ieee754_sqrt+0xec>
 8005076:	2f00      	cmp	r7, #0
 8005078:	eb07 0e06 	add.w	lr, r7, r6
 800507c:	da42      	bge.n	8005104 <__ieee754_sqrt+0x158>
 800507e:	f1be 0f00 	cmp.w	lr, #0
 8005082:	db3f      	blt.n	8005104 <__ieee754_sqrt+0x158>
 8005084:	f104 0801 	add.w	r8, r4, #1
 8005088:	1b12      	subs	r2, r2, r4
 800508a:	428f      	cmp	r7, r1
 800508c:	bf88      	it	hi
 800508e:	f102 32ff 	addhi.w	r2, r2, #4294967295
 8005092:	1bc9      	subs	r1, r1, r7
 8005094:	4433      	add	r3, r6
 8005096:	4644      	mov	r4, r8
 8005098:	0052      	lsls	r2, r2, #1
 800509a:	f1bc 0c01 	subs.w	ip, ip, #1
 800509e:	eb02 72d1 	add.w	r2, r2, r1, lsr #31
 80050a2:	ea4f 0656 	mov.w	r6, r6, lsr #1
 80050a6:	ea4f 0141 	mov.w	r1, r1, lsl #1
 80050aa:	d1dd      	bne.n	8005068 <__ieee754_sqrt+0xbc>
 80050ac:	430a      	orrs	r2, r1
 80050ae:	d006      	beq.n	80050be <__ieee754_sqrt+0x112>
 80050b0:	1c5c      	adds	r4, r3, #1
 80050b2:	bf13      	iteet	ne
 80050b4:	3301      	addne	r3, #1
 80050b6:	3501      	addeq	r5, #1
 80050b8:	4663      	moveq	r3, ip
 80050ba:	f023 0301 	bicne.w	r3, r3, #1
 80050be:	106a      	asrs	r2, r5, #1
 80050c0:	085b      	lsrs	r3, r3, #1
 80050c2:	07e9      	lsls	r1, r5, #31
 80050c4:	f102 527f 	add.w	r2, r2, #1069547520	; 0x3fc00000
 80050c8:	f502 1200 	add.w	r2, r2, #2097152	; 0x200000
 80050cc:	bf48      	it	mi
 80050ce:	f043 4300 	orrmi.w	r3, r3, #2147483648	; 0x80000000
 80050d2:	eb02 5500 	add.w	r5, r2, r0, lsl #20
 80050d6:	461c      	mov	r4, r3
 80050d8:	e780      	b.n	8004fdc <__ieee754_sqrt+0x30>
 80050da:	0aca      	lsrs	r2, r1, #11
 80050dc:	3815      	subs	r0, #21
 80050de:	0549      	lsls	r1, r1, #21
 80050e0:	2a00      	cmp	r2, #0
 80050e2:	d0fa      	beq.n	80050da <__ieee754_sqrt+0x12e>
 80050e4:	02d6      	lsls	r6, r2, #11
 80050e6:	d50a      	bpl.n	80050fe <__ieee754_sqrt+0x152>
 80050e8:	f1c3 0420 	rsb	r4, r3, #32
 80050ec:	fa21 f404 	lsr.w	r4, r1, r4
 80050f0:	1e5d      	subs	r5, r3, #1
 80050f2:	4099      	lsls	r1, r3
 80050f4:	4322      	orrs	r2, r4
 80050f6:	1b43      	subs	r3, r0, r5
 80050f8:	e78b      	b.n	8005012 <__ieee754_sqrt+0x66>
 80050fa:	4618      	mov	r0, r3
 80050fc:	e7f0      	b.n	80050e0 <__ieee754_sqrt+0x134>
 80050fe:	0052      	lsls	r2, r2, #1
 8005100:	3301      	adds	r3, #1
 8005102:	e7ef      	b.n	80050e4 <__ieee754_sqrt+0x138>
 8005104:	46a0      	mov	r8, r4
 8005106:	e7bf      	b.n	8005088 <__ieee754_sqrt+0xdc>
 8005108:	7ff00000 	.word	0x7ff00000
 800510c:	00000000 	.word	0x00000000

08005110 <__kernel_cos>:
 8005110:	e92d 4ff8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8005114:	ec59 8b10 	vmov	r8, r9, d0
 8005118:	f029 4600 	bic.w	r6, r9, #2147483648	; 0x80000000
 800511c:	f1b6 5f79 	cmp.w	r6, #1044381696	; 0x3e400000
 8005120:	ed2d 8b02 	vpush	{d8}
 8005124:	eeb0 8a41 	vmov.f32	s16, s2
 8005128:	eef0 8a61 	vmov.f32	s17, s3
 800512c:	da07      	bge.n	800513e <__kernel_cos+0x2e>
 800512e:	ee10 0a10 	vmov	r0, s0
 8005132:	4649      	mov	r1, r9
 8005134:	f7fb fcc4 	bl	8000ac0 <__aeabi_d2iz>
 8005138:	2800      	cmp	r0, #0
 800513a:	f000 8089 	beq.w	8005250 <__kernel_cos+0x140>
 800513e:	4642      	mov	r2, r8
 8005140:	464b      	mov	r3, r9
 8005142:	4640      	mov	r0, r8
 8005144:	4649      	mov	r1, r9
 8005146:	f7fb fa0b 	bl	8000560 <__aeabi_dmul>
 800514a:	2200      	movs	r2, #0
 800514c:	4b4e      	ldr	r3, [pc, #312]	; (8005288 <__kernel_cos+0x178>)
 800514e:	4604      	mov	r4, r0
 8005150:	460d      	mov	r5, r1
 8005152:	f7fb fa05 	bl	8000560 <__aeabi_dmul>
 8005156:	a340      	add	r3, pc, #256	; (adr r3, 8005258 <__kernel_cos+0x148>)
 8005158:	e9d3 2300 	ldrd	r2, r3, [r3]
 800515c:	4682      	mov	sl, r0
 800515e:	468b      	mov	fp, r1
 8005160:	4620      	mov	r0, r4
 8005162:	4629      	mov	r1, r5
 8005164:	f7fb f9fc 	bl	8000560 <__aeabi_dmul>
 8005168:	a33d      	add	r3, pc, #244	; (adr r3, 8005260 <__kernel_cos+0x150>)
 800516a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800516e:	f7fb f841 	bl	80001f4 <__adddf3>
 8005172:	4622      	mov	r2, r4
 8005174:	462b      	mov	r3, r5
 8005176:	f7fb f9f3 	bl	8000560 <__aeabi_dmul>
 800517a:	a33b      	add	r3, pc, #236	; (adr r3, 8005268 <__kernel_cos+0x158>)
 800517c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005180:	f7fb f836 	bl	80001f0 <__aeabi_dsub>
 8005184:	4622      	mov	r2, r4
 8005186:	462b      	mov	r3, r5
 8005188:	f7fb f9ea 	bl	8000560 <__aeabi_dmul>
 800518c:	a338      	add	r3, pc, #224	; (adr r3, 8005270 <__kernel_cos+0x160>)
 800518e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005192:	f7fb f82f 	bl	80001f4 <__adddf3>
 8005196:	4622      	mov	r2, r4
 8005198:	462b      	mov	r3, r5
 800519a:	f7fb f9e1 	bl	8000560 <__aeabi_dmul>
 800519e:	a336      	add	r3, pc, #216	; (adr r3, 8005278 <__kernel_cos+0x168>)
 80051a0:	e9d3 2300 	ldrd	r2, r3, [r3]
 80051a4:	f7fb f824 	bl	80001f0 <__aeabi_dsub>
 80051a8:	4622      	mov	r2, r4
 80051aa:	462b      	mov	r3, r5
 80051ac:	f7fb f9d8 	bl	8000560 <__aeabi_dmul>
 80051b0:	a333      	add	r3, pc, #204	; (adr r3, 8005280 <__kernel_cos+0x170>)
 80051b2:	e9d3 2300 	ldrd	r2, r3, [r3]
 80051b6:	f7fb f81d 	bl	80001f4 <__adddf3>
 80051ba:	4622      	mov	r2, r4
 80051bc:	462b      	mov	r3, r5
 80051be:	f7fb f9cf 	bl	8000560 <__aeabi_dmul>
 80051c2:	4622      	mov	r2, r4
 80051c4:	462b      	mov	r3, r5
 80051c6:	f7fb f9cb 	bl	8000560 <__aeabi_dmul>
 80051ca:	ec53 2b18 	vmov	r2, r3, d8
 80051ce:	4604      	mov	r4, r0
 80051d0:	460d      	mov	r5, r1
 80051d2:	4640      	mov	r0, r8
 80051d4:	4649      	mov	r1, r9
 80051d6:	f7fb f9c3 	bl	8000560 <__aeabi_dmul>
 80051da:	460b      	mov	r3, r1
 80051dc:	4602      	mov	r2, r0
 80051de:	4629      	mov	r1, r5
 80051e0:	4620      	mov	r0, r4
 80051e2:	f7fb f805 	bl	80001f0 <__aeabi_dsub>
 80051e6:	4b29      	ldr	r3, [pc, #164]	; (800528c <__kernel_cos+0x17c>)
 80051e8:	429e      	cmp	r6, r3
 80051ea:	4680      	mov	r8, r0
 80051ec:	4689      	mov	r9, r1
 80051ee:	dc11      	bgt.n	8005214 <__kernel_cos+0x104>
 80051f0:	4602      	mov	r2, r0
 80051f2:	460b      	mov	r3, r1
 80051f4:	4650      	mov	r0, sl
 80051f6:	4659      	mov	r1, fp
 80051f8:	f7fa fffa 	bl	80001f0 <__aeabi_dsub>
 80051fc:	460b      	mov	r3, r1
 80051fe:	4924      	ldr	r1, [pc, #144]	; (8005290 <__kernel_cos+0x180>)
 8005200:	4602      	mov	r2, r0
 8005202:	2000      	movs	r0, #0
 8005204:	f7fa fff4 	bl	80001f0 <__aeabi_dsub>
 8005208:	ecbd 8b02 	vpop	{d8}
 800520c:	ec41 0b10 	vmov	d0, r0, r1
 8005210:	e8bd 8ff8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8005214:	4b1f      	ldr	r3, [pc, #124]	; (8005294 <__kernel_cos+0x184>)
 8005216:	491e      	ldr	r1, [pc, #120]	; (8005290 <__kernel_cos+0x180>)
 8005218:	429e      	cmp	r6, r3
 800521a:	bfcc      	ite	gt
 800521c:	4d1e      	ldrgt	r5, [pc, #120]	; (8005298 <__kernel_cos+0x188>)
 800521e:	f5a6 1500 	suble.w	r5, r6, #2097152	; 0x200000
 8005222:	2400      	movs	r4, #0
 8005224:	4622      	mov	r2, r4
 8005226:	462b      	mov	r3, r5
 8005228:	2000      	movs	r0, #0
 800522a:	f7fa ffe1 	bl	80001f0 <__aeabi_dsub>
 800522e:	4622      	mov	r2, r4
 8005230:	4606      	mov	r6, r0
 8005232:	460f      	mov	r7, r1
 8005234:	462b      	mov	r3, r5
 8005236:	4650      	mov	r0, sl
 8005238:	4659      	mov	r1, fp
 800523a:	f7fa ffd9 	bl	80001f0 <__aeabi_dsub>
 800523e:	4642      	mov	r2, r8
 8005240:	464b      	mov	r3, r9
 8005242:	f7fa ffd5 	bl	80001f0 <__aeabi_dsub>
 8005246:	4602      	mov	r2, r0
 8005248:	460b      	mov	r3, r1
 800524a:	4630      	mov	r0, r6
 800524c:	4639      	mov	r1, r7
 800524e:	e7d9      	b.n	8005204 <__kernel_cos+0xf4>
 8005250:	2000      	movs	r0, #0
 8005252:	490f      	ldr	r1, [pc, #60]	; (8005290 <__kernel_cos+0x180>)
 8005254:	e7d8      	b.n	8005208 <__kernel_cos+0xf8>
 8005256:	bf00      	nop
 8005258:	be8838d4 	.word	0xbe8838d4
 800525c:	bda8fae9 	.word	0xbda8fae9
 8005260:	bdb4b1c4 	.word	0xbdb4b1c4
 8005264:	3e21ee9e 	.word	0x3e21ee9e
 8005268:	809c52ad 	.word	0x809c52ad
 800526c:	3e927e4f 	.word	0x3e927e4f
 8005270:	19cb1590 	.word	0x19cb1590
 8005274:	3efa01a0 	.word	0x3efa01a0
 8005278:	16c15177 	.word	0x16c15177
 800527c:	3f56c16c 	.word	0x3f56c16c
 8005280:	5555554c 	.word	0x5555554c
 8005284:	3fa55555 	.word	0x3fa55555
 8005288:	3fe00000 	.word	0x3fe00000
 800528c:	3fd33332 	.word	0x3fd33332
 8005290:	3ff00000 	.word	0x3ff00000
 8005294:	3fe90000 	.word	0x3fe90000
 8005298:	3fd20000 	.word	0x3fd20000
 800529c:	00000000 	.word	0x00000000

080052a0 <__kernel_rem_pio2>:
 80052a0:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80052a4:	ed2d 8b02 	vpush	{d8}
 80052a8:	f5ad 7d1b 	sub.w	sp, sp, #620	; 0x26c
 80052ac:	1ed4      	subs	r4, r2, #3
 80052ae:	9308      	str	r3, [sp, #32]
 80052b0:	9101      	str	r1, [sp, #4]
 80052b2:	4bc5      	ldr	r3, [pc, #788]	; (80055c8 <__kernel_rem_pio2+0x328>)
 80052b4:	99a6      	ldr	r1, [sp, #664]	; 0x298
 80052b6:	9009      	str	r0, [sp, #36]	; 0x24
 80052b8:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
 80052bc:	9304      	str	r3, [sp, #16]
 80052be:	9b08      	ldr	r3, [sp, #32]
 80052c0:	3b01      	subs	r3, #1
 80052c2:	9307      	str	r3, [sp, #28]
 80052c4:	2318      	movs	r3, #24
 80052c6:	fb94 f4f3 	sdiv	r4, r4, r3
 80052ca:	f06f 0317 	mvn.w	r3, #23
 80052ce:	ea24 74e4 	bic.w	r4, r4, r4, asr #31
 80052d2:	fb04 3303 	mla	r3, r4, r3, r3
 80052d6:	eb03 0a02 	add.w	sl, r3, r2
 80052da:	9b04      	ldr	r3, [sp, #16]
 80052dc:	9a07      	ldr	r2, [sp, #28]
 80052de:	ed9f 8bb6 	vldr	d8, [pc, #728]	; 80055b8 <__kernel_rem_pio2+0x318>
 80052e2:	eb03 0802 	add.w	r8, r3, r2
 80052e6:	9ba7      	ldr	r3, [sp, #668]	; 0x29c
 80052e8:	1aa7      	subs	r7, r4, r2
 80052ea:	eb03 0987 	add.w	r9, r3, r7, lsl #2
 80052ee:	ae22      	add	r6, sp, #136	; 0x88
 80052f0:	2500      	movs	r5, #0
 80052f2:	4545      	cmp	r5, r8
 80052f4:	dd13      	ble.n	800531e <__kernel_rem_pio2+0x7e>
 80052f6:	ed9f 8bb0 	vldr	d8, [pc, #704]	; 80055b8 <__kernel_rem_pio2+0x318>
 80052fa:	f50d 7be4 	add.w	fp, sp, #456	; 0x1c8
 80052fe:	2600      	movs	r6, #0
 8005300:	9b04      	ldr	r3, [sp, #16]
 8005302:	429e      	cmp	r6, r3
 8005304:	dc32      	bgt.n	800536c <__kernel_rem_pio2+0xcc>
 8005306:	9b09      	ldr	r3, [sp, #36]	; 0x24
 8005308:	9302      	str	r3, [sp, #8]
 800530a:	9b08      	ldr	r3, [sp, #32]
 800530c:	199d      	adds	r5, r3, r6
 800530e:	ab22      	add	r3, sp, #136	; 0x88
 8005310:	eb03 03c5 	add.w	r3, r3, r5, lsl #3
 8005314:	9306      	str	r3, [sp, #24]
 8005316:	ec59 8b18 	vmov	r8, r9, d8
 800531a:	2700      	movs	r7, #0
 800531c:	e01f      	b.n	800535e <__kernel_rem_pio2+0xbe>
 800531e:	42ef      	cmn	r7, r5
 8005320:	d407      	bmi.n	8005332 <__kernel_rem_pio2+0x92>
 8005322:	f859 0025 	ldr.w	r0, [r9, r5, lsl #2]
 8005326:	f7fb f8b1 	bl	800048c <__aeabi_i2d>
 800532a:	e8e6 0102 	strd	r0, r1, [r6], #8
 800532e:	3501      	adds	r5, #1
 8005330:	e7df      	b.n	80052f2 <__kernel_rem_pio2+0x52>
 8005332:	ec51 0b18 	vmov	r0, r1, d8
 8005336:	e7f8      	b.n	800532a <__kernel_rem_pio2+0x8a>
 8005338:	9906      	ldr	r1, [sp, #24]
 800533a:	9d02      	ldr	r5, [sp, #8]
 800533c:	e971 2302 	ldrd	r2, r3, [r1, #-8]!
 8005340:	9106      	str	r1, [sp, #24]
 8005342:	e8f5 0102 	ldrd	r0, r1, [r5], #8
 8005346:	9502      	str	r5, [sp, #8]
 8005348:	f7fb f90a 	bl	8000560 <__aeabi_dmul>
 800534c:	4602      	mov	r2, r0
 800534e:	460b      	mov	r3, r1
 8005350:	4640      	mov	r0, r8
 8005352:	4649      	mov	r1, r9
 8005354:	f7fa ff4e 	bl	80001f4 <__adddf3>
 8005358:	3701      	adds	r7, #1
 800535a:	4680      	mov	r8, r0
 800535c:	4689      	mov	r9, r1
 800535e:	9b07      	ldr	r3, [sp, #28]
 8005360:	429f      	cmp	r7, r3
 8005362:	dde9      	ble.n	8005338 <__kernel_rem_pio2+0x98>
 8005364:	e8eb 8902 	strd	r8, r9, [fp], #8
 8005368:	3601      	adds	r6, #1
 800536a:	e7c9      	b.n	8005300 <__kernel_rem_pio2+0x60>
 800536c:	9b04      	ldr	r3, [sp, #16]
 800536e:	aa0e      	add	r2, sp, #56	; 0x38
 8005370:	eb02 0383 	add.w	r3, r2, r3, lsl #2
 8005374:	930c      	str	r3, [sp, #48]	; 0x30
 8005376:	9ba7      	ldr	r3, [sp, #668]	; 0x29c
 8005378:	eb03 0384 	add.w	r3, r3, r4, lsl #2
 800537c:	9c04      	ldr	r4, [sp, #16]
 800537e:	930b      	str	r3, [sp, #44]	; 0x2c
 8005380:	ab9a      	add	r3, sp, #616	; 0x268
 8005382:	f104 5b00 	add.w	fp, r4, #536870912	; 0x20000000
 8005386:	eb03 03c4 	add.w	r3, r3, r4, lsl #3
 800538a:	f10b 3bff 	add.w	fp, fp, #4294967295
 800538e:	e953 8928 	ldrd	r8, r9, [r3, #-160]	; 0xa0
 8005392:	ea4f 0bcb 	mov.w	fp, fp, lsl #3
 8005396:	ab9a      	add	r3, sp, #616	; 0x268
 8005398:	445b      	add	r3, fp
 800539a:	f1a3 0698 	sub.w	r6, r3, #152	; 0x98
 800539e:	2500      	movs	r5, #0
 80053a0:	1b63      	subs	r3, r4, r5
 80053a2:	2b00      	cmp	r3, #0
 80053a4:	dc78      	bgt.n	8005498 <__kernel_rem_pio2+0x1f8>
 80053a6:	4650      	mov	r0, sl
 80053a8:	ec49 8b10 	vmov	d0, r8, r9
 80053ac:	f000 fd54 	bl	8005e58 <scalbn>
 80053b0:	ec57 6b10 	vmov	r6, r7, d0
 80053b4:	2200      	movs	r2, #0
 80053b6:	f04f 537f 	mov.w	r3, #1069547520	; 0x3fc00000
 80053ba:	ee10 0a10 	vmov	r0, s0
 80053be:	4639      	mov	r1, r7
 80053c0:	f7fb f8ce 	bl	8000560 <__aeabi_dmul>
 80053c4:	ec41 0b10 	vmov	d0, r0, r1
 80053c8:	f7ff f84e 	bl	8004468 <floor>
 80053cc:	2200      	movs	r2, #0
 80053ce:	ec51 0b10 	vmov	r0, r1, d0
 80053d2:	4b7e      	ldr	r3, [pc, #504]	; (80055cc <__kernel_rem_pio2+0x32c>)
 80053d4:	f7fb f8c4 	bl	8000560 <__aeabi_dmul>
 80053d8:	4602      	mov	r2, r0
 80053da:	460b      	mov	r3, r1
 80053dc:	4630      	mov	r0, r6
 80053de:	4639      	mov	r1, r7
 80053e0:	f7fa ff06 	bl	80001f0 <__aeabi_dsub>
 80053e4:	460f      	mov	r7, r1
 80053e6:	4606      	mov	r6, r0
 80053e8:	f7fb fb6a 	bl	8000ac0 <__aeabi_d2iz>
 80053ec:	9006      	str	r0, [sp, #24]
 80053ee:	f7fb f84d 	bl	800048c <__aeabi_i2d>
 80053f2:	4602      	mov	r2, r0
 80053f4:	460b      	mov	r3, r1
 80053f6:	4630      	mov	r0, r6
 80053f8:	4639      	mov	r1, r7
 80053fa:	f7fa fef9 	bl	80001f0 <__aeabi_dsub>
 80053fe:	f1ba 0f00 	cmp.w	sl, #0
 8005402:	4606      	mov	r6, r0
 8005404:	460f      	mov	r7, r1
 8005406:	dd6c      	ble.n	80054e2 <__kernel_rem_pio2+0x242>
 8005408:	1e62      	subs	r2, r4, #1
 800540a:	ab0e      	add	r3, sp, #56	; 0x38
 800540c:	f1ca 0118 	rsb	r1, sl, #24
 8005410:	f853 0022 	ldr.w	r0, [r3, r2, lsl #2]
 8005414:	9d06      	ldr	r5, [sp, #24]
 8005416:	fa40 f301 	asr.w	r3, r0, r1
 800541a:	441d      	add	r5, r3
 800541c:	408b      	lsls	r3, r1
 800541e:	1ac0      	subs	r0, r0, r3
 8005420:	ab0e      	add	r3, sp, #56	; 0x38
 8005422:	9506      	str	r5, [sp, #24]
 8005424:	f843 0022 	str.w	r0, [r3, r2, lsl #2]
 8005428:	f1ca 0317 	rsb	r3, sl, #23
 800542c:	fa40 f303 	asr.w	r3, r0, r3
 8005430:	9302      	str	r3, [sp, #8]
 8005432:	9b02      	ldr	r3, [sp, #8]
 8005434:	2b00      	cmp	r3, #0
 8005436:	dd62      	ble.n	80054fe <__kernel_rem_pio2+0x25e>
 8005438:	9b06      	ldr	r3, [sp, #24]
 800543a:	2200      	movs	r2, #0
 800543c:	3301      	adds	r3, #1
 800543e:	9306      	str	r3, [sp, #24]
 8005440:	4615      	mov	r5, r2
 8005442:	f06f 417f 	mvn.w	r1, #4278190080	; 0xff000000
 8005446:	4294      	cmp	r4, r2
 8005448:	f300 8095 	bgt.w	8005576 <__kernel_rem_pio2+0x2d6>
 800544c:	f1ba 0f00 	cmp.w	sl, #0
 8005450:	dd07      	ble.n	8005462 <__kernel_rem_pio2+0x1c2>
 8005452:	f1ba 0f01 	cmp.w	sl, #1
 8005456:	f000 80a2 	beq.w	800559e <__kernel_rem_pio2+0x2fe>
 800545a:	f1ba 0f02 	cmp.w	sl, #2
 800545e:	f000 80c1 	beq.w	80055e4 <__kernel_rem_pio2+0x344>
 8005462:	9b02      	ldr	r3, [sp, #8]
 8005464:	2b02      	cmp	r3, #2
 8005466:	d14a      	bne.n	80054fe <__kernel_rem_pio2+0x25e>
 8005468:	4632      	mov	r2, r6
 800546a:	463b      	mov	r3, r7
 800546c:	2000      	movs	r0, #0
 800546e:	4958      	ldr	r1, [pc, #352]	; (80055d0 <__kernel_rem_pio2+0x330>)
 8005470:	f7fa febe 	bl	80001f0 <__aeabi_dsub>
 8005474:	4606      	mov	r6, r0
 8005476:	460f      	mov	r7, r1
 8005478:	2d00      	cmp	r5, #0
 800547a:	d040      	beq.n	80054fe <__kernel_rem_pio2+0x25e>
 800547c:	4650      	mov	r0, sl
 800547e:	ed9f 0b50 	vldr	d0, [pc, #320]	; 80055c0 <__kernel_rem_pio2+0x320>
 8005482:	f000 fce9 	bl	8005e58 <scalbn>
 8005486:	4630      	mov	r0, r6
 8005488:	4639      	mov	r1, r7
 800548a:	ec53 2b10 	vmov	r2, r3, d0
 800548e:	f7fa feaf 	bl	80001f0 <__aeabi_dsub>
 8005492:	4606      	mov	r6, r0
 8005494:	460f      	mov	r7, r1
 8005496:	e032      	b.n	80054fe <__kernel_rem_pio2+0x25e>
 8005498:	2200      	movs	r2, #0
 800549a:	4b4e      	ldr	r3, [pc, #312]	; (80055d4 <__kernel_rem_pio2+0x334>)
 800549c:	4640      	mov	r0, r8
 800549e:	4649      	mov	r1, r9
 80054a0:	f7fb f85e 	bl	8000560 <__aeabi_dmul>
 80054a4:	f7fb fb0c 	bl	8000ac0 <__aeabi_d2iz>
 80054a8:	f7fa fff0 	bl	800048c <__aeabi_i2d>
 80054ac:	2200      	movs	r2, #0
 80054ae:	4b4a      	ldr	r3, [pc, #296]	; (80055d8 <__kernel_rem_pio2+0x338>)
 80054b0:	e9cd 0102 	strd	r0, r1, [sp, #8]
 80054b4:	f7fb f854 	bl	8000560 <__aeabi_dmul>
 80054b8:	4602      	mov	r2, r0
 80054ba:	460b      	mov	r3, r1
 80054bc:	4640      	mov	r0, r8
 80054be:	4649      	mov	r1, r9
 80054c0:	f7fa fe96 	bl	80001f0 <__aeabi_dsub>
 80054c4:	f7fb fafc 	bl	8000ac0 <__aeabi_d2iz>
 80054c8:	ab0e      	add	r3, sp, #56	; 0x38
 80054ca:	f843 0025 	str.w	r0, [r3, r5, lsl #2]
 80054ce:	e976 2302 	ldrd	r2, r3, [r6, #-8]!
 80054d2:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 80054d6:	f7fa fe8d 	bl	80001f4 <__adddf3>
 80054da:	3501      	adds	r5, #1
 80054dc:	4680      	mov	r8, r0
 80054de:	4689      	mov	r9, r1
 80054e0:	e75e      	b.n	80053a0 <__kernel_rem_pio2+0x100>
 80054e2:	d105      	bne.n	80054f0 <__kernel_rem_pio2+0x250>
 80054e4:	1e63      	subs	r3, r4, #1
 80054e6:	aa0e      	add	r2, sp, #56	; 0x38
 80054e8:	f852 0023 	ldr.w	r0, [r2, r3, lsl #2]
 80054ec:	15c3      	asrs	r3, r0, #23
 80054ee:	e79f      	b.n	8005430 <__kernel_rem_pio2+0x190>
 80054f0:	2200      	movs	r2, #0
 80054f2:	4b3a      	ldr	r3, [pc, #232]	; (80055dc <__kernel_rem_pio2+0x33c>)
 80054f4:	f7fb faba 	bl	8000a6c <__aeabi_dcmpge>
 80054f8:	2800      	cmp	r0, #0
 80054fa:	d139      	bne.n	8005570 <__kernel_rem_pio2+0x2d0>
 80054fc:	9002      	str	r0, [sp, #8]
 80054fe:	2200      	movs	r2, #0
 8005500:	2300      	movs	r3, #0
 8005502:	4630      	mov	r0, r6
 8005504:	4639      	mov	r1, r7
 8005506:	f7fb fa93 	bl	8000a30 <__aeabi_dcmpeq>
 800550a:	2800      	cmp	r0, #0
 800550c:	f000 80c7 	beq.w	800569e <__kernel_rem_pio2+0x3fe>
 8005510:	1e65      	subs	r5, r4, #1
 8005512:	462b      	mov	r3, r5
 8005514:	2200      	movs	r2, #0
 8005516:	9904      	ldr	r1, [sp, #16]
 8005518:	428b      	cmp	r3, r1
 800551a:	da6a      	bge.n	80055f2 <__kernel_rem_pio2+0x352>
 800551c:	2a00      	cmp	r2, #0
 800551e:	f000 8088 	beq.w	8005632 <__kernel_rem_pio2+0x392>
 8005522:	ab0e      	add	r3, sp, #56	; 0x38
 8005524:	f1aa 0a18 	sub.w	sl, sl, #24
 8005528:	f853 3025 	ldr.w	r3, [r3, r5, lsl #2]
 800552c:	2b00      	cmp	r3, #0
 800552e:	f000 80b4 	beq.w	800569a <__kernel_rem_pio2+0x3fa>
 8005532:	4650      	mov	r0, sl
 8005534:	ed9f 0b22 	vldr	d0, [pc, #136]	; 80055c0 <__kernel_rem_pio2+0x320>
 8005538:	f000 fc8e 	bl	8005e58 <scalbn>
 800553c:	00ec      	lsls	r4, r5, #3
 800553e:	ab72      	add	r3, sp, #456	; 0x1c8
 8005540:	191e      	adds	r6, r3, r4
 8005542:	ec59 8b10 	vmov	r8, r9, d0
 8005546:	f106 0a08 	add.w	sl, r6, #8
 800554a:	462f      	mov	r7, r5
 800554c:	2f00      	cmp	r7, #0
 800554e:	f280 80df 	bge.w	8005710 <__kernel_rem_pio2+0x470>
 8005552:	ed9f 8b19 	vldr	d8, [pc, #100]	; 80055b8 <__kernel_rem_pio2+0x318>
 8005556:	f04f 0a00 	mov.w	sl, #0
 800555a:	eba5 030a 	sub.w	r3, r5, sl
 800555e:	2b00      	cmp	r3, #0
 8005560:	f2c0 810a 	blt.w	8005778 <__kernel_rem_pio2+0x4d8>
 8005564:	f8df b078 	ldr.w	fp, [pc, #120]	; 80055e0 <__kernel_rem_pio2+0x340>
 8005568:	ec59 8b18 	vmov	r8, r9, d8
 800556c:	2700      	movs	r7, #0
 800556e:	e0f5      	b.n	800575c <__kernel_rem_pio2+0x4bc>
 8005570:	2302      	movs	r3, #2
 8005572:	9302      	str	r3, [sp, #8]
 8005574:	e760      	b.n	8005438 <__kernel_rem_pio2+0x198>
 8005576:	ab0e      	add	r3, sp, #56	; 0x38
 8005578:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 800557c:	b94d      	cbnz	r5, 8005592 <__kernel_rem_pio2+0x2f2>
 800557e:	b12b      	cbz	r3, 800558c <__kernel_rem_pio2+0x2ec>
 8005580:	a80e      	add	r0, sp, #56	; 0x38
 8005582:	f1c3 7380 	rsb	r3, r3, #16777216	; 0x1000000
 8005586:	f840 3022 	str.w	r3, [r0, r2, lsl #2]
 800558a:	2301      	movs	r3, #1
 800558c:	3201      	adds	r2, #1
 800558e:	461d      	mov	r5, r3
 8005590:	e759      	b.n	8005446 <__kernel_rem_pio2+0x1a6>
 8005592:	a80e      	add	r0, sp, #56	; 0x38
 8005594:	1acb      	subs	r3, r1, r3
 8005596:	f840 3022 	str.w	r3, [r0, r2, lsl #2]
 800559a:	462b      	mov	r3, r5
 800559c:	e7f6      	b.n	800558c <__kernel_rem_pio2+0x2ec>
 800559e:	1e62      	subs	r2, r4, #1
 80055a0:	ab0e      	add	r3, sp, #56	; 0x38
 80055a2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 80055a6:	f3c3 0316 	ubfx	r3, r3, #0, #23
 80055aa:	a90e      	add	r1, sp, #56	; 0x38
 80055ac:	f841 3022 	str.w	r3, [r1, r2, lsl #2]
 80055b0:	e757      	b.n	8005462 <__kernel_rem_pio2+0x1c2>
 80055b2:	bf00      	nop
 80055b4:	f3af 8000 	nop.w
	...
 80055c4:	3ff00000 	.word	0x3ff00000
 80055c8:	08006200 	.word	0x08006200
 80055cc:	40200000 	.word	0x40200000
 80055d0:	3ff00000 	.word	0x3ff00000
 80055d4:	3e700000 	.word	0x3e700000
 80055d8:	41700000 	.word	0x41700000
 80055dc:	3fe00000 	.word	0x3fe00000
 80055e0:	080061c0 	.word	0x080061c0
 80055e4:	1e62      	subs	r2, r4, #1
 80055e6:	ab0e      	add	r3, sp, #56	; 0x38
 80055e8:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 80055ec:	f3c3 0315 	ubfx	r3, r3, #0, #22
 80055f0:	e7db      	b.n	80055aa <__kernel_rem_pio2+0x30a>
 80055f2:	a90e      	add	r1, sp, #56	; 0x38
 80055f4:	f851 1023 	ldr.w	r1, [r1, r3, lsl #2]
 80055f8:	3b01      	subs	r3, #1
 80055fa:	430a      	orrs	r2, r1
 80055fc:	e78b      	b.n	8005516 <__kernel_rem_pio2+0x276>
 80055fe:	3301      	adds	r3, #1
 8005600:	f852 1d04 	ldr.w	r1, [r2, #-4]!
 8005604:	2900      	cmp	r1, #0
 8005606:	d0fa      	beq.n	80055fe <__kernel_rem_pio2+0x35e>
 8005608:	9a08      	ldr	r2, [sp, #32]
 800560a:	4422      	add	r2, r4
 800560c:	00d2      	lsls	r2, r2, #3
 800560e:	a922      	add	r1, sp, #136	; 0x88
 8005610:	18e3      	adds	r3, r4, r3
 8005612:	9206      	str	r2, [sp, #24]
 8005614:	440a      	add	r2, r1
 8005616:	9302      	str	r3, [sp, #8]
 8005618:	f10b 0108 	add.w	r1, fp, #8
 800561c:	f102 0308 	add.w	r3, r2, #8
 8005620:	1c66      	adds	r6, r4, #1
 8005622:	910a      	str	r1, [sp, #40]	; 0x28
 8005624:	2500      	movs	r5, #0
 8005626:	930d      	str	r3, [sp, #52]	; 0x34
 8005628:	9b02      	ldr	r3, [sp, #8]
 800562a:	42b3      	cmp	r3, r6
 800562c:	da04      	bge.n	8005638 <__kernel_rem_pio2+0x398>
 800562e:	461c      	mov	r4, r3
 8005630:	e6a6      	b.n	8005380 <__kernel_rem_pio2+0xe0>
 8005632:	9a0c      	ldr	r2, [sp, #48]	; 0x30
 8005634:	2301      	movs	r3, #1
 8005636:	e7e3      	b.n	8005600 <__kernel_rem_pio2+0x360>
 8005638:	9b06      	ldr	r3, [sp, #24]
 800563a:	18ef      	adds	r7, r5, r3
 800563c:	ab22      	add	r3, sp, #136	; 0x88
 800563e:	441f      	add	r7, r3
 8005640:	9b0b      	ldr	r3, [sp, #44]	; 0x2c
 8005642:	f853 0026 	ldr.w	r0, [r3, r6, lsl #2]
 8005646:	f7fa ff21 	bl	800048c <__aeabi_i2d>
 800564a:	9b09      	ldr	r3, [sp, #36]	; 0x24
 800564c:	461c      	mov	r4, r3
 800564e:	9b0d      	ldr	r3, [sp, #52]	; 0x34
 8005650:	e9c7 0100 	strd	r0, r1, [r7]
 8005654:	eb03 0b05 	add.w	fp, r3, r5
 8005658:	2700      	movs	r7, #0
 800565a:	f04f 0800 	mov.w	r8, #0
 800565e:	f04f 0900 	mov.w	r9, #0
 8005662:	9b07      	ldr	r3, [sp, #28]
 8005664:	429f      	cmp	r7, r3
 8005666:	dd08      	ble.n	800567a <__kernel_rem_pio2+0x3da>
 8005668:	9b0a      	ldr	r3, [sp, #40]	; 0x28
 800566a:	aa72      	add	r2, sp, #456	; 0x1c8
 800566c:	18eb      	adds	r3, r5, r3
 800566e:	4413      	add	r3, r2
 8005670:	e9c3 8902 	strd	r8, r9, [r3, #8]
 8005674:	3601      	adds	r6, #1
 8005676:	3508      	adds	r5, #8
 8005678:	e7d6      	b.n	8005628 <__kernel_rem_pio2+0x388>
 800567a:	e97b 2302 	ldrd	r2, r3, [fp, #-8]!
 800567e:	e8f4 0102 	ldrd	r0, r1, [r4], #8
 8005682:	f7fa ff6d 	bl	8000560 <__aeabi_dmul>
 8005686:	4602      	mov	r2, r0
 8005688:	460b      	mov	r3, r1
 800568a:	4640      	mov	r0, r8
 800568c:	4649      	mov	r1, r9
 800568e:	f7fa fdb1 	bl	80001f4 <__adddf3>
 8005692:	3701      	adds	r7, #1
 8005694:	4680      	mov	r8, r0
 8005696:	4689      	mov	r9, r1
 8005698:	e7e3      	b.n	8005662 <__kernel_rem_pio2+0x3c2>
 800569a:	3d01      	subs	r5, #1
 800569c:	e741      	b.n	8005522 <__kernel_rem_pio2+0x282>
 800569e:	f1ca 0000 	rsb	r0, sl, #0
 80056a2:	ec47 6b10 	vmov	d0, r6, r7
 80056a6:	f000 fbd7 	bl	8005e58 <scalbn>
 80056aa:	ec57 6b10 	vmov	r6, r7, d0
 80056ae:	2200      	movs	r2, #0
 80056b0:	4b99      	ldr	r3, [pc, #612]	; (8005918 <__kernel_rem_pio2+0x678>)
 80056b2:	ee10 0a10 	vmov	r0, s0
 80056b6:	4639      	mov	r1, r7
 80056b8:	f7fb f9d8 	bl	8000a6c <__aeabi_dcmpge>
 80056bc:	b1f8      	cbz	r0, 80056fe <__kernel_rem_pio2+0x45e>
 80056be:	2200      	movs	r2, #0
 80056c0:	4b96      	ldr	r3, [pc, #600]	; (800591c <__kernel_rem_pio2+0x67c>)
 80056c2:	4630      	mov	r0, r6
 80056c4:	4639      	mov	r1, r7
 80056c6:	f7fa ff4b 	bl	8000560 <__aeabi_dmul>
 80056ca:	f7fb f9f9 	bl	8000ac0 <__aeabi_d2iz>
 80056ce:	4680      	mov	r8, r0
 80056d0:	f7fa fedc 	bl	800048c <__aeabi_i2d>
 80056d4:	2200      	movs	r2, #0
 80056d6:	4b90      	ldr	r3, [pc, #576]	; (8005918 <__kernel_rem_pio2+0x678>)
 80056d8:	f7fa ff42 	bl	8000560 <__aeabi_dmul>
 80056dc:	460b      	mov	r3, r1
 80056de:	4602      	mov	r2, r0
 80056e0:	4639      	mov	r1, r7
 80056e2:	4630      	mov	r0, r6
 80056e4:	f7fa fd84 	bl	80001f0 <__aeabi_dsub>
 80056e8:	f7fb f9ea 	bl	8000ac0 <__aeabi_d2iz>
 80056ec:	1c65      	adds	r5, r4, #1
 80056ee:	ab0e      	add	r3, sp, #56	; 0x38
 80056f0:	f10a 0a18 	add.w	sl, sl, #24
 80056f4:	f843 0024 	str.w	r0, [r3, r4, lsl #2]
 80056f8:	f843 8025 	str.w	r8, [r3, r5, lsl #2]
 80056fc:	e719      	b.n	8005532 <__kernel_rem_pio2+0x292>
 80056fe:	4630      	mov	r0, r6
 8005700:	4639      	mov	r1, r7
 8005702:	f7fb f9dd 	bl	8000ac0 <__aeabi_d2iz>
 8005706:	ab0e      	add	r3, sp, #56	; 0x38
 8005708:	4625      	mov	r5, r4
 800570a:	f843 0024 	str.w	r0, [r3, r4, lsl #2]
 800570e:	e710      	b.n	8005532 <__kernel_rem_pio2+0x292>
 8005710:	ab0e      	add	r3, sp, #56	; 0x38
 8005712:	f853 0027 	ldr.w	r0, [r3, r7, lsl #2]
 8005716:	f7fa feb9 	bl	800048c <__aeabi_i2d>
 800571a:	4642      	mov	r2, r8
 800571c:	464b      	mov	r3, r9
 800571e:	f7fa ff1f 	bl	8000560 <__aeabi_dmul>
 8005722:	2200      	movs	r2, #0
 8005724:	e96a 0102 	strd	r0, r1, [sl, #-8]!
 8005728:	4b7c      	ldr	r3, [pc, #496]	; (800591c <__kernel_rem_pio2+0x67c>)
 800572a:	4640      	mov	r0, r8
 800572c:	4649      	mov	r1, r9
 800572e:	f7fa ff17 	bl	8000560 <__aeabi_dmul>
 8005732:	3f01      	subs	r7, #1
 8005734:	4680      	mov	r8, r0
 8005736:	4689      	mov	r9, r1
 8005738:	e708      	b.n	800554c <__kernel_rem_pio2+0x2ac>
 800573a:	eb06 03c7 	add.w	r3, r6, r7, lsl #3
 800573e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005742:	e8fb 0102 	ldrd	r0, r1, [fp], #8
 8005746:	f7fa ff0b 	bl	8000560 <__aeabi_dmul>
 800574a:	4602      	mov	r2, r0
 800574c:	460b      	mov	r3, r1
 800574e:	4640      	mov	r0, r8
 8005750:	4649      	mov	r1, r9
 8005752:	f7fa fd4f 	bl	80001f4 <__adddf3>
 8005756:	3701      	adds	r7, #1
 8005758:	4680      	mov	r8, r0
 800575a:	4689      	mov	r9, r1
 800575c:	9b04      	ldr	r3, [sp, #16]
 800575e:	429f      	cmp	r7, r3
 8005760:	dc01      	bgt.n	8005766 <__kernel_rem_pio2+0x4c6>
 8005762:	45ba      	cmp	sl, r7
 8005764:	dae9      	bge.n	800573a <__kernel_rem_pio2+0x49a>
 8005766:	ab4a      	add	r3, sp, #296	; 0x128
 8005768:	eb03 03ca 	add.w	r3, r3, sl, lsl #3
 800576c:	e9c3 8900 	strd	r8, r9, [r3]
 8005770:	f10a 0a01 	add.w	sl, sl, #1
 8005774:	3e08      	subs	r6, #8
 8005776:	e6f0      	b.n	800555a <__kernel_rem_pio2+0x2ba>
 8005778:	9ba6      	ldr	r3, [sp, #664]	; 0x298
 800577a:	2b03      	cmp	r3, #3
 800577c:	d85b      	bhi.n	8005836 <__kernel_rem_pio2+0x596>
 800577e:	e8df f003 	tbb	[pc, r3]
 8005782:	264a      	.short	0x264a
 8005784:	0226      	.short	0x0226
 8005786:	ab9a      	add	r3, sp, #616	; 0x268
 8005788:	441c      	add	r4, r3
 800578a:	f5a4 749c 	sub.w	r4, r4, #312	; 0x138
 800578e:	46a2      	mov	sl, r4
 8005790:	46ab      	mov	fp, r5
 8005792:	f1bb 0f00 	cmp.w	fp, #0
 8005796:	dc6c      	bgt.n	8005872 <__kernel_rem_pio2+0x5d2>
 8005798:	46a2      	mov	sl, r4
 800579a:	46ab      	mov	fp, r5
 800579c:	f1bb 0f01 	cmp.w	fp, #1
 80057a0:	f300 8086 	bgt.w	80058b0 <__kernel_rem_pio2+0x610>
 80057a4:	2000      	movs	r0, #0
 80057a6:	2100      	movs	r1, #0
 80057a8:	2d01      	cmp	r5, #1
 80057aa:	f300 80a0 	bgt.w	80058ee <__kernel_rem_pio2+0x64e>
 80057ae:	9b02      	ldr	r3, [sp, #8]
 80057b0:	e9dd 784a 	ldrd	r7, r8, [sp, #296]	; 0x128
 80057b4:	e9dd 564c 	ldrd	r5, r6, [sp, #304]	; 0x130
 80057b8:	2b00      	cmp	r3, #0
 80057ba:	f040 809e 	bne.w	80058fa <__kernel_rem_pio2+0x65a>
 80057be:	9b01      	ldr	r3, [sp, #4]
 80057c0:	e9c3 7800 	strd	r7, r8, [r3]
 80057c4:	e9c3 5602 	strd	r5, r6, [r3, #8]
 80057c8:	e9c3 0104 	strd	r0, r1, [r3, #16]
 80057cc:	e033      	b.n	8005836 <__kernel_rem_pio2+0x596>
 80057ce:	3408      	adds	r4, #8
 80057d0:	ab4a      	add	r3, sp, #296	; 0x128
 80057d2:	441c      	add	r4, r3
 80057d4:	462e      	mov	r6, r5
 80057d6:	2000      	movs	r0, #0
 80057d8:	2100      	movs	r1, #0
 80057da:	2e00      	cmp	r6, #0
 80057dc:	da3a      	bge.n	8005854 <__kernel_rem_pio2+0x5b4>
 80057de:	9b02      	ldr	r3, [sp, #8]
 80057e0:	2b00      	cmp	r3, #0
 80057e2:	d03d      	beq.n	8005860 <__kernel_rem_pio2+0x5c0>
 80057e4:	4602      	mov	r2, r0
 80057e6:	f101 4300 	add.w	r3, r1, #2147483648	; 0x80000000
 80057ea:	9c01      	ldr	r4, [sp, #4]
 80057ec:	e9c4 2300 	strd	r2, r3, [r4]
 80057f0:	4602      	mov	r2, r0
 80057f2:	460b      	mov	r3, r1
 80057f4:	e9dd 014a 	ldrd	r0, r1, [sp, #296]	; 0x128
 80057f8:	f7fa fcfa 	bl	80001f0 <__aeabi_dsub>
 80057fc:	ae4c      	add	r6, sp, #304	; 0x130
 80057fe:	2401      	movs	r4, #1
 8005800:	42a5      	cmp	r5, r4
 8005802:	da30      	bge.n	8005866 <__kernel_rem_pio2+0x5c6>
 8005804:	9b02      	ldr	r3, [sp, #8]
 8005806:	b113      	cbz	r3, 800580e <__kernel_rem_pio2+0x56e>
 8005808:	f101 4300 	add.w	r3, r1, #2147483648	; 0x80000000
 800580c:	4619      	mov	r1, r3
 800580e:	9b01      	ldr	r3, [sp, #4]
 8005810:	e9c3 0102 	strd	r0, r1, [r3, #8]
 8005814:	e00f      	b.n	8005836 <__kernel_rem_pio2+0x596>
 8005816:	ab9a      	add	r3, sp, #616	; 0x268
 8005818:	441c      	add	r4, r3
 800581a:	f5a4 749c 	sub.w	r4, r4, #312	; 0x138
 800581e:	2000      	movs	r0, #0
 8005820:	2100      	movs	r1, #0
 8005822:	2d00      	cmp	r5, #0
 8005824:	da10      	bge.n	8005848 <__kernel_rem_pio2+0x5a8>
 8005826:	9b02      	ldr	r3, [sp, #8]
 8005828:	b113      	cbz	r3, 8005830 <__kernel_rem_pio2+0x590>
 800582a:	f101 4300 	add.w	r3, r1, #2147483648	; 0x80000000
 800582e:	4619      	mov	r1, r3
 8005830:	9b01      	ldr	r3, [sp, #4]
 8005832:	e9c3 0100 	strd	r0, r1, [r3]
 8005836:	9b06      	ldr	r3, [sp, #24]
 8005838:	f003 0007 	and.w	r0, r3, #7
 800583c:	f50d 7d1b 	add.w	sp, sp, #620	; 0x26c
 8005840:	ecbd 8b02 	vpop	{d8}
 8005844:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8005848:	e974 2302 	ldrd	r2, r3, [r4, #-8]!
 800584c:	f7fa fcd2 	bl	80001f4 <__adddf3>
 8005850:	3d01      	subs	r5, #1
 8005852:	e7e6      	b.n	8005822 <__kernel_rem_pio2+0x582>
 8005854:	e974 2302 	ldrd	r2, r3, [r4, #-8]!
 8005858:	f7fa fccc 	bl	80001f4 <__adddf3>
 800585c:	3e01      	subs	r6, #1
 800585e:	e7bc      	b.n	80057da <__kernel_rem_pio2+0x53a>
 8005860:	4602      	mov	r2, r0
 8005862:	460b      	mov	r3, r1
 8005864:	e7c1      	b.n	80057ea <__kernel_rem_pio2+0x54a>
 8005866:	e8f6 2302 	ldrd	r2, r3, [r6], #8
 800586a:	f7fa fcc3 	bl	80001f4 <__adddf3>
 800586e:	3401      	adds	r4, #1
 8005870:	e7c6      	b.n	8005800 <__kernel_rem_pio2+0x560>
 8005872:	e95a 8904 	ldrd	r8, r9, [sl, #-16]
 8005876:	ed3a 7b02 	vldmdb	sl!, {d7}
 800587a:	4640      	mov	r0, r8
 800587c:	ec53 2b17 	vmov	r2, r3, d7
 8005880:	4649      	mov	r1, r9
 8005882:	ed8d 7b04 	vstr	d7, [sp, #16]
 8005886:	f7fa fcb5 	bl	80001f4 <__adddf3>
 800588a:	4602      	mov	r2, r0
 800588c:	460b      	mov	r3, r1
 800588e:	4606      	mov	r6, r0
 8005890:	460f      	mov	r7, r1
 8005892:	4640      	mov	r0, r8
 8005894:	4649      	mov	r1, r9
 8005896:	f7fa fcab 	bl	80001f0 <__aeabi_dsub>
 800589a:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 800589e:	f7fa fca9 	bl	80001f4 <__adddf3>
 80058a2:	f10b 3bff 	add.w	fp, fp, #4294967295
 80058a6:	e9ca 0100 	strd	r0, r1, [sl]
 80058aa:	e94a 6702 	strd	r6, r7, [sl, #-8]
 80058ae:	e770      	b.n	8005792 <__kernel_rem_pio2+0x4f2>
 80058b0:	e95a 6704 	ldrd	r6, r7, [sl, #-16]
 80058b4:	ed3a 7b02 	vldmdb	sl!, {d7}
 80058b8:	4630      	mov	r0, r6
 80058ba:	ec53 2b17 	vmov	r2, r3, d7
 80058be:	4639      	mov	r1, r7
 80058c0:	ed8d 7b04 	vstr	d7, [sp, #16]
 80058c4:	f7fa fc96 	bl	80001f4 <__adddf3>
 80058c8:	4602      	mov	r2, r0
 80058ca:	460b      	mov	r3, r1
 80058cc:	4680      	mov	r8, r0
 80058ce:	4689      	mov	r9, r1
 80058d0:	4630      	mov	r0, r6
 80058d2:	4639      	mov	r1, r7
 80058d4:	f7fa fc8c 	bl	80001f0 <__aeabi_dsub>
 80058d8:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 80058dc:	f7fa fc8a 	bl	80001f4 <__adddf3>
 80058e0:	f10b 3bff 	add.w	fp, fp, #4294967295
 80058e4:	e9ca 0100 	strd	r0, r1, [sl]
 80058e8:	e94a 8902 	strd	r8, r9, [sl, #-8]
 80058ec:	e756      	b.n	800579c <__kernel_rem_pio2+0x4fc>
 80058ee:	e974 2302 	ldrd	r2, r3, [r4, #-8]!
 80058f2:	f7fa fc7f 	bl	80001f4 <__adddf3>
 80058f6:	3d01      	subs	r5, #1
 80058f8:	e756      	b.n	80057a8 <__kernel_rem_pio2+0x508>
 80058fa:	9b01      	ldr	r3, [sp, #4]
 80058fc:	9a01      	ldr	r2, [sp, #4]
 80058fe:	601f      	str	r7, [r3, #0]
 8005900:	f108 4400 	add.w	r4, r8, #2147483648	; 0x80000000
 8005904:	605c      	str	r4, [r3, #4]
 8005906:	609d      	str	r5, [r3, #8]
 8005908:	f106 4300 	add.w	r3, r6, #2147483648	; 0x80000000
 800590c:	60d3      	str	r3, [r2, #12]
 800590e:	f101 4300 	add.w	r3, r1, #2147483648	; 0x80000000
 8005912:	6110      	str	r0, [r2, #16]
 8005914:	6153      	str	r3, [r2, #20]
 8005916:	e78e      	b.n	8005836 <__kernel_rem_pio2+0x596>
 8005918:	41700000 	.word	0x41700000
 800591c:	3e700000 	.word	0x3e700000

08005920 <__kernel_sin>:
 8005920:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8005924:	ec55 4b10 	vmov	r4, r5, d0
 8005928:	b085      	sub	sp, #20
 800592a:	f025 4300 	bic.w	r3, r5, #2147483648	; 0x80000000
 800592e:	f1b3 5f79 	cmp.w	r3, #1044381696	; 0x3e400000
 8005932:	ed8d 1b00 	vstr	d1, [sp]
 8005936:	9002      	str	r0, [sp, #8]
 8005938:	da06      	bge.n	8005948 <__kernel_sin+0x28>
 800593a:	ee10 0a10 	vmov	r0, s0
 800593e:	4629      	mov	r1, r5
 8005940:	f7fb f8be 	bl	8000ac0 <__aeabi_d2iz>
 8005944:	2800      	cmp	r0, #0
 8005946:	d051      	beq.n	80059ec <__kernel_sin+0xcc>
 8005948:	4622      	mov	r2, r4
 800594a:	462b      	mov	r3, r5
 800594c:	4620      	mov	r0, r4
 800594e:	4629      	mov	r1, r5
 8005950:	f7fa fe06 	bl	8000560 <__aeabi_dmul>
 8005954:	4682      	mov	sl, r0
 8005956:	468b      	mov	fp, r1
 8005958:	4602      	mov	r2, r0
 800595a:	460b      	mov	r3, r1
 800595c:	4620      	mov	r0, r4
 800595e:	4629      	mov	r1, r5
 8005960:	f7fa fdfe 	bl	8000560 <__aeabi_dmul>
 8005964:	a341      	add	r3, pc, #260	; (adr r3, 8005a6c <__kernel_sin+0x14c>)
 8005966:	e9d3 2300 	ldrd	r2, r3, [r3]
 800596a:	4680      	mov	r8, r0
 800596c:	4689      	mov	r9, r1
 800596e:	4650      	mov	r0, sl
 8005970:	4659      	mov	r1, fp
 8005972:	f7fa fdf5 	bl	8000560 <__aeabi_dmul>
 8005976:	a33f      	add	r3, pc, #252	; (adr r3, 8005a74 <__kernel_sin+0x154>)
 8005978:	e9d3 2300 	ldrd	r2, r3, [r3]
 800597c:	f7fa fc38 	bl	80001f0 <__aeabi_dsub>
 8005980:	4652      	mov	r2, sl
 8005982:	465b      	mov	r3, fp
 8005984:	f7fa fdec 	bl	8000560 <__aeabi_dmul>
 8005988:	a33c      	add	r3, pc, #240	; (adr r3, 8005a7c <__kernel_sin+0x15c>)
 800598a:	e9d3 2300 	ldrd	r2, r3, [r3]
 800598e:	f7fa fc31 	bl	80001f4 <__adddf3>
 8005992:	4652      	mov	r2, sl
 8005994:	465b      	mov	r3, fp
 8005996:	f7fa fde3 	bl	8000560 <__aeabi_dmul>
 800599a:	a33a      	add	r3, pc, #232	; (adr r3, 8005a84 <__kernel_sin+0x164>)
 800599c:	e9d3 2300 	ldrd	r2, r3, [r3]
 80059a0:	f7fa fc26 	bl	80001f0 <__aeabi_dsub>
 80059a4:	4652      	mov	r2, sl
 80059a6:	465b      	mov	r3, fp
 80059a8:	f7fa fdda 	bl	8000560 <__aeabi_dmul>
 80059ac:	a337      	add	r3, pc, #220	; (adr r3, 8005a8c <__kernel_sin+0x16c>)
 80059ae:	e9d3 2300 	ldrd	r2, r3, [r3]
 80059b2:	f7fa fc1f 	bl	80001f4 <__adddf3>
 80059b6:	9b02      	ldr	r3, [sp, #8]
 80059b8:	4606      	mov	r6, r0
 80059ba:	460f      	mov	r7, r1
 80059bc:	b9db      	cbnz	r3, 80059f6 <__kernel_sin+0xd6>
 80059be:	4602      	mov	r2, r0
 80059c0:	460b      	mov	r3, r1
 80059c2:	4650      	mov	r0, sl
 80059c4:	4659      	mov	r1, fp
 80059c6:	f7fa fdcb 	bl	8000560 <__aeabi_dmul>
 80059ca:	a325      	add	r3, pc, #148	; (adr r3, 8005a60 <__kernel_sin+0x140>)
 80059cc:	e9d3 2300 	ldrd	r2, r3, [r3]
 80059d0:	f7fa fc0e 	bl	80001f0 <__aeabi_dsub>
 80059d4:	4642      	mov	r2, r8
 80059d6:	464b      	mov	r3, r9
 80059d8:	f7fa fdc2 	bl	8000560 <__aeabi_dmul>
 80059dc:	4602      	mov	r2, r0
 80059de:	460b      	mov	r3, r1
 80059e0:	4620      	mov	r0, r4
 80059e2:	4629      	mov	r1, r5
 80059e4:	f7fa fc06 	bl	80001f4 <__adddf3>
 80059e8:	4604      	mov	r4, r0
 80059ea:	460d      	mov	r5, r1
 80059ec:	ec45 4b10 	vmov	d0, r4, r5
 80059f0:	b005      	add	sp, #20
 80059f2:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 80059f6:	2200      	movs	r2, #0
 80059f8:	4b1b      	ldr	r3, [pc, #108]	; (8005a68 <__kernel_sin+0x148>)
 80059fa:	e9dd 0100 	ldrd	r0, r1, [sp]
 80059fe:	f7fa fdaf 	bl	8000560 <__aeabi_dmul>
 8005a02:	4632      	mov	r2, r6
 8005a04:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8005a08:	463b      	mov	r3, r7
 8005a0a:	4640      	mov	r0, r8
 8005a0c:	4649      	mov	r1, r9
 8005a0e:	f7fa fda7 	bl	8000560 <__aeabi_dmul>
 8005a12:	4602      	mov	r2, r0
 8005a14:	460b      	mov	r3, r1
 8005a16:	e9dd 0102 	ldrd	r0, r1, [sp, #8]
 8005a1a:	f7fa fbe9 	bl	80001f0 <__aeabi_dsub>
 8005a1e:	4652      	mov	r2, sl
 8005a20:	465b      	mov	r3, fp
 8005a22:	f7fa fd9d 	bl	8000560 <__aeabi_dmul>
 8005a26:	e9dd 2300 	ldrd	r2, r3, [sp]
 8005a2a:	f7fa fbe1 	bl	80001f0 <__aeabi_dsub>
 8005a2e:	a30c      	add	r3, pc, #48	; (adr r3, 8005a60 <__kernel_sin+0x140>)
 8005a30:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005a34:	4606      	mov	r6, r0
 8005a36:	460f      	mov	r7, r1
 8005a38:	4640      	mov	r0, r8
 8005a3a:	4649      	mov	r1, r9
 8005a3c:	f7fa fd90 	bl	8000560 <__aeabi_dmul>
 8005a40:	4602      	mov	r2, r0
 8005a42:	460b      	mov	r3, r1
 8005a44:	4630      	mov	r0, r6
 8005a46:	4639      	mov	r1, r7
 8005a48:	f7fa fbd4 	bl	80001f4 <__adddf3>
 8005a4c:	4602      	mov	r2, r0
 8005a4e:	460b      	mov	r3, r1
 8005a50:	4620      	mov	r0, r4
 8005a52:	4629      	mov	r1, r5
 8005a54:	f7fa fbcc 	bl	80001f0 <__aeabi_dsub>
 8005a58:	e7c6      	b.n	80059e8 <__kernel_sin+0xc8>
 8005a5a:	bf00      	nop
 8005a5c:	f3af 8000 	nop.w
 8005a60:	55555549 	.word	0x55555549
 8005a64:	3fc55555 	.word	0x3fc55555
 8005a68:	3fe00000 	.word	0x3fe00000
 8005a6c:	5acfd57c 	.word	0x5acfd57c
 8005a70:	3de5d93a 	.word	0x3de5d93a
 8005a74:	8a2b9ceb 	.word	0x8a2b9ceb
 8005a78:	3e5ae5e6 	.word	0x3e5ae5e6
 8005a7c:	57b1fe7d 	.word	0x57b1fe7d
 8005a80:	3ec71de3 	.word	0x3ec71de3
 8005a84:	19c161d5 	.word	0x19c161d5
 8005a88:	3f2a01a0 	.word	0x3f2a01a0
 8005a8c:	1110f8a6 	.word	0x1110f8a6
 8005a90:	3f811111 	.word	0x3f811111
 8005a94:	00000000 	.word	0x00000000

08005a98 <__kernel_tan>:
 8005a98:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8005a9c:	ec5b ab10 	vmov	sl, fp, d0
 8005aa0:	4bbf      	ldr	r3, [pc, #764]	; (8005da0 <__kernel_tan+0x308>)
 8005aa2:	b089      	sub	sp, #36	; 0x24
 8005aa4:	f02b 4700 	bic.w	r7, fp, #2147483648	; 0x80000000
 8005aa8:	429f      	cmp	r7, r3
 8005aaa:	ec59 8b11 	vmov	r8, r9, d1
 8005aae:	4606      	mov	r6, r0
 8005ab0:	f8cd b008 	str.w	fp, [sp, #8]
 8005ab4:	dc22      	bgt.n	8005afc <__kernel_tan+0x64>
 8005ab6:	ee10 0a10 	vmov	r0, s0
 8005aba:	4659      	mov	r1, fp
 8005abc:	f7fb f800 	bl	8000ac0 <__aeabi_d2iz>
 8005ac0:	2800      	cmp	r0, #0
 8005ac2:	d145      	bne.n	8005b50 <__kernel_tan+0xb8>
 8005ac4:	1c73      	adds	r3, r6, #1
 8005ac6:	4652      	mov	r2, sl
 8005ac8:	4313      	orrs	r3, r2
 8005aca:	433b      	orrs	r3, r7
 8005acc:	d110      	bne.n	8005af0 <__kernel_tan+0x58>
 8005ace:	ec4b ab10 	vmov	d0, sl, fp
 8005ad2:	f000 f9ad 	bl	8005e30 <fabs>
 8005ad6:	49b3      	ldr	r1, [pc, #716]	; (8005da4 <__kernel_tan+0x30c>)
 8005ad8:	ec53 2b10 	vmov	r2, r3, d0
 8005adc:	2000      	movs	r0, #0
 8005ade:	f7fa fe69 	bl	80007b4 <__aeabi_ddiv>
 8005ae2:	4682      	mov	sl, r0
 8005ae4:	468b      	mov	fp, r1
 8005ae6:	ec4b ab10 	vmov	d0, sl, fp
 8005aea:	b009      	add	sp, #36	; 0x24
 8005aec:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
 8005af0:	2e01      	cmp	r6, #1
 8005af2:	d0f8      	beq.n	8005ae6 <__kernel_tan+0x4e>
 8005af4:	465b      	mov	r3, fp
 8005af6:	2000      	movs	r0, #0
 8005af8:	49ab      	ldr	r1, [pc, #684]	; (8005da8 <__kernel_tan+0x310>)
 8005afa:	e7f0      	b.n	8005ade <__kernel_tan+0x46>
 8005afc:	4bab      	ldr	r3, [pc, #684]	; (8005dac <__kernel_tan+0x314>)
 8005afe:	429f      	cmp	r7, r3
 8005b00:	dd26      	ble.n	8005b50 <__kernel_tan+0xb8>
 8005b02:	9b02      	ldr	r3, [sp, #8]
 8005b04:	2b00      	cmp	r3, #0
 8005b06:	da09      	bge.n	8005b1c <__kernel_tan+0x84>
 8005b08:	f10b 4300 	add.w	r3, fp, #2147483648	; 0x80000000
 8005b0c:	469b      	mov	fp, r3
 8005b0e:	ee10 aa10 	vmov	sl, s0
 8005b12:	f109 4300 	add.w	r3, r9, #2147483648	; 0x80000000
 8005b16:	ee11 8a10 	vmov	r8, s2
 8005b1a:	4699      	mov	r9, r3
 8005b1c:	4652      	mov	r2, sl
 8005b1e:	465b      	mov	r3, fp
 8005b20:	a181      	add	r1, pc, #516	; (adr r1, 8005d28 <__kernel_tan+0x290>)
 8005b22:	e9d1 0100 	ldrd	r0, r1, [r1]
 8005b26:	f7fa fb63 	bl	80001f0 <__aeabi_dsub>
 8005b2a:	4642      	mov	r2, r8
 8005b2c:	464b      	mov	r3, r9
 8005b2e:	4604      	mov	r4, r0
 8005b30:	460d      	mov	r5, r1
 8005b32:	a17f      	add	r1, pc, #508	; (adr r1, 8005d30 <__kernel_tan+0x298>)
 8005b34:	e9d1 0100 	ldrd	r0, r1, [r1]
 8005b38:	f7fa fb5a 	bl	80001f0 <__aeabi_dsub>
 8005b3c:	4622      	mov	r2, r4
 8005b3e:	462b      	mov	r3, r5
 8005b40:	f7fa fb58 	bl	80001f4 <__adddf3>
 8005b44:	f04f 0800 	mov.w	r8, #0
 8005b48:	4682      	mov	sl, r0
 8005b4a:	468b      	mov	fp, r1
 8005b4c:	f04f 0900 	mov.w	r9, #0
 8005b50:	4652      	mov	r2, sl
 8005b52:	465b      	mov	r3, fp
 8005b54:	4650      	mov	r0, sl
 8005b56:	4659      	mov	r1, fp
 8005b58:	f7fa fd02 	bl	8000560 <__aeabi_dmul>
 8005b5c:	4602      	mov	r2, r0
 8005b5e:	460b      	mov	r3, r1
 8005b60:	e9cd 0100 	strd	r0, r1, [sp]
 8005b64:	f7fa fcfc 	bl	8000560 <__aeabi_dmul>
 8005b68:	e9dd 2300 	ldrd	r2, r3, [sp]
 8005b6c:	4604      	mov	r4, r0
 8005b6e:	460d      	mov	r5, r1
 8005b70:	4650      	mov	r0, sl
 8005b72:	4659      	mov	r1, fp
 8005b74:	f7fa fcf4 	bl	8000560 <__aeabi_dmul>
 8005b78:	a36f      	add	r3, pc, #444	; (adr r3, 8005d38 <__kernel_tan+0x2a0>)
 8005b7a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005b7e:	e9cd 0104 	strd	r0, r1, [sp, #16]
 8005b82:	4620      	mov	r0, r4
 8005b84:	4629      	mov	r1, r5
 8005b86:	f7fa fceb 	bl	8000560 <__aeabi_dmul>
 8005b8a:	a36d      	add	r3, pc, #436	; (adr r3, 8005d40 <__kernel_tan+0x2a8>)
 8005b8c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005b90:	f7fa fb30 	bl	80001f4 <__adddf3>
 8005b94:	4622      	mov	r2, r4
 8005b96:	462b      	mov	r3, r5
 8005b98:	f7fa fce2 	bl	8000560 <__aeabi_dmul>
 8005b9c:	a36a      	add	r3, pc, #424	; (adr r3, 8005d48 <__kernel_tan+0x2b0>)
 8005b9e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005ba2:	f7fa fb27 	bl	80001f4 <__adddf3>
 8005ba6:	4622      	mov	r2, r4
 8005ba8:	462b      	mov	r3, r5
 8005baa:	f7fa fcd9 	bl	8000560 <__aeabi_dmul>
 8005bae:	a368      	add	r3, pc, #416	; (adr r3, 8005d50 <__kernel_tan+0x2b8>)
 8005bb0:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005bb4:	f7fa fb1e 	bl	80001f4 <__adddf3>
 8005bb8:	4622      	mov	r2, r4
 8005bba:	462b      	mov	r3, r5
 8005bbc:	f7fa fcd0 	bl	8000560 <__aeabi_dmul>
 8005bc0:	a365      	add	r3, pc, #404	; (adr r3, 8005d58 <__kernel_tan+0x2c0>)
 8005bc2:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005bc6:	f7fa fb15 	bl	80001f4 <__adddf3>
 8005bca:	4622      	mov	r2, r4
 8005bcc:	462b      	mov	r3, r5
 8005bce:	f7fa fcc7 	bl	8000560 <__aeabi_dmul>
 8005bd2:	a363      	add	r3, pc, #396	; (adr r3, 8005d60 <__kernel_tan+0x2c8>)
 8005bd4:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005bd8:	f7fa fb0c 	bl	80001f4 <__adddf3>
 8005bdc:	e9dd 2300 	ldrd	r2, r3, [sp]
 8005be0:	f7fa fcbe 	bl	8000560 <__aeabi_dmul>
 8005be4:	a360      	add	r3, pc, #384	; (adr r3, 8005d68 <__kernel_tan+0x2d0>)
 8005be6:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005bea:	e9cd 0106 	strd	r0, r1, [sp, #24]
 8005bee:	4620      	mov	r0, r4
 8005bf0:	4629      	mov	r1, r5
 8005bf2:	f7fa fcb5 	bl	8000560 <__aeabi_dmul>
 8005bf6:	a35e      	add	r3, pc, #376	; (adr r3, 8005d70 <__kernel_tan+0x2d8>)
 8005bf8:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005bfc:	f7fa fafa 	bl	80001f4 <__adddf3>
 8005c00:	4622      	mov	r2, r4
 8005c02:	462b      	mov	r3, r5
 8005c04:	f7fa fcac 	bl	8000560 <__aeabi_dmul>
 8005c08:	a35b      	add	r3, pc, #364	; (adr r3, 8005d78 <__kernel_tan+0x2e0>)
 8005c0a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005c0e:	f7fa faf1 	bl	80001f4 <__adddf3>
 8005c12:	4622      	mov	r2, r4
 8005c14:	462b      	mov	r3, r5
 8005c16:	f7fa fca3 	bl	8000560 <__aeabi_dmul>
 8005c1a:	a359      	add	r3, pc, #356	; (adr r3, 8005d80 <__kernel_tan+0x2e8>)
 8005c1c:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005c20:	f7fa fae8 	bl	80001f4 <__adddf3>
 8005c24:	4622      	mov	r2, r4
 8005c26:	462b      	mov	r3, r5
 8005c28:	f7fa fc9a 	bl	8000560 <__aeabi_dmul>
 8005c2c:	a356      	add	r3, pc, #344	; (adr r3, 8005d88 <__kernel_tan+0x2f0>)
 8005c2e:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005c32:	f7fa fadf 	bl	80001f4 <__adddf3>
 8005c36:	4622      	mov	r2, r4
 8005c38:	462b      	mov	r3, r5
 8005c3a:	f7fa fc91 	bl	8000560 <__aeabi_dmul>
 8005c3e:	a354      	add	r3, pc, #336	; (adr r3, 8005d90 <__kernel_tan+0x2f8>)
 8005c40:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005c44:	f7fa fad6 	bl	80001f4 <__adddf3>
 8005c48:	4602      	mov	r2, r0
 8005c4a:	460b      	mov	r3, r1
 8005c4c:	e9dd 0106 	ldrd	r0, r1, [sp, #24]
 8005c50:	f7fa fad0 	bl	80001f4 <__adddf3>
 8005c54:	e9dd 2304 	ldrd	r2, r3, [sp, #16]
 8005c58:	f7fa fc82 	bl	8000560 <__aeabi_dmul>
 8005c5c:	4642      	mov	r2, r8
 8005c5e:	464b      	mov	r3, r9
 8005c60:	f7fa fac8 	bl	80001f4 <__adddf3>
 8005c64:	e9dd 2300 	ldrd	r2, r3, [sp]
 8005c68:	f7fa fc7a 	bl	8000560 <__aeabi_dmul>
 8005c6c:	4642      	mov	r2, r8
 8005c6e:	464b      	mov	r3, r9
 8005c70:	f7fa fac0 	bl	80001f4 <__adddf3>
 8005c74:	a348      	add	r3, pc, #288	; (adr r3, 8005d98 <__kernel_tan+0x300>)
 8005c76:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005c7a:	4604      	mov	r4, r0
 8005c7c:	460d      	mov	r5, r1
 8005c7e:	e9dd 0104 	ldrd	r0, r1, [sp, #16]
 8005c82:	f7fa fc6d 	bl	8000560 <__aeabi_dmul>
 8005c86:	4622      	mov	r2, r4
 8005c88:	462b      	mov	r3, r5
 8005c8a:	f7fa fab3 	bl	80001f4 <__adddf3>
 8005c8e:	e9cd 0100 	strd	r0, r1, [sp]
 8005c92:	460b      	mov	r3, r1
 8005c94:	4602      	mov	r2, r0
 8005c96:	4659      	mov	r1, fp
 8005c98:	4650      	mov	r0, sl
 8005c9a:	f7fa faab 	bl	80001f4 <__adddf3>
 8005c9e:	4b43      	ldr	r3, [pc, #268]	; (8005dac <__kernel_tan+0x314>)
 8005ca0:	429f      	cmp	r7, r3
 8005ca2:	4604      	mov	r4, r0
 8005ca4:	460d      	mov	r5, r1
 8005ca6:	f340 8083 	ble.w	8005db0 <__kernel_tan+0x318>
 8005caa:	4630      	mov	r0, r6
 8005cac:	f7fa fbee 	bl	800048c <__aeabi_i2d>
 8005cb0:	4622      	mov	r2, r4
 8005cb2:	4680      	mov	r8, r0
 8005cb4:	4689      	mov	r9, r1
 8005cb6:	462b      	mov	r3, r5
 8005cb8:	4620      	mov	r0, r4
 8005cba:	4629      	mov	r1, r5
 8005cbc:	f7fa fc50 	bl	8000560 <__aeabi_dmul>
 8005cc0:	4642      	mov	r2, r8
 8005cc2:	4606      	mov	r6, r0
 8005cc4:	460f      	mov	r7, r1
 8005cc6:	464b      	mov	r3, r9
 8005cc8:	4620      	mov	r0, r4
 8005cca:	4629      	mov	r1, r5
 8005ccc:	f7fa fa92 	bl	80001f4 <__adddf3>
 8005cd0:	4602      	mov	r2, r0
 8005cd2:	460b      	mov	r3, r1
 8005cd4:	4630      	mov	r0, r6
 8005cd6:	4639      	mov	r1, r7
 8005cd8:	f7fa fd6c 	bl	80007b4 <__aeabi_ddiv>
 8005cdc:	e9dd 2300 	ldrd	r2, r3, [sp]
 8005ce0:	f7fa fa86 	bl	80001f0 <__aeabi_dsub>
 8005ce4:	4602      	mov	r2, r0
 8005ce6:	460b      	mov	r3, r1
 8005ce8:	4650      	mov	r0, sl
 8005cea:	4659      	mov	r1, fp
 8005cec:	f7fa fa80 	bl	80001f0 <__aeabi_dsub>
 8005cf0:	4602      	mov	r2, r0
 8005cf2:	460b      	mov	r3, r1
 8005cf4:	f7fa fa7e 	bl	80001f4 <__adddf3>
 8005cf8:	4602      	mov	r2, r0
 8005cfa:	460b      	mov	r3, r1
 8005cfc:	4640      	mov	r0, r8
 8005cfe:	4649      	mov	r1, r9
 8005d00:	f7fa fa76 	bl	80001f0 <__aeabi_dsub>
 8005d04:	9b02      	ldr	r3, [sp, #8]
 8005d06:	4604      	mov	r4, r0
 8005d08:	1798      	asrs	r0, r3, #30
 8005d0a:	f000 0002 	and.w	r0, r0, #2
 8005d0e:	f1c0 0001 	rsb	r0, r0, #1
 8005d12:	460d      	mov	r5, r1
 8005d14:	f7fa fbba 	bl	800048c <__aeabi_i2d>
 8005d18:	4602      	mov	r2, r0
 8005d1a:	460b      	mov	r3, r1
 8005d1c:	4620      	mov	r0, r4
 8005d1e:	4629      	mov	r1, r5
 8005d20:	f7fa fc1e 	bl	8000560 <__aeabi_dmul>
 8005d24:	e6dd      	b.n	8005ae2 <__kernel_tan+0x4a>
 8005d26:	bf00      	nop
 8005d28:	54442d18 	.word	0x54442d18
 8005d2c:	3fe921fb 	.word	0x3fe921fb
 8005d30:	33145c07 	.word	0x33145c07
 8005d34:	3c81a626 	.word	0x3c81a626
 8005d38:	74bf7ad4 	.word	0x74bf7ad4
 8005d3c:	3efb2a70 	.word	0x3efb2a70
 8005d40:	32f0a7e9 	.word	0x32f0a7e9
 8005d44:	3f12b80f 	.word	0x3f12b80f
 8005d48:	1a8d1068 	.word	0x1a8d1068
 8005d4c:	3f3026f7 	.word	0x3f3026f7
 8005d50:	fee08315 	.word	0xfee08315
 8005d54:	3f57dbc8 	.word	0x3f57dbc8
 8005d58:	e96e8493 	.word	0xe96e8493
 8005d5c:	3f8226e3 	.word	0x3f8226e3
 8005d60:	1bb341fe 	.word	0x1bb341fe
 8005d64:	3faba1ba 	.word	0x3faba1ba
 8005d68:	db605373 	.word	0xdb605373
 8005d6c:	bef375cb 	.word	0xbef375cb
 8005d70:	a03792a6 	.word	0xa03792a6
 8005d74:	3f147e88 	.word	0x3f147e88
 8005d78:	f2f26501 	.word	0xf2f26501
 8005d7c:	3f4344d8 	.word	0x3f4344d8
 8005d80:	c9560328 	.word	0xc9560328
 8005d84:	3f6d6d22 	.word	0x3f6d6d22
 8005d88:	8406d637 	.word	0x8406d637
 8005d8c:	3f9664f4 	.word	0x3f9664f4
 8005d90:	1110fe7a 	.word	0x1110fe7a
 8005d94:	3fc11111 	.word	0x3fc11111
 8005d98:	55555563 	.word	0x55555563
 8005d9c:	3fd55555 	.word	0x3fd55555
 8005da0:	3e2fffff 	.word	0x3e2fffff
 8005da4:	3ff00000 	.word	0x3ff00000
 8005da8:	bff00000 	.word	0xbff00000
 8005dac:	3fe59427 	.word	0x3fe59427
 8005db0:	2e01      	cmp	r6, #1
 8005db2:	d036      	beq.n	8005e22 <__kernel_tan+0x38a>
 8005db4:	460f      	mov	r7, r1
 8005db6:	4602      	mov	r2, r0
 8005db8:	460b      	mov	r3, r1
 8005dba:	2000      	movs	r0, #0
 8005dbc:	491a      	ldr	r1, [pc, #104]	; (8005e28 <__kernel_tan+0x390>)
 8005dbe:	f7fa fcf9 	bl	80007b4 <__aeabi_ddiv>
 8005dc2:	2600      	movs	r6, #0
 8005dc4:	e9cd 0102 	strd	r0, r1, [sp, #8]
 8005dc8:	4652      	mov	r2, sl
 8005dca:	465b      	mov	r3, fp
 8005dcc:	4630      	mov	r0, r6
 8005dce:	4639      	mov	r1, r7
 8005dd0:	f7fa fa0e 	bl	80001f0 <__aeabi_dsub>
 8005dd4:	e9dd 4502 	ldrd	r4, r5, [sp, #8]
 8005dd8:	4602      	mov	r2, r0
 8005dda:	460b      	mov	r3, r1
 8005ddc:	e9dd 0100 	ldrd	r0, r1, [sp]
 8005de0:	f7fa fa06 	bl	80001f0 <__aeabi_dsub>
 8005de4:	4632      	mov	r2, r6
 8005de6:	462b      	mov	r3, r5
 8005de8:	f7fa fbba 	bl	8000560 <__aeabi_dmul>
 8005dec:	4632      	mov	r2, r6
 8005dee:	4682      	mov	sl, r0
 8005df0:	468b      	mov	fp, r1
 8005df2:	462b      	mov	r3, r5
 8005df4:	4630      	mov	r0, r6
 8005df6:	4639      	mov	r1, r7
 8005df8:	f7fa fbb2 	bl	8000560 <__aeabi_dmul>
 8005dfc:	2200      	movs	r2, #0
 8005dfe:	4b0b      	ldr	r3, [pc, #44]	; (8005e2c <__kernel_tan+0x394>)
 8005e00:	f7fa f9f8 	bl	80001f4 <__adddf3>
 8005e04:	4602      	mov	r2, r0
 8005e06:	460b      	mov	r3, r1
 8005e08:	4650      	mov	r0, sl
 8005e0a:	4659      	mov	r1, fp
 8005e0c:	f7fa f9f2 	bl	80001f4 <__adddf3>
 8005e10:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8005e14:	f7fa fba4 	bl	8000560 <__aeabi_dmul>
 8005e18:	4632      	mov	r2, r6
 8005e1a:	462b      	mov	r3, r5
 8005e1c:	f7fa f9ea 	bl	80001f4 <__adddf3>
 8005e20:	e65f      	b.n	8005ae2 <__kernel_tan+0x4a>
 8005e22:	4682      	mov	sl, r0
 8005e24:	468b      	mov	fp, r1
 8005e26:	e65e      	b.n	8005ae6 <__kernel_tan+0x4e>
 8005e28:	bff00000 	.word	0xbff00000
 8005e2c:	3ff00000 	.word	0x3ff00000

08005e30 <fabs>:
 8005e30:	ec51 0b10 	vmov	r0, r1, d0
 8005e34:	ee10 2a10 	vmov	r2, s0
 8005e38:	f021 4300 	bic.w	r3, r1, #2147483648	; 0x80000000
 8005e3c:	ec43 2b10 	vmov	d0, r2, r3
 8005e40:	4770      	bx	lr

08005e42 <matherr>:
 8005e42:	2000      	movs	r0, #0
 8005e44:	4770      	bx	lr
	...

08005e48 <nan>:
 8005e48:	ed9f 0b01 	vldr	d0, [pc, #4]	; 8005e50 <nan+0x8>
 8005e4c:	4770      	bx	lr
 8005e4e:	bf00      	nop
 8005e50:	00000000 	.word	0x00000000
 8005e54:	7ff80000 	.word	0x7ff80000

08005e58 <scalbn>:
 8005e58:	b570      	push	{r4, r5, r6, lr}
 8005e5a:	ec55 4b10 	vmov	r4, r5, d0
 8005e5e:	f3c5 520a 	ubfx	r2, r5, #20, #11
 8005e62:	4606      	mov	r6, r0
 8005e64:	462b      	mov	r3, r5
 8005e66:	b9aa      	cbnz	r2, 8005e94 <scalbn+0x3c>
 8005e68:	f025 4300 	bic.w	r3, r5, #2147483648	; 0x80000000
 8005e6c:	4323      	orrs	r3, r4
 8005e6e:	d03b      	beq.n	8005ee8 <scalbn+0x90>
 8005e70:	4b31      	ldr	r3, [pc, #196]	; (8005f38 <scalbn+0xe0>)
 8005e72:	4629      	mov	r1, r5
 8005e74:	2200      	movs	r2, #0
 8005e76:	ee10 0a10 	vmov	r0, s0
 8005e7a:	f7fa fb71 	bl	8000560 <__aeabi_dmul>
 8005e7e:	4b2f      	ldr	r3, [pc, #188]	; (8005f3c <scalbn+0xe4>)
 8005e80:	429e      	cmp	r6, r3
 8005e82:	4604      	mov	r4, r0
 8005e84:	460d      	mov	r5, r1
 8005e86:	da12      	bge.n	8005eae <scalbn+0x56>
 8005e88:	a327      	add	r3, pc, #156	; (adr r3, 8005f28 <scalbn+0xd0>)
 8005e8a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005e8e:	f7fa fb67 	bl	8000560 <__aeabi_dmul>
 8005e92:	e009      	b.n	8005ea8 <scalbn+0x50>
 8005e94:	f240 71ff 	movw	r1, #2047	; 0x7ff
 8005e98:	428a      	cmp	r2, r1
 8005e9a:	d10c      	bne.n	8005eb6 <scalbn+0x5e>
 8005e9c:	ee10 2a10 	vmov	r2, s0
 8005ea0:	4620      	mov	r0, r4
 8005ea2:	4629      	mov	r1, r5
 8005ea4:	f7fa f9a6 	bl	80001f4 <__adddf3>
 8005ea8:	4604      	mov	r4, r0
 8005eaa:	460d      	mov	r5, r1
 8005eac:	e01c      	b.n	8005ee8 <scalbn+0x90>
 8005eae:	f3c1 520a 	ubfx	r2, r1, #20, #11
 8005eb2:	460b      	mov	r3, r1
 8005eb4:	3a36      	subs	r2, #54	; 0x36
 8005eb6:	4432      	add	r2, r6
 8005eb8:	f240 71fe 	movw	r1, #2046	; 0x7fe
 8005ebc:	428a      	cmp	r2, r1
 8005ebe:	dd0b      	ble.n	8005ed8 <scalbn+0x80>
 8005ec0:	ec45 4b11 	vmov	d1, r4, r5
 8005ec4:	ed9f 0b1a 	vldr	d0, [pc, #104]	; 8005f30 <scalbn+0xd8>
 8005ec8:	f000 f83c 	bl	8005f44 <copysign>
 8005ecc:	a318      	add	r3, pc, #96	; (adr r3, 8005f30 <scalbn+0xd8>)
 8005ece:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005ed2:	ec51 0b10 	vmov	r0, r1, d0
 8005ed6:	e7da      	b.n	8005e8e <scalbn+0x36>
 8005ed8:	2a00      	cmp	r2, #0
 8005eda:	dd08      	ble.n	8005eee <scalbn+0x96>
 8005edc:	f023 43ff 	bic.w	r3, r3, #2139095040	; 0x7f800000
 8005ee0:	f423 03e0 	bic.w	r3, r3, #7340032	; 0x700000
 8005ee4:	ea43 5502 	orr.w	r5, r3, r2, lsl #20
 8005ee8:	ec45 4b10 	vmov	d0, r4, r5
 8005eec:	bd70      	pop	{r4, r5, r6, pc}
 8005eee:	f112 0f35 	cmn.w	r2, #53	; 0x35
 8005ef2:	da0d      	bge.n	8005f10 <scalbn+0xb8>
 8005ef4:	f24c 3350 	movw	r3, #50000	; 0xc350
 8005ef8:	429e      	cmp	r6, r3
 8005efa:	ec45 4b11 	vmov	d1, r4, r5
 8005efe:	dce1      	bgt.n	8005ec4 <scalbn+0x6c>
 8005f00:	ed9f 0b09 	vldr	d0, [pc, #36]	; 8005f28 <scalbn+0xd0>
 8005f04:	f000 f81e 	bl	8005f44 <copysign>
 8005f08:	a307      	add	r3, pc, #28	; (adr r3, 8005f28 <scalbn+0xd0>)
 8005f0a:	e9d3 2300 	ldrd	r2, r3, [r3]
 8005f0e:	e7e0      	b.n	8005ed2 <scalbn+0x7a>
 8005f10:	f023 43ff 	bic.w	r3, r3, #2139095040	; 0x7f800000
 8005f14:	3236      	adds	r2, #54	; 0x36
 8005f16:	f423 03e0 	bic.w	r3, r3, #7340032	; 0x700000
 8005f1a:	ea43 5502 	orr.w	r5, r3, r2, lsl #20
 8005f1e:	4620      	mov	r0, r4
 8005f20:	4629      	mov	r1, r5
 8005f22:	2200      	movs	r2, #0
 8005f24:	4b06      	ldr	r3, [pc, #24]	; (8005f40 <scalbn+0xe8>)
 8005f26:	e7b2      	b.n	8005e8e <scalbn+0x36>
 8005f28:	c2f8f359 	.word	0xc2f8f359
 8005f2c:	01a56e1f 	.word	0x01a56e1f
 8005f30:	8800759c 	.word	0x8800759c
 8005f34:	7e37e43c 	.word	0x7e37e43c
 8005f38:	43500000 	.word	0x43500000
 8005f3c:	ffff3cb0 	.word	0xffff3cb0
 8005f40:	3c900000 	.word	0x3c900000

08005f44 <copysign>:
 8005f44:	ec51 0b10 	vmov	r0, r1, d0
 8005f48:	ee11 0a90 	vmov	r0, s3
 8005f4c:	ee10 2a10 	vmov	r2, s0
 8005f50:	f021 4100 	bic.w	r1, r1, #2147483648	; 0x80000000
 8005f54:	f000 4000 	and.w	r0, r0, #2147483648	; 0x80000000
 8005f58:	ea41 0300 	orr.w	r3, r1, r0
 8005f5c:	ec43 2b10 	vmov	d0, r2, r3
 8005f60:	4770      	bx	lr
	...

08005f64 <_init>:
 8005f64:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8005f66:	bf00      	nop
 8005f68:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8005f6a:	bc08      	pop	{r3}
 8005f6c:	469e      	mov	lr, r3
 8005f6e:	4770      	bx	lr

08005f70 <_fini>:
 8005f70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8005f72:	bf00      	nop
 8005f74:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8005f76:	bc08      	pop	{r3}
 8005f78:	469e      	mov	lr, r3
 8005f7a:	4770      	bx	lr