Finished Task Rand in vhdl

This commit is contained in:
schoeffelbe82781 2024-12-04 09:37:28 +01:00
parent 4cb356e25b
commit a980ef180e

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@ -60,6 +60,9 @@ begin
end process task_state_transitions;
sync : process ( clk, reset ) is
variable var_lsfr_logic : std_logic_vector( 31 downto 0);
variable var_lsfr_signed : SIGNED( 31 downto 0);
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
@ -85,21 +88,24 @@ begin
case Calc_State is
when CALC_IDLE =>
signal_write <= '0';
lsfr_std_logic <= STD_LOGIC_VECTOR(lsfr);
if(lsfr_std_logic(0) = '1') then
lsfr <= SIGNED(lsfr_std_logic srl 1);
lsfr <= SIGNED(lsfr_std_logic XOR POLYNOM);
var_lsfr_logic := STD_LOGIC_VECTOR(lsfr);
if(var_lsfr_logic(0) = '1') then
var_lsfr_logic := '0' & (var_lsfr_logic(31 downto 1));
--var_lsfr_logic := (var_lsfr_logic(31:1);
var_lsfr_logic := (var_lsfr_logic XOR POLYNOM);
else
lsfr <= SIGNED(lsfr_std_logic srl 1);
--var_lsfr_logic := (var_lsfr_logic srl 1);
var_lsfr_logic := '0' & var_lsfr_logic(31 downto 1);
end if;
lsfr <= SIGNED(lsfr_std_logic);
lsfr_dump <= lsfr;
var_lsfr_signed := SIGNED(var_lsfr_logic);
lsfr_dump <= SIGNED(var_lsfr_logic);
if(lsfr_std_logic(30) = '1') then
lsfr <= lsfr(31 downto 31) & "1000000" & lsfr(23 downto 0);
if(var_lsfr_signed(30) = '1') then
var_lsfr_signed := var_lsfr_signed(31 downto 31) & "1000000" & var_lsfr_signed(23 downto 0);
else
lsfr <= lsfr(31 downto 31) & "011111" & lsfr(24 downto 0);
var_lsfr_signed := var_lsfr_signed(31 downto 31) & "011111" & var_lsfr_signed(24 downto 0);
end if;
lsfr <= var_lsfr_signed;
Calc_State <= CALC_WRITE;
when CALC_WRITE =>
signal_write <= '1';