Versuch add abgeschlossen. Funktioniert auch praktisch!

hardware/signal_processing/add.vhd

@@ -13,8 +13,8 @@ entity add is
 
         task_start : in std_logic;
         task_state : out work.task.State;
-
-        signal_a_read : out std_logic;
+					
+        signal_a_read : out std_logic;				--signal_read wird als Bestätigung gesetzt, dass die Daten gelesen wurden, d.h. bei der nächsten rising edge werden die nächsten Daten angelegt.
         signal_a_readdata : in std_logic_vector( 31 downto 0 );
 
         signal_b_read : out std_logic;
@@ -30,7 +30,39 @@ architecture rtl of add is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	--hier noch einige Signale anlegen
+	signal done_flag  : std_logic;
+	signal start_flag : std_logic;
+
+	--Zustände für die Zustandsmaschine für die Berechnung
+	type CalcState is (
+		CALC_IDLE,
+		CALC_ADD,
+		CALC_STORE_RESULT
+	);
+
+	--Signale für die Zustandsmaschine für die Berechnung
+	signal current_calc_state : CalcState;
+	signal next_calc_state : CalcState;
+
+	signal ergebnis : signed( 31 downto 0);	--das hier vielleicht zu std_logic_vector oder float
+	signal ergebnis_valid : std_logic;
+
 begin
+
+	u_float_add : entity work.float_add --Das hier ist der IP Core !!!
+	port map(
+		clk =>		clk,
+		reset =>	reset,
+		start =>	start_flag,
+		done =>		done_flag,
+		A =>		signal_a_readdata,
+		B =>		signal_b_readdata,
+		sum =>		signal_writedata
+	);
+
+    --task_state_transitions wird nicht geaendert
+    --Übergangsschaltnetz der Zustandsmaschine zu Steuerung der Tasks
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -40,7 +72,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN  ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -50,28 +82,76 @@ begin
         end case;
     end process task_state_transitions;
 
-    sync : process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            current_task_state <= work.task.TASK_IDLE;
-            index <= 0;
-        elsif ( rising_edge( clk ) ) then
-            current_task_state <= next_task_state;
-            case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
-            when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
-            end case;
-        end if;
-    end process sync;
+	
+	--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Fertig
+	calc_state_transitions: process (all) is
+	begin
+		next_calc_state <= current_calc_state; 
+		case current_calc_state is
+			when CALC_IDLE=>
+				if (current_task_state= work.task.TASK_RUNNING) then 
+					next_calc_state <= CALC_ADD;
+				end if;
+			when CALC_ADD =>
+				if (done_flag = '1') then
+					next_calc_state <= CALC_STORE_RESULT;
+				end if;
+			when CALC_STORE_RESULT =>
+				next_calc_state <= CALC_IDLE;
+		end case;
+	end process calc_state_transitions;
 
-    task_state <= current_task_state;
+
+	--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks 
+	task_sync : process (clk, reset) is
+	begin
+		if (reset = '1') then
+			current_task_state <= work.task.TASK_IDLE;
+			
+		elsif (rising_edge( clk)) then
+			current_task_state <= next_task_state; 
+			case next_task_state is
+				when work.task. TASK_IDLE => null;
+				when work.task. TASK_RUNNING => null; 
+				when work.task. TASK_DONE => null;
+			end case;
+		end if;
+	end process task_sync;
+
+	--Zustandsspeicher und Ausgangsschaltnetz zu Berechnung 
+	sync : process (clk, reset) is
+	begin
+		if (reset = '1') then
+			index <= 0;
+			current_calc_state <= CALC_IDLE;
+			ergebnis <= (others => '0'); 
+			ergebnis_valid <= '0';
+			signal_write <= '0';
+			--signal_writedata <= (others => '0'); 
+			signal_a_read <= '0';
+			signal_b_read <= '0';
+		elsif (rising_edge( clk)) then
+			current_calc_state <= next_calc_state; 
+			ergebnis_valid <= '0';
+			case next_calc_state is 
+				when CALC_IDLE =>
+					start_flag <= '0';
+					signal_a_read <= '0';	--Daten wurden noch nicht verwendet.
+					signal_b_read <= '0';
+					signal_write <= '0';
+				when CALC_ADD => 				--hier Berechnung mit IP Core?
+					start_flag <= '1';
+				when CALC_STORE_RESULT =>
+					start_flag <= '0';
+					index <= index + 1;
+					signal_write <= '1';
+					--signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core anschliessen
+					--mitteilen, dass die Daten gelesen wurden und jetzt neue Daten angelegt werden sollen
+					signal_a_read <= '1';	
+					signal_b_read <= '1';
+			end case;
+		end if;
+	end process sync;
+	task_state <= current_task_state;
 
 end architecture rtl;

hardware/signal_processing/fft.vhd

@@ -1,26 +1,13 @@
 ------------------------------------------------------------------------
 -- fft
 --
--- calculation of FFT magnitudes
+-- calculation of FFT magnitude
 --
 -- Inputs:
 -- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
 --
 -- Outputs
 -- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
--- 
---
--- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor 
--- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist) 
--- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln 
--- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0) 
--- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich) 
--- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float) 
--- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32). 
--- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist) 
--- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html) 
--- (z.B: ein Array verwenden, um die Werte zu sortieren)
--- Dann das Ergebnis in den Ausgangsfifo speichern 
 --
 -----------------------------------------------------------------------
 library ieee;
@@ -35,10 +22,10 @@ library work;
 entity fft is
   generic (
 
-    -- input data width of real/img part 
+    -- input data width of real/img part
       input_data_width : integer := 32;
 
-    -- output data width of real/img part 
+    -- output data width of real/img part
       output_data_width : integer := 32
 
     );
@@ -48,10 +35,10 @@ entity fft is
 
         task_start : in std_logic;
         task_state : out work.task.State;
-	  
+
         signal_read : out std_logic;
         signal_readdata : in std_logic_vector( 31 downto 0 );
-		  
+
         signal_write : out std_logic;
         signal_writedata : out std_logic_vector( 31 downto 0 )
     );
@@ -59,103 +46,12 @@ end entity fft;
 
 architecture rtl of fft is
 
-
--- Signale für Task State Machine
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
-    --signal index : integer range 0 to 2000;
 
--- component des Verilog IP-Cores fuer die FFT
-component fftmain is
-	port(
-		clock: in std_logic; -- Master Clock
-		reset: in std_logic; -- Active High Asynchronous Reset
-		di_en: in std_logic; --  Input Data Enable
-		di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
-                di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
-		do_en: out std_logic; -- Output Data Enable
-		do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
-                do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
-	);
-end component;
-
---  Signale Input skaliert
-    signal fft_float_input : signed( 31 downto 0 ); 
-    signal fft_float_scaled_input : signed( 31 downto 0 ); 
-
--- Signale fuer FFT-IP Core
-    -- fft data input signal
-    signal fft_input_data_enable: std_logic;
-    signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
-    signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
-    -- fft output data
-    signal fft_output_valid : std_logic;
-    signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
-    signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
-
--- Signale fuer Magnitude IP-Core
-    signal fft_mag_calc_valid : std_logic;	
-    signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
-
--- Signale fuer Ergebnis skaliert
-    signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);	
-    signal fft_float_scaled : signed( 31 downto 0 ); 
-	 
--- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
-	
-    signal data_memory : work.reg32.RegArray( 0 to 1023 );
-    signal index_reversed : std_logic_vector(9 downto 0);
-    signal index_output_sv : std_logic_vector(9 downto 0);
-    signal index_output : integer range 0 to 1023;
-
--- Signal um in den Write FIFO zu schreiben
-    signal wr_fifo : std_logic;	 
-	  
 begin
-    
-    -----------------------------------------------------------------------------------------------
-    -- Hier muss der Verilog FFT IP-Core instanziert werden
-    -----------------------------------------------------------------------------------------------
-
-    --u_fft : fftmain
-    --    port map (		      
-    --        clock => , -- system clock				
-    --        reset => , -- Active High Asynchronous Reset				    
-    --	    di_en => , -- Input Data Enable
-    --	    di_re => , -- Input Data (Real)
-    --      di_im => , -- Input Data (Imag)				
-    --      do_en => , -- Output Data Enable				
-    --	    do_re => , -- Output Data (Real)
-    --      do_im =>  -- Output Data (Imag)
-    --    ); 
-    
-    fft_output_valid <= '0';
-    data_out_re <= (others => '0');
-    data_out_im <= (others => '0');
-
-    -----------------------------------------------------------------------------------------------
-    -- Hier muss der VHDL Magnitue IP-COre instanziert werden
-    -----------------------------------------------------------------------------------------------
-			 
-    -- u_fft_mag_calc : entity work.fft_magnitude_calc
-    -- port map (
-    --  clk => , -- system clock
-    --  reset => , -- Active High Asynchronous Reset	
-    --	input_valid => , -- Input Data Valid
-    --	input_re => ,  -- Input Realteil in Fixpoint format
-    --	input_im =>  , -- Input Imaginaerteil in Fixpoint format
-    --	output_valid => , -- Output Data Valid
-    --	output_magnitude =>  -- Magnitude Output in Fixpoint format
-    --  );
-
-    fft_mag_calc_valid <= '1' when index = 0 else '0';
-    fft_mag_calc_result <= (others => '0');
-
-    -----------------------------------------------------------------------------------------------
-    -- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
-    -----------------------------------------------------------------------------------------------
-    task_state_transitions : process (all) is
+    task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
         case current_task_state is
@@ -164,7 +60,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if (  index = 2 ) then
+                if ( index = work.task.STREAM_LEN - 1 ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -174,157 +70,28 @@ begin
         end case;
     end process task_state_transitions;
 
-    -----------------------------------------------------------------------------------------------
-    -- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
-    -----------------------------------------------------------------------------------------------
-
-    -- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
-
-
-    -----------------------------------------------------------------------------------------------
-    -- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
-    -----------------------------------------------------------------------------------------------
-   sync : process ( clk, reset ) is
+    sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
             index <= 0;
-            wr_fifo <= '0';
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
-            wr_fifo <= '0';
             case next_task_state is
-		    when work.task.TASK_IDLE => 
-                      index <= 0;
-		    when work.task.TASK_RUNNING =>
-                      -- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
-                      -- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
-		      if (  index_output = work.task.STREAM_LEN - 1 ) then
-		      	  index <= index + 1;	
-                      end if;
-                      if index = 1 then				 
-			  wr_fifo <= '1';
-		      end if; 
-		    when work.task.TASK_DONE => null;
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
             end case;
         end if;
-    end process sync; 
-	 
+    end process sync;
 
-    -----------------------------------------------------------------------------------------------
-    --
-    -- Skalierung der Eingangswerte welche vom FIFO gelesen werden
-    -- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
-    -- und im naechsten Takt schon weiter verarbeitet werden können
-    --
-    -- Erforderliches Scaling:
-    --
-    -- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
-    -- multiplication is a simple addition of the exponents.
-    -- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
-    -- This means an divsion through 16 -> exponent needs an addition of - 4
-    --
-    -- fft_float_input = gelesener Wert vom FIFO (floating point)
-    -- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
-    -- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
-    -----------------------------------------------------------------------------------------------
-
-    fft_float_input <= signed(signal_readdata);
-
-    fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden 
-				
-
-    -----------------------------------------------------------------------------------------------
-    --
-    -- Skalierung der Eingangswerte welche vom FIFO gelesen werden
-    -- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
-    -- und im naechsten Takt schon weiter verarbeitet werden können
-    --
-    -- Erforderliches Scaling:
-    --
-    -- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
-    -- multiplication is a simple addition of the exponents.
-    -- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16 
-    -- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
-    -- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
-    -- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
-    --
-    -- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
-    -- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
-    -----------------------------------------------------------------------------------------------
-
-    data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
-
-    fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
-
-
-    -----------------------------------------------------------------------------------------------
-    -- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
-	-- Umordnung der Ausgangswerte erfolgen
-	-- 
-	-- index_output_sv = std_logic_vector des Integer Ausgangsindex
-	-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
-	--
-    c_index_output_sv:
-            index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
-    c_reversed_index:
-            index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
-	
-	   
-    -----------------------------------------------------------------------------------------------
-    -- Prozess steuert das hochzaehlen des Ausgang Index
-    -----------------------------------------------------------------------------------------------
-	p_number_output_sample: process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            index_output <= 0; 
-        elsif ( rising_edge( clk ) ) then
-            -- Ruecksetz Bedingung für index_output
-            if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
-		index_output <= 0;
-            -- index_output hochzaehlen um in natural order im array zu speichern
-	    elsif fft_mag_calc_valid = '1' then
-		index_output <= index_output + 1;
-            -- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
-	    elsif wr_fifo = '1' then
-		index_output <= index_output + 1;
-	    end if;
-        end if;
-    end process p_number_output_sample;
-	
-    -----------------------------------------------------------------------------------------------
-    -- Prozess speichert das skalierte Endergbenis iun der natural order
-    -----------------------------------------------------------------------------------------------
-    p_output2float_memory: process ( clk, reset) is
-    begin
-        if ( reset = '1' ) then
-	    null;
-        elsif ( rising_edge( clk ) ) then
-            if fft_mag_calc_valid = '1' then
-	                data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
-            end if;
-        end if;
-    end process p_output2float_memory;	
-	
-    -----------------------------------------------------------------------------------------------
-    -- Schreiben der berechneten Werte in den FIFO
-    -----------------------------------------------------------------------------------------------
-   p_output_fifo: process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            signal_writedata <= (others => '0');
-		  signal_write <= '0';
-        elsif ( rising_edge( clk ) ) then
-		  signal_write <= '0';		  
-            if wr_fifo = '1' then
-		  signal_writedata <= data_memory(index_output);
-	          signal_write <= '1';
-            end if;
-        end if;
-    end process p_output_fifo;	
-	
-	
-	-- Hier sollen die sonstigen benoetigten Anweisungen stehen
-    task_state <= current_task_state;	
+    task_state <= current_task_state;
 
 end architecture rtl;

software/signal_processing/add.c

@@ -5,6 +5,18 @@
 int task_add_run( void * task ) {
 
     // TODO
+	add_config * config = ( add_config * ) task;
+
+// Nachfolgende Antworten lesen..
+	for ( uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++) {
+		float a;
+		data_channel_read( config->sources[ 0 ], ( uint32_t * ) & a );
+		float b;
+		data_channel_read( config->sources[ 1 ], ( uint32_t * ) & b );
+		float_word c;
+		c.value = a + b;
+		data_channel_write( config->sink, c.word );
+	}
 
     return 0;
 }

tests/hardware/task_add_sine_cosine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 09:41:58 on Nov 20,2024
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.sine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.cosine_data
+# Loading work.sine_cosine_data
+# Loading work.test_task_add_sine_cosine(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.float_add(mixed)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_sine_cosine
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 09:41:59 on Nov 20,2024, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 1

tests/hardware/task_add_sine_cosine/work/@_opt2/VH_HASH_DATA

@@ -0,0 +1,156 @@
+[N
+13
+12
+13 CHECK_RESULTS
+8
+12 data_channel
+13
+8 GUI_MODE
+3
+3 rtl
+7
+5 DEPTH
+10
+25 test_task_add_sine_cosine
+1
+105 /users/ads1/brandlfl78731/linux/A_VHDL/signal_processing_vorlage/tests/hardware/task_add_sine_cosine/work
+2
+24 avalon_slave_transitions
+9
+6 struct
+6
+4 fifo
+4
+9 REG_COUNT
+5
+16 REG_ACCESS_TYPES
+11
+4 test
+]
+[G
+1
+6
+3
+1
+7
+1
+0
+1024
+0
+0 0
+0
+0
+]
+[G
+1
+2
+3
+1
+4
+1
+0
+6
+0
+0 0
+0
+0
+]
+[G
+1
+2
+3
+2
+4
+1
+0
+7
+0
+0 0
+0
+0
+]
+[G
+1
+10
+11
+1
+13
+0
+0
+1
+0
+0 0
+0
+0
+]
+[G
+1
+10
+11
+1
+12
+0
+0
+1
+0
+0 0
+0
+0
+]
+[G
+1
+2
+3
+1
+5
+0
+0
+0
+0
+6 0
+2
+1
+1
+3
+3
+3
+1
+1
+0 5 1 1
+]
+[G
+1
+2
+3
+2
+5
+0
+0
+0
+0
+7 0
+3
+1
+1
+1
+2
+1
+2
+1
+1
+0 6 1 1
+]
+[G
+1
+8
+9
+1
+7
+1
+0
+1024
+0
+0 0
+0
+0
+]

tests/hardware/task_add_sine_cosine/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

tests/hardware/task_fft/Makefile

@@ -11,8 +11,6 @@ verilog_srcs = \
 vhdl_srcs = \
     ../../../hardware/system/reg32.vhd \
     ../../../hardware/system/avalon_slave.vhd \
-    ../test_utility.vhd \
-    ../test_avalon_slave.vhd \
     ../../hardware/test_data_channel.vhd \
     ../../../hardware/system/avalon_slave_transitions.vhd \
     ../../../hardware/system/task.vhd \

tests/hardware/task_fft/test_task_fft.vhd

@@ -63,7 +63,7 @@ architecture test of test_task_fft is
         variable writedata_float : float32;
         variable writedata_real : real;
         variable expected_real : real;
-        variable abs_err : real := 0.6;
+        variable abs_err : real := 0.5e-1;
         variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
         variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
         file data_file : text;
@@ -110,13 +110,11 @@ architecture test of test_task_fft is
         std.textio.write( data_file_fft, "]" & LF );
         file_close( data_file_fft );
 
-        index := 0;
         while index < STREAM_LEN loop
             writedata_float := to_float( result( index ) );
             writedata_real := to_real( writedata_float );
             expected_real := work.fft_data.expected( index );
             assert_near( writedata_real, expected_real, abs_err );
-            index := index + 1;
         end loop;
 
         file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );

tests/hardware/task_fft/vsim.wave

@@ -1,2 +1 @@
 add wave -position end  sim:/test_task_fft/dut/*
-add wave -position end  sim:/test_task_fft/dut/u_fft/*