2023-10-31 07:47:27 +01:00
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.float.all;
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use work.task.all;
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entity sine is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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step_size : in work.reg32.word;
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phase : in work.reg32.word;
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amplitude : in work.reg32.word;
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity sine;
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architecture rtl of sine is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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2024-01-09 08:41:42 +01:00
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signal index : integer range 1 to 1025;
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--Signale anlegen:
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signal data_valid_intern : std_logic;
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signal angle_intern : signed(31 downto 0);
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signal busy_intern : std_logic;
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signal result_valid_intern : std_logic;
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signal sine_intern : signed(31 downto 0);
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signal count : INTEGER RANGE 1 TO 1025;
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type CalcState is(
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CALC_IDLE,
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CALC_ZUWEISEN,--1) dem IP-Core einen neuen angle Wert zuführen
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CALC_WARTEN,--2) warten bis dieser einen neuen Sinuswert berechnet hat
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--(dauert einige Takte - Hinweis result_valid und busy Signale des IP-Cores)
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CALC_SKALIEREN,--3) den berechneten Wert skalieren
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CALC_IN_FIFO_ABSPEICHERN); --4) im FIFO abspeichern
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signal current_calc_state : CalcState;
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signal next_calc_state : CalcState;
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2023-10-31 07:47:27 +01:00
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begin
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2024-01-09 08:41:42 +01:00
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--IP-Core instanzieren und entsprechende Signale verbinden:
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u_float_sine: entity work.float_sine
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generic map (
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ITERATIONS => 8
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)
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port map (
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clk => clk,
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reset => reset,
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data_valid => data_valid_intern,
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angle => angle_intern,
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busy => busy_intern,
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result_valid => result_valid_intern,
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sine => sine_intern
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);
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2023-10-31 07:47:27 +01:00
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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2024-01-09 08:41:42 +01:00
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if ( index = work.task.STREAM_LEN ) then
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2023-10-31 07:47:27 +01:00
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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2024-01-09 08:41:42 +01:00
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calc_state_transitions : process (all) is
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begin
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next_calc_state <= current_calc_state;
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case current_calc_state is
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when CALC_IDLE =>
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if(current_task_state = work.task.TASK_RUNNING) then
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next_calc_state <= CALC_ZUWEISEN;
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end if;
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when CALC_ZUWEISEN =>
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next_calc_state <= CALC_WARTEN;
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when CALC_WARTEN =>
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if(result_valid_intern = '1' and busy_intern = '0') then--busy_intern = '0'
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next_calc_state <= CALC_SKALIEREN;
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end if;
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when CALC_SKALIEREN =>
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next_calc_state <= CALC_IN_FIFO_ABSPEICHERN;
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when CALC_IN_FIFO_ABSPEICHERN =>
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next_calc_state <= CALC_ZUWEISEN;
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if(index = 1024) then
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next_calc_state <= CALC_IDLE;
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end if;
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end case;
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end process calc_state_transitions;
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2023-10-31 07:47:27 +01:00
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sync : process ( clk, reset ) is
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2024-01-09 08:41:42 +01:00
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VARIABLE sine_scaled : signed ( 31 downto 0 );
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2023-10-31 07:47:27 +01:00
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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2024-01-09 08:41:42 +01:00
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index <= 1;
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count <= 1;
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sine_scaled := (others => '0');
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data_valid_intern <= '0';
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signal_write <= '0';
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signal_writedata <= ( others => '0' );
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2023-10-31 07:47:27 +01:00
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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when work.task.TASK_RUNNING =>
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when work.task.TASK_DONE =>
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end case;
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--A:
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current_calc_state <= next_calc_state;
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data_valid_intern <= '0';
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signal_write <= '0';
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case next_calc_state is
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when CALC_IDLE =>
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angle_intern <= (others => '0');
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count <= 1;
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when CALC_ZUWEISEN =>
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--if(index > 1) then
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angle_intern <= angle_intern + signed(step_size);
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--end if;
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data_valid_intern <= '1';
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when CALC_WARTEN =>
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when CALC_SKALIEREN =>
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--if(result_valid_intern = '1') then
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sine_scaled := sine_intern;
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sine_scaled(30 downto 23) := sine_scaled(30 downto 23) + ( signed(amplitude(30 downto 23)) - 127);
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--end if;
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when CALC_IN_FIFO_ABSPEICHERN =>
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if(index > 1) then
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signal_writedata <= std_logic_vector(sine_scaled);
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end if;
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signal_write <= '1';
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index <= index + 1;
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count <= count + 1;
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end case;
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--E
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2023-10-31 07:47:27 +01:00
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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