signal_processing_vorlage/hardware/signal_processing/sine.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.float.all;
    use work.task.all;

entity sine is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        step_size : in work.reg32.word;
        phase : in work.reg32.word;
        amplitude : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity sine;

architecture rtl of sine is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 1 to 1025;

    --Signale anlegen:
    signal data_valid_intern : std_logic;
    signal angle_intern : signed(31 downto 0);
    signal busy_intern : std_logic;
    signal result_valid_intern : std_logic;
    signal sine_intern : signed(31 downto 0);
    signal count : INTEGER RANGE 1 TO 1025;

    


type CalcState is(
	CALC_IDLE,
	CALC_ZUWEISEN,--1) dem IP-Core einen neuen angle Wert zuführen
	CALC_WARTEN,--2) warten bis dieser einen neuen Sinuswert berechnet hat
		    --(dauert einige Takte - Hinweis result_valid und busy Signale des IP-Cores)
	CALC_SKALIEREN,--3) den berechneten Wert skalieren
	CALC_IN_FIFO_ABSPEICHERN); --4) im FIFO abspeichern

signal current_calc_state : CalcState;
signal next_calc_state : CalcState;


begin

    --IP-Core instanzieren und entsprechende Signale verbinden:
    u_float_sine: entity work.float_sine
	generic map (
		ITERATIONS => 8
	)
        port map (
            	clk => clk,
            	reset => reset,
		data_valid => data_valid_intern,
		angle => angle_intern,
		busy => busy_intern,
		result_valid => result_valid_intern,
		sine => sine_intern
        );

    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;


    calc_state_transitions : process (all) is
    begin
		next_calc_state <= current_calc_state;
		case current_calc_state is
			when CALC_IDLE =>
			if(current_task_state = work.task.TASK_RUNNING) then
			next_calc_state <= CALC_ZUWEISEN;
			end if;
			when CALC_ZUWEISEN =>
			next_calc_state <= CALC_WARTEN;
			when CALC_WARTEN =>
			if(result_valid_intern = '1' and busy_intern = '0') then--busy_intern = '0'
			next_calc_state <= CALC_SKALIEREN;
			end if;
			when CALC_SKALIEREN =>
			next_calc_state <= CALC_IN_FIFO_ABSPEICHERN;
			when CALC_IN_FIFO_ABSPEICHERN =>
			next_calc_state <= CALC_ZUWEISEN;

			if(index = 1024) then
			next_calc_state <= CALC_IDLE;
			end if;
		end case;
    end process calc_state_transitions;


    sync : process ( clk, reset ) is

    
    VARIABLE sine_scaled : signed ( 31 downto 0 );

    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 1;
	    count <= 1;
	    sine_scaled := (others => '0');
	    data_valid_intern <= '0';
	    signal_write <= '0';
            signal_writedata <= ( others => '0' );
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
            when work.task.TASK_RUNNING =>
            when work.task.TASK_DONE =>
            end case;

	    --A:
            	current_calc_state <= next_calc_state;
		data_valid_intern <= '0';
		signal_write <= '0';
		case next_calc_state is
			when CALC_IDLE =>
			angle_intern <= (others => '0');
			count <= 1;
			when CALC_ZUWEISEN =>
			--if(index > 1) then
			angle_intern <= angle_intern + signed(step_size);
			--end if;
			data_valid_intern <= '1';
			when CALC_WARTEN =>
			when CALC_SKALIEREN =>
			--if(result_valid_intern = '1') then
				sine_scaled := sine_intern;
				sine_scaled(30 downto 23) := sine_scaled(30 downto 23) + ( signed(amplitude(30 downto 23)) - 127);
				
			--end if;
			when CALC_IN_FIFO_ABSPEICHERN =>

			if(index > 1) then
			signal_writedata <= std_logic_vector(sine_scaled);
			end if;

			signal_write <= '1';

			index <= index + 1;
			count <= count + 1;
		end case;
	     --E

        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;