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Loesung von add sin cos und rand

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erhardtph78456
2024-12-04 08:58:18 +01:00
parent 0d1b73e3e0
commit a325c8ddb6
6 changed files with 215 additions and 41 deletions
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hardware/signal_processing/add.vhd
+61 -11
View File
@@ -6,6 +6,7 @@ library work;
use work.reg32.all;
use work.task.all;
-- Anlegen der Variablen des Programms
entity add is
port (
clk : in std_logic;
@@ -25,12 +26,30 @@ entity add is
);
end entity add;
-- Signale anlegen
architecture rtl of add is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal index_run :integer range 0 to 2;
signal start_value : std_logic;
signal done_value : std_logic;
signal write_value : std_logic_vector( 31 downto 0 );
begin
-- Instanziierung der float_add.vhd
u_float_add : entity work.float_add
port map(
clk => clk,
reset => reset,
start => start_value,
done => done_value,
a => signal_a_readdata,
b => signal_b_readdata,
sum => write_value
);
-- Zustandsautomat fuer die Zustandsswechsel
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
@@ -40,7 +59,7 @@ begin
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
if ( index = work.task.STREAM_LEN ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
@@ -50,24 +69,55 @@ begin
end case;
end process task_state_transitions;
-- Zustandautomat fuer die Berechnung
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
-- alle Signale in der Reset Bedingung initialisieren
start_value <= '0';
signal_a_read <= '0';
signal_b_read <= '0';
signal_write <= '0';
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
-- idle
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
-- running
when work.task.TASK_RUNNING =>
case index_run is
when 0 =>
signal_writedata <= ( others => '0' );
start_value <= '1';
index_run <= index_run + 1;
when 1 =>
if(done_value = '1') then
start_value <= '0';
signal_write <= '1';
signal_writedata <= write_value;
signal_a_read <= '1';
signal_b_read <= '1';
index_run <= index_run + 1;
end if;
when 2 =>
signal_write <= '0';
signal_a_read <= '0';
signal_b_read <= '0';
index_run <= 0;
index <= index + 1;
end case;
-- done
when work.task.TASK_DONE =>
index <= 0;
end case;
end if;
end process sync;
hardware/signal_processing/rand.vhd
+30 -10
View File
@@ -25,6 +25,11 @@ architecture rtl of rand is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal lfsr : std_logic_vector( 31 downto 0 );
signal lfsr_next : std_logic_vector( 31 downto 0 );
signal bitte : std_logic;
signal exponent : std_logic_vector( 7 downto 0 );
signal ieee754 : std_logic_vector( 31 downto 0 );
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
@@ -46,24 +51,39 @@ begin
end case;
end process task_state_transitions;
exponent <= std_logic_vector(to_unsigned(128, 8) + unsigned(lfsr(23 downto 23))) when (lfsr(30) = '1')
else std_logic_vector(to_unsigned(124, 8) + unsigned(lfsr(24 downto 23)));
ieee754 <= lfsr(31) & exponent(7 downto 0) & lfsr(22 downto 0);
bitte <= (lfsr(31) XOR lfsr(21) XOR lfsr(1));
lfsr_next <= lfsr(30 downto 0) & bitte;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
-- alle Signale in der Reset Bedingung initialisieren
lfsr <= seed;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
lfsr <= seed;
when work.task.TASK_RUNNING =>
signal_write <= '1';
signal_writedata <= ( ieee754 );
lfsr <= lfsr_next;
index <= index + 1;
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;
hardware/signal_processing/sine.vhd
+59 -11
View File
@@ -29,8 +29,31 @@ architecture rtl of sine is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal index_run :integer range 0 to 2;
signal data_valid : std_logic;
signal busy : std_logic;
signal result_valid : std_logic;
signal angle : signed(31 downto 0);
signal write_value : signed(31 downto 0);
begin
-- Instanziierung der float_sine.vhd
u_float_sine : entity work.float_sine
generic map(
ITERATIONS => 8
)
port map(
clk => clk,
reset => reset,
data_valid => data_valid,
busy => busy,
result_valid => result_valid,
angle => angle,
sine => write_value
);
-- Zustandsautomat fuer die Zustandsswechsel
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
@@ -40,7 +63,7 @@ begin
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
if ( index = work.task.STREAM_LEN ) then -- - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
@@ -50,24 +73,49 @@ begin
end case;
end process task_state_transitions;
-- Zustandautomat fuer die Berechnung
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
-- alle Signale in der Reset Bedingung initialisieren
data_valid <= '0';
signal_write <= '0';
angle <= x"00000000";
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
-- idle
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
-- running
when work.task.TASK_RUNNING =>
case index_run is
when 0 =>
signal_write <= '0';
angle <= angle + signed(step_size);--signed(phase)
data_valid <= '1';
index_run <= index_run + 1;
when 1 =>
data_valid <= '0';
if(result_valid = '1') then
signal_write <= '1';
signal_writedata <= std_logic_vector(write_value);
index_run <= index_run + 1;
end if;
when 2 =>
signal_write <= '0';
index_run <= 0;
index <= index + 1;
end case;
-- done
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
end case;
end if;
end process sync;