erhardtph78456 a325c8ddb6 Loesung von add sin cos und rand

2024-12-04 08:58:18 +01:00

hardware

Loesung von add sin cos und rand

2024-12-04 08:58:18 +01:00

software/signal_processing

Loesung von add sin cos und rand

2024-12-04 08:58:18 +01:00

tests

Initial commit

2023-10-31 07:47:27 +01:00

.gitignore

Initial commit

2023-10-31 07:47:27 +01:00

data_channel_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_task_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_timestamp_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hdl_sources.qsf

Initial commit

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init.sh

Initial commit

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Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qpf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

S

Description

Lösung des Praktikums Systementwurf

259 KiB

Languages

VHDL 36.5%

C 17.6%

Verilog 15.1%

Python 10.8%

Makefile 8.3%

Other 11.7%