signal_processing_vorlage/tests/hardware/task_crc/transcript

# //  Questa Sim-64
# //  Version 2023.2 linux_x86_64 Apr 11 2023
# //
# //  Copyright 1991-2023 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# vsim -voptargs="+acc" work.test_task_crc -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gGUI_MODE=true -gCHECK_RESULTS=true 
# Start time: 09:14:29 on Dec 18,2024
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
# ** Warning: (vopt-3040) Command line generic/parameter "GUI_MODE" not found in design.
# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "crc(rtl)".
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2.
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.fixed_float_types
# Loading ieee.math_real(body)
# Loading ieee.fixed_generic_pkg(body)
# Loading ieee.float_generic_pkg(body)
# Loading ieee.fixed_pkg
# Loading ieee.float_pkg
# Loading work.reg32(body)
# Loading work.avalon_slave
# Loading work.test_utility(body)
# Loading work.test_avalon_slave(body)
# Loading work.task(body)
# Loading work.crc_data
# Loading work.fft_data
# Loading work.test_hardware_task(body)
# Loading work.test_data_channel_pkg(body)
# Loading std.env(body)
# Loading work.test_task_crc(test)#1
# Loading work.task_crc(struct)#1
# Loading work.hardware_task_control(rtl)#1
# Loading work.avalon_slave_transitions(rtl)#1
# Loading work.crc(rtl)#1
# Loading work.data_channel(struct)#1
# Loading work.data_channel_control(rtl)#1
# Loading work.avalon_slave_transitions(rtl)#2
# Loading work.data_sink_mux(rtl)#1
# Loading work.fifo(rtl)#1
# Loading work.data_source_mux(rtl)#1
# do vsim.wave
#  set StdArithNoWarnings 1
# 1
#  set NumericStdNoWarnings 1
# 1
#  run -all
#     test_execute ... [ OK ]
#     test_crc_value ... [ OK ]
# 1
# Break in Process stimulus at test_task_crc.vhd line 131