Initial commit
This commit is contained in:
muellerlu
Binary file not shown.
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@@ -0,0 +1 @@
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create_clock -name clk -period 10 [get_ports clk]
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Executable
+880
@@ -0,0 +1,880 @@
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create_clock -name lfxt_clk -period 600 -waveform { 0 300 } [get_pins lfxt_clk_pad/C ]
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create_clock -name sysclk_byp -period 600 -waveform { 0 300 } [get_pins sysclk_byp_pad/C ]
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create_clock -name usbclk_byp -period 600 -waveform { 0 300 } [get_pins usbclk_byp_pad/C ]
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create_clock -name vsysclk -period 15 -waveform { 0 7.5 }
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create_clock -name vsysclk_ddr -period 7.5 -waveform { 0 3.75 }
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create_clock -name sysclk -period 2 -waveform { 0 1 } [get_pins i_MAIN_PLL/PLLOUT]
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create_clock -name usbclk -period 8 -waveform { 0 4 } [get_pins i_USB_PLL/PLLOUT]
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#create_generated_clock -name sysclk -source i_MAIN_PLL/REF -master_clock lfxt_clk -multiply_by 40 -add [get_pins i_MAIN_PLL/PLLOUT]
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#create_generated_clock -name usbclk -source i_USB_PLL/REF -master_clock lfxt_clk -multiply_by 6 -add [get_pins i_USB_PLL/PLLOUT]
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set_clock_uncertainty -setup 0.2 [get_clocks sysclk]
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set_clock_uncertainty -setup 0.1 [get_clocks usbclk]
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set_false_path -from [get_ports nmi]
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set_false_path -from [get_ports reset_n]
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set_input_delay -clock vsysclk 10.5 [get_ports reset_n]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[15] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[14] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[13] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[12] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[11] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[10] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[9] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[8] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[7] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[6] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[5] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[4] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[3] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[2] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[1] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[0] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[15] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[14] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[13] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[12] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[11] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[10] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[9] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[8] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[7] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[6] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[5] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[4] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[3] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[2] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[1] }]
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set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[0] }]
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set_input_delay -clock vsysclk 10.5 [get_ports nmi]
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set_input_delay -clock vsysclk 10.5 [get_ports scan_mode]
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set_input_delay -clock vsysclk 10.5 [get_ports sysclk_byp]
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set_input_delay -clock vsysclk 10.5 [get_ports usbclk_byp]
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set_output_delay -clock vsysclk 4.5 [get_ports mclk]
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set_output_delay -clock vsysclk 4.5 [get_ports BS_ren_0]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[16] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[15] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[14] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[13] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[12] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[11] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[10] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[9] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[8] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[7] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[6] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[5] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[4] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports BS_ren_1]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[16] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[15] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[14] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[13] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[12] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[11] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[10] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[9] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[8] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[7] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[6] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[5] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[4] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cke]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cs_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr0_we_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cas_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr0_ras_n]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[12] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[11] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[10] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[9] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[8] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[7] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[6] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[5] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[4] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_ba[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_ba[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cke]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cs_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr1_we_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cas_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr1_ras_n]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[12] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[11] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[10] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[9] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[8] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[7] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[6] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[5] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[4] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_ba[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_ba[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cke]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cs_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr2_we_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cas_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr2_ras_n]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[12] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[11] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[10] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[9] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[8] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[7] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[6] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[5] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[4] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_ba[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_ba[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[0] }]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cke]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cs_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr3_we_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cas_n]
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set_output_delay -clock vsysclk 4.5 [get_ports ddr3_ras_n]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[12] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[11] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[10] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[9] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[8] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[7] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[6] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[5] }]
|
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[4] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[3] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[2] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[1] }]
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[0] }]
|
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_ba[1] }]
|
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_ba[0] }]
|
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[3] }]
|
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[2] }]
|
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set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[1] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[0] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[31] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[30] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[29] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[28] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[27] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[26] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[25] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[24] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[23] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[22] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[21] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[20] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[19] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[18] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[17] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[16] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[15] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[14] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[13] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[12] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[11] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[10] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[9] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[8] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[7] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[6] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[5] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[4] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[3] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[2] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[1] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[0] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[31] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[30] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[29] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[28] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[27] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[26] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[25] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[24] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[23] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[22] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[21] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[20] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[19] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[18] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[17] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[16] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[15] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[14] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[13] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[12] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[11] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[10] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[9] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[8] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[7] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[6] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[5] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[4] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[3] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[2] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[1] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[0] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[31] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[30] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[29] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[28] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[27] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[26] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[25] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[24] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[23] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[22] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[21] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[20] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[19] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[18] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[17] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[16] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[15] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[14] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[13] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[12] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[11] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[10] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[9] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[8] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[7] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[6] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[5] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[4] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[3] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[2] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[1] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[0] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[31] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[30] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[29] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[28] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[27] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[26] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[25] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[24] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[23] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[22] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[21] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[20] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[19] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[18] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[17] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[16] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[15] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[14] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[13] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[12] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[11] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[10] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[9] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[8] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[7] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[6] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[5] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[4] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[3] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[2] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[1] }]
|
||||
set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[0] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[31] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[30] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[29] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[28] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[27] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[26] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[25] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[24] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[23] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[22] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[21] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[20] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[19] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[18] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[17] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[16] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[15] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[14] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[13] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[12] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[11] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[10] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[9] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[8] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[7] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[6] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[5] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[4] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[3] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[2] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[1] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[0] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[31] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[30] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[29] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[28] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[27] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[26] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[25] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[24] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[23] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[22] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[21] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[20] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[19] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[18] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[17] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[16] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[15] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[14] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[13] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[12] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[11] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[10] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[9] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[8] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[7] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[6] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[5] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[4] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[3] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[2] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[1] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[0] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[31] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[30] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[29] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[28] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[27] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[26] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[25] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[24] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[23] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[22] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[21] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[20] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[19] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[18] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[17] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[16] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[15] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[14] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[13] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[12] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[11] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[10] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[9] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[8] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[7] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[6] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[5] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[4] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[3] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[2] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[1] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[0] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[31] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[30] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[29] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[28] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[27] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[26] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[25] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[24] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[23] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[22] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[21] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[20] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[19] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[18] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[17] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[16] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[15] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[14] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[13] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[12] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[11] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[10] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[9] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[8] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[7] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[6] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[5] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[4] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[3] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[2] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[1] }]
|
||||
set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[0] }]
|
||||
set_load 10 [get_ports mclk]
|
||||
set_load 10 [get_ports BS_ren_0]
|
||||
set_load 10 [get_ports { BS_addr_0[16] }]
|
||||
set_load 10 [get_ports { BS_addr_0[15] }]
|
||||
set_load 10 [get_ports { BS_addr_0[14] }]
|
||||
set_load 10 [get_ports { BS_addr_0[13] }]
|
||||
set_load 10 [get_ports { BS_addr_0[12] }]
|
||||
set_load 10 [get_ports { BS_addr_0[11] }]
|
||||
set_load 10 [get_ports { BS_addr_0[10] }]
|
||||
set_load 10 [get_ports { BS_addr_0[9] }]
|
||||
set_load 10 [get_ports { BS_addr_0[8] }]
|
||||
set_load 10 [get_ports { BS_addr_0[7] }]
|
||||
set_load 10 [get_ports { BS_addr_0[6] }]
|
||||
set_load 10 [get_ports { BS_addr_0[5] }]
|
||||
set_load 10 [get_ports { BS_addr_0[4] }]
|
||||
set_load 10 [get_ports { BS_addr_0[3] }]
|
||||
set_load 10 [get_ports { BS_addr_0[2] }]
|
||||
set_load 10 [get_ports { BS_addr_0[1] }]
|
||||
set_load 10 [get_ports { BS_addr_0[0] }]
|
||||
set_load 10 [get_ports BS_ren_1]
|
||||
set_load 10 [get_ports { BS_addr_1[16] }]
|
||||
set_load 10 [get_ports { BS_addr_1[15] }]
|
||||
set_load 10 [get_ports { BS_addr_1[14] }]
|
||||
set_load 10 [get_ports { BS_addr_1[13] }]
|
||||
set_load 10 [get_ports { BS_addr_1[12] }]
|
||||
set_load 10 [get_ports { BS_addr_1[11] }]
|
||||
set_load 10 [get_ports { BS_addr_1[10] }]
|
||||
set_load 10 [get_ports { BS_addr_1[9] }]
|
||||
set_load 10 [get_ports { BS_addr_1[8] }]
|
||||
set_load 10 [get_ports { BS_addr_1[7] }]
|
||||
set_load 10 [get_ports { BS_addr_1[6] }]
|
||||
set_load 10 [get_ports { BS_addr_1[5] }]
|
||||
set_load 10 [get_ports { BS_addr_1[4] }]
|
||||
set_load 10 [get_ports { BS_addr_1[3] }]
|
||||
set_load 10 [get_ports { BS_addr_1[2] }]
|
||||
set_load 10 [get_ports { BS_addr_1[1] }]
|
||||
set_load 10 [get_ports { BS_addr_1[0] }]
|
||||
set_load 10 [get_ports ddr0_cke]
|
||||
set_load 10 [get_ports ddr0_cs_n]
|
||||
set_load 10 [get_ports ddr0_we_n]
|
||||
set_load 10 [get_ports ddr0_cas_n]
|
||||
set_load 10 [get_ports ddr0_ras_n]
|
||||
set_load 10 [get_ports { ddr0_adr[12] }]
|
||||
set_load 10 [get_ports { ddr0_adr[11] }]
|
||||
set_load 10 [get_ports { ddr0_adr[10] }]
|
||||
set_load 10 [get_ports { ddr0_adr[9] }]
|
||||
set_load 10 [get_ports { ddr0_adr[8] }]
|
||||
set_load 10 [get_ports { ddr0_adr[7] }]
|
||||
set_load 10 [get_ports { ddr0_adr[6] }]
|
||||
set_load 10 [get_ports { ddr0_adr[5] }]
|
||||
set_load 10 [get_ports { ddr0_adr[4] }]
|
||||
set_load 10 [get_ports { ddr0_adr[3] }]
|
||||
set_load 10 [get_ports { ddr0_adr[2] }]
|
||||
set_load 10 [get_ports { ddr0_adr[1] }]
|
||||
set_load 10 [get_ports { ddr0_adr[0] }]
|
||||
set_load 10 [get_ports { ddr0_ba[1] }]
|
||||
set_load 10 [get_ports { ddr0_ba[0] }]
|
||||
set_load 10 [get_ports { ddr0_dm[3] }]
|
||||
set_load 10 [get_ports { ddr0_dm[2] }]
|
||||
set_load 10 [get_ports { ddr0_dm[1] }]
|
||||
set_load 10 [get_ports { ddr0_dm[0] }]
|
||||
set_load 10 [get_ports ddr1_cke]
|
||||
set_load 10 [get_ports ddr1_cs_n]
|
||||
set_load 10 [get_ports ddr1_we_n]
|
||||
set_load 10 [get_ports ddr1_cas_n]
|
||||
set_load 10 [get_ports ddr1_ras_n]
|
||||
set_load 10 [get_ports { ddr1_adr[12] }]
|
||||
set_load 10 [get_ports { ddr1_adr[11] }]
|
||||
set_load 10 [get_ports { ddr1_adr[10] }]
|
||||
set_load 10 [get_ports { ddr1_adr[9] }]
|
||||
set_load 10 [get_ports { ddr1_adr[8] }]
|
||||
set_load 10 [get_ports { ddr1_adr[7] }]
|
||||
set_load 10 [get_ports { ddr1_adr[6] }]
|
||||
set_load 10 [get_ports { ddr1_adr[5] }]
|
||||
set_load 10 [get_ports { ddr1_adr[4] }]
|
||||
set_load 10 [get_ports { ddr1_adr[3] }]
|
||||
set_load 10 [get_ports { ddr1_adr[2] }]
|
||||
set_load 10 [get_ports { ddr1_adr[1] }]
|
||||
set_load 10 [get_ports { ddr1_adr[0] }]
|
||||
set_load 10 [get_ports { ddr1_ba[1] }]
|
||||
set_load 10 [get_ports { ddr1_ba[0] }]
|
||||
set_load 10 [get_ports { ddr1_dm[3] }]
|
||||
set_load 10 [get_ports { ddr1_dm[2] }]
|
||||
set_load 10 [get_ports { ddr1_dm[1] }]
|
||||
set_load 10 [get_ports { ddr1_dm[0] }]
|
||||
set_load 10 [get_ports ddr2_cke]
|
||||
set_load 10 [get_ports ddr2_cs_n]
|
||||
set_load 10 [get_ports ddr2_we_n]
|
||||
set_load 10 [get_ports ddr2_cas_n]
|
||||
set_load 10 [get_ports ddr2_ras_n]
|
||||
set_load 10 [get_ports { ddr2_adr[12] }]
|
||||
set_load 10 [get_ports { ddr2_adr[11] }]
|
||||
set_load 10 [get_ports { ddr2_adr[10] }]
|
||||
set_load 10 [get_ports { ddr2_adr[9] }]
|
||||
set_load 10 [get_ports { ddr2_adr[8] }]
|
||||
set_load 10 [get_ports { ddr2_adr[7] }]
|
||||
set_load 10 [get_ports { ddr2_adr[6] }]
|
||||
set_load 10 [get_ports { ddr2_adr[5] }]
|
||||
set_load 10 [get_ports { ddr2_adr[4] }]
|
||||
set_load 10 [get_ports { ddr2_adr[3] }]
|
||||
set_load 10 [get_ports { ddr2_adr[2] }]
|
||||
set_load 10 [get_ports { ddr2_adr[1] }]
|
||||
set_load 10 [get_ports { ddr2_adr[0] }]
|
||||
set_load 10 [get_ports { ddr2_ba[1] }]
|
||||
set_load 10 [get_ports { ddr2_ba[0] }]
|
||||
set_load 10 [get_ports { ddr2_dm[3] }]
|
||||
set_load 10 [get_ports { ddr2_dm[2] }]
|
||||
set_load 10 [get_ports { ddr2_dm[1] }]
|
||||
set_load 10 [get_ports { ddr2_dm[0] }]
|
||||
set_load 10 [get_ports ddr3_cke]
|
||||
set_load 10 [get_ports ddr3_cs_n]
|
||||
set_load 10 [get_ports ddr3_we_n]
|
||||
set_load 10 [get_ports ddr3_cas_n]
|
||||
set_load 10 [get_ports ddr3_ras_n]
|
||||
set_load 10 [get_ports { ddr3_adr[12] }]
|
||||
set_load 10 [get_ports { ddr3_adr[11] }]
|
||||
set_load 10 [get_ports { ddr3_adr[10] }]
|
||||
set_load 10 [get_ports { ddr3_adr[9] }]
|
||||
set_load 10 [get_ports { ddr3_adr[8] }]
|
||||
set_load 10 [get_ports { ddr3_adr[7] }]
|
||||
set_load 10 [get_ports { ddr3_adr[6] }]
|
||||
set_load 10 [get_ports { ddr3_adr[5] }]
|
||||
set_load 10 [get_ports { ddr3_adr[4] }]
|
||||
set_load 10 [get_ports { ddr3_adr[3] }]
|
||||
set_load 10 [get_ports { ddr3_adr[2] }]
|
||||
set_load 10 [get_ports { ddr3_adr[1] }]
|
||||
set_load 10 [get_ports { ddr3_adr[0] }]
|
||||
set_load 10 [get_ports { ddr3_ba[1] }]
|
||||
set_load 10 [get_ports { ddr3_ba[0] }]
|
||||
set_load 10 [get_ports { ddr3_dm[3] }]
|
||||
set_load 10 [get_ports { ddr3_dm[2] }]
|
||||
set_load 10 [get_ports { ddr3_dm[1] }]
|
||||
set_load 10 [get_ports { ddr3_dm[0] }]
|
||||
set_load 10 [get_ports { ddr0_dq[31] }]
|
||||
set_load 10 [get_ports { ddr0_dq[30] }]
|
||||
set_load 10 [get_ports { ddr0_dq[29] }]
|
||||
set_load 10 [get_ports { ddr0_dq[28] }]
|
||||
set_load 10 [get_ports { ddr0_dq[27] }]
|
||||
set_load 10 [get_ports { ddr0_dq[26] }]
|
||||
set_load 10 [get_ports { ddr0_dq[25] }]
|
||||
set_load 10 [get_ports { ddr0_dq[24] }]
|
||||
set_load 10 [get_ports { ddr0_dq[23] }]
|
||||
set_load 10 [get_ports { ddr0_dq[22] }]
|
||||
set_load 10 [get_ports { ddr0_dq[21] }]
|
||||
set_load 10 [get_ports { ddr0_dq[20] }]
|
||||
set_load 10 [get_ports { ddr0_dq[19] }]
|
||||
set_load 10 [get_ports { ddr0_dq[18] }]
|
||||
set_load 10 [get_ports { ddr0_dq[17] }]
|
||||
set_load 10 [get_ports { ddr0_dq[16] }]
|
||||
set_load 10 [get_ports { ddr0_dq[15] }]
|
||||
set_load 10 [get_ports { ddr0_dq[14] }]
|
||||
set_load 10 [get_ports { ddr0_dq[13] }]
|
||||
set_load 10 [get_ports { ddr0_dq[12] }]
|
||||
set_load 10 [get_ports { ddr0_dq[11] }]
|
||||
set_load 10 [get_ports { ddr0_dq[10] }]
|
||||
set_load 10 [get_ports { ddr0_dq[9] }]
|
||||
set_load 10 [get_ports { ddr0_dq[8] }]
|
||||
set_load 10 [get_ports { ddr0_dq[7] }]
|
||||
set_load 10 [get_ports { ddr0_dq[6] }]
|
||||
set_load 10 [get_ports { ddr0_dq[5] }]
|
||||
set_load 10 [get_ports { ddr0_dq[4] }]
|
||||
set_load 10 [get_ports { ddr0_dq[3] }]
|
||||
set_load 10 [get_ports { ddr0_dq[2] }]
|
||||
set_load 10 [get_ports { ddr0_dq[1] }]
|
||||
set_load 10 [get_ports { ddr0_dq[0] }]
|
||||
set_load 10 [get_ports { ddr1_dq[31] }]
|
||||
set_load 10 [get_ports { ddr1_dq[30] }]
|
||||
set_load 10 [get_ports { ddr1_dq[29] }]
|
||||
set_load 10 [get_ports { ddr1_dq[28] }]
|
||||
set_load 10 [get_ports { ddr1_dq[27] }]
|
||||
set_load 10 [get_ports { ddr1_dq[26] }]
|
||||
set_load 10 [get_ports { ddr1_dq[25] }]
|
||||
set_load 10 [get_ports { ddr1_dq[24] }]
|
||||
set_load 10 [get_ports { ddr1_dq[23] }]
|
||||
set_load 10 [get_ports { ddr1_dq[22] }]
|
||||
set_load 10 [get_ports { ddr1_dq[21] }]
|
||||
set_load 10 [get_ports { ddr1_dq[20] }]
|
||||
set_load 10 [get_ports { ddr1_dq[19] }]
|
||||
set_load 10 [get_ports { ddr1_dq[18] }]
|
||||
set_load 10 [get_ports { ddr1_dq[17] }]
|
||||
set_load 10 [get_ports { ddr1_dq[16] }]
|
||||
set_load 10 [get_ports { ddr1_dq[15] }]
|
||||
set_load 10 [get_ports { ddr1_dq[14] }]
|
||||
set_load 10 [get_ports { ddr1_dq[13] }]
|
||||
set_load 10 [get_ports { ddr1_dq[12] }]
|
||||
set_load 10 [get_ports { ddr1_dq[11] }]
|
||||
set_load 10 [get_ports { ddr1_dq[10] }]
|
||||
set_load 10 [get_ports { ddr1_dq[9] }]
|
||||
set_load 10 [get_ports { ddr1_dq[8] }]
|
||||
set_load 10 [get_ports { ddr1_dq[7] }]
|
||||
set_load 10 [get_ports { ddr1_dq[6] }]
|
||||
set_load 10 [get_ports { ddr1_dq[5] }]
|
||||
set_load 10 [get_ports { ddr1_dq[4] }]
|
||||
set_load 10 [get_ports { ddr1_dq[3] }]
|
||||
set_load 10 [get_ports { ddr1_dq[2] }]
|
||||
set_load 10 [get_ports { ddr1_dq[1] }]
|
||||
set_load 10 [get_ports { ddr1_dq[0] }]
|
||||
set_load 10 [get_ports { ddr2_dq[31] }]
|
||||
set_load 10 [get_ports { ddr2_dq[30] }]
|
||||
set_load 10 [get_ports { ddr2_dq[29] }]
|
||||
set_load 10 [get_ports { ddr2_dq[28] }]
|
||||
set_load 10 [get_ports { ddr2_dq[27] }]
|
||||
set_load 10 [get_ports { ddr2_dq[26] }]
|
||||
set_load 10 [get_ports { ddr2_dq[25] }]
|
||||
set_load 10 [get_ports { ddr2_dq[24] }]
|
||||
set_load 10 [get_ports { ddr2_dq[23] }]
|
||||
set_load 10 [get_ports { ddr2_dq[22] }]
|
||||
set_load 10 [get_ports { ddr2_dq[21] }]
|
||||
set_load 10 [get_ports { ddr2_dq[20] }]
|
||||
set_load 10 [get_ports { ddr2_dq[19] }]
|
||||
set_load 10 [get_ports { ddr2_dq[18] }]
|
||||
set_load 10 [get_ports { ddr2_dq[17] }]
|
||||
set_load 10 [get_ports { ddr2_dq[16] }]
|
||||
set_load 10 [get_ports { ddr2_dq[15] }]
|
||||
set_load 10 [get_ports { ddr2_dq[14] }]
|
||||
set_load 10 [get_ports { ddr2_dq[13] }]
|
||||
set_load 10 [get_ports { ddr2_dq[12] }]
|
||||
set_load 10 [get_ports { ddr2_dq[11] }]
|
||||
set_load 10 [get_ports { ddr2_dq[10] }]
|
||||
set_load 10 [get_ports { ddr2_dq[9] }]
|
||||
set_load 10 [get_ports { ddr2_dq[8] }]
|
||||
set_load 10 [get_ports { ddr2_dq[7] }]
|
||||
set_load 10 [get_ports { ddr2_dq[6] }]
|
||||
set_load 10 [get_ports { ddr2_dq[5] }]
|
||||
set_load 10 [get_ports { ddr2_dq[4] }]
|
||||
set_load 10 [get_ports { ddr2_dq[3] }]
|
||||
set_load 10 [get_ports { ddr2_dq[2] }]
|
||||
set_load 10 [get_ports { ddr2_dq[1] }]
|
||||
set_load 10 [get_ports { ddr2_dq[0] }]
|
||||
set_load 10 [get_ports { ddr3_dq[31] }]
|
||||
set_load 10 [get_ports { ddr3_dq[30] }]
|
||||
set_load 10 [get_ports { ddr3_dq[29] }]
|
||||
set_load 10 [get_ports { ddr3_dq[28] }]
|
||||
set_load 10 [get_ports { ddr3_dq[27] }]
|
||||
set_load 10 [get_ports { ddr3_dq[26] }]
|
||||
set_load 10 [get_ports { ddr3_dq[25] }]
|
||||
set_load 10 [get_ports { ddr3_dq[24] }]
|
||||
set_load 10 [get_ports { ddr3_dq[23] }]
|
||||
set_load 10 [get_ports { ddr3_dq[22] }]
|
||||
set_load 10 [get_ports { ddr3_dq[21] }]
|
||||
set_load 10 [get_ports { ddr3_dq[20] }]
|
||||
set_load 10 [get_ports { ddr3_dq[19] }]
|
||||
set_load 10 [get_ports { ddr3_dq[18] }]
|
||||
set_load 10 [get_ports { ddr3_dq[17] }]
|
||||
set_load 10 [get_ports { ddr3_dq[16] }]
|
||||
set_load 10 [get_ports { ddr3_dq[15] }]
|
||||
set_load 10 [get_ports { ddr3_dq[14] }]
|
||||
set_load 10 [get_ports { ddr3_dq[13] }]
|
||||
set_load 10 [get_ports { ddr3_dq[12] }]
|
||||
set_load 10 [get_ports { ddr3_dq[11] }]
|
||||
set_load 10 [get_ports { ddr3_dq[10] }]
|
||||
set_load 10 [get_ports { ddr3_dq[9] }]
|
||||
set_load 10 [get_ports { ddr3_dq[8] }]
|
||||
set_load 10 [get_ports { ddr3_dq[7] }]
|
||||
set_load 10 [get_ports { ddr3_dq[6] }]
|
||||
set_load 10 [get_ports { ddr3_dq[5] }]
|
||||
set_load 10 [get_ports { ddr3_dq[4] }]
|
||||
set_load 10 [get_ports { ddr3_dq[3] }]
|
||||
set_load 10 [get_ports { ddr3_dq[2] }]
|
||||
set_load 10 [get_ports { ddr3_dq[1] }]
|
||||
set_load 10 [get_ports { ddr3_dq[0] }]
|
||||
set_load 10 [get_ports usb_plus]
|
||||
set_load 10 [get_ports usb_minus]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[31] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[30] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[29] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[28] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[27] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[26] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[25] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[24] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[23] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[22] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[21] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[20] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[19] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[18] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[17] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[16] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[15] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[14] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[13] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[12] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[11] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[10] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[9] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[8] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[7] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[6] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[5] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[4] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[3] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[2] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[1] }]
|
||||
set_input_transition 0.1 [get_ports { ddr0_dq[0] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[31] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[30] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[29] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[28] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[27] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[26] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[25] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[24] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[23] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[22] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[21] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[20] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[19] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[18] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[17] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[16] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[15] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[14] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[13] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[12] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[11] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[10] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[9] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[8] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[7] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[6] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[5] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[4] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[3] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[2] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[1] }]
|
||||
set_input_transition 0.1 [get_ports { ddr1_dq[0] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[31] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[30] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[29] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[28] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[27] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[26] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[25] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[24] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[23] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[22] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[21] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[20] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[19] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[18] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[17] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[16] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[15] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[14] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[13] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[12] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[11] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[10] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[9] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[8] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[7] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[6] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[5] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[4] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[3] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[2] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[1] }]
|
||||
set_input_transition 0.1 [get_ports { ddr2_dq[0] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[31] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[30] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[29] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[28] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[27] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[26] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[25] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[24] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[23] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[22] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[21] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[20] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[19] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[18] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[17] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[16] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[15] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[14] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[13] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[12] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[11] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[10] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[9] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[8] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[7] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[6] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[5] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[4] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[3] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[2] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[1] }]
|
||||
set_input_transition 0.1 [get_ports { ddr3_dq[0] }]
|
||||
set_input_transition 0.1 [get_ports usb_plus]
|
||||
set_input_transition 0.1 [get_ports usb_minus]
|
||||
set_input_transition 0.1 [get_ports reset_n]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[15] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[14] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[13] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[12] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[11] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[10] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[9] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[8] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[7] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[6] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[5] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[4] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[3] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[2] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[1] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_0[0] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[15] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[14] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[13] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[12] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[11] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[10] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[9] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[8] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[7] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[6] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[5] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[4] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[3] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[2] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[1] }]
|
||||
set_input_transition 0.1 [get_ports { BS_data_1[0] }]
|
||||
set_input_transition 0.1 [get_ports lfxt_clk]
|
||||
set_input_transition 0.1 [get_ports nmi]
|
||||
set_input_transition 0.1 [get_ports scan_mode]
|
||||
set_input_transition 0.1 [get_ports sysclk_byp]
|
||||
set_input_transition 0.1 [get_ports usbclk_byp]
|
||||
set_case_analysis 0 [get_ports scan_mode]
|
||||
set_input_delay 0.7 [get_ports usb_minus]
|
||||
set_input_delay 0.7 [get_ports usb_plus]
|
||||
set_clock_groups -name CLOCK_GROUP__0 -asynchronous -group [get_clocks lfxt_clk] -group [get_clocks sysclk] -group [get_clocks usbclk]
|
||||
|
||||
|
||||
|
||||
Executable
+29
@@ -0,0 +1,29 @@
|
||||
#
|
||||
# Created by Oasys-RTL -- (c) Mentor Graphics Corporation
|
||||
#
|
||||
VERSION 5.8 ;
|
||||
NAMESCASESENSITIVE ON ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN demo_chip ;
|
||||
UNITS DISTANCE MICRONS 2000 ;
|
||||
|
||||
PROPERTYDEFINITIONS
|
||||
END PROPERTYDEFINITIONS
|
||||
|
||||
DIEAREA ( 0 0 ) ( 2834850 2834850 ) ;
|
||||
|
||||
REGIONS 2 ;
|
||||
- __r__6 ( 64840 50430 ) ( 1549550 1203580 ) ;
|
||||
- __r__7 ( 1254060 1513530 ) ( 2803620 2767590 ) ;
|
||||
END REGIONS
|
||||
COMPONENTS 352 ;
|
||||
- i_cpu_sys cpu_sys
|
||||
+ REGION __r__6
|
||||
;
|
||||
- i_usbf usb_sys
|
||||
+ REGION __r__7
|
||||
;
|
||||
END COMPONENTS
|
||||
|
||||
END DESIGN
|
||||
Executable
+89
@@ -0,0 +1,89 @@
|
||||
######################################################################
|
||||
# Design : demo_chip
|
||||
# SDC timing constraint file
|
||||
######################################################################
|
||||
set clock_period 100.0
|
||||
set sysclk_multiplier 40
|
||||
set usbclk_multiplier 6
|
||||
set clock_margin 0.20
|
||||
set pad_load 10
|
||||
set transition 0.1
|
||||
set io_clock_period [ expr ${clock_period} / ${sysclk_multiplier} ]
|
||||
set io_clock_period_ddr [ expr ${io_clock_period} / 2 ]
|
||||
|
||||
# ------------------------------------------------------------------
|
||||
# Clock definitions
|
||||
# ------------------------------------------------------------------
|
||||
# PLL input clock 10MHz
|
||||
create_clock -name lfxt_clk -period ${clock_period} [ get_ports lfxt_clk ]
|
||||
|
||||
# Main system clock - 400MHz
|
||||
create_generated_clock \
|
||||
-name sysclk \
|
||||
-source [ get_pins i_MAIN_PLL/REF ] \
|
||||
-multiply_by ${sysclk_multiplier} \
|
||||
-add -master_clock lfxt_clk \
|
||||
[ get_pins i_MAIN_PLL/PLLOUT ]
|
||||
|
||||
# USB clock - 60MHz
|
||||
create_generated_clock \
|
||||
-name usbclk \
|
||||
-source [ get_pins i_USB_PLL/REF ] \
|
||||
-multiply_by ${usbclk_multiplier} \
|
||||
-add -master_clock lfxt_clk \
|
||||
[ get_pins i_USB_PLL/PLLOUT ]
|
||||
|
||||
# Scan mode clocks
|
||||
create_clock -name sysclk_byp -period ${clock_period} [ get_ports sysclk_byp ]
|
||||
create_clock -name usbclk_byp -period ${clock_period} [ get_ports usbclk_byp ]
|
||||
|
||||
# Virtual clocks for I/O and DDR timing
|
||||
create_clock -name vsysclk -period ${io_clock_period}
|
||||
create_clock -name vsysclk_ddr -period ${io_clock_period_ddr}
|
||||
|
||||
# Apply uncertainties to clocks
|
||||
set_clock_uncertainty -setup ${clock_margin} [ get_clocks sysclk ]
|
||||
set_clock_uncertainty -setup ${clock_margin} [ get_clocks usbclk ]
|
||||
|
||||
# ------------------------------------------------------------------
|
||||
# port timings
|
||||
# ------------------------------------------------------------------
|
||||
set_input_delay 0.4 [get_ports usb_minus]
|
||||
set_input_delay 0.4 [get_ports usb_plus]
|
||||
set_input_delay -clock vsysclk [ expr 0.4 *${io_clock_period} ] \
|
||||
[ remove_from_collection [ all_inputs ] [ get_ports { lfxt_clk usb_plus usb_minus ddr*dq }] ]
|
||||
set_output_delay -clock vsysclk [ expr 0.3 * ${io_clock_period} ] \
|
||||
[ remove_from_collection [ all_outputs ] [ get_ports { usb_plus usb_minus }] ]
|
||||
|
||||
# DDR input timings
|
||||
set_input_delay -clock vsysclk_ddr [ expr 0.4 * ${io_clock_period_ddr} ] \
|
||||
[ get_ports { ddr*dq* }]
|
||||
|
||||
# ------------------------------------------------------------------
|
||||
# external conditions
|
||||
# ------------------------------------------------------------------
|
||||
set_load ${pad_load} [ all_outputs ]
|
||||
set_input_transition ${transition} [ all_inputs ]
|
||||
|
||||
# ------------------------------------------------------------------
|
||||
# Exceptions
|
||||
# ------------------------------------------------------------------
|
||||
# NMI and reset are asynchronous
|
||||
set_false_path -from [ get_ports nmi ]
|
||||
set_false_path -from [ get_ports reset_n ]
|
||||
|
||||
# Power up/down will take long time --> set false paths
|
||||
set_false_path -through [ get_pins {nova0/power_control nova0/power_ack nova1/power_control nova1/power_ack i_usbf/*power_control i_usbf/*power_ack }]
|
||||
|
||||
# All clock domain crossings are async
|
||||
set_clock_groups -asynchronous \
|
||||
-group lfxt_clk \
|
||||
-group sysclk \
|
||||
-group usbclk
|
||||
|
||||
# Block scan clocks with case analysis
|
||||
set_case_analysis 0 [get_ports scan_mode]
|
||||
set_false_path -from SCAN_ENABLE
|
||||
|
||||
set_input_delay 0.7 [get_ports usb_minus]
|
||||
set_input_delay 0.7 [get_ports usb_plus]
|
||||
@@ -0,0 +1,76 @@
|
||||
# =============================================================================
|
||||
# Constraints File: cpu.sdc
|
||||
# Project: BCDC Microtec Academy - RISC-V CPU
|
||||
# Top Module: cpu
|
||||
# =============================================================================
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 1. Primary Clock - 25 MHz input clock
|
||||
# -----------------------------------------------------------------------------
|
||||
create_clock -name clk_25mhz \
|
||||
-period 40.000 \
|
||||
-waveform {0 20} \
|
||||
[get_ports clk_25mhz]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 2. Generated Clock - 12.5 MHz (divided by 2 inside always_ff)
|
||||
# -----------------------------------------------------------------------------
|
||||
#create_generated_clock -name clk_12p5 \
|
||||
# -source [get_ports clk_25mhz] \
|
||||
# -divide_by 2 \
|
||||
# [get_pins thePC/clk]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 3. Clock Uncertainty & Transition
|
||||
# -----------------------------------------------------------------------------
|
||||
set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz]
|
||||
set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz]
|
||||
|
||||
set_clock_transition 0.1 [get_clocks clk_25mhz]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 4. Input Delays (btn pins - relative to clk_25mhz)
|
||||
# -----------------------------------------------------------------------------
|
||||
set_input_delay -clock clk_25mhz -max 2.0 [get_ports {btn[*]}]
|
||||
set_input_delay -clock clk_25mhz -min 0.5 [get_ports {btn[*]}]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 5. Output Delays (led pins)
|
||||
# -----------------------------------------------------------------------------
|
||||
set_output_delay -clock clk_25mhz -max 2.0 [get_ports {led[*]}]
|
||||
set_output_delay -clock clk_25mhz -min 0.5 [get_ports {led[*]}]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 6. False Paths
|
||||
# -----------------------------------------------------------------------------
|
||||
# Reset is async and driven from a button - no timing analysis needed
|
||||
set_false_path -from [get_ports {btn[0]}]
|
||||
|
||||
# LED outputs driven from combinational/slow logic - relax if needed
|
||||
# set_false_path -to [get_ports {led[*]}]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 7. Clock Domain Crossing
|
||||
# -----------------------------------------------------------------------------
|
||||
# clk12p5 is derived from clk_25mhz via FF division - set as async crossing
|
||||
# to prevent hold violations across the two domains
|
||||
#set_clock_groups -asynchronous \
|
||||
-group [get_clocks clk_25mhz] \
|
||||
-group [get_clocks clk_12p5]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 8. Drive Strength & Load (adjust to your target technology)
|
||||
# -----------------------------------------------------------------------------
|
||||
#set_driving_cell -lib_cell <YOUR_INPUT_BUF> [get_ports {btn[*]}]
|
||||
|
||||
set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[*]}]
|
||||
|
||||
set_load 0.05 [get_ports {led[*]}]
|
||||
|
||||
# -----------------------------------------------------------------------------
|
||||
# 9. Max Fanout & Transition
|
||||
# -----------------------------------------------------------------------------
|
||||
set_max_fanout 20 [current_design]
|
||||
set_max_transition 0.5 [current_design]
|
||||
|
||||
|
||||
Reference in New Issue
Block a user