Initial commit
This commit is contained in:
muellerlu
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To be added soon
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nova_spec.doc:specifications of nova design
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : Beha_BitStream_ram.v
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// Generated : May 16,2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Behavior RAM for encoded bitstream storing, NOT synthesizable
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module Beha_BitStream_ram(clk,BitStream_ram_ren,BitStream_ram_addr,BitStream_ram_data);
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input clk;
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input BitStream_ram_ren;
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input [16:0] BitStream_ram_addr;
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output [15:0] BitStream_ram_data;
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reg [15:0] BitStream_ram_data;
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reg [15:0] BitStream_ram[0:`Beha_Bitstream_ram_size];
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initial
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begin
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$readmemh("D:/nova_opencores/bin2hex/akiyo300_1ref.txt",BitStream_ram);
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end
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always @ (posedge clk)
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if (BitStream_ram_ren == 0)
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BitStream_ram_data <= #2 BitStream_ram[BitStream_ram_addr];
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endmodule
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : BitStream_buffer.v
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// Generated : May 16,2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Circular buffer,interfacing between Beha_Bitstream_ram and the decoder
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module BitStream_buffer (clk,reset_n,BitStream_buffer_input,pc,
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BitStream_ram_ren,BitStream_buffer_valid_n,BitStream_buffer_output,BitStream_ram_addr);
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input clk,reset_n;
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input [15:0] BitStream_buffer_input;
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input [6:0] pc;
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output BitStream_ram_ren;
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output BitStream_buffer_valid_n;
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output [15:0] BitStream_buffer_output;
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output [16:0]BitStream_ram_addr;
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reg BitStream_ram_ren;
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reg BitStream_buffer_valid_n;
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reg [15:0] BitStream_buffer_output;
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reg [16:0]BitStream_ram_addr;
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reg [0:127]BS_buffer;
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reg [6:0] pc_previous;
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reg [3:0] reset_counter;
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reg [2:0] half_fill_counter;
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reg [6:0] buffer_index; //for buffer write
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/*
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// synopsys translate_off
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integer pc_statistical;
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initial
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begin
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pc_statistical = $fopen("pc_statistical.txt");
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end
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always @ (posedge clk)
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$fdisplay (pc_statistical,"%d",pc);
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// synopsys translate_on
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*/
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always @ (posedge clk)
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if (reset_n == 1'b0)
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pc_previous <= 0;
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else
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pc_previous <= pc;
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always @ (posedge clk)
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if (reset_n == 1'b0)
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reset_counter <= 0;
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else if (reset_counter < 10)
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reset_counter <= reset_counter + 1;
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always @ (posedge clk)
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if (reset_n == 1'b0)
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half_fill_counter <= 0;
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else if (reset_counter == 10)
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begin
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if (((pc > 63 && pc_previous <= 63) || (pc <63 && pc_previous >=63)) && half_fill_counter == 0)
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half_fill_counter <= 1;
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else if (pc > 63 && half_fill_counter == 0 && buffer_index == 0)
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half_fill_counter <= 1;
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else if (pc < 63 && half_fill_counter == 0 && buffer_index == 64)
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half_fill_counter <= 1;
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else if (half_fill_counter > 0 && half_fill_counter < 5)
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half_fill_counter <= half_fill_counter + 1;
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else if (half_fill_counter == 5)
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half_fill_counter <= 0;
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end
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always @ (posedge clk)
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if (reset_n == 1'b0)
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buffer_index <= 0;
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else if (reset_counter > 1 && reset_counter < 10)
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buffer_index <= buffer_index + 16;
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else if (half_fill_counter > 1 && half_fill_counter <= 5)
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buffer_index <= buffer_index + 16;
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always @ (posedge clk)
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if (reset_n == 1'b0)
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BitStream_buffer_valid_n <= 1'b1;
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else if (reset_counter == 10)
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BitStream_buffer_valid_n <= 1'b0;
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always @ (posedge clk)
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if (reset_n == 1'b0)
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BitStream_ram_ren <= 1'b0;
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else if (reset_counter < 9)
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BitStream_ram_ren <= 1'b0;
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else if (reset_counter == 9)
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BitStream_ram_ren <= 1'b1;
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else
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begin
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if (((pc > 63 && pc_previous <= 63) || (pc <63 && pc_previous >=63)) && half_fill_counter == 0)
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BitStream_ram_ren <= 0;
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else if (half_fill_counter > 0 && half_fill_counter < 5)
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BitStream_ram_ren <= 0;
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else
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BitStream_ram_ren <= 1;
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end
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always @ (posedge clk)
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if (reset_n == 1'b0)
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BitStream_ram_addr <= 0;
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else if (reset_counter > 0 && reset_counter < 9)
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BitStream_ram_addr <= BitStream_ram_addr + 1;
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else if (half_fill_counter > 0 && half_fill_counter < 5 && BitStream_ram_addr != 17'd131071) //no wrap around
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BitStream_ram_addr <= BitStream_ram_addr + 1;
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integer i;
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always @ (posedge clk)
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if (reset_n == 1'b0)
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BS_buffer <= 0;
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else if ((reset_counter > 1 && reset_counter < 10) || (half_fill_counter > 1 && half_fill_counter <= 5))
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case (buffer_index[6:4])
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3'b000:
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for (i=0;i<16;i=i+1)
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BS_buffer[i] <= BitStream_buffer_input[15-i];
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3'b001:
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for (i=0;i<16;i=i+1)
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BS_buffer[16+i] <= BitStream_buffer_input[15-i];
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3'b010:
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for (i=0;i<16;i=i+1)
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BS_buffer[32+i] <= BitStream_buffer_input[15-i];
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3'b011:
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for (i=0;i<16;i=i+1)
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BS_buffer[48+i] <= BitStream_buffer_input[15-i];
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3'b100:
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for (i=0;i<16;i=i+1)
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BS_buffer[64+i] <= BitStream_buffer_input[15-i];
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3'b101:
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for (i=0;i<16;i=i+1)
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BS_buffer[80+i] <= BitStream_buffer_input[15-i];
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3'b110:
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for (i=0;i<16;i=i+1)
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BS_buffer[96+i] <= BitStream_buffer_input[15-i];
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3'b111:
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for (i=0;i<16;i=i+1)
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BS_buffer[112+i] <= BitStream_buffer_input[15-i];
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endcase
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always @ (posedge clk)
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//always @ (reset_n or BitStream_buffer_valid_n or pc)
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if (reset_n == 1'b0)
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BitStream_buffer_output <= 0;
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else if (BitStream_buffer_valid_n == 0)
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case (pc)
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0 :BitStream_buffer_output <= BS_buffer[0:15];
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1 :BitStream_buffer_output <= BS_buffer[1:16];
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2 :BitStream_buffer_output <= BS_buffer[2:17];
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3 :BitStream_buffer_output <= BS_buffer[3:18];
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4 :BitStream_buffer_output <= BS_buffer[4:19];
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5 :BitStream_buffer_output <= BS_buffer[5:20];
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6 :BitStream_buffer_output <= BS_buffer[6:21];
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7 :BitStream_buffer_output <= BS_buffer[7:22];
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8 :BitStream_buffer_output <= BS_buffer[8:23];
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9 :BitStream_buffer_output <= BS_buffer[9:24];
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10 :BitStream_buffer_output <= BS_buffer[10:25];
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11 :BitStream_buffer_output <= BS_buffer[11:26];
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12 :BitStream_buffer_output <= BS_buffer[12:27];
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13 :BitStream_buffer_output <= BS_buffer[13:28];
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14 :BitStream_buffer_output <= BS_buffer[14:29];
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15 :BitStream_buffer_output <= BS_buffer[15:30];
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16 :BitStream_buffer_output <= BS_buffer[16:31];
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17 :BitStream_buffer_output <= BS_buffer[17:32];
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18 :BitStream_buffer_output <= BS_buffer[18:33];
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19 :BitStream_buffer_output <= BS_buffer[19:34];
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20 :BitStream_buffer_output <= BS_buffer[20:35];
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21 :BitStream_buffer_output <= BS_buffer[21:36];
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22 :BitStream_buffer_output <= BS_buffer[22:37];
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23 :BitStream_buffer_output <= BS_buffer[23:38];
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24 :BitStream_buffer_output <= BS_buffer[24:39];
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25 :BitStream_buffer_output <= BS_buffer[25:40];
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26 :BitStream_buffer_output <= BS_buffer[26:41];
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27 :BitStream_buffer_output <= BS_buffer[27:42];
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28 :BitStream_buffer_output <= BS_buffer[28:43];
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29 :BitStream_buffer_output <= BS_buffer[29:44];
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30 :BitStream_buffer_output <= BS_buffer[30:45];
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31 :BitStream_buffer_output <= BS_buffer[31:46];
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32 :BitStream_buffer_output <= BS_buffer[32:47];
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33 :BitStream_buffer_output <= BS_buffer[33:48];
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34 :BitStream_buffer_output <= BS_buffer[34:49];
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35 :BitStream_buffer_output <= BS_buffer[35:50];
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36 :BitStream_buffer_output <= BS_buffer[36:51];
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37 :BitStream_buffer_output <= BS_buffer[37:52];
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38 :BitStream_buffer_output <= BS_buffer[38:53];
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39 :BitStream_buffer_output <= BS_buffer[39:54];
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40 :BitStream_buffer_output <= BS_buffer[40:55];
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41 :BitStream_buffer_output <= BS_buffer[41:56];
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42 :BitStream_buffer_output <= BS_buffer[42:57];
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43 :BitStream_buffer_output <= BS_buffer[43:58];
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44 :BitStream_buffer_output <= BS_buffer[44:59];
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45 :BitStream_buffer_output <= BS_buffer[45:60];
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46 :BitStream_buffer_output <= BS_buffer[46:61];
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47 :BitStream_buffer_output <= BS_buffer[47:62];
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48 :BitStream_buffer_output <= BS_buffer[48:63];
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49 :BitStream_buffer_output <= BS_buffer[49:64];
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50 :BitStream_buffer_output <= BS_buffer[50:65];
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51 :BitStream_buffer_output <= BS_buffer[51:66];
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52 :BitStream_buffer_output <= BS_buffer[52:67];
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53 :BitStream_buffer_output <= BS_buffer[53:68];
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54 :BitStream_buffer_output <= BS_buffer[54:69];
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55 :BitStream_buffer_output <= BS_buffer[55:70];
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56 :BitStream_buffer_output <= BS_buffer[56:71];
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57 :BitStream_buffer_output <= BS_buffer[57:72];
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58 :BitStream_buffer_output <= BS_buffer[58:73];
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59 :BitStream_buffer_output <= BS_buffer[59:74];
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60 :BitStream_buffer_output <= BS_buffer[60:75];
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61 :BitStream_buffer_output <= BS_buffer[61:76];
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62 :BitStream_buffer_output <= BS_buffer[62:77];
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63 :BitStream_buffer_output <= BS_buffer[63:78];
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64 :BitStream_buffer_output <= BS_buffer[64:79];
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65 :BitStream_buffer_output <= BS_buffer[65:80];
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66 :BitStream_buffer_output <= BS_buffer[66:81];
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67 :BitStream_buffer_output <= BS_buffer[67:82];
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68 :BitStream_buffer_output <= BS_buffer[68:83];
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69 :BitStream_buffer_output <= BS_buffer[69:84];
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70 :BitStream_buffer_output <= BS_buffer[70:85];
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71 :BitStream_buffer_output <= BS_buffer[71:86];
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72 :BitStream_buffer_output <= BS_buffer[72:87];
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73 :BitStream_buffer_output <= BS_buffer[73:88];
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74 :BitStream_buffer_output <= BS_buffer[74:89];
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75 :BitStream_buffer_output <= BS_buffer[75:90];
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76 :BitStream_buffer_output <= BS_buffer[76:91];
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77 :BitStream_buffer_output <= BS_buffer[77:92];
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78 :BitStream_buffer_output <= BS_buffer[78:93];
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79 :BitStream_buffer_output <= BS_buffer[79:94];
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80 :BitStream_buffer_output <= BS_buffer[80:95];
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81 :BitStream_buffer_output <= BS_buffer[81:96];
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82 :BitStream_buffer_output <= BS_buffer[82:97];
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83 :BitStream_buffer_output <= BS_buffer[83:98];
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84 :BitStream_buffer_output <= BS_buffer[84:99];
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85 :BitStream_buffer_output <= BS_buffer[85:100];
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86 :BitStream_buffer_output <= BS_buffer[86:101];
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87 :BitStream_buffer_output <= BS_buffer[87:102];
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88 :BitStream_buffer_output <= BS_buffer[88:103];
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89 :BitStream_buffer_output <= BS_buffer[89:104];
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90 :BitStream_buffer_output <= BS_buffer[90:105];
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91 :BitStream_buffer_output <= BS_buffer[91:106];
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92 :BitStream_buffer_output <= BS_buffer[92:107];
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93 :BitStream_buffer_output <= BS_buffer[93:108];
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94 :BitStream_buffer_output <= BS_buffer[94:109];
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95 :BitStream_buffer_output <= BS_buffer[95:110];
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96 :BitStream_buffer_output <= BS_buffer[96:111];
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97 :BitStream_buffer_output <= BS_buffer[97:112];
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98 :BitStream_buffer_output <= BS_buffer[98:113];
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99 :BitStream_buffer_output <= BS_buffer[99:114];
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100:BitStream_buffer_output <= BS_buffer[100:115];
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101:BitStream_buffer_output <= BS_buffer[101:116];
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102:BitStream_buffer_output <= BS_buffer[102:117];
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103:BitStream_buffer_output <= BS_buffer[103:118];
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104:BitStream_buffer_output <= BS_buffer[104:119];
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105:BitStream_buffer_output <= BS_buffer[105:120];
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106:BitStream_buffer_output <= BS_buffer[106:121];
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107:BitStream_buffer_output <= BS_buffer[107:122];
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108:BitStream_buffer_output <= BS_buffer[108:123];
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109:BitStream_buffer_output <= BS_buffer[109:124];
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110:BitStream_buffer_output <= BS_buffer[110:125];
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111:BitStream_buffer_output <= BS_buffer[111:126];
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112:BitStream_buffer_output <= BS_buffer[112:127];
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113:BitStream_buffer_output <= {BS_buffer[113:127],BS_buffer[0]};
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114:BitStream_buffer_output <= {BS_buffer[114:127],BS_buffer[0:1]};
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115:BitStream_buffer_output <= {BS_buffer[115:127],BS_buffer[0:2]};
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116:BitStream_buffer_output <= {BS_buffer[116:127],BS_buffer[0:3]};
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117:BitStream_buffer_output <= {BS_buffer[117:127],BS_buffer[0:4]};
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118:BitStream_buffer_output <= {BS_buffer[118:127],BS_buffer[0:5]};
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119:BitStream_buffer_output <= {BS_buffer[119:127],BS_buffer[0:6]};
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120:BitStream_buffer_output <= {BS_buffer[120:127],BS_buffer[0:7]};
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121:BitStream_buffer_output <= {BS_buffer[121:127],BS_buffer[0:8]};
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122:BitStream_buffer_output <= {BS_buffer[122:127],BS_buffer[0:9]};
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123:BitStream_buffer_output <= {BS_buffer[123:127],BS_buffer[0:10]};
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124:BitStream_buffer_output <= {BS_buffer[124:127],BS_buffer[0:11]};
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125:BitStream_buffer_output <= {BS_buffer[125:127],BS_buffer[0:12]};
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126:BitStream_buffer_output <= {BS_buffer[126:127],BS_buffer[0:13]};
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127:BitStream_buffer_output <= {BS_buffer[127],BS_buffer[0:14]};
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endcase
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endmodule
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||||
|
||||
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||||
@@ -0,0 +1,745 @@
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||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : BitStream_controller.v
|
||||
// Generated : June 12,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// top module for bitstream controller
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module BitStream_controller (clk,reset_n,freq_ctrl0,freq_ctrl1,BitStream_buffer_input,pin_disable_DF,
|
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trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,gclk_end_of_MB_DEC,
|
||||
curr_DC_IsZero,
|
||||
|
||||
BitStream_ram_ren,BitStream_ram_addr,pic_num,
|
||||
mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip,
|
||||
slice_data_state,residual_state,cavlc_decoder_state,
|
||||
end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame,
|
||||
Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
|
||||
QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
|
||||
CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff,
|
||||
Is_skip_run_entry,skip_mv_calc,disable_DF,
|
||||
coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7,
|
||||
coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15,
|
||||
mv_is16x16,mv_below8x8,
|
||||
mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
|
||||
end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
|
||||
|
||||
slice_header_s6
|
||||
);
|
||||
input clk,reset_n;
|
||||
input freq_ctrl0;
|
||||
input freq_ctrl1;
|
||||
input [15:0] BitStream_buffer_input;
|
||||
input pin_disable_DF;
|
||||
input trigger_CAVLC;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input end_of_DCBlk_IQIT;
|
||||
input end_of_one_blk4x4_sum;
|
||||
input end_of_MB_DEC;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input curr_DC_IsZero;
|
||||
|
||||
output BitStream_ram_ren;
|
||||
output [16:0] BitStream_ram_addr;
|
||||
output [5:0] pic_num;
|
||||
|
||||
output [3:0] mb_type_general;
|
||||
output [3:0] mb_num_h;
|
||||
output [3:0] mb_num_v;
|
||||
output NextMB_IsSkip;
|
||||
output LowerMB_IsSkip;
|
||||
output [3:0] slice_data_state;
|
||||
output [3:0] residual_state;
|
||||
output [3:0] cavlc_decoder_state;
|
||||
output end_of_one_residual_block;
|
||||
output end_of_NonZeroCoeff_CAVLC;
|
||||
output end_of_one_frame;
|
||||
output [1:0] Intra16x16_predmode;
|
||||
output [63:0] Intra4x4_predmode_CurrMb;
|
||||
output [1:0] Intra_chroma_predmode;
|
||||
output [5:0] QPy;
|
||||
output [5:0] QPc;
|
||||
output [1:0] i4x4_CbCr;
|
||||
output [3:0] slice_alpha_c0_offset_div2;
|
||||
output [3:0] slice_beta_offset_div2;
|
||||
output [3:0] CodedBlockPatternLuma;
|
||||
output [1:0] CodedBlockPatternChroma;
|
||||
output [4:0] TotalCoeff;
|
||||
output Is_skip_run_entry;
|
||||
output skip_mv_calc;
|
||||
output disable_DF;
|
||||
output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5;
|
||||
output [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
|
||||
output [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
|
||||
output mv_is16x16;
|
||||
output [3:0] mv_below8x8;
|
||||
output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
output end_of_BS_DEC;
|
||||
output [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
|
||||
output [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
|
||||
output slice_header_s6;
|
||||
|
||||
wire gclk_parser;
|
||||
wire gclk_nal;
|
||||
wire gclk_slice;
|
||||
wire gclk_sps;
|
||||
wire gclk_pps;
|
||||
wire gclk_slice_header;
|
||||
wire gclk_slice_data;
|
||||
wire gclk_residual;
|
||||
wire gclk_cavlc;
|
||||
wire gclk_bs_dec;
|
||||
wire gclk_Intra4x4PredMode_mbAddrB_RF;
|
||||
wire gclk_mvx_mbAddrB_RF;
|
||||
wire gclk_mvy_mbAddrB_RF;
|
||||
wire gclk_mvx_mbAddrC_RF;
|
||||
wire gclk_mvy_mbAddrC_RF;
|
||||
wire gclk_LumaLevel_mbAddrB_RF;
|
||||
wire gclk_ChromaLevel_Cb_mbAddrB_RF;
|
||||
wire gclk_ChromaLevel_Cr_mbAddrB_RF;
|
||||
wire [6:0] pc;
|
||||
wire [5:0] QPy,QPc;
|
||||
wire [3:0] CodedBlockPatternLuma;
|
||||
wire [1:0] CodedBlockPatternChroma;
|
||||
wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5;
|
||||
wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
|
||||
wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
|
||||
wire [63:0] Intra4x4PredMode_CurrMb;
|
||||
wire mv_is16x16;
|
||||
wire Is_skip_run_end;
|
||||
wire Is_skipMB_mv_calc;
|
||||
wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
|
||||
wire BitStream_buffer_valid_n;
|
||||
wire [15:0] BitStream_buffer_output;
|
||||
wire [1:0] parser_state;
|
||||
wire [2:0] nal_unit_state;
|
||||
wire [1:0] slice_layer_wo_partitioning_state;
|
||||
wire [3:0] slice_header_state;
|
||||
wire [2:0] ref_pic_list_reordering_state;
|
||||
wire [1:0] dec_ref_pic_marking_state;
|
||||
wire [3:0] slice_data_state;
|
||||
wire [1:0] sub_mb_pred_state;
|
||||
wire [2:0] mb_pred_state;
|
||||
wire [3:0] seq_parameter_set_state;
|
||||
wire [3:0] pic_parameter_set_state;
|
||||
wire [3:0] residual_state;
|
||||
wire [3:0] cavlc_decoder_state;
|
||||
wire [3:0] exp_golomb_len;
|
||||
wire [3:0] dependent_variable_len;
|
||||
wire [4:0] cavlc_consumed_bits_len;
|
||||
wire heading_one_en;
|
||||
wire [3:0] heading_one_pos;
|
||||
wire [7:0] exp_golomb_decoding_output;
|
||||
wire [9:0] dependent_variable_decoding_output;
|
||||
wire Intra4x4PredMode_mbAddrB_cs_n;
|
||||
wire Intra4x4PredMode_mbAddrB_wr_n;
|
||||
wire [3:0] Intra4x4PredMode_mbAddrB_rd_addr;
|
||||
wire [3:0] Intra4x4PredMode_mbAddrB_wr_addr;
|
||||
wire [15:0] Intra4x4PredMode_mbAddrB_din;
|
||||
wire [15:0] Intra4x4PredMode_mbAddrB_dout;
|
||||
wire mvx_mbAddrB_cs_n;
|
||||
wire mvy_mbAddrB_cs_n;
|
||||
wire mvx_mbAddrC_cs_n;
|
||||
wire mvy_mbAddrC_cs_n;
|
||||
wire mvx_mbAddrB_wr_n;
|
||||
wire mvy_mbAddrB_wr_n;
|
||||
wire mvx_mbAddrC_wr_n;
|
||||
wire mvy_mbAddrC_wr_n;
|
||||
wire [3:0] mvx_mbAddrB_rd_addr;
|
||||
wire [3:0] mvy_mbAddrB_rd_addr;
|
||||
wire [3:0] mvx_mbAddrC_rd_addr;
|
||||
wire [3:0] mvy_mbAddrC_rd_addr;
|
||||
wire [3:0] mvx_mbAddrB_wr_addr;
|
||||
wire [3:0] mvy_mbAddrB_wr_addr;
|
||||
wire [3:0] mvx_mbAddrC_wr_addr;
|
||||
wire [3:0] mvy_mbAddrC_wr_addr;
|
||||
wire [31:0] mvx_mbAddrA;
|
||||
wire [31:0] mvy_mbAddrA;
|
||||
wire [31:0] mvx_mbAddrB_din;
|
||||
wire [31:0] mvx_mbAddrB_dout;
|
||||
wire [31:0] mvy_mbAddrB_din;
|
||||
wire [31:0] mvy_mbAddrB_dout;
|
||||
wire [7:0] mvx_mbAddrC_din;
|
||||
wire [7:0] mvx_mbAddrC_dout;
|
||||
wire [7:0] mvy_mbAddrC_din;
|
||||
wire [7:0] mvy_mbAddrC_dout;
|
||||
wire end_of_NonZeroCoeff_CAVLC;
|
||||
wire start_code_prefix_found;
|
||||
wire [4:0] nal_unit_type;
|
||||
wire deblocking_filter_control_present_flag;
|
||||
wire [1:0] disable_deblocking_filter_idc;
|
||||
wire disable_DF;
|
||||
wire [6:0] mb_skip_run;
|
||||
wire [2:0] NumMbPart;
|
||||
wire [2:0] NumSubMbPart;
|
||||
wire [1:0] MBTypeGen_mbAddrA;
|
||||
wire MBTypeGen_mbAddrD;
|
||||
wire [21:0]MBTypeGen_mbAddrB_reg;
|
||||
wire [3:0] log2_max_frame_num_minus4;
|
||||
wire [3:0] log2_max_pic_order_cnt_lsb_minus4;
|
||||
wire constrained_intra_pred_flag;
|
||||
wire num_ref_idx_active_override_flag;
|
||||
wire [2:0] num_ref_idx_l0_active_minus1;
|
||||
wire [2:0] slice_type;
|
||||
wire [4:0] mb_type;
|
||||
wire [3:0] mb_type_general;
|
||||
wire [1:0] sub_mb_type;
|
||||
wire [5:0] pic_init_qp_minus26;
|
||||
wire [4:0] chroma_qp_index_offset;
|
||||
wire [2:0] rem_intra4x4_pred_mode;
|
||||
wire [7:0] mvd;
|
||||
wire prev_intra4x4_pred_mode_flag;
|
||||
wire cavlc_decoder_en;
|
||||
wire [5:0] pic_num;
|
||||
wire [6:0] mb_num;
|
||||
wire [3:0] mb_num_h;
|
||||
wire [3:0] mb_num_v;
|
||||
wire [3:0] luma4x4BlkIdx;
|
||||
wire [1:0] mbPartIdx;
|
||||
wire [1:0] subMbPartIdx;
|
||||
wire compIdx;
|
||||
wire suffix_length_initialized;
|
||||
wire IsRunLoop;
|
||||
wire [1:0] i8x8,i4x4;
|
||||
wire [1:0] i4x4_CbCr;
|
||||
wire [3:0] coeffNum;
|
||||
wire [3:0] i_level;
|
||||
wire [3:0] i_run;
|
||||
wire [3:0] i_TotalCoeff;
|
||||
wire [4:0] TotalCoeff;
|
||||
wire [1:0] TrailingOnes;
|
||||
wire [4:0] maxNumCoeff;
|
||||
wire [3:0] zerosLeft;
|
||||
wire [3:0] run;
|
||||
|
||||
wire [1:0] Luma_8x8_AllZeroCoeff_mbAddrA;
|
||||
wire [19:0] LumaLevel_mbAddrA;
|
||||
wire [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
|
||||
wire LumaLevel_mbAddrB_cs_n;
|
||||
wire [19:0] LumaLevel_mbAddrB_dout;
|
||||
wire ChromaLevel_Cb_mbAddrB_cs_n;
|
||||
wire ChromaLevel_Cr_mbAddrB_cs_n;
|
||||
wire [1:0] bs_dec_counter;
|
||||
wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
|
||||
wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
wire mv_mbAddrB_rd_for_DF;
|
||||
|
||||
BitStream_buffer BitStream_buffer (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.BitStream_buffer_input(BitStream_buffer_input),
|
||||
.pc(pc),
|
||||
.BitStream_ram_ren(BitStream_ram_ren),
|
||||
.BitStream_buffer_valid_n(BitStream_buffer_valid_n),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.BitStream_ram_addr(BitStream_ram_addr)
|
||||
);
|
||||
bitstream_gclk_gen bitstream_gclk_gen (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.freq_ctrl0(freq_ctrl0),
|
||||
.freq_ctrl1(freq_ctrl1),
|
||||
.parser_state(parser_state),
|
||||
.nal_unit_state(nal_unit_state),
|
||||
.slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state),
|
||||
.slice_header_state(slice_header_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.seq_parameter_set_state(seq_parameter_set_state),
|
||||
.pic_parameter_set_state(pic_parameter_set_state),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.mb_num(mb_num),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.start_code_prefix_found(start_code_prefix_found),
|
||||
.pc_2to0(pc[2:0]),
|
||||
.deblocking_filter_control_present_flag(deblocking_filter_control_present_flag),
|
||||
.disable_deblocking_filter_idc(disable_deblocking_filter_idc),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n),
|
||||
.mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n),
|
||||
.mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n),
|
||||
.mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n),
|
||||
.mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n),
|
||||
.LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n),
|
||||
.ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n),
|
||||
.ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n),
|
||||
.trigger_CAVLC(trigger_CAVLC),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.disable_DF(disable_DF),
|
||||
.bs_dec_counter(bs_dec_counter),
|
||||
|
||||
.gclk_parser(gclk_parser),
|
||||
.gclk_nal(gclk_nal),
|
||||
.gclk_slice(gclk_slice),
|
||||
.gclk_sps(gclk_sps),
|
||||
.gclk_pps(gclk_pps),
|
||||
.gclk_slice_header(gclk_slice_header),
|
||||
.gclk_slice_data(gclk_slice_data),
|
||||
.gclk_residual(gclk_residual),
|
||||
.gclk_cavlc(gclk_cavlc),
|
||||
.gclk_Intra4x4PredMode_mbAddrB_RF(gclk_Intra4x4PredMode_mbAddrB_RF),
|
||||
.gclk_mvx_mbAddrB_RF(gclk_mvx_mbAddrB_RF),
|
||||
.gclk_mvy_mbAddrB_RF(gclk_mvy_mbAddrB_RF),
|
||||
.gclk_mvx_mbAddrC_RF(gclk_mvx_mbAddrC_RF),
|
||||
.gclk_mvy_mbAddrC_RF(gclk_mvy_mbAddrC_RF),
|
||||
.gclk_LumaLevel_mbAddrB_RF(gclk_LumaLevel_mbAddrB_RF),
|
||||
.gclk_ChromaLevel_Cb_mbAddrB_RF(gclk_ChromaLevel_Cb_mbAddrB_RF),
|
||||
.gclk_ChromaLevel_Cr_mbAddrB_RF(gclk_ChromaLevel_Cr_mbAddrB_RF),
|
||||
.gclk_bs_dec(gclk_bs_dec),
|
||||
.end_of_one_frame(end_of_one_frame)
|
||||
);
|
||||
BitStream_parser_FSM BitStream_parser_FSM(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.gclk_parser(gclk_parser),
|
||||
.gclk_nal(gclk_nal),
|
||||
.gclk_slice(gclk_slice),
|
||||
.gclk_sps(gclk_sps),
|
||||
.gclk_pps(gclk_pps),
|
||||
.gclk_slice_header(gclk_slice_header),
|
||||
.gclk_slice_data(gclk_slice_data),
|
||||
.gclk_residual(gclk_residual),
|
||||
.gclk_cavlc(gclk_cavlc),
|
||||
.trigger_CAVLC(trigger_CAVLC),
|
||||
.BitStream_buffer_valid_n(BitStream_buffer_valid_n),
|
||||
.nal_unit_type(nal_unit_type),
|
||||
.slice_type(slice_type),
|
||||
.num_ref_idx_active_override_flag(num_ref_idx_active_override_flag),
|
||||
.deblocking_filter_control_present_flag(deblocking_filter_control_present_flag),
|
||||
.disable_deblocking_filter_idc(disable_deblocking_filter_idc),
|
||||
.mb_skip_run(mb_skip_run),
|
||||
.mb_type_general(mb_type_general),
|
||||
.prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.pc_2to0(pc[2:0]),
|
||||
.NumSubMbPart(NumSubMbPart),
|
||||
.NumMbPart(NumMbPart),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.TrailingOnes(TrailingOnes),
|
||||
.maxNumCoeff(maxNumCoeff),
|
||||
.zerosLeft(zerosLeft),
|
||||
.run(run),
|
||||
|
||||
.parser_state(parser_state),
|
||||
.nal_unit_state(nal_unit_state),
|
||||
.slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state),
|
||||
.slice_header_state(slice_header_state),
|
||||
.slice_header_s6(slice_header_s6),
|
||||
.ref_pic_list_reordering_state(ref_pic_list_reordering_state),
|
||||
.dec_ref_pic_marking_state(dec_ref_pic_marking_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.sub_mb_pred_state(sub_mb_pred_state),
|
||||
.mb_pred_state(mb_pred_state),
|
||||
.seq_parameter_set_state(seq_parameter_set_state),
|
||||
.pic_parameter_set_state(pic_parameter_set_state),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.heading_one_en(heading_one_en),
|
||||
.pic_num(pic_num),
|
||||
.mb_num(mb_num),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.NextMB_IsSkip(NextMB_IsSkip),
|
||||
.LowerMB_IsSkip(LowerMB_IsSkip),
|
||||
.Is_skip_run_entry(Is_skip_run_entry),
|
||||
.Is_skip_run_end(Is_skip_run_end),
|
||||
.luma4x4BlkIdx(luma4x4BlkIdx),
|
||||
.mbPartIdx(mbPartIdx),
|
||||
.subMbPartIdx(subMbPartIdx),
|
||||
.compIdx(compIdx),
|
||||
.i8x8(i8x8),
|
||||
.i4x4(i4x4),
|
||||
.i4x4_CbCr(i4x4_CbCr),
|
||||
.coeffNum(coeffNum),
|
||||
.i_level(i_level),
|
||||
.i_run(i_run),
|
||||
.i_TotalCoeff(i_TotalCoeff),
|
||||
.suffix_length_initialized(suffix_length_initialized),
|
||||
.IsRunLoop(IsRunLoop)
|
||||
);
|
||||
pc_decoding pc_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.parser_state(parser_state),
|
||||
.nal_unit_state(nal_unit_state),
|
||||
.slice_header_state(slice_header_state),
|
||||
.ref_pic_list_reordering_state(ref_pic_list_reordering_state),
|
||||
.dec_ref_pic_marking_state(dec_ref_pic_marking_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.sub_mb_pred_state(sub_mb_pred_state),
|
||||
.mb_pred_state(mb_pred_state),
|
||||
.seq_parameter_set_state(seq_parameter_set_state),
|
||||
.pic_parameter_set_state(pic_parameter_set_state),
|
||||
.exp_golomb_len(exp_golomb_len),
|
||||
.dependent_variable_len(dependent_variable_len),
|
||||
.cavlc_consumed_bits_len(cavlc_consumed_bits_len),
|
||||
.pc(pc)
|
||||
);
|
||||
heading_one_detector heading_one_detector (
|
||||
.heading_one_en(heading_one_en),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.heading_one_pos(heading_one_pos)
|
||||
);
|
||||
exp_golomb_decoding exp_golomb_decoding (
|
||||
.reset_n(reset_n),
|
||||
.heading_one_pos(heading_one_pos),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.num_ref_idx_l0_active_minus1(num_ref_idx_l0_active_minus1),
|
||||
.exp_golomb_decoding_output(exp_golomb_decoding_output),
|
||||
.exp_golomb_len(exp_golomb_len),
|
||||
.slice_header_state(slice_header_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.mb_pred_state(mb_pred_state),
|
||||
.sub_mb_pred_state(sub_mb_pred_state),
|
||||
.seq_parameter_set_state(seq_parameter_set_state),
|
||||
.pic_parameter_set_state(pic_parameter_set_state)
|
||||
);
|
||||
dependent_variable_decoding dependent_variable_decoding (
|
||||
.slice_header_state(slice_header_state),
|
||||
.log2_max_frame_num_minus4(log2_max_frame_num_minus4),
|
||||
.log2_max_pic_order_cnt_lsb_minus4(log2_max_pic_order_cnt_lsb_minus4),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.dependent_variable_len(dependent_variable_len),
|
||||
.dependent_variable_decoding_output(dependent_variable_decoding_output)
|
||||
);
|
||||
QP_decoding QP_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.slice_header_state(slice_header_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.pic_init_qp_minus26(pic_init_qp_minus26),
|
||||
.exp_golomb_decoding_output_5to0(exp_golomb_decoding_output[5:0]),
|
||||
.chroma_qp_index_offset(chroma_qp_index_offset),
|
||||
.QPy(QPy),
|
||||
.QPc(QPc)
|
||||
);
|
||||
CodedBlockPattern_decoding CodedBlockPattern_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.slice_data_state(slice_data_state),
|
||||
.slice_type(slice_type),
|
||||
.mb_type(mb_type),
|
||||
.mb_type_general(mb_type_general),
|
||||
.exp_golomb_decoding_output_5to0(exp_golomb_decoding_output[5:0]),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma)
|
||||
);
|
||||
Intra4x4_PredMode_decoding Intra4x4_PredMode_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_pred_state(mb_pred_state),
|
||||
.luma4x4BlkIdx(luma4x4BlkIdx),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.MBTypeGen_mbAddrA(MBTypeGen_mbAddrA),
|
||||
.MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg),
|
||||
.constrained_intra_pred_flag(constrained_intra_pred_flag),
|
||||
.rem_intra4x4_pred_mode(rem_intra4x4_pred_mode),
|
||||
.prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag),
|
||||
.Intra4x4PredMode_mbAddrB_dout(Intra4x4PredMode_mbAddrB_dout),
|
||||
//pic_num can be wired out for debug purpose
|
||||
//.pic_num(pic_num),
|
||||
|
||||
.Intra4x4PredMode_CurrMb(Intra4x4_predmode_CurrMb),
|
||||
.Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n),
|
||||
.Intra4x4PredMode_mbAddrB_wr_n(Intra4x4PredMode_mbAddrB_wr_n),
|
||||
.Intra4x4PredMode_mbAddrB_rd_addr(Intra4x4PredMode_mbAddrB_rd_addr),
|
||||
.Intra4x4PredMode_mbAddrB_wr_addr(Intra4x4PredMode_mbAddrB_wr_addr),
|
||||
.Intra4x4PredMode_mbAddrB_din(Intra4x4PredMode_mbAddrB_din)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`Intra4x4_PredMode_RF_data_width,`Intra4x4_PredMode_RF_data_depth)
|
||||
Intra4x4_PredMode_RF (
|
||||
.clk(gclk_Intra4x4PredMode_mbAddrB_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(Intra4x4PredMode_mbAddrB_cs_n),
|
||||
.wr_n(Intra4x4PredMode_mbAddrB_wr_n),
|
||||
.rd_addr(Intra4x4PredMode_mbAddrB_rd_addr),
|
||||
.wr_addr(Intra4x4PredMode_mbAddrB_wr_addr),
|
||||
.data_in(Intra4x4PredMode_mbAddrB_din),
|
||||
.data_out(Intra4x4PredMode_mbAddrB_dout)
|
||||
);
|
||||
Inter_mv_decoding Inter_mv_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.Is_skip_run_entry(Is_skip_run_entry),
|
||||
.Is_skip_run_end(Is_skip_run_end),
|
||||
.slice_data_state(slice_data_state),
|
||||
.mb_pred_state(mb_pred_state),
|
||||
.sub_mb_pred_state(sub_mb_pred_state),
|
||||
.mvd(mvd),
|
||||
.mb_num(mb_num),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.mb_type_general(mb_type_general),
|
||||
.sub_mb_type(sub_mb_type),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.mbPartIdx(mbPartIdx),
|
||||
.subMbPartIdx(subMbPartIdx),
|
||||
.compIdx(compIdx),
|
||||
.MBTypeGen_mbAddrA(MBTypeGen_mbAddrA),
|
||||
.MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg),
|
||||
.MBTypeGen_mbAddrD(MBTypeGen_mbAddrD),
|
||||
.mvx_mbAddrB_dout(mvx_mbAddrB_dout),
|
||||
.mvy_mbAddrB_dout(mvy_mbAddrB_dout),
|
||||
.mvx_mbAddrC_dout(mvx_mbAddrC_dout),
|
||||
.mvy_mbAddrC_dout(mvy_mbAddrC_dout),
|
||||
.mv_mbAddrB_rd_for_DF(mv_mbAddrB_rd_for_DF),
|
||||
|
||||
.skip_mv_calc(skip_mv_calc),
|
||||
.Is_skipMB_mv_calc(Is_skipMB_mv_calc),
|
||||
.mvx_mbAddrA(mvx_mbAddrA),
|
||||
.mvy_mbAddrA(mvy_mbAddrA),
|
||||
.mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n),
|
||||
.mvx_mbAddrB_wr_n(mvx_mbAddrB_wr_n),
|
||||
.mvx_mbAddrB_rd_addr(mvx_mbAddrB_rd_addr),
|
||||
.mvx_mbAddrB_wr_addr(mvx_mbAddrB_wr_addr),
|
||||
.mvx_mbAddrB_din(mvx_mbAddrB_din),
|
||||
.mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n),
|
||||
.mvy_mbAddrB_wr_n(mvy_mbAddrB_wr_n),
|
||||
.mvy_mbAddrB_rd_addr(mvy_mbAddrB_rd_addr),
|
||||
.mvy_mbAddrB_wr_addr(mvy_mbAddrB_wr_addr),
|
||||
.mvy_mbAddrB_din(mvy_mbAddrB_din),
|
||||
.mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n),
|
||||
.mvx_mbAddrC_wr_n(mvx_mbAddrC_wr_n),
|
||||
.mvx_mbAddrC_rd_addr(mvx_mbAddrC_rd_addr),
|
||||
.mvx_mbAddrC_wr_addr(mvx_mbAddrC_wr_addr),
|
||||
.mvx_mbAddrC_din(mvx_mbAddrC_din),
|
||||
.mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n),
|
||||
.mvy_mbAddrC_wr_n(mvy_mbAddrC_wr_n),
|
||||
.mvy_mbAddrC_rd_addr(mvy_mbAddrC_rd_addr),
|
||||
.mvy_mbAddrC_wr_addr(mvy_mbAddrC_wr_addr),
|
||||
.mvy_mbAddrC_din(mvy_mbAddrC_din),
|
||||
.mv_is16x16(mv_is16x16),
|
||||
.mvx_CurrMb0(mvx_CurrMb0),
|
||||
.mvx_CurrMb1(mvx_CurrMb1),
|
||||
.mvx_CurrMb2(mvx_CurrMb2),
|
||||
.mvx_CurrMb3(mvx_CurrMb3),
|
||||
.mvy_CurrMb0(mvy_CurrMb0),
|
||||
.mvy_CurrMb1(mvy_CurrMb1),
|
||||
.mvy_CurrMb2(mvy_CurrMb2),
|
||||
.mvy_CurrMb3(mvy_CurrMb3)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`mvx_mbAddrB_RF_data_width,`mvx_mbAddrB_RF_data_depth)
|
||||
mvx_mbAddrB_RF (
|
||||
.clk(gclk_mvx_mbAddrB_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(mvx_mbAddrB_cs_n),
|
||||
.wr_n(mvx_mbAddrB_wr_n),
|
||||
.rd_addr(mvx_mbAddrB_rd_addr),
|
||||
.wr_addr(mvx_mbAddrB_wr_addr),
|
||||
.data_in(mvx_mbAddrB_din),
|
||||
.data_out(mvx_mbAddrB_dout)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`mvy_mbAddrB_RF_data_width,`mvy_mbAddrB_RF_data_depth)
|
||||
mvy_mbAddrB_RF (
|
||||
.clk(gclk_mvy_mbAddrB_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(mvy_mbAddrB_cs_n),
|
||||
.wr_n(mvy_mbAddrB_wr_n),
|
||||
.rd_addr(mvy_mbAddrB_rd_addr),
|
||||
.wr_addr(mvy_mbAddrB_wr_addr),
|
||||
.data_in(mvy_mbAddrB_din),
|
||||
.data_out(mvy_mbAddrB_dout)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`mvx_mbAddrC_RF_data_width,`mvx_mbAddrC_RF_data_depth)
|
||||
mvx_mbAddrC_RF (
|
||||
.clk(gclk_mvx_mbAddrC_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(mvx_mbAddrC_cs_n),
|
||||
.wr_n(mvx_mbAddrC_wr_n),
|
||||
.rd_addr(mvx_mbAddrC_rd_addr),
|
||||
.wr_addr(mvx_mbAddrC_wr_addr),
|
||||
.data_in(mvx_mbAddrC_din),
|
||||
.data_out(mvx_mbAddrC_dout)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`mvy_mbAddrC_RF_data_width,`mvy_mbAddrC_RF_data_depth)
|
||||
mvy_mbAddrC_RF (
|
||||
.clk(gclk_mvy_mbAddrC_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(mvy_mbAddrC_cs_n),
|
||||
.wr_n(mvy_mbAddrC_wr_n),
|
||||
.rd_addr(mvy_mbAddrC_rd_addr),
|
||||
.wr_addr(mvy_mbAddrC_wr_addr),
|
||||
.data_in(mvy_mbAddrC_din),
|
||||
.data_out(mvy_mbAddrC_dout)
|
||||
);
|
||||
syntax_decoding syntax_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.pin_disable_DF(pin_disable_DF),
|
||||
.parser_state(parser_state),
|
||||
.nal_unit_state(nal_unit_state),
|
||||
.seq_parameter_set_state(seq_parameter_set_state),
|
||||
.pic_parameter_set_state(pic_parameter_set_state),
|
||||
.slice_header_state(slice_header_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.mb_pred_state(mb_pred_state),
|
||||
.sub_mb_pred_state(sub_mb_pred_state),
|
||||
.exp_golomb_decoding_output(exp_golomb_decoding_output),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.dependent_variable_decoding_output(dependent_variable_decoding_output),
|
||||
.mbPartIdx(mbPartIdx),
|
||||
|
||||
.nal_unit_type(nal_unit_type),
|
||||
.start_code_prefix_found(start_code_prefix_found),
|
||||
.deblocking_filter_control_present_flag(deblocking_filter_control_present_flag),
|
||||
.disable_deblocking_filter_idc(disable_deblocking_filter_idc),
|
||||
.disable_DF(disable_DF),
|
||||
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
|
||||
.slice_beta_offset_div2(slice_beta_offset_div2),
|
||||
.mb_skip_run(mb_skip_run),
|
||||
.NumMbPart(NumMbPart),
|
||||
.NumSubMbPart(NumSubMbPart),
|
||||
.MBTypeGen_mbAddrA(MBTypeGen_mbAddrA),
|
||||
.MBTypeGen_mbAddrD(MBTypeGen_mbAddrD),
|
||||
.MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg),
|
||||
.log2_max_frame_num_minus4(log2_max_frame_num_minus4),
|
||||
.log2_max_pic_order_cnt_lsb_minus4(log2_max_pic_order_cnt_lsb_minus4),
|
||||
.constrained_intra_pred_flag(constrained_intra_pred_flag),
|
||||
.num_ref_idx_active_override_flag(num_ref_idx_active_override_flag),
|
||||
.num_ref_idx_l0_active_minus1(num_ref_idx_l0_active_minus1),
|
||||
.slice_type(slice_type),
|
||||
.mb_type(mb_type),
|
||||
.mb_type_general(mb_type_general),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.intra_chroma_pred_mode(Intra_chroma_predmode),
|
||||
.sub_mb_type(sub_mb_type),
|
||||
.pic_init_qp_minus26(pic_init_qp_minus26),
|
||||
.chroma_qp_index_offset(chroma_qp_index_offset),
|
||||
.rem_intra4x4_pred_mode(rem_intra4x4_pred_mode),
|
||||
.prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag),
|
||||
.mvd(mvd),
|
||||
.mv_below8x8(mv_below8x8)
|
||||
);
|
||||
cavlc_decoder cavlc_decoder(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.gclk_LumaLevel_mbAddrB_RF(gclk_LumaLevel_mbAddrB_RF),
|
||||
.gclk_ChromaLevel_Cb_mbAddrB_RF(gclk_ChromaLevel_Cb_mbAddrB_RF),
|
||||
.gclk_ChromaLevel_Cr_mbAddrB_RF(gclk_ChromaLevel_Cr_mbAddrB_RF),
|
||||
.slice_data_state(slice_data_state),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.i8x8(i8x8),
|
||||
.i4x4(i4x4),
|
||||
.i4x4_CbCr(i4x4_CbCr),
|
||||
.i_level(i_level),
|
||||
.i_run(i_run),
|
||||
.i_TotalCoeff(i_TotalCoeff),
|
||||
.coeffNum(coeffNum),
|
||||
.heading_one_pos(heading_one_pos),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.suffix_length_initialized(suffix_length_initialized),
|
||||
.IsRunLoop(IsRunLoop),
|
||||
|
||||
.Luma_8x8_AllZeroCoeff_mbAddrA(Luma_8x8_AllZeroCoeff_mbAddrA),
|
||||
.LumaLevel_mbAddrA(LumaLevel_mbAddrA),
|
||||
.LumaLevel_CurrMb0(LumaLevel_CurrMb0),
|
||||
.LumaLevel_CurrMb1(LumaLevel_CurrMb1),
|
||||
.LumaLevel_CurrMb2(LumaLevel_CurrMb2),
|
||||
.LumaLevel_CurrMb3(LumaLevel_CurrMb3),
|
||||
.LumaLevel_mbAddrB_dout(LumaLevel_mbAddrB_dout),
|
||||
.LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n),
|
||||
.ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n),
|
||||
.ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
|
||||
.cavlc_consumed_bits_len(cavlc_consumed_bits_len),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.TrailingOnes(TrailingOnes),
|
||||
.maxNumCoeff(maxNumCoeff),
|
||||
.zerosLeft(zerosLeft),
|
||||
.run(run),
|
||||
.coeffLevel_0(coeffLevel_0),
|
||||
.coeffLevel_1(coeffLevel_1),
|
||||
.coeffLevel_2(coeffLevel_2),
|
||||
.coeffLevel_3(coeffLevel_3),
|
||||
.coeffLevel_4(coeffLevel_4),
|
||||
.coeffLevel_5(coeffLevel_5),
|
||||
.coeffLevel_6(coeffLevel_6),
|
||||
.coeffLevel_7(coeffLevel_7),
|
||||
.coeffLevel_8(coeffLevel_8),
|
||||
.coeffLevel_9(coeffLevel_9),
|
||||
.coeffLevel_10(coeffLevel_10),
|
||||
.coeffLevel_11(coeffLevel_11),
|
||||
.coeffLevel_12(coeffLevel_12),
|
||||
.coeffLevel_13(coeffLevel_13),
|
||||
.coeffLevel_14(coeffLevel_14),
|
||||
.coeffLevel_15(coeffLevel_15)
|
||||
);
|
||||
bs_decoding bs_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.gclk_bs_dec(gclk_bs_dec),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.disable_DF(disable_DF),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.mb_type_general(mb_type_general),
|
||||
.slice_data_state(slice_data_state),
|
||||
.residual_state(residual_state),
|
||||
.MBTypeGen_mbAddrA(MBTypeGen_mbAddrA),
|
||||
.MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.curr_DC_IsZero(curr_DC_IsZero),
|
||||
.Is_skipMB_mv_calc(Is_skipMB_mv_calc),
|
||||
.mvx_mbAddrA(mvx_mbAddrA),
|
||||
.mvy_mbAddrA(mvy_mbAddrA),
|
||||
.mvx_mbAddrB_dout(mvx_mbAddrB_dout),
|
||||
.mvy_mbAddrB_dout(mvy_mbAddrB_dout),
|
||||
.mvx_CurrMb0(mvx_CurrMb0),
|
||||
.mvx_CurrMb1(mvx_CurrMb1),
|
||||
.mvx_CurrMb2(mvx_CurrMb2),
|
||||
.mvx_CurrMb3(mvx_CurrMb3),
|
||||
.mvy_CurrMb0(mvy_CurrMb0),
|
||||
.mvy_CurrMb1(mvy_CurrMb1),
|
||||
.mvy_CurrMb2(mvy_CurrMb2),
|
||||
.mvy_CurrMb3(mvy_CurrMb3),
|
||||
|
||||
.bs_dec_counter(bs_dec_counter),
|
||||
.end_of_BS_DEC(end_of_BS_DEC),
|
||||
.mv_mbAddrB_rd_for_DF(mv_mbAddrB_rd_for_DF),
|
||||
.bs_V0(bs_V0),
|
||||
.bs_V1(bs_V1),
|
||||
.bs_V2(bs_V2),
|
||||
.bs_V3(bs_V3),
|
||||
.bs_H0(bs_H0),
|
||||
.bs_H1(bs_H1),
|
||||
.bs_H2(bs_H2),
|
||||
.bs_H3(bs_H3)
|
||||
);
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,639 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : BitStream_parser_FSM_gating.v
|
||||
// Generated : June 26,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// BitStream_parser_FSM,clock gating version
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module BitStream_parser_FSM (clk,reset_n,end_of_one_blk4x4_sum,end_of_MB_DEC,
|
||||
gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps,gclk_slice_header,
|
||||
gclk_slice_data,gclk_residual,gclk_cavlc,
|
||||
trigger_CAVLC,BitStream_buffer_valid_n,nal_unit_type,
|
||||
slice_type,num_ref_idx_active_override_flag,
|
||||
deblocking_filter_control_present_flag,disable_deblocking_filter_idc,
|
||||
mb_skip_run,mb_type_general,prev_intra4x4_pred_mode_flag,CodedBlockPatternLuma,
|
||||
CodedBlockPatternChroma,pc_2to0,NumSubMbPart,NumMbPart,
|
||||
TotalCoeff,TrailingOnes,maxNumCoeff,zerosLeft,run,
|
||||
|
||||
parser_state,nal_unit_state,slice_layer_wo_partitioning_state,slice_header_state,slice_header_s6,
|
||||
ref_pic_list_reordering_state,dec_ref_pic_marking_state,slice_data_state,sub_mb_pred_state,
|
||||
mb_pred_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state,
|
||||
heading_one_en,pic_num,mb_num,mb_num_h,mb_num_v,
|
||||
NextMB_IsSkip,LowerMB_IsSkip,Is_skip_run_entry,Is_skip_run_end,
|
||||
luma4x4BlkIdx,mbPartIdx,subMbPartIdx,compIdx,i8x8,i4x4,i4x4_CbCr,
|
||||
coeffNum,i_level,i_run,i_TotalCoeff,
|
||||
suffix_length_initialized,IsRunLoop);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input end_of_one_blk4x4_sum;
|
||||
input end_of_MB_DEC;
|
||||
input gclk_parser;
|
||||
input gclk_nal;
|
||||
input gclk_slice;
|
||||
input gclk_sps;
|
||||
input gclk_pps;
|
||||
input gclk_slice_header;
|
||||
input gclk_slice_data;
|
||||
input gclk_residual;
|
||||
input gclk_cavlc;
|
||||
input trigger_CAVLC;
|
||||
input BitStream_buffer_valid_n;
|
||||
input [4:0] nal_unit_type;
|
||||
input [2:0] slice_type;
|
||||
input num_ref_idx_active_override_flag;
|
||||
input deblocking_filter_control_present_flag;
|
||||
input [1:0] disable_deblocking_filter_idc;
|
||||
input [6:0] mb_skip_run;
|
||||
input [3:0] mb_type_general;
|
||||
input prev_intra4x4_pred_mode_flag;
|
||||
input [3:0] CodedBlockPatternLuma;
|
||||
input [1:0] CodedBlockPatternChroma;
|
||||
input [2:0] pc_2to0;
|
||||
input [2:0] NumMbPart;
|
||||
input [2:0] NumSubMbPart;
|
||||
input [4:0] TotalCoeff;
|
||||
input [1:0] TrailingOnes;
|
||||
input [4:0] maxNumCoeff;
|
||||
input [3:0] zerosLeft;
|
||||
input [3:0] run;
|
||||
|
||||
output [1:0] parser_state;
|
||||
output [2:0] nal_unit_state;
|
||||
output [1:0] slice_layer_wo_partitioning_state;
|
||||
output [3:0] slice_header_state;
|
||||
output slice_header_s6;
|
||||
output [2:0] ref_pic_list_reordering_state;
|
||||
output [1:0] dec_ref_pic_marking_state;
|
||||
output [3:0] slice_data_state;
|
||||
output [1:0] sub_mb_pred_state;
|
||||
output [2:0] mb_pred_state;
|
||||
output [3:0] seq_parameter_set_state;
|
||||
output [3:0] pic_parameter_set_state;
|
||||
output [3:0] residual_state;
|
||||
output [3:0] cavlc_decoder_state;
|
||||
output heading_one_en;
|
||||
output [5:0] pic_num;
|
||||
output [6:0] mb_num;
|
||||
output [3:0] mb_num_h;
|
||||
output [3:0] mb_num_v;
|
||||
output NextMB_IsSkip;
|
||||
output LowerMB_IsSkip;
|
||||
output Is_skip_run_entry;
|
||||
output Is_skip_run_end;
|
||||
output [3:0] luma4x4BlkIdx;
|
||||
output [1:0] mbPartIdx;
|
||||
output [1:0] subMbPartIdx;
|
||||
output compIdx;
|
||||
output [1:0] i8x8,i4x4;
|
||||
output [1:0] i4x4_CbCr;
|
||||
output [3:0] coeffNum;
|
||||
output [3:0] i_level;
|
||||
output [3:0] i_run;
|
||||
output [3:0] i_TotalCoeff;
|
||||
output suffix_length_initialized;
|
||||
output IsRunLoop;
|
||||
|
||||
reg [1:0] parser_state;
|
||||
reg [2:0] nal_unit_state;
|
||||
reg [1:0] slice_layer_wo_partitioning_state;
|
||||
reg [3:0] seq_parameter_set_state;
|
||||
reg [3:0] pic_parameter_set_state;
|
||||
reg [3:0] slice_header_state;
|
||||
reg [2:0] ref_pic_list_reordering_state;
|
||||
reg [1:0] dec_ref_pic_marking_state;
|
||||
reg [3:0] slice_data_state;
|
||||
reg [2:0] mb_pred_state;
|
||||
reg [1:0] sub_mb_pred_state;
|
||||
reg [3:0] residual_state;
|
||||
reg [3:0] cavlc_decoder_state;
|
||||
|
||||
wire heading_one_en;
|
||||
reg [6:0] mb_num;
|
||||
reg [3:0] mb_num_h;
|
||||
reg [3:0] mb_num_v;
|
||||
reg [1:0] mbPartIdx;
|
||||
reg [1:0] subMbPartIdx;
|
||||
reg compIdx;
|
||||
reg [1:0] i8x8,i4x4;
|
||||
reg [1:0] i4x4_CbCr;
|
||||
reg [3:0] coeffNum;
|
||||
reg [3:0] coeffNum_reg;
|
||||
reg [3:0] i_level,i_run,i_TotalCoeff;
|
||||
reg [6:0] count_mb_skip_run;//number of MBs to be skipped
|
||||
reg [7:0] count_pcm_byte;
|
||||
reg [3:0] luma4x4BlkIdx;
|
||||
reg [5:0] pic_num;
|
||||
reg suffix_length_initialized;
|
||||
reg IsRunLoop;
|
||||
|
||||
/*
|
||||
// synopsys translate_off
|
||||
integer tracefile;
|
||||
initial
|
||||
begin
|
||||
tracefile = $fopen("trace.txt");
|
||||
end
|
||||
// synopsys translate_on
|
||||
*/
|
||||
|
||||
//--------------
|
||||
//parser_state
|
||||
//--------------
|
||||
always @ (posedge gclk_parser or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
parser_state <= `rst_parser;
|
||||
else
|
||||
case (parser_state)
|
||||
`rst_parser :parser_state <= (BitStream_buffer_valid_n == 1'b0)? `start_code_prefix:`rst_parser;
|
||||
`start_code_prefix:parser_state <= `nal_unit;
|
||||
`nal_unit :parser_state <= `rst_parser;
|
||||
endcase
|
||||
//---------------
|
||||
//nal_unit_state
|
||||
//---------------
|
||||
always @ (posedge gclk_nal or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
nal_unit_state <= `rst_nal_unit;
|
||||
else
|
||||
case (nal_unit_state)
|
||||
`rst_nal_unit:nal_unit_state <= `forbidden_zero_bit_2_nal_unit_type;
|
||||
`forbidden_zero_bit_2_nal_unit_type:
|
||||
case (nal_unit_type)
|
||||
5'b00001:nal_unit_state <= `slice_layer_non_IDR_rbsp;
|
||||
5'b00101:nal_unit_state <= `slice_layer_IDR_rbsp;
|
||||
5'b00111:nal_unit_state <= `seq_parameter_set_rbsp;
|
||||
5'b01000:nal_unit_state <= `pic_parameter_set_rbsp;
|
||||
endcase
|
||||
`slice_layer_non_IDR_rbsp,`slice_layer_IDR_rbsp:nal_unit_state <= `rbsp_trailing_one_bit;
|
||||
`seq_parameter_set_rbsp :nal_unit_state <= `rbsp_trailing_one_bit;
|
||||
`pic_parameter_set_rbsp :nal_unit_state <= `rbsp_trailing_one_bit;
|
||||
`rbsp_trailing_one_bit :nal_unit_state <= (pc_2to0 == 3'b000)? `rst_nal_unit:`rbsp_trailing_zero_bits;
|
||||
`rbsp_trailing_zero_bits:nal_unit_state <= `rst_nal_unit;
|
||||
endcase
|
||||
//----------------------------------
|
||||
//slice_layer_wo_partitioning_state
|
||||
//----------------------------------
|
||||
always @ (posedge gclk_slice or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
slice_layer_wo_partitioning_state <= `rst_slice_layer_wo_partitioning;
|
||||
else
|
||||
case (slice_layer_wo_partitioning_state)
|
||||
`rst_slice_layer_wo_partitioning :slice_layer_wo_partitioning_state <= `slice_header;
|
||||
`slice_header :slice_layer_wo_partitioning_state <= `slice_data;
|
||||
`slice_data :slice_layer_wo_partitioning_state <= `rst_slice_layer_wo_partitioning;
|
||||
endcase
|
||||
//------------------------
|
||||
//seq_parameter_set_state
|
||||
//------------------------
|
||||
always @ (posedge gclk_sps or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
seq_parameter_set_state <= `rst_seq_parameter_set;
|
||||
else
|
||||
case (seq_parameter_set_state)
|
||||
`rst_seq_parameter_set :seq_parameter_set_state <= `fixed_header;
|
||||
`fixed_header :seq_parameter_set_state <= `level_idc_s;
|
||||
`level_idc_s :seq_parameter_set_state <= `seq_parameter_set_id_sps_s;
|
||||
`seq_parameter_set_id_sps_s :seq_parameter_set_state <= `log2_max_frame_num_minus4_s;
|
||||
`log2_max_frame_num_minus4_s :seq_parameter_set_state <= `pic_order_cnt_type_s;
|
||||
`pic_order_cnt_type_s :seq_parameter_set_state <= `log2_max_pic_order_cnt_lsb_minus4_s;
|
||||
`log2_max_pic_order_cnt_lsb_minus4_s :seq_parameter_set_state <= `num_ref_frames_s;
|
||||
`num_ref_frames_s :seq_parameter_set_state <= `gaps_in_frame_num_value_allowed_flag_s;
|
||||
`gaps_in_frame_num_value_allowed_flag_s :seq_parameter_set_state <= `pic_width_in_mbs_minus1_s;
|
||||
`pic_width_in_mbs_minus1_s :seq_parameter_set_state <= `pic_height_in_map_units_minus1_s;
|
||||
`pic_height_in_map_units_minus1_s :seq_parameter_set_state <= `frame_mbs_only_flag_2_frame_cropping_flag;
|
||||
`frame_mbs_only_flag_2_frame_cropping_flag:seq_parameter_set_state <= `vui_parameter_present_flag_s;
|
||||
`vui_parameter_present_flag_s :seq_parameter_set_state <= `rst_seq_parameter_set;
|
||||
endcase
|
||||
//------------------------
|
||||
//pic_parameter_set_state
|
||||
//------------------------
|
||||
always @ (posedge gclk_pps or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
pic_parameter_set_state <= `rst_pic_parameter_set;
|
||||
else
|
||||
case (pic_parameter_set_state)
|
||||
`rst_pic_parameter_set :pic_parameter_set_state <= `pic_parameter_set_id_pps_s;
|
||||
`pic_parameter_set_id_pps_s :pic_parameter_set_state <= `seq_parameter_set_id_pps_s;
|
||||
`seq_parameter_set_id_pps_s :pic_parameter_set_state <= `entropy_coding_mode_flag_2_pic_order_present_flag;
|
||||
`entropy_coding_mode_flag_2_pic_order_present_flag :pic_parameter_set_state <= `num_slice_groups_minus1_s;
|
||||
`num_slice_groups_minus1_s :pic_parameter_set_state <= `num_ref_idx_l0_active_minus1_pps_s;
|
||||
`num_ref_idx_l0_active_minus1_pps_s :pic_parameter_set_state <= `num_ref_idx_l1_active_minus1_pps_s;
|
||||
`num_ref_idx_l1_active_minus1_pps_s :pic_parameter_set_state <= `weighted_pred_flag_2_weighted_bipred_idc;
|
||||
`weighted_pred_flag_2_weighted_bipred_idc :pic_parameter_set_state <= `pic_init_qp_minus26_s;
|
||||
`pic_init_qp_minus26_s :pic_parameter_set_state <= `pic_init_qs_minus26_s;
|
||||
`pic_init_qs_minus26_s :pic_parameter_set_state <= `chroma_qp_index_offset_s;
|
||||
`chroma_qp_index_offset_s :pic_parameter_set_state <= `deblocking_filter_control_2_redundant_pic_cnt_present_flag;
|
||||
`deblocking_filter_control_2_redundant_pic_cnt_present_flag:pic_parameter_set_state <= `rst_pic_parameter_set;
|
||||
endcase
|
||||
//-------------------
|
||||
//slice_header_state
|
||||
//-------------------
|
||||
always @ (posedge gclk_slice_header or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
slice_header_state <= `rst_slice_header;
|
||||
ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering;
|
||||
dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking;
|
||||
end
|
||||
else
|
||||
case (slice_header_state)
|
||||
`rst_slice_header :slice_header_state <= `first_mb_in_slice_s;
|
||||
`first_mb_in_slice_s :slice_header_state <= `slice_type_s;
|
||||
`slice_type_s :slice_header_state <= `pic_parameter_set_id_slice_header_s;
|
||||
`pic_parameter_set_id_slice_header_s:slice_header_state <= `frame_num_s;
|
||||
`frame_num_s:
|
||||
if (nal_unit_type == 5'b00101) slice_header_state <= `idr_pic_id_s;
|
||||
else slice_header_state <= `pic_order_cnt_lsb_s;
|
||||
`idr_pic_id_s :slice_header_state <= `pic_order_cnt_lsb_s;
|
||||
`pic_order_cnt_lsb_s:
|
||||
if (slice_type == 3'b101) slice_header_state <= `num_ref_idx_active_override_flag_s;
|
||||
else slice_header_state <= `dec_ref_pic_marking;
|
||||
`num_ref_idx_active_override_flag_s:
|
||||
if (num_ref_idx_active_override_flag == 1'b1) slice_header_state <= `num_ref_idx_l0_active_minus1_slice_header_s;
|
||||
else slice_header_state <= `ref_pic_list_reordering;
|
||||
`num_ref_idx_l0_active_minus1_slice_header_s :slice_header_state <= `ref_pic_list_reordering;
|
||||
`ref_pic_list_reordering:
|
||||
case (ref_pic_list_reordering_state)
|
||||
`rst_ref_pic_list_reordering:
|
||||
if (slice_type == 3'b101)
|
||||
ref_pic_list_reordering_state <= `ref_pic_list_reordering_flag_l0_s;
|
||||
else
|
||||
begin
|
||||
ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering;
|
||||
slice_header_state <= `dec_ref_pic_marking;
|
||||
end
|
||||
`ref_pic_list_reordering_flag_l0_s:
|
||||
begin
|
||||
ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering;
|
||||
slice_header_state <= `dec_ref_pic_marking;
|
||||
end
|
||||
endcase
|
||||
`dec_ref_pic_marking:
|
||||
case (dec_ref_pic_marking_state)
|
||||
`rst_dec_ref_pic_marking:
|
||||
dec_ref_pic_marking_state <= (nal_unit_type == 3'b101)? `no_output_of_prior_pics_flag_2_long_term_reference_flag:`adaptive_ref_pic_marking_mode_flag_s;
|
||||
`no_output_of_prior_pics_flag_2_long_term_reference_flag:
|
||||
begin
|
||||
dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking;
|
||||
slice_header_state <= `slice_qp_delta_s;
|
||||
end
|
||||
`adaptive_ref_pic_marking_mode_flag_s:
|
||||
begin
|
||||
dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking;
|
||||
slice_header_state <= `slice_qp_delta_s;
|
||||
end
|
||||
endcase
|
||||
`slice_qp_delta_s:
|
||||
slice_header_state <= (deblocking_filter_control_present_flag == 1'b1)? `disable_deblocking_filter_idc_s:`rst_slice_header;
|
||||
`disable_deblocking_filter_idc_s:
|
||||
slice_header_state <= (disable_deblocking_filter_idc != 2'b01)? `slice_alpha_c0_offset_div2_s:`rst_slice_header;
|
||||
`slice_alpha_c0_offset_div2_s:slice_header_state <= `slice_beta_offset_div2_s;
|
||||
`slice_beta_offset_div2_s :slice_header_state <= `rst_slice_header;
|
||||
endcase
|
||||
|
||||
assign slice_header_s6 = (slice_header_state == `frame_num_s)? 1'b1:1'b0;
|
||||
//------------------
|
||||
//slice_data_state
|
||||
//------------------
|
||||
reg Is_skip_run_entry; //for trigger inter pred.Originally it's a wire type which will trigger inter_pred signal too early
|
||||
//than expected:cause inter_pred rise up before mv_below8x8 is set to 4'b0 for P_skip.Thus the
|
||||
//preload_counter after inter_pred will sample wrong mv_below8x8/mv_below8x8_curr.
|
||||
//Then it is changed to reg type to appear one cycle later @ May 15,2006
|
||||
wire Is_skip_run_end; //for stop triggering inter pred
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
Is_skip_run_entry <= 1'b0;
|
||||
else if (slice_data_state == `mb_skip_run_s && mb_skip_run != 0)
|
||||
Is_skip_run_entry <= 1'b1;
|
||||
else
|
||||
Is_skip_run_entry <= 1'b0;
|
||||
|
||||
assign Is_skip_run_end = (slice_data_state == `skip_run_duration && end_of_MB_DEC && (mb_num == 98 || count_mb_skip_run == (mb_skip_run - 1)))? 1'b1:1'b0;
|
||||
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
slice_data_state <= `rst_slice_data;
|
||||
mb_pred_state <= `rst_mb_pred;
|
||||
sub_mb_pred_state <= `rst_sub_mb_pred;
|
||||
end
|
||||
else
|
||||
case (slice_data_state)
|
||||
`rst_slice_data :slice_data_state <= (slice_type != 3'b111)? `mb_skip_run_s:`mb_type_s;
|
||||
`mb_skip_run_s :slice_data_state <= (mb_skip_run == 0)? `mb_type_s:`skip_run_duration;
|
||||
`skip_run_duration:slice_data_state <= (mb_num == 98)? `rst_slice_data:(count_mb_skip_run < (mb_skip_run - 1))? `skip_run_duration:`mb_type_s;
|
||||
`mb_type_s :slice_data_state <= (mb_type_general == `MB_P_8x8 || mb_type_general == `MB_P_8x8ref0)? `sub_mb_pred:`mb_pred;
|
||||
`sub_mb_pred:
|
||||
case (sub_mb_pred_state)
|
||||
`rst_sub_mb_pred:sub_mb_pred_state <= `sub_mb_type_s;
|
||||
`sub_mb_type_s :sub_mb_pred_state <= (mbPartIdx == 2'b11)? `sub_mvd_l0_s:`sub_mb_type_s;
|
||||
`sub_mvd_l0_s:
|
||||
if (mbPartIdx == 2'b11 && {1'b0,subMbPartIdx} == (NumSubMbPart - 1) && compIdx == 1'b1)
|
||||
begin
|
||||
sub_mb_pred_state <= `rst_sub_mb_pred;
|
||||
slice_data_state <= `coded_block_pattern_s;
|
||||
end
|
||||
endcase
|
||||
`mb_pred:
|
||||
case (mb_pred_state)
|
||||
`rst_mb_pred:
|
||||
if (mb_type_general[3] == 1'b1) //Intra
|
||||
mb_pred_state <= (mb_type_general == `MB_Intra4x4)? `prev_intra4x4_pred_mode_flag_s:`intra_chroma_pred_mode_s;
|
||||
else
|
||||
mb_pred_state <= `mvd_l0_s;
|
||||
`prev_intra4x4_pred_mode_flag_s:
|
||||
mb_pred_state <= (prev_intra4x4_pred_mode_flag == 1'b0)? `rem_intra4x4_pred_mode_s:
|
||||
(luma4x4BlkIdx == 4'b1111)? `intra_chroma_pred_mode_s:`prev_intra4x4_pred_mode_flag_s;
|
||||
`rem_intra4x4_pred_mode_s:
|
||||
mb_pred_state <= (luma4x4BlkIdx == 4'b1111)? `intra_chroma_pred_mode_s:`prev_intra4x4_pred_mode_flag_s;
|
||||
`intra_chroma_pred_mode_s:
|
||||
begin
|
||||
mb_pred_state <= `rst_mb_pred;
|
||||
slice_data_state <= (mb_type_general[3:2] != 2'b10)? `coded_block_pattern_s:`mb_qp_delta_s;
|
||||
end
|
||||
`mvd_l0_s:
|
||||
if ({1'b0,mbPartIdx} == (NumMbPart - 1) && compIdx == 1'b1)
|
||||
begin
|
||||
mb_pred_state <= `rst_mb_pred;
|
||||
slice_data_state <= `coded_block_pattern_s;
|
||||
end
|
||||
endcase
|
||||
`coded_block_pattern_s:slice_data_state <= (CodedBlockPatternLuma == 0 && CodedBlockPatternChroma == 0)? `residual:`mb_qp_delta_s;
|
||||
`mb_qp_delta_s:
|
||||
slice_data_state <= (CodedBlockPatternLuma == 0 && CodedBlockPatternChroma == 0 && mb_type_general[3:2] != 2'b10)? `mb_num_update:`residual;
|
||||
`residual:slice_data_state <= `mb_num_update;
|
||||
`mb_num_update:slice_data_state <= `rst_slice_data;
|
||||
endcase
|
||||
//---------------
|
||||
//residual_state
|
||||
//---------------
|
||||
always @ (posedge gclk_residual or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
residual_state <= `rst_residual;
|
||||
else
|
||||
case (residual_state)
|
||||
`rst_residual:
|
||||
if (mb_type_general[3] == 1'b1 && mb_type_general != `MB_Intra4x4)//Intra16x16
|
||||
residual_state <= `Intra16x16DCLevel_s;
|
||||
else
|
||||
residual_state <= (CodedBlockPatternLuma == 0)? `LumaLevel_0_s:`LumaLevel_s;
|
||||
`Intra16x16DCLevel_s:residual_state <= (CodedBlockPatternLuma == 0)? `Intra16x16ACLevel_0_s:`Intra16x16ACLevel_s;
|
||||
`Intra16x16ACLevel_s,`Intra16x16ACLevel_0_s,`LumaLevel_s,`LumaLevel_0_s:
|
||||
residual_state <= (CodedBlockPatternChroma == 0)? `ChromaACLevel_0_s:`ChromaDCLevel_Cb_s;
|
||||
`ChromaDCLevel_Cb_s:residual_state <= `ChromaDCLevel_Cr_s;
|
||||
`ChromaDCLevel_Cr_s:residual_state <= (CodedBlockPatternChroma == 2'b01)? `ChromaACLevel_0_s:`ChromaACLevel_Cb_s;
|
||||
`ChromaACLevel_Cb_s:residual_state <= `ChromaACLevel_Cr_s;
|
||||
`ChromaACLevel_Cr_s:residual_state <= `rst_residual;
|
||||
`ChromaACLevel_0_s :residual_state <= `rst_residual;
|
||||
endcase
|
||||
//--------------------
|
||||
//cavlc_decoder_state
|
||||
//--------------------
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
cavlc_decoder_state <= `rst_cavlc_decoder;
|
||||
else
|
||||
case (cavlc_decoder_state)
|
||||
`rst_cavlc_decoder :cavlc_decoder_state <= `nAnB_decoding_s;
|
||||
`nAnB_decoding_s :cavlc_decoder_state <= `nC_decoding_s;
|
||||
`nC_decoding_s :cavlc_decoder_state <= `NumCoeffTrailingOnes_LUT;
|
||||
`NumCoeffTrailingOnes_LUT://add trigger_CAVLC to trap a special case:after all-zero CrDC2x2 CAVLC decoding.
|
||||
//Without adding trigger_CAVLC here,the gclk_cavlc can not catch trigger_CAVLC
|
||||
//because it rises up too early (rise up at NumCoeffTrailingOnes_LUT instead of rst_cavlc_decoder)
|
||||
cavlc_decoder_state <= (TotalCoeff == 0)? ((trigger_CAVLC)? `nAnB_decoding_s:`rst_cavlc_decoder):(TrailingOnes == 0)? `LevelPrefix:`TrailingOnesSignFlag;
|
||||
`TrailingOnesSignFlag:cavlc_decoder_state <= (TotalCoeff == {3'b0,TrailingOnes})?`total_zeros_LUT:`LevelPrefix;
|
||||
`LevelPrefix :cavlc_decoder_state <= `LevelSuffix;
|
||||
`LevelSuffix :cavlc_decoder_state <= ({1'b0,i_level} == TotalCoeff-1)? ((TotalCoeff == maxNumCoeff)?`LevelRunCombination:`total_zeros_LUT):`LevelPrefix;
|
||||
`total_zeros_LUT :cavlc_decoder_state <= (TotalCoeff == 1)? `RunOfZeros:`run_before_LUT;
|
||||
`run_before_LUT :cavlc_decoder_state <= `RunOfZeros;
|
||||
`RunOfZeros :cavlc_decoder_state <= ({1'b0,i_run} == (TotalCoeff - 1) || {1'b0,i_run} == (TotalCoeff - 2) || zerosLeft == 0)? `LevelRunCombination:`run_before_LUT;
|
||||
`LevelRunCombination :cavlc_decoder_state <= (i_TotalCoeff == 0)? `rst_cavlc_decoder:`LevelRunCombination;
|
||||
endcase
|
||||
assign heading_one_en = (
|
||||
seq_parameter_set_state == `seq_parameter_set_id_sps_s ||
|
||||
seq_parameter_set_state == `log2_max_frame_num_minus4_s ||
|
||||
seq_parameter_set_state == `pic_order_cnt_type_s ||
|
||||
seq_parameter_set_state == `log2_max_pic_order_cnt_lsb_minus4_s ||
|
||||
seq_parameter_set_state == `num_ref_frames_s ||
|
||||
seq_parameter_set_state == `pic_width_in_mbs_minus1_s ||
|
||||
seq_parameter_set_state == `pic_height_in_map_units_minus1_s ||
|
||||
pic_parameter_set_state == `pic_parameter_set_id_pps_s ||
|
||||
pic_parameter_set_state == `seq_parameter_set_id_pps_s ||
|
||||
pic_parameter_set_state == `num_slice_groups_minus1_s ||
|
||||
pic_parameter_set_state == `num_ref_idx_l0_active_minus1_pps_s ||
|
||||
pic_parameter_set_state == `num_ref_idx_l1_active_minus1_pps_s ||
|
||||
pic_parameter_set_state == `pic_init_qp_minus26_s ||
|
||||
pic_parameter_set_state == `pic_init_qs_minus26_s ||
|
||||
pic_parameter_set_state == `chroma_qp_index_offset_s ||
|
||||
slice_header_state == `first_mb_in_slice_s ||
|
||||
slice_header_state == `slice_type_s ||
|
||||
slice_header_state == `pic_parameter_set_id_slice_header_s ||
|
||||
slice_header_state == `idr_pic_id_s ||
|
||||
slice_header_state == `num_ref_idx_l0_active_minus1_slice_header_s ||
|
||||
slice_header_state == `slice_qp_delta_s ||
|
||||
slice_header_state == `disable_deblocking_filter_idc_s ||
|
||||
slice_header_state == `slice_alpha_c0_offset_div2_s ||
|
||||
slice_header_state == `slice_beta_offset_div2_s ||
|
||||
slice_data_state == `mb_skip_run_s ||
|
||||
slice_data_state == `mb_type_s ||
|
||||
slice_data_state == `coded_block_pattern_s ||
|
||||
slice_data_state == `mb_qp_delta_s ||
|
||||
mb_pred_state == `intra_chroma_pred_mode_s ||
|
||||
mb_pred_state == `mvd_l0_s ||
|
||||
sub_mb_pred_state == `sub_mb_type_s ||
|
||||
sub_mb_pred_state == `sub_mvd_l0_s ||
|
||||
cavlc_decoder_state == `NumCoeffTrailingOnes_LUT ||
|
||||
cavlc_decoder_state == `LevelPrefix ||
|
||||
cavlc_decoder_state == `total_zeros_LUT)? 1'b0:1'b1;
|
||||
|
||||
//count_mb_skip_run
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
count_mb_skip_run <= 1'b0;
|
||||
else if (slice_data_state == `skip_run_duration)
|
||||
count_mb_skip_run <= (mb_num == 98)? 0:(count_mb_skip_run < (mb_skip_run - 1))? (count_mb_skip_run + 1):0;
|
||||
|
||||
assign NextMB_IsSkip = (slice_data_state == `skip_run_duration && (count_mb_skip_run < (mb_skip_run - 1)))? 1'b1:1'b0;
|
||||
|
||||
reg LowerMB_IsSkip;
|
||||
always @ (slice_data_state or mb_skip_run or count_mb_skip_run)
|
||||
if (slice_data_state == `skip_run_duration)
|
||||
begin
|
||||
if (mb_skip_run < 13)
|
||||
LowerMB_IsSkip <= 1'b0;
|
||||
else
|
||||
LowerMB_IsSkip <= (count_mb_skip_run < (mb_skip_run - 12))? 1'b1:1'b0;
|
||||
end
|
||||
else
|
||||
LowerMB_IsSkip <= 1'b0;
|
||||
|
||||
//mb_num_h
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
mb_num_h <= 0;
|
||||
else if (slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update)
|
||||
mb_num_h <= (mb_num_h == 10) ? 0:(mb_num_h + 1);
|
||||
|
||||
//mb_num_v
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
mb_num_v <= 0;
|
||||
else if ((slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) && mb_num_h == 10)
|
||||
mb_num_v <= (mb_num_v == 8) ? 0:(mb_num_v + 1);
|
||||
|
||||
//mb_num
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
mb_num <= 0;
|
||||
else if (slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update)
|
||||
mb_num <= (mb_num == 98)? 0:(mb_num + 1);
|
||||
|
||||
//pic_num
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
pic_num <= 0;
|
||||
else if ((slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) && mb_num == 98)
|
||||
pic_num <= pic_num + 1;
|
||||
|
||||
//luma4x4BlkIdx
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
luma4x4BlkIdx <= 0;
|
||||
else
|
||||
case (mb_pred_state)
|
||||
`prev_intra4x4_pred_mode_flag_s:
|
||||
if (prev_intra4x4_pred_mode_flag == 1'b1)
|
||||
luma4x4BlkIdx <= (luma4x4BlkIdx == 4'b1111)? 0:(luma4x4BlkIdx + 1);
|
||||
`rem_intra4x4_pred_mode_s:luma4x4BlkIdx <= (luma4x4BlkIdx == 4'b1111)? 0:(luma4x4BlkIdx + 1);
|
||||
endcase
|
||||
|
||||
//mbPartIdx
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
mbPartIdx <= 0;
|
||||
else if (mb_pred_state == `mvd_l0_s && compIdx == 1'b1)
|
||||
mbPartIdx <= ({1'b0,mbPartIdx} < (NumMbPart-1))? (mbPartIdx + 1):0;
|
||||
else if (sub_mb_pred_state == `sub_mb_type_s)
|
||||
mbPartIdx <= (mbPartIdx == 2'b11)? 0:(mbPartIdx + 1);
|
||||
else if (sub_mb_pred_state == `sub_mvd_l0_s && {1'b0,subMbPartIdx} == NumSubMbPart - 1 && compIdx == 1'b1)
|
||||
mbPartIdx <= (mbPartIdx == 2'b11)? 0:(mbPartIdx + 1);
|
||||
|
||||
//subMbPartIdx
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
subMbPartIdx <= 0;
|
||||
else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1'b1)
|
||||
subMbPartIdx <= ({1'b0,subMbPartIdx} < NumSubMbPart-1)? (subMbPartIdx + 1):0;
|
||||
|
||||
//compIdx
|
||||
always @ (posedge gclk_slice_data or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
compIdx <= 0;
|
||||
else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s)
|
||||
compIdx <= ~ compIdx;
|
||||
|
||||
//i8x8
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
i8x8 <= 0;
|
||||
else if (slice_data_state == `residual && residual_state == `rst_residual && mb_type_general != `MB_Intra16x16_CBPChroma0 && mb_type_general != `MB_Intra16x16_CBPChroma1 && mb_type_general != `MB_Intra16x16_CBPChroma2)
|
||||
i8x8 <= 0;
|
||||
else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_blk4x4_sum == 1 && i4x4 == 2'b11)
|
||||
i8x8 <= (i8x8 == 2'b11)? 0:(i8x8 + 1);
|
||||
|
||||
//i4x4
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
i4x4 <= 0;
|
||||
else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_blk4x4_sum == 1)
|
||||
i4x4 <= (i4x4 == 2'b11)? 0:(i4x4 + 1);
|
||||
|
||||
//i4x4_CbCr
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
i4x4_CbCr <= 0;
|
||||
else if ((residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && end_of_one_blk4x4_sum == 1'b1)
|
||||
i4x4_CbCr <= (i4x4_CbCr == 2'b11)? 0:(i4x4_CbCr + 1);
|
||||
|
||||
//suffix_length_initialized
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
suffix_length_initialized <= 1'b0;
|
||||
else if (cavlc_decoder_state == `rst_cavlc_decoder)
|
||||
suffix_length_initialized <= 1'b0;
|
||||
else if (cavlc_decoder_state == `LevelPrefix)
|
||||
suffix_length_initialized <= 1'b1;
|
||||
|
||||
//i_level
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
i_level <= 0;
|
||||
else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT)
|
||||
i_level <= 0;
|
||||
else if (cavlc_decoder_state == `TrailingOnesSignFlag)
|
||||
i_level <= i_level + TrailingOnes;
|
||||
else if (cavlc_decoder_state == `LevelSuffix && {1'b0,i_level} != (TotalCoeff-1))
|
||||
i_level <= i_level + 1;
|
||||
|
||||
//i_run
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
i_run <= 0;
|
||||
else if (cavlc_decoder_state == `total_zeros_LUT)
|
||||
i_run <= 0;
|
||||
else if (cavlc_decoder_state == `RunOfZeros && {1'b0,i_run} != (TotalCoeff - 1) && {1'b0,i_run} != (TotalCoeff - 2) && zerosLeft != 0)
|
||||
i_run <= i_run + 1;
|
||||
|
||||
//i_TotalCoeff
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
i_TotalCoeff <= 0;
|
||||
//enter from LevelSuffix
|
||||
else if (cavlc_decoder_state == `LevelSuffix && {1'b0,i_level} == (TotalCoeff-1) && TotalCoeff == maxNumCoeff)
|
||||
i_TotalCoeff <= TotalCoeff - 1;
|
||||
//enter from RunOfZeros
|
||||
else if (cavlc_decoder_state == `RunOfZeros && ({1'b0,i_run} == (TotalCoeff - 1) || {1'b0,i_run} == (TotalCoeff - 2) || zerosLeft == 0))
|
||||
i_TotalCoeff <= TotalCoeff - 1;
|
||||
//Inside LevelRunCombination loop
|
||||
else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff != 0)
|
||||
i_TotalCoeff <= i_TotalCoeff-1;
|
||||
|
||||
//coeffNum
|
||||
always @ (cavlc_decoder_state or run or coeffNum_reg)
|
||||
if (cavlc_decoder_state == `nAnB_decoding_s)
|
||||
coeffNum <= 4'b1111;
|
||||
else if (cavlc_decoder_state == `LevelRunCombination)
|
||||
coeffNum <= coeffNum_reg + run + 1;
|
||||
else
|
||||
coeffNum <= coeffNum_reg;
|
||||
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
coeffNum_reg <= 0;
|
||||
else
|
||||
coeffNum_reg <= coeffNum;
|
||||
|
||||
//IsRunLoop
|
||||
always @ (posedge gclk_cavlc or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
IsRunLoop <= 0;
|
||||
else if (cavlc_decoder_state == `RunOfZeros)
|
||||
IsRunLoop <= ({1'b0,i_run} == TotalCoeff - 1 || {1'b0,i_run} == TotalCoeff - 2 || zerosLeft == 0)? 1'b0:1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : CodedBlockPattern_decoding.v
|
||||
// Generated : June 5,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding CodedBlockPatternLuma & CodedBlockPatternChroma (Table9-4 Page156 of H.264/AVC standard 2003)
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module CodedBlockPattern_decoding (clk,reset_n,slice_data_state,slice_type,mb_type,mb_type_general,
|
||||
exp_golomb_decoding_output_5to0,CodedBlockPatternLuma,CodedBlockPatternChroma);
|
||||
input clk,reset_n;
|
||||
input [3:0] slice_data_state;
|
||||
input [2:0] slice_type;
|
||||
input [4:0] mb_type;
|
||||
input [3:0] mb_type_general;
|
||||
input [5:0] exp_golomb_decoding_output_5to0;
|
||||
output [3:0] CodedBlockPatternLuma;
|
||||
output [1:0] CodedBlockPatternChroma;
|
||||
reg [3:0] CodedBlockPatternLuma;
|
||||
reg [1:0] CodedBlockPatternChroma;
|
||||
|
||||
reg [3:0] CodedBlockPatternLuma_reg;
|
||||
reg [1:0] CodedBlockPatternChroma_reg;
|
||||
|
||||
always @ (posedge clk)
|
||||
CodedBlockPatternLuma_reg <= (reset_n == 0)? 0:CodedBlockPatternLuma;
|
||||
always @ (posedge clk)
|
||||
CodedBlockPatternChroma_reg <= (reset_n == 0)? 0:CodedBlockPatternChroma;
|
||||
|
||||
always @ (slice_data_state or mb_type_general or slice_type or mb_type or exp_golomb_decoding_output_5to0
|
||||
or CodedBlockPatternLuma_reg)
|
||||
if (mb_type_general[3:2] == 2'b10)//Intra16x16
|
||||
begin
|
||||
if (slice_type == 0 || slice_type == 5) //P_slice
|
||||
CodedBlockPatternLuma <= (mb_type < 18)? 4'd0:4'd15;
|
||||
else //I_slice
|
||||
CodedBlockPatternLuma <= (mb_type < 13)? 4'd0:4'd15;
|
||||
end
|
||||
else if (slice_data_state == `coded_block_pattern_s)
|
||||
case (mb_type_general[3])
|
||||
1'b0: //Inter
|
||||
if (exp_golomb_decoding_output_5to0 < 2) //CBP = 0,16
|
||||
CodedBlockPatternLuma <= 0;
|
||||
else if (exp_golomb_decoding_output_5to0 < 6) //CBP =1,2,4,8
|
||||
case (exp_golomb_decoding_output_5to0[2:0])
|
||||
3'b010:CodedBlockPatternLuma <= 4'd1;
|
||||
3'b011:CodedBlockPatternLuma <= 4'd2;
|
||||
3'b100:CodedBlockPatternLuma <= 4'd4;
|
||||
3'b101:CodedBlockPatternLuma <= 4'd8;
|
||||
default:CodedBlockPatternLuma <= CodedBlockPatternLuma_reg;
|
||||
endcase
|
||||
else
|
||||
case (exp_golomb_decoding_output_5to0)
|
||||
6 :CodedBlockPatternLuma <= 4'd0;
|
||||
24,32 :CodedBlockPatternLuma <= 4'd1;
|
||||
25,33 :CodedBlockPatternLuma <= 4'd2;
|
||||
7,20,36 :CodedBlockPatternLuma <= 4'd3;
|
||||
26,34 :CodedBlockPatternLuma <= 4'd4;
|
||||
8,21,37 :CodedBlockPatternLuma <= 4'd5;
|
||||
17,44,46:CodedBlockPatternLuma <= 4'd6;
|
||||
13,28,40:CodedBlockPatternLuma <= 4'd7;
|
||||
27,35 :CodedBlockPatternLuma <= 4'd8;
|
||||
18,45,47:CodedBlockPatternLuma <= 4'd9;
|
||||
9,22,38 :CodedBlockPatternLuma <= 4'd10;
|
||||
14,29,41:CodedBlockPatternLuma <= 4'd11;
|
||||
10,23,39:CodedBlockPatternLuma <= 4'd12;
|
||||
15,30,42:CodedBlockPatternLuma <= 4'd13;
|
||||
16,31,43:CodedBlockPatternLuma <= 4'd14;
|
||||
11,12,19:CodedBlockPatternLuma <= 4'd15;
|
||||
default :CodedBlockPatternLuma <= CodedBlockPatternLuma_reg;
|
||||
endcase
|
||||
1'b1: //Intra4x4
|
||||
if (exp_golomb_decoding_output_5to0 < 3) //CBP = 47,31,15
|
||||
CodedBlockPatternLuma <= 4'd15;
|
||||
else
|
||||
case (exp_golomb_decoding_output_5to0)
|
||||
3,16,41 :CodedBlockPatternLuma <= 4'd0;
|
||||
29,33,42:CodedBlockPatternLuma <= 4'd1;
|
||||
30,34,43:CodedBlockPatternLuma <= 4'd2;
|
||||
17,21,25:CodedBlockPatternLuma <= 4'd3;
|
||||
31,35,44:CodedBlockPatternLuma <= 4'd4;
|
||||
18,22,26:CodedBlockPatternLuma <= 4'd5;
|
||||
37,39,46:CodedBlockPatternLuma <= 4'd6;
|
||||
4,8,12 :CodedBlockPatternLuma <= 4'd7;
|
||||
32,36,45:CodedBlockPatternLuma <= 4'd8;
|
||||
38,40,47:CodedBlockPatternLuma <= 4'd9;
|
||||
19,23,27:CodedBlockPatternLuma <= 4'd10;
|
||||
5,9,13 :CodedBlockPatternLuma <= 4'd11;
|
||||
20,24,28:CodedBlockPatternLuma <= 4'd12;
|
||||
6,10,14 :CodedBlockPatternLuma <= 4'd13;
|
||||
7,11,15 :CodedBlockPatternLuma <= 4'd14;
|
||||
default :CodedBlockPatternLuma <= CodedBlockPatternLuma_reg;
|
||||
endcase
|
||||
endcase
|
||||
else
|
||||
CodedBlockPatternLuma <= CodedBlockPatternLuma_reg;
|
||||
|
||||
|
||||
always @ (slice_data_state or mb_type_general or exp_golomb_decoding_output_5to0 or CodedBlockPatternChroma_reg)
|
||||
if (mb_type_general[3:2] == 2'b10)//Intra16x16
|
||||
CodedBlockPatternChroma <= mb_type_general[1:0];
|
||||
else if (slice_data_state == `coded_block_pattern_s)
|
||||
case (mb_type_general[3])
|
||||
1'b0: //Inter
|
||||
if (exp_golomb_decoding_output_5to0 < 2) //CBP = 0,16
|
||||
CodedBlockPatternChroma <= {1'b0,exp_golomb_decoding_output_5to0[0]};
|
||||
else if (exp_golomb_decoding_output_5to0 < 6) //CBP =1,2,4,8
|
||||
CodedBlockPatternChroma <= 2'd0;
|
||||
else
|
||||
case (exp_golomb_decoding_output_5to0)
|
||||
7,8,9,10,11,13,14,15,16,17,18 :CodedBlockPatternChroma <= 2'd0;
|
||||
19,32,33,34,35,36,37,38,39,40,41,42,43,44,45:CodedBlockPatternChroma <= 2'd1;
|
||||
default :CodedBlockPatternChroma <= 2'd2;
|
||||
endcase
|
||||
1'b1: //Intra4x4
|
||||
if (exp_golomb_decoding_output_5to0 < 3) //CBP = 47,31,15
|
||||
case (exp_golomb_decoding_output_5to0[1:0])
|
||||
2'b00 :CodedBlockPatternChroma <= 2'd2;
|
||||
2'b01 :CodedBlockPatternChroma <= 2'd1;
|
||||
default:CodedBlockPatternChroma <= 2'd0;
|
||||
endcase
|
||||
else
|
||||
case (exp_golomb_decoding_output_5to0)
|
||||
3,8,9,10,11,17,18,19,20,29,30,31,32,37,38:CodedBlockPatternChroma <= 2'd0;
|
||||
4,5,6,7,16,21,22,23,24,33,34,35,36,39,40 :CodedBlockPatternChroma <= 2'd1;
|
||||
default :CodedBlockPatternChroma <= 2'd2;
|
||||
endcase
|
||||
endcase
|
||||
else
|
||||
CodedBlockPatternChroma <= CodedBlockPatternChroma_reg;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,740 @@
|
||||
//-----------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : DF_mem_ctrl.v
|
||||
// Generated : Nov 27,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// controller for DF_mbAddrA_RAM & DF_mbAddrB_RAM & dis_frame_RAM
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module DF_mem_ctrl (clk,reset_n,gclk_end_of_MB_DEC,disable_DF,mb_num_h,mb_num_v,
|
||||
bs_curr_MR,bs_curr_MW,blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,
|
||||
DF_edge_counter_MR,DF_edge_counter_MW,one_edge_counter_MR,one_edge_counter_MW,
|
||||
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
||||
p3_MW,p2_MW,p1_MW,p0_MW,q3_MW,q2_MW,q1_MW,q0_MW,
|
||||
buf0_0,buf0_1,buf0_2,buf0_3,
|
||||
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3,
|
||||
t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3,
|
||||
|
||||
mb_num_h_DF,mb_num_v_DF,end_of_MB_DF,end_of_lastMB_DF,
|
||||
DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrA_RF_rd_addr,DF_mbAddrA_RF_wr_addr,DF_mbAddrA_RF_din,
|
||||
DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,DF_mbAddrB_RAM_addr,DF_mbAddrB_RAM_din,
|
||||
dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din);
|
||||
input clk,reset_n;
|
||||
input disable_DF;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [2:0] bs_curr_MR,bs_curr_MW;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input [4:0] blk4x4_rec_counter_2_raster_order;
|
||||
input [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
|
||||
input [1:0] one_edge_counter_MR,one_edge_counter_MW;
|
||||
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
input [7:0] p3_MW,p2_MW,p1_MW,p0_MW;
|
||||
input [7:0] q3_MW,q2_MW,q1_MW,q0_MW;
|
||||
input [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
|
||||
input [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
|
||||
input [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
|
||||
input [31:0] t0_0,t0_1,t0_2,t0_3;
|
||||
input [31:0] t1_0,t1_1,t1_2,t1_3;
|
||||
input [31:0] t2_0,t2_1,t2_2,t2_3;
|
||||
|
||||
output [3:0] mb_num_h_DF;
|
||||
output [3:0] mb_num_v_DF;
|
||||
output end_of_MB_DF;
|
||||
output end_of_lastMB_DF;
|
||||
output DF_mbAddrA_RF_rd;
|
||||
output DF_mbAddrA_RF_wr;
|
||||
output [4:0] DF_mbAddrA_RF_rd_addr;
|
||||
output [4:0] DF_mbAddrA_RF_wr_addr;
|
||||
output [31:0] DF_mbAddrA_RF_din;
|
||||
|
||||
output DF_mbAddrB_RAM_rd;
|
||||
output DF_mbAddrB_RAM_wr;
|
||||
output [8:0] DF_mbAddrB_RAM_addr;
|
||||
output [31:0] DF_mbAddrB_RAM_din;
|
||||
|
||||
output dis_frame_RAM_wr;
|
||||
output [13:0] dis_frame_RAM_wr_addr;
|
||||
output [31:0] dis_frame_RAM_din;
|
||||
|
||||
wire Is_mbAddrA_wr;
|
||||
wire Is_mbAddrA_real_wr;
|
||||
wire Is_mbAddrA_virtual_wr;
|
||||
wire Is_mbAddrB_wr;
|
||||
wire Is_currMB_wr;
|
||||
wire Is_12cycles_wr;
|
||||
wire dis_frame_RAM_wr_tmp;
|
||||
|
||||
reg [3:0] mb_num_h_DF;
|
||||
reg [3:0] mb_num_v_DF;
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin mb_num_h_DF <= 0; mb_num_v_DF <= 0; end
|
||||
else if (!disable_DF)
|
||||
begin mb_num_h_DF <= mb_num_h; mb_num_v_DF <= mb_num_v; end
|
||||
|
||||
|
||||
reg [3:0] DF_12_cycles;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
DF_12_cycles <= 4'd12;
|
||||
else if (!disable_DF && DF_edge_counter_MW == 6'd47 && one_edge_counter_MW == 2'd3)
|
||||
DF_12_cycles <= 0;
|
||||
else if (DF_12_cycles != 4'd12)
|
||||
DF_12_cycles <= DF_12_cycles + 1;
|
||||
|
||||
reg end_of_MB_DF;
|
||||
reg end_of_lastMB_DF;//end of MB_DF of 98th MB of one frame.Does not need to rise MB_rec_DF_align since there is only
|
||||
//DF and no reconstruction.So dispart end_of_lastMB_DF from end_of_MB_DF
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
end_of_MB_DF <= 1'b0;
|
||||
end_of_lastMB_DF <= 1'b0;
|
||||
end
|
||||
else if (DF_12_cycles == 4'd11)
|
||||
begin
|
||||
end_of_MB_DF <= (!(mb_num_h_DF == 10 && mb_num_v_DF == 8))? 1'b1:1'b0;
|
||||
end_of_lastMB_DF <= (mb_num_h_DF == 10 && mb_num_v_DF == 8)? 1'b1:1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
end_of_MB_DF <= 1'b0;
|
||||
end_of_lastMB_DF <= 1'b0;
|
||||
end
|
||||
|
||||
wire [1:0] write_0to3_cycle;
|
||||
assign write_0to3_cycle = (DF_12_cycles == 4'd12)? one_edge_counter_MW:DF_12_cycles[1:0];
|
||||
//-------------------------------------------------------------------
|
||||
//DF_mbAddrA_RF control
|
||||
//-------------------------------------------------------------------
|
||||
|
||||
//For edge 18,34,42,it will update mbAddrB of left MB.So no matter bs_curr_MR is equal to 0 or not,
|
||||
//mbAddrA should be read out for writing to mbAddrB of left MB.Otherwise,the value written to left
|
||||
//mbAddrB will be a wrong value.
|
||||
assign DF_mbAddrA_RF_rd = (mb_num_h_DF != 0 && (((
|
||||
DF_edge_counter_MR == 6'd0 || DF_edge_counter_MR == 6'd2 || DF_edge_counter_MR == 6'd16 ||
|
||||
DF_edge_counter_MR == 6'd32 || DF_edge_counter_MR == 6'd40) && bs_curr_MR != 0) || (
|
||||
DF_edge_counter_MR == 6'd18 || DF_edge_counter_MR == 6'd34 || DF_edge_counter_MR == 6'd42)));
|
||||
|
||||
assign DF_mbAddrA_RF_wr = (DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd30 ||
|
||||
DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd40 ||
|
||||
DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b01 || DF_12_cycles[3:2] == 2'b10);
|
||||
//DF_mbAddrA_RF_rd_addr
|
||||
reg [2:0] DF_mbAddrA_RF_rd_addr_blk4x4;
|
||||
always @ (DF_mbAddrA_RF_rd or DF_edge_counter_MR)
|
||||
if (DF_mbAddrA_RF_rd)
|
||||
case (DF_edge_counter_MR)
|
||||
6'd0 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd0; //mbAddrA0
|
||||
6'd2 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd1; //mbAddrA1
|
||||
6'd16:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd2; //mbAddrA2
|
||||
6'd18:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd3; //mbAddrA3
|
||||
6'd32:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd4; //mbAddrA4
|
||||
6'd34:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd5; //mbAddrA5
|
||||
6'd40:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd6; //mbAddrA6
|
||||
6'd42:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd7; //mbAddrA7
|
||||
default:DF_mbAddrA_RF_rd_addr_blk4x4 <= 0;
|
||||
endcase
|
||||
else
|
||||
DF_mbAddrA_RF_rd_addr_blk4x4 <= 0;
|
||||
assign DF_mbAddrA_RF_rd_addr = {5{DF_mbAddrA_RF_rd}} &
|
||||
({DF_mbAddrA_RF_rd_addr_blk4x4,2'b0} + one_edge_counter_MR);
|
||||
//DF_mbAddrA_RF_wr_addr
|
||||
reg [2:0] DF_mbAddrA_RF_wr_addr_blk4x4;
|
||||
always @ (DF_mbAddrA_RF_wr or DF_edge_counter_MW or DF_12_cycles[3:2])
|
||||
if (DF_mbAddrA_RF_wr)
|
||||
begin
|
||||
if (DF_edge_counter_MW != 6'd48)
|
||||
case (DF_edge_counter_MW)
|
||||
6'd16:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd0; //mbAddrA0
|
||||
6'd30:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd1; //mbAddrA1
|
||||
6'd32:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd2; //mbAddrA2
|
||||
6'd33:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd3; //mbAddrA3
|
||||
6'd40:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd4; //mbAddrA4
|
||||
6'd41:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd5; //mbAddrA5
|
||||
default:DF_mbAddrA_RF_wr_addr_blk4x4 <= 0;
|
||||
endcase
|
||||
else if (DF_12_cycles[3:2] == 2'b01)
|
||||
DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd6;
|
||||
else
|
||||
DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd7;
|
||||
end
|
||||
else
|
||||
DF_mbAddrA_RF_wr_addr_blk4x4 <= 0;
|
||||
|
||||
assign DF_mbAddrA_RF_wr_addr = {5{DF_mbAddrA_RF_wr}} &
|
||||
({DF_mbAddrA_RF_wr_addr_blk4x4,2'b0} + write_0to3_cycle);
|
||||
|
||||
//DF_mbAddrA_RF_din
|
||||
wire Is_mbAddrA_t1;
|
||||
assign Is_mbAddrA_t1 = (DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 ||
|
||||
DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b10);
|
||||
|
||||
reg [31:0] DF_mbAddrA_RF_din;
|
||||
always @ (DF_mbAddrA_RF_wr or Is_mbAddrA_t1 or write_0to3_cycle or
|
||||
t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3)
|
||||
if (DF_mbAddrA_RF_wr)
|
||||
begin
|
||||
if (Is_mbAddrA_t1)
|
||||
case (write_0to3_cycle)
|
||||
2'd0:DF_mbAddrA_RF_din <= t1_0;
|
||||
2'd1:DF_mbAddrA_RF_din <= t1_1;
|
||||
2'd2:DF_mbAddrA_RF_din <= t1_2;
|
||||
2'd3:DF_mbAddrA_RF_din <= t1_3;
|
||||
endcase
|
||||
else
|
||||
case (write_0to3_cycle)
|
||||
2'd0:DF_mbAddrA_RF_din <= t0_0;
|
||||
2'd1:DF_mbAddrA_RF_din <= t0_1;
|
||||
2'd2:DF_mbAddrA_RF_din <= t0_2;
|
||||
2'd3:DF_mbAddrA_RF_din <= t0_3;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
DF_mbAddrA_RF_din <= 0;
|
||||
//-------------------------------------------------------------------
|
||||
//DF_mbAddrB_RAM control
|
||||
//-------------------------------------------------------------------
|
||||
assign DF_mbAddrB_RAM_rd = (((
|
||||
DF_edge_counter_MR == 6'd4 || DF_edge_counter_MR == 6'd8 || DF_edge_counter_MR == 6'd12 ||
|
||||
DF_edge_counter_MR == 6'd13 || DF_edge_counter_MR == 6'd36 || DF_edge_counter_MR == 6'd37 ||
|
||||
DF_edge_counter_MR == 6'd44 || DF_edge_counter_MR == 6'd45) && mb_num_v_DF != 0) ||
|
||||
DF_edge_counter_MR == 6'd20 || DF_edge_counter_MR == 6'd24 || DF_edge_counter_MR == 6'd28 ||
|
||||
DF_edge_counter_MR == 6'd29);
|
||||
|
||||
wire DF_mbAddrB_RAM_wr_curr;
|
||||
assign DF_mbAddrB_RAM_wr_curr = (((
|
||||
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd30 ||
|
||||
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd39 ||
|
||||
DF_edge_counter_MW == 6'd46 || DF_edge_counter_MW == 6'd47) && mb_num_v_DF != 4'd8) ||
|
||||
DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd14 ||
|
||||
DF_edge_counter_MW == 6'd15);
|
||||
|
||||
wire DF_mbAddrB_RAM_wr_leftMB;
|
||||
assign DF_mbAddrB_RAM_wr_leftMB = (mb_num_h_DF != 0 && mb_num_v_DF != 4'd8 && (
|
||||
DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45));
|
||||
|
||||
assign DF_mbAddrB_RAM_wr = DF_mbAddrB_RAM_wr_curr | DF_mbAddrB_RAM_wr_leftMB;
|
||||
|
||||
reg [2:0] DF_mbAddrB_RAM_addr_blk4x4;
|
||||
always @ (DF_mbAddrB_RAM_rd or DF_edge_counter_MR or DF_mbAddrB_RAM_wr_curr
|
||||
or DF_mbAddrB_RAM_wr_leftMB or DF_edge_counter_MW)
|
||||
if (DF_mbAddrB_RAM_rd)
|
||||
case (DF_edge_counter_MR)
|
||||
6'd4, 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0;
|
||||
6'd8, 6'd24:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1;
|
||||
6'd12,6'd28:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2;
|
||||
6'd13,6'd29:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3;
|
||||
6'd36 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4;
|
||||
6'd37 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5;
|
||||
6'd44 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6;
|
||||
6'd45 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7;
|
||||
default :DF_mbAddrB_RAM_addr_blk4x4 <= 0;
|
||||
endcase
|
||||
else if (DF_mbAddrB_RAM_wr_curr)
|
||||
case (DF_edge_counter_MW)
|
||||
6'd5, 6'd21:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0;
|
||||
6'd9, 6'd25:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1;
|
||||
6'd14,6'd30:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2;
|
||||
6'd15,6'd31:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3;
|
||||
6'd38 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4;
|
||||
6'd39 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5;
|
||||
6'd46 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6;
|
||||
6'd47 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7;
|
||||
default :DF_mbAddrB_RAM_addr_blk4x4 <= 0;
|
||||
endcase
|
||||
else if (DF_mbAddrB_RAM_wr_leftMB)
|
||||
case (DF_edge_counter_MW)
|
||||
6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3;
|
||||
6'd37:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5;
|
||||
default:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7;
|
||||
endcase
|
||||
else
|
||||
DF_mbAddrB_RAM_addr_blk4x4 <= 0;
|
||||
|
||||
reg [1:0] DF_mbAddrB_RAM_addr_offset;
|
||||
always @ (DF_mbAddrB_RAM_rd or one_edge_counter_MR or DF_mbAddrB_RAM_wr or one_edge_counter_MW)
|
||||
if (DF_mbAddrB_RAM_rd) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MR;
|
||||
else if (DF_mbAddrB_RAM_wr) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MW;
|
||||
else DF_mbAddrB_RAM_addr_offset <= 0;
|
||||
|
||||
wire [3:0] mb_num_h_DF_m1;
|
||||
assign mb_num_h_DF_m1 = {4{Is_mbAddrA_wr | DF_mbAddrB_RAM_wr_leftMB}} & (mb_num_h_DF - 1);
|
||||
|
||||
wire [8:0] mb_num_h_DF_x32;
|
||||
assign mb_num_h_DF_x32 = (DF_mbAddrB_RAM_wr_leftMB)? {mb_num_h_DF_m1,5'b0}:{mb_num_h_DF,5'b0};
|
||||
assign DF_mbAddrB_RAM_addr = mb_num_h_DF_x32 + {DF_mbAddrB_RAM_addr_blk4x4,2'b0} + DF_mbAddrB_RAM_addr_offset;
|
||||
|
||||
reg [31:0] DF_mbAddrB_RAM_din;
|
||||
always @ (DF_mbAddrB_RAM_wr_curr or DF_mbAddrB_RAM_wr_leftMB or one_edge_counter_MW
|
||||
or q0_MW or q1_MW or q2_MW or q3_MW or t2_0 or t2_1 or t2_2 or t2_3)
|
||||
if (DF_mbAddrB_RAM_wr_curr)
|
||||
DF_mbAddrB_RAM_din <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
else if (DF_mbAddrB_RAM_wr_leftMB)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:DF_mbAddrB_RAM_din <= t2_0;
|
||||
2'd1:DF_mbAddrB_RAM_din <= t2_1;
|
||||
2'd2:DF_mbAddrB_RAM_din <= t2_2;
|
||||
2'd3:DF_mbAddrB_RAM_din <= t2_3;
|
||||
endcase
|
||||
else
|
||||
DF_mbAddrB_RAM_din <= 0;
|
||||
//-------------------------------------------------------------------
|
||||
//dis_frame_RAM write control
|
||||
//-------------------------------------------------------------------
|
||||
//dis_frame_RAM_wr
|
||||
assign Is_mbAddrA_wr = (mb_num_h_DF != 0 && (
|
||||
DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd16 ||
|
||||
DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd34 ||
|
||||
DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd42));
|
||||
assign Is_mbAddrA_real_wr = (Is_mbAddrA_wr && bs_curr_MW != 0);
|
||||
assign Is_mbAddrA_virtual_wr = (Is_mbAddrA_wr && bs_curr_MW == 0);
|
||||
|
||||
assign Is_mbAddrB_wr = (mb_num_v_DF != 0 && (
|
||||
DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd13 ||
|
||||
DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd38 ||
|
||||
DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd46));
|
||||
assign Is_currMB_wr = ((
|
||||
DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd15 ||
|
||||
DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd22 ||
|
||||
DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd26 ||
|
||||
DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd30 ||
|
||||
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd35 ||
|
||||
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd41 ||
|
||||
DF_edge_counter_MW == 6'd43 || DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd47) &&
|
||||
one_edge_counter_MW != 3'd4);
|
||||
assign Is_12cycles_wr = (DF_12_cycles != 4'd12);
|
||||
|
||||
assign dis_frame_RAM_wr_tmp =
|
||||
( disable_DF && blk4x4_sum_counter[2] != 1'b1) ||
|
||||
(!disable_DF && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr || Is_12cycles_wr));
|
||||
assign dis_frame_RAM_wr = (dis_frame_RAM_wr_tmp & (~Is_mbAddrA_virtual_wr));
|
||||
|
||||
wire Is_luma_wr;
|
||||
wire Is_chroma_wr;
|
||||
wire Is_1st_cycle_wr; //if it is the position of first line of a 4x4 block,for both DF disable & enable
|
||||
wire Is_MB_LeftTop_wr; //if it is the position of most left-top for a whole MB,only for DF is disabled
|
||||
assign Is_luma_wr = (dis_frame_RAM_wr_tmp && (
|
||||
(disable_DF && blk4x4_rec_counter_2_raster_order[4] == 1'b0) ||
|
||||
(!disable_DF && (((Is_mbAddrA_wr || Is_mbAddrB_wr) && !DF_edge_counter_MW[5]) ||
|
||||
(Is_currMB_wr && DF_edge_counter_MW < 6'd39)))))? 1'b1:1'b0;
|
||||
|
||||
assign Is_chroma_wr = (dis_frame_RAM_wr_tmp && !Is_luma_wr)? 1'b1:1'b0;
|
||||
|
||||
assign Is_1st_cycle_wr = (
|
||||
( disable_DF && blk4x4_sum_counter == 0) ||
|
||||
(!disable_DF && (one_edge_counter_MW == 0 && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr)) ||
|
||||
(DF_12_cycles[1:0] == 2'b00 && DF_12_cycles[3:2] != 2'b11)))? 1'b1:1'b0;
|
||||
|
||||
assign Is_MB_LeftTop_wr = (disable_DF && blk4x4_sum_counter == 0 && (
|
||||
(blk4x4_rec_counter_2_raster_order[4] == 1'b0 && blk4x4_rec_counter_2_raster_order[3:0] == 4'b0) ||
|
||||
(blk4x4_rec_counter_2_raster_order[4] == 1'b1 && blk4x4_rec_counter_2_raster_order[1:0] == 2'b0))) ? 1'b1:1'b0;
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
// dis_frame_RAM_wr_addr_base
|
||||
// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
|
||||
// Luma:0 Cb:6336 Cr:7920
|
||||
//---------------------------------------------------------------------------------
|
||||
reg [12:0] dis_frame_RAM_wr_addr_base;
|
||||
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_12cycles_wr
|
||||
or blk4x4_rec_counter_2_raster_order[2] or DF_edge_counter_MW)
|
||||
if (disable_DF)
|
||||
begin
|
||||
if (Is_MB_LeftTop_wr)
|
||||
begin
|
||||
if (Is_luma_wr) //luma
|
||||
dis_frame_RAM_wr_addr_base <= 13'd0;
|
||||
else if (blk4x4_rec_counter_2_raster_order[2] == 1'b0) //Cb
|
||||
dis_frame_RAM_wr_addr_base <= 13'd6336;
|
||||
else //Cr
|
||||
dis_frame_RAM_wr_addr_base <= 13'd7920;
|
||||
end
|
||||
else
|
||||
dis_frame_RAM_wr_addr_base <= 13'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (Is_1st_cycle_wr) //update only @ 1st write cycle
|
||||
begin
|
||||
if (Is_luma_wr) //luma
|
||||
dis_frame_RAM_wr_addr_base <= 13'd0;
|
||||
else if (DF_edge_counter_MW < 6'd45 && DF_edge_counter_MW != 40 && DF_edge_counter_MW != 42) //Cb
|
||||
dis_frame_RAM_wr_addr_base <= 13'd6336;
|
||||
else //Cr
|
||||
dis_frame_RAM_wr_addr_base <= 13'd7920;
|
||||
end
|
||||
else
|
||||
dis_frame_RAM_wr_addr_base <= 0;
|
||||
end
|
||||
//---------------------------------------------------------------------------------
|
||||
// dis_frame_RAM_wr_addr_x
|
||||
// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
|
||||
// x position inside a frame,since every 4 horizontal pixels have been combined as
|
||||
// a single 32bit word,thus 0 ~ 43 for luma and 0 ~ 21 for chroma
|
||||
//---------------------------------------------------------------------------------
|
||||
wire [3:0] mb_num_v_DF_m1;
|
||||
assign mb_num_v_DF_m1 = {4{Is_mbAddrB_wr}} & (mb_num_v_DF - 1);
|
||||
|
||||
reg [1:0] blk4x4_xoffset; //0 ~ 3,xoffset for blk4x4 inside a MB
|
||||
always @ (Is_luma_wr or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW)
|
||||
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
||||
3'b100: //Is_mbAddrA_wr
|
||||
if (Is_luma_wr) blk4x4_xoffset <= 2'd3;
|
||||
else blk4x4_xoffset <= 2'd1;
|
||||
3'b010: //Is_mbAddrB_wr
|
||||
case (DF_edge_counter_MW)
|
||||
6'd5,6'd37,6'd45:blk4x4_xoffset <= 2'd0;
|
||||
6'd9,6'd38,6'd46:blk4x4_xoffset <= 2'd1;
|
||||
6'd13 :blk4x4_xoffset <= 2'd2;
|
||||
6'd14 :blk4x4_xoffset <= 2'd3;
|
||||
default :blk4x4_xoffset <= 0;
|
||||
endcase
|
||||
3'b001: //Is_currMB_wr
|
||||
case (DF_edge_counter_MW)
|
||||
//6'd6,6'd21,6'd23,6'd22,6'd39,6'd41,6'd47:blk4x4_xoffset <= 0;
|
||||
6'd10,6'd25,6'd27,6'd26,6'd43,6'd44 :blk4x4_xoffset <= 2'd1;
|
||||
6'd15,6'd29,6'd31,6'd33 :blk4x4_xoffset <= 2'd2;
|
||||
6'd17,6'd30,6'd35,6'd36 :blk4x4_xoffset <= 2'd3;
|
||||
default :blk4x4_xoffset <= 0;
|
||||
endcase
|
||||
default:
|
||||
if (DF_12_cycles != 4'd12)
|
||||
case (DF_12_cycles[3:2])
|
||||
2'b00 :blk4x4_xoffset <= 0; //buf2 -> blk22
|
||||
2'b01,2'b10 :blk4x4_xoffset <= 2'd1; //T0 -> blk21,T1 -> blk23
|
||||
default :blk4x4_xoffset <= 0;
|
||||
endcase
|
||||
else
|
||||
blk4x4_xoffset <= 0;
|
||||
endcase
|
||||
|
||||
reg [5:0] dis_frame_RAM_wr_addr_x;
|
||||
|
||||
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_mbAddrA_wr
|
||||
or Is_mbAddrB_wr or Is_currMB_wr or blk4x4_rec_counter_2_raster_order[1:0]
|
||||
or mb_num_h or mb_num_h_DF_m1 or mb_num_h_DF or blk4x4_xoffset)
|
||||
if (disable_DF)
|
||||
begin
|
||||
if (Is_MB_LeftTop_wr)
|
||||
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h,2'b0} + blk4x4_rec_counter_2_raster_order[1:0]):({1'b0,mb_num_h,1'b0} + blk4x4_rec_counter_2_raster_order[0]);
|
||||
else
|
||||
dis_frame_RAM_wr_addr_x <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (Is_1st_cycle_wr)
|
||||
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
||||
3'b100: //Is_mbAddrA_wr
|
||||
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF_m1,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF_m1,1'b0} + blk4x4_xoffset);
|
||||
3'b010,3'b001: //Is_mbAddrB_wr,Is_currMB_wr
|
||||
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset);
|
||||
|
||||
default: //for DF_12_cycles != 4'd12
|
||||
dis_frame_RAM_wr_addr_x <= {1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset;
|
||||
endcase
|
||||
else
|
||||
dis_frame_RAM_wr_addr_x <= 0;
|
||||
end
|
||||
//---------------------------------------------------------------------------------
|
||||
// dis_frame_RAM_wr_addr_y
|
||||
// a)Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
|
||||
// b)For 2,3,4 write cycles,dis_frame_RAM_wr_addr is directly +44/+22 instead of
|
||||
// changing dis_frame_RAM_wr_addr_y
|
||||
// c)y addr increase 1 means +44 for luma or +22 for choma
|
||||
//---------------------------------------------------------------------------------
|
||||
reg [1:0] blk4x4_yoffset; //0 ~ 3,yoffset for blk4x4 inside a MB
|
||||
always @ (Is_mbAddrA_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW)
|
||||
if (Is_mbAddrA_wr)
|
||||
case (DF_edge_counter_MW)
|
||||
6'd0,6'd32,6'd40:blk4x4_yoffset <= 2'd0;
|
||||
6'd2,6'd34,6'd42:blk4x4_yoffset <= 2'd1;
|
||||
6'd16 :blk4x4_yoffset <= 2'd2;
|
||||
6'd18 :blk4x4_yoffset <= 2'd3;
|
||||
default :blk4x4_yoffset <= 0;
|
||||
endcase
|
||||
else if (Is_currMB_wr)
|
||||
case (DF_edge_counter_MW)
|
||||
//6'd6,6'd10,6'd15,6'd17,6'd39,6'd43,6'd47:blk4x4_yoffset <= 0;
|
||||
6'd21,6'd25,6'd29,6'd30,6'd41,6'd44 :blk4x4_yoffset <= 2'd1;
|
||||
6'd23,6'd27,6'd31,6'd35 :blk4x4_yoffset <= 2'd2;
|
||||
6'd22,6'd26,6'd33,6'd36 :blk4x4_yoffset <= 2'd3;
|
||||
default :blk4x4_yoffset <= 0;
|
||||
endcase
|
||||
else if (DF_12_cycles != 4'd12)
|
||||
case (DF_12_cycles[2])
|
||||
1'b0:blk4x4_yoffset <= 2'd1; // 0 ~ 3:buf2->22; 8 ~ 11:T1->23
|
||||
1'b1:blk4x4_yoffset <= 0; // 4 ~ 7:T0->21
|
||||
endcase
|
||||
else
|
||||
blk4x4_yoffset <= 0;
|
||||
|
||||
reg [7:0] dis_frame_RAM_wr_addr_y; //y position inside a frame,0 ~ 143 for luma & 0 ~ 71 for chroma
|
||||
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr
|
||||
or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_mbAddrB_wr or Is_currMB_wr
|
||||
or blk4x4_sum_counter[1:0] or blk4x4_rec_counter_2_raster_order[4:1]
|
||||
or mb_num_v or mb_num_v_DF or mb_num_v_DF_m1
|
||||
or one_edge_counter_MW or blk4x4_yoffset or DF_12_cycles)
|
||||
if (disable_DF)
|
||||
begin
|
||||
if (Is_MB_LeftTop_wr)
|
||||
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)?
|
||||
({mb_num_v,4'b0} + {blk4x4_rec_counter_2_raster_order[3:2],2'b00} + blk4x4_sum_counter[1:0]):
|
||||
({1'b0,mb_num_v,3'b0} + {blk4x4_rec_counter_2_raster_order[1], 2'b00} + blk4x4_sum_counter[1:0]);
|
||||
else
|
||||
dis_frame_RAM_wr_addr_y <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (Is_1st_cycle_wr)
|
||||
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
||||
3'b100: //Is_mbAddrA_wr
|
||||
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma
|
||||
(({mb_num_v_DF,4'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW):
|
||||
(({1'b0,mb_num_v_DF,3'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW);
|
||||
3'b010: //Is_mbAddrB_wr
|
||||
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma
|
||||
(({mb_num_v_DF_m1,4'b0} + 4'd12) + one_edge_counter_MW):
|
||||
(({1'b0,mb_num_v_DF_m1,3'b0} + 4'd4 ) + one_edge_counter_MW);
|
||||
3'b001: //Is_currMB_wr
|
||||
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma
|
||||
(({mb_num_v_DF,4'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW):
|
||||
(({1'b0,mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW);
|
||||
default:
|
||||
if (DF_12_cycles != 4'd12)
|
||||
dis_frame_RAM_wr_addr_y <= {mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0} + DF_12_cycles[1:0];
|
||||
else
|
||||
dis_frame_RAM_wr_addr_y <= 0;
|
||||
endcase
|
||||
else
|
||||
dis_frame_RAM_wr_addr_y <= 0;
|
||||
end
|
||||
|
||||
|
||||
wire [12:0] dis_frame_RAM_wr_addr_y_ext; //every "y" increase will increase 44(luma) or 22(chroma) for
|
||||
//dis_frame_RAM address
|
||||
|
||||
assign dis_frame_RAM_wr_addr_y_ext = (Is_luma_wr)?
|
||||
//luma, x44 = x32 + x8 + x4
|
||||
( {dis_frame_RAM_wr_addr_y,5'b0} + {2'b0,dis_frame_RAM_wr_addr_y,3'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0}):
|
||||
//chroma,x22 = x16 + x4 + x2
|
||||
({1'b0,dis_frame_RAM_wr_addr_y,4'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0} + {4'b0,dis_frame_RAM_wr_addr_y,1'b0});
|
||||
|
||||
wire [13:0] dis_frame_RAM_wr_addr_tmp;
|
||||
reg [13:0] dis_frame_RAM_wr_addr_LeftTop_reg;
|
||||
reg [13:0] dis_frame_RAM_wr_addr_reg;
|
||||
reg [13:0] dis_frame_RAM_wr_addr;
|
||||
|
||||
assign dis_frame_RAM_wr_addr_tmp = dis_frame_RAM_wr_addr_base + dis_frame_RAM_wr_addr_y_ext + dis_frame_RAM_wr_addr_x;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
dis_frame_RAM_wr_addr_LeftTop_reg <= 0;
|
||||
else if (Is_MB_LeftTop_wr)
|
||||
dis_frame_RAM_wr_addr_LeftTop_reg <= dis_frame_RAM_wr_addr_tmp;
|
||||
|
||||
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_chroma_wr or dis_frame_RAM_wr_addr_tmp
|
||||
or dis_frame_RAM_wr_addr_reg or blk4x4_rec_counter_2_raster_order or dis_frame_RAM_wr_addr_LeftTop_reg)
|
||||
if (disable_DF)
|
||||
begin
|
||||
if (Is_MB_LeftTop_wr)
|
||||
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp;
|
||||
else if (Is_1st_cycle_wr)
|
||||
case (blk4x4_rec_counter_2_raster_order[4])
|
||||
1'b0:
|
||||
case (blk4x4_rec_counter_2_raster_order[3:2])
|
||||
2'b00:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0];
|
||||
2'b01:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 176;
|
||||
2'b10:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 352;
|
||||
2'b11:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 528;
|
||||
endcase
|
||||
1'b1:
|
||||
dis_frame_RAM_wr_addr <= (blk4x4_rec_counter_2_raster_order[1])?
|
||||
(dis_frame_RAM_wr_addr_LeftTop_reg + 88 + blk4x4_rec_counter_2_raster_order[0]):
|
||||
(dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[0]);
|
||||
endcase
|
||||
else if (Is_luma_wr)
|
||||
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44;
|
||||
else if (Is_chroma_wr)
|
||||
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22;
|
||||
else
|
||||
dis_frame_RAM_wr_addr <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (Is_1st_cycle_wr)
|
||||
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp;
|
||||
else if (Is_luma_wr)
|
||||
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44;
|
||||
else if (Is_chroma_wr)
|
||||
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22;
|
||||
else
|
||||
dis_frame_RAM_wr_addr <= 0;
|
||||
end
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
dis_frame_RAM_wr_addr_reg <= 0;
|
||||
else if (dis_frame_RAM_wr_tmp)
|
||||
dis_frame_RAM_wr_addr_reg <= dis_frame_RAM_wr_addr;
|
||||
|
||||
//dis_frame_RAM_din
|
||||
wire Is_mbAddrB_t1;
|
||||
wire Is_currMB_buf0;
|
||||
wire Is_currMB_buf2;
|
||||
wire Is_currMB_buf3;
|
||||
wire Is_currMB_t1;
|
||||
assign Is_mbAddrB_t1 = (DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd38 ||
|
||||
DF_edge_counter_MW == 6'd46);
|
||||
assign Is_currMB_buf0 = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd15 ||
|
||||
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 ||
|
||||
DF_edge_counter_MW == 6'd47);
|
||||
assign Is_currMB_buf2 = (DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd33 ||
|
||||
DF_edge_counter_MW == 6'd41);
|
||||
assign Is_currMB_buf3 = (DF_edge_counter_MW == 6'd26);
|
||||
assign Is_currMB_t1 = (DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd23 ||
|
||||
DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 ||
|
||||
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd44);
|
||||
|
||||
reg [31:0] dis_frame_RAM_din;
|
||||
always @ (disable_DF or dis_frame_RAM_wr or blk4x4_sum_counter or one_edge_counter_MW or
|
||||
DF_12_cycles or Is_mbAddrA_real_wr or Is_mbAddrB_wr or Is_mbAddrB_t1 or Is_currMB_buf0 or
|
||||
Is_currMB_buf2 or Is_currMB_buf3 or Is_currMB_t1 or Is_currMB_wr or
|
||||
blk4x4_sum_PE0_out or blk4x4_sum_PE1_out or blk4x4_sum_PE2_out or blk4x4_sum_PE3_out or
|
||||
p0_MW or p1_MW or p2_MW or p3_MW or
|
||||
buf0_0 or buf0_1 or buf0_2 or buf0_3 or
|
||||
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3 or
|
||||
t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3)
|
||||
if (disable_DF && dis_frame_RAM_wr)
|
||||
begin
|
||||
if (blk4x4_sum_counter[2] == 1'b0)
|
||||
dis_frame_RAM_din <= {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out};
|
||||
else
|
||||
dis_frame_RAM_din <= 0;
|
||||
end
|
||||
else if (!disable_DF && dis_frame_RAM_wr)
|
||||
case ({Is_mbAddrA_real_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
||||
3'b100: //Is_mbAddrA_wr
|
||||
dis_frame_RAM_din <= {p0_MW,p1_MW,p2_MW,p3_MW};
|
||||
3'b010: //Is_mbAddrB_wr
|
||||
begin
|
||||
if (Is_mbAddrB_t1) //T1 -> mbAddrB
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= t1_0;
|
||||
2'd1:dis_frame_RAM_din <= t1_1;
|
||||
2'd2:dis_frame_RAM_din <= t1_2;
|
||||
2'd3:dis_frame_RAM_din <= t1_3;
|
||||
endcase
|
||||
else //T0 -> mbAddrB
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= t0_0;
|
||||
2'd1:dis_frame_RAM_din <= t0_1;
|
||||
2'd2:dis_frame_RAM_din <= t0_2;
|
||||
2'd3:dis_frame_RAM_din <= t0_3;
|
||||
endcase
|
||||
end
|
||||
3'b001: //Is_currMB_wr
|
||||
case ({Is_currMB_buf0,Is_currMB_buf2,Is_currMB_buf3,Is_currMB_t1})
|
||||
4'b1000: //Is_currMB_buf0
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= buf0_0;
|
||||
2'd1:dis_frame_RAM_din <= buf0_1;
|
||||
2'd2:dis_frame_RAM_din <= buf0_2;
|
||||
2'd3:dis_frame_RAM_din <= buf0_3;
|
||||
endcase
|
||||
4'b0100: //Is_currMB_buf2
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= buf2_0;
|
||||
2'd1:dis_frame_RAM_din <= buf2_1;
|
||||
2'd2:dis_frame_RAM_din <= buf2_2;
|
||||
2'd3:dis_frame_RAM_din <= buf2_3;
|
||||
endcase
|
||||
4'b0010: //Is_currMB_buf3
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= buf3_0;
|
||||
2'd1:dis_frame_RAM_din <= buf3_1;
|
||||
2'd2:dis_frame_RAM_din <= buf3_2;
|
||||
2'd3:dis_frame_RAM_din <= buf3_3;
|
||||
endcase
|
||||
4'b0001: //Is_currMB_t1
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= t1_0;
|
||||
2'd1:dis_frame_RAM_din <= t1_1;
|
||||
2'd2:dis_frame_RAM_din <= t1_2;
|
||||
2'd3:dis_frame_RAM_din <= t1_3;
|
||||
endcase
|
||||
default: //Is_currMB_t0
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:dis_frame_RAM_din <= t0_0;
|
||||
2'd1:dis_frame_RAM_din <= t0_1;
|
||||
2'd2:dis_frame_RAM_din <= t0_2;
|
||||
2'd3:dis_frame_RAM_din <= t0_3;
|
||||
endcase
|
||||
endcase
|
||||
default://additional 12 cycles
|
||||
case (DF_12_cycles[3:2])
|
||||
2'b00: //0 ~ 3,buf2 -> blk22
|
||||
case (DF_12_cycles[1:0])
|
||||
2'd0:dis_frame_RAM_din <= buf2_0;
|
||||
2'd1:dis_frame_RAM_din <= buf2_1;
|
||||
2'd2:dis_frame_RAM_din <= buf2_2;
|
||||
2'd3:dis_frame_RAM_din <= buf2_3;
|
||||
endcase
|
||||
2'b01: //4 ~ 7,T0 -> blk21
|
||||
case (DF_12_cycles[1:0])
|
||||
2'd0:dis_frame_RAM_din <= t0_0;
|
||||
2'd1:dis_frame_RAM_din <= t0_1;
|
||||
2'd2:dis_frame_RAM_din <= t0_2;
|
||||
2'd3:dis_frame_RAM_din <= t0_3;
|
||||
endcase
|
||||
default://8 ~ 11,T1 -> blk23
|
||||
case (DF_12_cycles[1:0])
|
||||
2'd0:dis_frame_RAM_din <= t1_0;
|
||||
2'd1:dis_frame_RAM_din <= t1_1;
|
||||
2'd2:dis_frame_RAM_din <= t1_2;
|
||||
2'd3:dis_frame_RAM_din <= t1_3;
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
else
|
||||
dis_frame_RAM_din <= 0;
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,861 @@
|
||||
//-----------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : DF_pipeline.v
|
||||
// Generated : Dec 2, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// 5-stage pipeline control for deblocking filter
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module DF_pipeline (clk,gclk_DF,gclk_end_of_MB_DEC,reset_n,disable_DF,end_of_BS_DEC,
|
||||
end_of_MB_DF,end_of_lastMB_DF,
|
||||
bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
|
||||
QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
|
||||
DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout,
|
||||
buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3,
|
||||
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3,
|
||||
|
||||
DF_duration,
|
||||
DF_edge_counter_MR,DF_edge_counter_MW,
|
||||
one_edge_counter_MR,one_edge_counter_MW,
|
||||
bs_curr_MR,bs_curr_MW,
|
||||
p0_MW,p1_MW,p2_MW,p3_MW,q0_MW,q1_MW,q2_MW,q3_MW);
|
||||
input clk;
|
||||
input gclk_DF;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input reset_n;
|
||||
input disable_DF;
|
||||
input end_of_BS_DEC;
|
||||
input end_of_MB_DF;
|
||||
input end_of_lastMB_DF;
|
||||
input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
|
||||
input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
input [5:0] QPy,QPc;
|
||||
input [3:0] slice_alpha_c0_offset_div2,slice_beta_offset_div2;
|
||||
input [31:0] DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout;
|
||||
input [31:0] buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3;
|
||||
input [31:0] buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3;
|
||||
|
||||
output DF_duration;
|
||||
output [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
|
||||
output [1:0] one_edge_counter_MR,one_edge_counter_MW;
|
||||
output [2:0] bs_curr_MR;
|
||||
output [2:0] bs_curr_MW;
|
||||
output [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
|
||||
output [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
|
||||
|
||||
reg DF_duration;
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
DF_duration <= 1'b0;
|
||||
else if (end_of_BS_DEC)
|
||||
DF_duration <= 1'b1;
|
||||
else if (end_of_MB_DF || end_of_lastMB_DF)
|
||||
DF_duration <= 1'b0;
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
//1.MR: Memory Read
|
||||
//---------------------------------------------------------------------
|
||||
//DF_edge_counter_MR & one_edge_counter_MR
|
||||
reg [5:0] DF_edge_counter_MR;
|
||||
reg [1:0] one_edge_counter_MR;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
DF_edge_counter_MR <= 6'd48;
|
||||
else if (end_of_BS_DEC == 1'b1)
|
||||
DF_edge_counter_MR <= 0;
|
||||
else if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd48)
|
||||
DF_edge_counter_MR <= DF_edge_counter_MR + 1;
|
||||
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
one_edge_counter_MR <= 2'd3;
|
||||
else if (end_of_BS_DEC == 1'b1)
|
||||
one_edge_counter_MR <= 2'd0;
|
||||
else
|
||||
begin
|
||||
if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd47 && DF_edge_counter_MR[5:4] != 2'b11) //!47,!48
|
||||
one_edge_counter_MR <= 2'd0;
|
||||
else if (one_edge_counter_MR != 2'd3)
|
||||
one_edge_counter_MR <= one_edge_counter_MR + 1;
|
||||
end
|
||||
|
||||
//lumaEdgeFlag_MR,chromaEdgeFlag_MR
|
||||
wire lumaEdgeFlag_MR,chromaEdgeFlag_MR;
|
||||
assign lumaEdgeFlag_MR = !DF_edge_counter_MR[5];
|
||||
assign chromaEdgeFlag_MR = DF_edge_counter_MR[5] && (DF_edge_counter_MR != 6'd48);
|
||||
|
||||
//bs_curr_MR
|
||||
reg [2:0] bs_curr_MR;
|
||||
always @ (disable_DF or lumaEdgeFlag_MR or chromaEdgeFlag_MR or
|
||||
DF_edge_counter_MR[4:0] or one_edge_counter_MR[1] or
|
||||
bs_V0 or bs_V1 or bs_V2 or bs_V3 or bs_H0 or bs_H1 or bs_H2 or bs_H3)
|
||||
if (!disable_DF && lumaEdgeFlag_MR)
|
||||
case (DF_edge_counter_MR[4:0])
|
||||
5'd0 :bs_curr_MR <= bs_V0[2:0];
|
||||
5'd1 :bs_curr_MR <= bs_V1[2:0];
|
||||
5'd2 :bs_curr_MR <= bs_V0[5:3];
|
||||
5'd3 :bs_curr_MR <= bs_V1[5:3];
|
||||
5'd4 :bs_curr_MR <= bs_H0[2:0];
|
||||
5'd5 :bs_curr_MR <= bs_H1[2:0];
|
||||
5'd6 :bs_curr_MR <= bs_V2[2:0];
|
||||
5'd7 :bs_curr_MR <= bs_V2[5:3];
|
||||
5'd8 :bs_curr_MR <= bs_H0[5:3];
|
||||
5'd9 :bs_curr_MR <= bs_H1[5:3];
|
||||
5'd10:bs_curr_MR <= bs_V3[2:0];
|
||||
5'd11:bs_curr_MR <= bs_V3[5:3];
|
||||
5'd12:bs_curr_MR <= bs_H0[8:6];
|
||||
5'd13:bs_curr_MR <= bs_H0[11:9];
|
||||
5'd14:bs_curr_MR <= bs_H1[8:6];
|
||||
5'd15:bs_curr_MR <= bs_H1[11:9];
|
||||
5'd16:bs_curr_MR <= bs_V0[8:6];
|
||||
5'd17:bs_curr_MR <= bs_V1[8:6];
|
||||
5'd18:bs_curr_MR <= bs_V0[11:9];
|
||||
5'd19:bs_curr_MR <= bs_V1[11:9];
|
||||
5'd20:bs_curr_MR <= bs_H2[2:0];
|
||||
5'd21:bs_curr_MR <= bs_H3[2:0];
|
||||
5'd22:bs_curr_MR <= bs_V2[8:6];
|
||||
5'd23:bs_curr_MR <= bs_V2[11:9];
|
||||
5'd24:bs_curr_MR <= bs_H2[5:3];
|
||||
5'd25:bs_curr_MR <= bs_H3[5:3];
|
||||
5'd26:bs_curr_MR <= bs_V3[8:6];
|
||||
5'd27:bs_curr_MR <= bs_V3[11:9];
|
||||
5'd28:bs_curr_MR <= bs_H2[8:6];
|
||||
5'd29:bs_curr_MR <= bs_H2[11:9];
|
||||
5'd30:bs_curr_MR <= bs_H3[8:6];
|
||||
5'd31:bs_curr_MR <= bs_H3[11:9];
|
||||
endcase
|
||||
else if (!disable_DF && chromaEdgeFlag_MR)
|
||||
case (DF_edge_counter_MR[3:0])
|
||||
4'd0,4'd8: //32,40
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_V0[2:0];
|
||||
1'b1:bs_curr_MR <= bs_V0[5:3];
|
||||
endcase
|
||||
4'd2,4'd10: //34,42
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_V0[8:6];
|
||||
1'b1:bs_curr_MR <= bs_V0[11:9];
|
||||
endcase
|
||||
4'd1,4'd9: //33,41
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_V2[2:0];
|
||||
1'b1:bs_curr_MR <= bs_V2[5:3];
|
||||
endcase
|
||||
4'd3,4'd11: //35,43
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_V2[8:6];
|
||||
1'b1:bs_curr_MR <= bs_V2[11:9];
|
||||
endcase
|
||||
4'd4,4'd12: //36,44
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_H0[2:0];
|
||||
1'b1:bs_curr_MR <= bs_H0[5:3];
|
||||
endcase
|
||||
4'd5,4'd13: //37,45
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_H0[8:6];
|
||||
1'b1:bs_curr_MR <= bs_H0[11:9];
|
||||
endcase
|
||||
4'd6,4'd14: //38,46
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_H2[2:0];
|
||||
1'b1:bs_curr_MR <= bs_H2[5:3];
|
||||
endcase
|
||||
4'd7,4'd15: //39,47
|
||||
case (one_edge_counter_MR[1])
|
||||
1'b0:bs_curr_MR <= bs_H2[8:6];
|
||||
1'b1:bs_curr_MR <= bs_H2[11:9];
|
||||
endcase
|
||||
endcase
|
||||
else
|
||||
bs_curr_MR <= 0;
|
||||
|
||||
// Pipelined parameters
|
||||
reg [2:0] bs_curr_TD;
|
||||
reg lumaEdgeFlag_TD,chromaEdgeFlag_TD;
|
||||
reg [5:0] DF_edge_counter_TD;
|
||||
reg [1:0] one_edge_counter_TD;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
bs_curr_TD <= 0;
|
||||
lumaEdgeFlag_TD <= 0;
|
||||
chromaEdgeFlag_TD <= 0;
|
||||
DF_edge_counter_TD <= 6'd48;
|
||||
one_edge_counter_TD <= 2'd3;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs_curr_TD <= bs_curr_MR;
|
||||
lumaEdgeFlag_TD <= lumaEdgeFlag_MR;
|
||||
chromaEdgeFlag_TD <= chromaEdgeFlag_MR;
|
||||
DF_edge_counter_TD <= DF_edge_counter_MR;
|
||||
one_edge_counter_TD <= one_edge_counter_MR;
|
||||
end
|
||||
//---------------------------------------------------------------------
|
||||
//2.TD: Threshold Decider
|
||||
//---------------------------------------------------------------------
|
||||
wire [6:0] indexA_y_unclipped,indexA_c_unclipped;
|
||||
wire [6:0] indexB_y_unclipped,indexB_c_unclipped;
|
||||
assign indexA_y_unclipped = QPy + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0};
|
||||
assign indexA_c_unclipped = QPc + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0};
|
||||
assign indexB_y_unclipped = QPy + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0};
|
||||
assign indexB_c_unclipped = QPc + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0};
|
||||
|
||||
wire [5:0] indexA_y,indexA_c;
|
||||
wire [5:0] indexB_y,indexB_c;
|
||||
assign indexA_y = (indexA_y_unclipped[6] == 1)? 0:((indexA_y_unclipped[5:0] > 6'd51)? 6'd51:indexA_y_unclipped[5:0]);
|
||||
assign indexA_c = (indexA_c_unclipped[6] == 1)? 0:((indexA_c_unclipped[5:0] > 6'd51)? 6'd51:indexA_c_unclipped[5:0]);
|
||||
assign indexB_y = (indexB_y_unclipped[6] == 1)? 0:((indexB_y_unclipped[5:0] > 6'd51)? 6'd51:indexB_y_unclipped[5:0]);
|
||||
assign indexB_c = (indexB_c_unclipped[6] == 1)? 0:((indexB_c_unclipped[5:0] > 6'd51)? 6'd51:indexB_c_unclipped[5:0]);
|
||||
|
||||
reg [5:0] indexA_y_reg,indexA_c_reg;
|
||||
reg [5:0] indexB_y_reg,indexB_c_reg;
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin indexA_y_reg <= 0; indexA_c_reg <= 0; indexB_y_reg <= 0; indexB_c_reg <= 0; end
|
||||
else if (!disable_DF)
|
||||
begin
|
||||
indexA_y_reg <= indexA_y; indexA_c_reg <= indexA_c;
|
||||
indexB_y_reg <= indexB_y; indexB_c_reg <= indexB_c;
|
||||
end
|
||||
|
||||
wire [5:0] indexA,indexB;
|
||||
assign indexA = (lumaEdgeFlag_TD)? indexA_y_reg:((chromaEdgeFlag_TD)? indexA_c_reg:0);
|
||||
assign indexB = (lumaEdgeFlag_TD)? indexB_y_reg:((chromaEdgeFlag_TD)? indexB_c_reg:0);
|
||||
|
||||
reg [7:0] alpha,beta;
|
||||
//alpha
|
||||
always @ (indexA)
|
||||
if (indexA < 16)
|
||||
alpha <= 0;
|
||||
else
|
||||
case (indexA)
|
||||
6'd16,6'd17:alpha <= 8'd4;
|
||||
6'd18:alpha <= 8'd5; 6'd19:alpha <= 8'd6; 6'd20:alpha <= 8'd7; 6'd21:alpha <= 8'd8;
|
||||
6'd22:alpha <= 8'd9; 6'd23:alpha <= 8'd10; 6'd24:alpha <= 8'd12; 6'd25:alpha <= 8'd13;
|
||||
6'd26:alpha <= 8'd15; 6'd27:alpha <= 8'd17; 6'd28:alpha <= 8'd20; 6'd29:alpha <= 8'd22;
|
||||
6'd30:alpha <= 8'd25; 6'd31:alpha <= 8'd28; 6'd32:alpha <= 8'd32; 6'd33:alpha <= 8'd36;
|
||||
6'd34:alpha <= 8'd40; 6'd35:alpha <= 8'd45; 6'd36:alpha <= 8'd50; 6'd37:alpha <= 8'd56;
|
||||
6'd38:alpha <= 8'd63; 6'd39:alpha <= 8'd71; 6'd40:alpha <= 8'd80; 6'd41:alpha <= 8'd90;
|
||||
6'd42:alpha <= 8'd101; 6'd43:alpha <= 8'd113; 6'd44:alpha <= 8'd127; 6'd45:alpha <= 8'd144;
|
||||
6'd46:alpha <= 8'd162; 6'd47:alpha <= 8'd182; 6'd48:alpha <= 8'd203; 6'd49:alpha <= 8'd226;
|
||||
default:alpha <= 8'd255;
|
||||
endcase
|
||||
//beta
|
||||
always @ (indexB)
|
||||
if (indexB < 16)
|
||||
beta <= 0;
|
||||
else if (indexB > 15 && indexB < 26)
|
||||
case (indexB)
|
||||
6'd16,6'd17,6'd18 :beta <= 8'd2;
|
||||
6'd19,6'd20,6'd21,6'd22 :beta <= 8'd3;
|
||||
6'd23,6'd24,6'd25 :beta <= 8'd4;
|
||||
default:beta <= 0;
|
||||
endcase
|
||||
else
|
||||
beta <= indexB[5:1] - 3'd7;
|
||||
|
||||
wire [7:0] absolute_TD0_a,absolute_TD0_b;
|
||||
wire [7:0] absolute_TD1_a,absolute_TD1_b;
|
||||
wire [7:0] absolute_TD2_a,absolute_TD2_b;
|
||||
wire [7:0] absolute_TD0_out,absolute_TD1_out,absolute_TD2_out;
|
||||
absolute absolute_TD0 (.a(absolute_TD0_a),.b(absolute_TD0_b),.out(absolute_TD0_out));
|
||||
absolute absolute_TD1 (.a(absolute_TD1_a),.b(absolute_TD1_b),.out(absolute_TD1_out));
|
||||
absolute absolute_TD2 (.a(absolute_TD2_a),.b(absolute_TD2_b),.out(absolute_TD2_out));
|
||||
|
||||
//p0 ~ p3
|
||||
wire Is_p_from_mbAddrA;
|
||||
wire Is_p_from_mbAddrB;
|
||||
wire Is_p_from_buf0;
|
||||
wire Is_p_from_buf1;
|
||||
wire Is_p_from_buf2;
|
||||
wire Is_p_from_buf3;
|
||||
assign Is_p_from_mbAddrA = (DF_edge_counter_TD == 6'd0 || DF_edge_counter_TD == 6'd2 ||
|
||||
DF_edge_counter_TD == 6'd16 || DF_edge_counter_TD == 6'd18 || DF_edge_counter_TD == 6'd32 ||
|
||||
DF_edge_counter_TD == 6'd34 || DF_edge_counter_TD == 6'd40 || DF_edge_counter_TD == 6'd42);
|
||||
|
||||
assign Is_p_from_mbAddrB = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd8 ||
|
||||
DF_edge_counter_TD == 6'd12 || DF_edge_counter_TD == 6'd13 || DF_edge_counter_TD == 6'd20 ||
|
||||
DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd29 ||
|
||||
DF_edge_counter_TD == 6'd36 || DF_edge_counter_TD == 6'd37 || DF_edge_counter_TD == 6'd44 ||
|
||||
DF_edge_counter_TD == 6'd45);
|
||||
|
||||
assign Is_p_from_buf0 = (DF_edge_counter_TD == 6'd1 || DF_edge_counter_TD == 6'd5 ||
|
||||
DF_edge_counter_TD == 6'd10 || DF_edge_counter_TD == 6'd14 || DF_edge_counter_TD == 6'd17 ||
|
||||
DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd26 || DF_edge_counter_TD == 6'd30 ||
|
||||
DF_edge_counter_TD == 6'd33 || DF_edge_counter_TD == 6'd38 || DF_edge_counter_TD == 6'd41 ||
|
||||
DF_edge_counter_TD == 6'd46);
|
||||
|
||||
assign Is_p_from_buf1 = (DF_edge_counter_TD == 6'd6 || DF_edge_counter_TD == 6'd9 ||
|
||||
DF_edge_counter_TD == 6'd15 || DF_edge_counter_TD == 6'd22 || DF_edge_counter_TD == 6'd25 ||
|
||||
DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || DF_edge_counter_TD == 6'd47);
|
||||
|
||||
assign Is_p_from_buf2 = (DF_edge_counter_TD == 6'd3 || DF_edge_counter_TD == 6'd11 ||
|
||||
DF_edge_counter_TD == 6'd19 || DF_edge_counter_TD == 6'd27 || DF_edge_counter_TD == 6'd35 ||
|
||||
DF_edge_counter_TD == 6'd43);
|
||||
|
||||
assign Is_p_from_buf3 = (DF_edge_counter_TD == 6'd7 || DF_edge_counter_TD == 6'd23);
|
||||
|
||||
reg [7:0] p0,p1,p2,p3;
|
||||
always @ (Is_p_from_mbAddrA or Is_p_from_mbAddrB or Is_p_from_buf0 or Is_p_from_buf1 or
|
||||
Is_p_from_buf2 or Is_p_from_buf3 or one_edge_counter_TD or
|
||||
DF_mbAddrA_RF_dout or DF_mbAddrB_RAM_dout or
|
||||
buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or
|
||||
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3)
|
||||
case ({Is_p_from_mbAddrA,Is_p_from_mbAddrB,Is_p_from_buf0,Is_p_from_buf1,Is_p_from_buf2,Is_p_from_buf3})
|
||||
6'b100000:{p0,p1,p2,p3} <= DF_mbAddrA_RF_dout;
|
||||
6'b010000:{p0,p1,p2,p3} <= DF_mbAddrB_RAM_dout;
|
||||
6'b001000: case (one_edge_counter_TD)
|
||||
2'b00:{p0,p1,p2,p3} <= buf0_0;
|
||||
2'b01:{p0,p1,p2,p3} <= buf0_1;
|
||||
2'b10:{p0,p1,p2,p3} <= buf0_2;
|
||||
2'b11:{p0,p1,p2,p3} <= buf0_3;
|
||||
endcase
|
||||
6'b000100: case (one_edge_counter_TD)
|
||||
2'b00:{p0,p1,p2,p3} <= buf1_0;
|
||||
2'b01:{p0,p1,p2,p3} <= buf1_1;
|
||||
2'b10:{p0,p1,p2,p3} <= buf1_2;
|
||||
2'b11:{p0,p1,p2,p3} <= buf1_3;
|
||||
endcase
|
||||
6'b000010: case (one_edge_counter_TD)
|
||||
2'b00:{p0,p1,p2,p3} <= buf2_0;
|
||||
2'b01:{p0,p1,p2,p3} <= buf2_1;
|
||||
2'b10:{p0,p1,p2,p3} <= buf2_2;
|
||||
2'b11:{p0,p1,p2,p3} <= buf2_3;
|
||||
endcase
|
||||
6'b000001: case (one_edge_counter_TD)
|
||||
2'b00:{p0,p1,p2,p3} <= buf3_0;
|
||||
2'b01:{p0,p1,p2,p3} <= buf3_1;
|
||||
2'b10:{p0,p1,p2,p3} <= buf3_2;
|
||||
2'b11:{p0,p1,p2,p3} <= buf3_3;
|
||||
endcase
|
||||
default:{p0,p1,p2,p3} <= 0;
|
||||
endcase
|
||||
|
||||
//q0 ~ q3
|
||||
wire Is_q_from_buf0;
|
||||
wire Is_q_from_buf1;
|
||||
wire Is_q_from_buf2;
|
||||
wire Is_q_from_buf3;
|
||||
|
||||
assign Is_q_from_buf0 = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd12 ||
|
||||
DF_edge_counter_TD == 6'd20 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd36 ||
|
||||
DF_edge_counter_TD == 6'd44);
|
||||
|
||||
assign Is_q_from_buf1 = (DF_edge_counter_TD == 6'd8 || DF_edge_counter_TD == 6'd13 ||
|
||||
DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd29 || DF_edge_counter_TD == 6'd37 ||
|
||||
DF_edge_counter_TD == 6'd45);
|
||||
|
||||
assign Is_q_from_buf2 = (DF_edge_counter_TD == 6'd5 || DF_edge_counter_TD == 6'd14 ||
|
||||
DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd30 || DF_edge_counter_TD == 6'd38 ||
|
||||
DF_edge_counter_TD == 6'd46);
|
||||
|
||||
assign Is_q_from_buf3 = (DF_edge_counter_TD == 6'd9 || DF_edge_counter_TD == 6'd15 ||
|
||||
DF_edge_counter_TD == 6'd25 || DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 ||
|
||||
DF_edge_counter_TD == 6'd47);
|
||||
|
||||
reg [7:0] q0,q1,q2,q3;
|
||||
always @ (Is_q_from_buf0 or Is_q_from_buf1 or Is_q_from_buf2 or Is_q_from_buf3 or
|
||||
rec_DF_RAM_dout or one_edge_counter_TD or DF_edge_counter_TD or
|
||||
buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or
|
||||
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3)
|
||||
case ({Is_q_from_buf0,Is_q_from_buf1,Is_q_from_buf2,Is_q_from_buf3})
|
||||
4'b1000:case (one_edge_counter_TD)
|
||||
2'b00:{q3,q2,q1,q0} <= buf0_0;
|
||||
2'b01:{q3,q2,q1,q0} <= buf0_1;
|
||||
2'b10:{q3,q2,q1,q0} <= buf0_2;
|
||||
2'b11:{q3,q2,q1,q0} <= buf0_3;
|
||||
endcase
|
||||
4'b0100:case (one_edge_counter_TD)
|
||||
2'b00:{q3,q2,q1,q0} <= buf1_0;
|
||||
2'b01:{q3,q2,q1,q0} <= buf1_1;
|
||||
2'b10:{q3,q2,q1,q0} <= buf1_2;
|
||||
2'b11:{q3,q2,q1,q0} <= buf1_3;
|
||||
endcase
|
||||
4'b0010:case (one_edge_counter_TD)
|
||||
2'b00:{q3,q2,q1,q0} <= buf2_0;
|
||||
2'b01:{q3,q2,q1,q0} <= buf2_1;
|
||||
2'b10:{q3,q2,q1,q0} <= buf2_2;
|
||||
2'b11:{q3,q2,q1,q0} <= buf2_3;
|
||||
endcase
|
||||
4'b0001:case (one_edge_counter_TD)
|
||||
2'b00:{q3,q2,q1,q0} <= buf3_0;
|
||||
2'b01:{q3,q2,q1,q0} <= buf3_1;
|
||||
2'b10:{q3,q2,q1,q0} <= buf3_2;
|
||||
2'b11:{q3,q2,q1,q0} <= buf3_3;
|
||||
endcase
|
||||
default:if (DF_edge_counter_TD != 6'd48) {q3,q2,q1,q0} <= rec_DF_RAM_dout;
|
||||
else {q3,q2,q1,q0} <= 0;
|
||||
endcase
|
||||
|
||||
// |p0 - q0| < alpha
|
||||
assign absolute_TD0_a = (!disable_DF && bs_curr_TD != 0)? p0:0;
|
||||
assign absolute_TD0_b = (!disable_DF && bs_curr_TD != 0)? q0:0;
|
||||
|
||||
// |p1 - p0| < beta
|
||||
assign absolute_TD1_a = (!disable_DF && bs_curr_TD != 0)? p0:0;
|
||||
assign absolute_TD1_b = (!disable_DF && bs_curr_TD != 0)? p1:0;
|
||||
|
||||
// |q1 - q0| < beta
|
||||
assign absolute_TD2_a = (!disable_DF && bs_curr_TD != 0)? q0:0;
|
||||
assign absolute_TD2_b = (!disable_DF && bs_curr_TD != 0)? q1:0;
|
||||
|
||||
// Threshold
|
||||
wire threshold;
|
||||
assign threshold = ((absolute_TD0_out < alpha) && (absolute_TD1_out < beta) &&
|
||||
(absolute_TD2_out < beta))? 1'b1:1'b0;
|
||||
|
||||
// Pipelined parameters
|
||||
reg [2:0] bs_curr_PRE;
|
||||
reg [5:0] DF_edge_counter_PRE;
|
||||
reg [1:0] one_edge_counter_PRE;
|
||||
reg lumaEdgeFlag_PRE,chromaEdgeFlag_PRE;
|
||||
reg [7:0] p0_PRE,p1_PRE,p2_PRE,p3_PRE;
|
||||
reg [7:0] q0_PRE,q1_PRE,q2_PRE,q3_PRE;
|
||||
reg [5:0] indexA_PRE;
|
||||
reg [7:0] alpha_PRE,beta_PRE;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
bs_curr_PRE <= 0;
|
||||
DF_edge_counter_PRE <= 6'd48;
|
||||
one_edge_counter_PRE <= 2'd3;
|
||||
lumaEdgeFlag_PRE <= 0;
|
||||
chromaEdgeFlag_PRE <= 0;
|
||||
indexA_PRE <= 0;
|
||||
alpha_PRE <= 0;
|
||||
beta_PRE <= 0;
|
||||
p0_PRE <= 0; p1_PRE <= 0; p2_PRE <= 0; p3_PRE <= 0;
|
||||
q0_PRE <= 0; q1_PRE <= 0; q2_PRE <= 0; q3_PRE <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs_curr_PRE <= (threshold)? bs_curr_TD:0;
|
||||
DF_edge_counter_PRE <= DF_edge_counter_TD;
|
||||
one_edge_counter_PRE<= one_edge_counter_TD;
|
||||
lumaEdgeFlag_PRE <= (threshold)? lumaEdgeFlag_TD:0;
|
||||
chromaEdgeFlag_PRE <= (threshold)? chromaEdgeFlag_TD:0;
|
||||
indexA_PRE <= (threshold)? indexA:0;
|
||||
alpha_PRE <= (threshold)? alpha:0;
|
||||
beta_PRE <= (threshold)? beta:0;
|
||||
p0_PRE <= p0; p1_PRE <= p1; p2_PRE <= p2; p3_PRE <= p3;
|
||||
q0_PRE <= q0; q1_PRE <= q1; q2_PRE <= q2; q3_PRE <= q3;
|
||||
end
|
||||
//---------------------------------------------------------------------
|
||||
//3.PRE: Precomputation
|
||||
//---------------------------------------------------------------------
|
||||
wire [7:0] absolute_PRE0_a,absolute_PRE0_b;
|
||||
wire [7:0] absolute_PRE1_a,absolute_PRE1_b;
|
||||
wire [7:0] absolute_PRE2_a,absolute_PRE2_b;
|
||||
wire [7:0] absolute_PRE0_out,absolute_PRE1_out,absolute_PRE2_out;
|
||||
|
||||
absolute absolute_PRE0 (.a(absolute_PRE0_a),.b(absolute_PRE0_b),.out(absolute_PRE0_out));
|
||||
absolute absolute_PRE1 (.a(absolute_PRE1_a),.b(absolute_PRE1_b),.out(absolute_PRE1_out));
|
||||
absolute absolute_PRE2 (.a(absolute_PRE2_a),.b(absolute_PRE2_b),.out(absolute_PRE2_out));
|
||||
|
||||
// |p2 - p0| < beta
|
||||
assign absolute_PRE0_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p2_PRE:0;
|
||||
assign absolute_PRE0_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p0_PRE:0;
|
||||
|
||||
// |q2 - q0| < beta
|
||||
assign absolute_PRE1_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q2_PRE:0;
|
||||
assign absolute_PRE1_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q0_PRE:0;
|
||||
|
||||
// |p0 - q0| < alpha >> 2 + 2
|
||||
assign absolute_PRE2_a = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? p0_PRE:0;
|
||||
assign absolute_PRE2_b = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? q0_PRE:0;
|
||||
|
||||
wire p2_m_p0_less_beta,q2_m_q0_less_beta,p0_m_q0_less_alpha_shift;
|
||||
assign p2_m_p0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0:
|
||||
((absolute_PRE0_out < beta_PRE)? 1'b1:1'b0);
|
||||
assign q2_m_q0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0:
|
||||
((absolute_PRE1_out < beta_PRE)? 1'b1:1'b0);
|
||||
assign p0_m_q0_less_alpha_shift = (!lumaEdgeFlag_PRE || bs_curr_PRE != 4)? 1'b0:
|
||||
((absolute_PRE2_out < ((alpha_PRE >> 2) + 2))? 1'b1:1'b0);
|
||||
// bs = 1 ~ 3
|
||||
reg [4:0] c1;
|
||||
always @ (bs_curr_PRE or indexA_PRE)
|
||||
if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
|
||||
case (bs_curr_PRE)
|
||||
3'd1:
|
||||
if (indexA_PRE < 23) c1 <= 5'd0;
|
||||
else if (indexA_PRE < 33) c1 <= 5'd1;
|
||||
else if (indexA_PRE < 37) c1 <= 5'd2;
|
||||
else if (indexA_PRE < 40) c1 <= 5'd3;
|
||||
else if (indexA_PRE < 43) c1 <= 5'd4;
|
||||
else
|
||||
case (indexA_PRE)
|
||||
6'd43:c1 <= 5'd5; 6'd44,6'd45:c1 <= 5'd6;
|
||||
6'd46:c1 <= 5'd7; 6'd47:c1 <= 5'd8; 6'd48:c1 <= 5'd9;
|
||||
6'd49:c1 <= 5'd10; 6'd50:c1 <= 5'd11; 6'd51:c1 <= 5'd13;
|
||||
default:c1 <= 0;
|
||||
endcase
|
||||
3'd2:
|
||||
if (indexA_PRE < 21) c1 <= 5'd0;
|
||||
else if (indexA_PRE < 31) c1 <= 5'd1;
|
||||
else if (indexA_PRE < 35) c1 <= 5'd2;
|
||||
else if (indexA_PRE < 38) c1 <= 5'd3;
|
||||
else
|
||||
case (indexA_PRE)
|
||||
6'd38,6'd39:c1 <= 5'd4;
|
||||
6'd40,6'd41:c1 <= 5'd5;
|
||||
6'd42:c1 <= 5'd6; 6'd43:c1 <= 5'd7; 6'd44,6'd45:c1 <= 5'd8;
|
||||
6'd46:c1 <= 5'd10; 6'd47:c1 <= 5'd11; 6'd48:c1 <= 5'd12;
|
||||
6'd49:c1 <= 5'd13; 6'd50:c1 <= 5'd15; 6'd51:c1 <= 5'd17;
|
||||
default:c1 <= 5'd0;
|
||||
endcase
|
||||
3'd3:
|
||||
if (indexA_PRE < 17) c1 <= 5'd0;
|
||||
else if (indexA_PRE < 27) c1 <= 5'd1;
|
||||
else if (indexA_PRE < 31) c1 <= 5'd2;
|
||||
else if (indexA_PRE < 34) c1 <= 5'd3;
|
||||
else if (indexA_PRE < 37) c1 <= 5'd4;
|
||||
else
|
||||
case (indexA_PRE)
|
||||
6'd37:c1 <= 5'd5; 6'd38,6'd39:c1 <= 5'd6;
|
||||
6'd40:c1 <= 5'd7; 6'd41:c1 <= 5'd8; 6'd42:c1 <= 5'd9; 6'd43:c1 <= 5'd10;
|
||||
6'd44:c1 <= 5'd11; 6'd45:c1 <= 5'd13; 6'd46:c1 <= 5'd14; 6'd47:c1 <= 5'd16;
|
||||
6'd48:c1 <= 5'd18; 6'd49:c1 <= 5'd20; 6'd50:c1 <= 5'd23; 6'd51:c1 <= 5'd25;
|
||||
default:c1 <= 5'd0;
|
||||
endcase
|
||||
default:c1 <= 0;
|
||||
endcase
|
||||
else
|
||||
c1 <= 0;
|
||||
|
||||
reg [4:0] c0;
|
||||
always @ (bs_curr_PRE or lumaEdgeFlag_PRE or c1 or p2_m_p0_less_beta or q2_m_q0_less_beta)
|
||||
if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
|
||||
begin
|
||||
if (lumaEdgeFlag_PRE) //filter luma edge
|
||||
c0 <= ( p2_m_p0_less_beta && q2_m_q0_less_beta)? (c1 + 2):
|
||||
((!p2_m_p0_less_beta && !q2_m_q0_less_beta)? c1:(c1+1));
|
||||
else //filter chroma edge
|
||||
c0 <= c1 + 1;
|
||||
end
|
||||
else
|
||||
c0 <= 0;
|
||||
|
||||
//delta_0i = [(q0 - p0) << 2 + (p1 - q1) + 4] >> 3 : P151 (8-334) of H.264/AVC standard 2003
|
||||
wire [8:0] delta_0i;
|
||||
wire need_delta_0i;
|
||||
wire [8:0] q0_m_p0; //p0 - q0
|
||||
wire [11:0] delta_0i_tmp; //[(p0 - q0) << 2 + (p1 - q1) + 4]
|
||||
assign need_delta_0i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4);
|
||||
assign q0_m_p0 = (need_delta_0i)? ({1'b0,q0_PRE} + {1'b1,~p0_PRE} + 1):0;
|
||||
assign delta_0i_tmp = (need_delta_0i)? ({q0_m_p0[8],q0_m_p0,2'b0} + p1_PRE + {4'b1111,~q1_PRE} + 5):0;
|
||||
assign delta_0i = delta_0i_tmp[11:3];
|
||||
|
||||
|
||||
//delta p1i = [(p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)] >> 1 : P152 (8-341) of H.264/AVC standard 2003
|
||||
//delta q1i = [(q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)] >> 1 : P152 (8-343) of H.264/AVC standard 2003
|
||||
wire [8:0] delta_p1i,delta_q1i;
|
||||
wire need_p1i;
|
||||
wire need_q1i;
|
||||
wire [8:0] p0_q0_sum; //p0+q0+1
|
||||
wire [9:0] neg_p1_shift; //-(p1 << 1)
|
||||
wire [9:0] neg_q1_shift; //-(q1 << 1)
|
||||
wire [9:0] delta_p1i_tmp;// (p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)
|
||||
wire [9:0] delta_q1i_tmp;// (q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)
|
||||
assign need_p1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta);
|
||||
assign need_q1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta);
|
||||
assign p0_q0_sum = (need_p1i || need_q1i)? ({1'b0,p0_PRE} + {1'b0,q0_PRE} + 1):0;
|
||||
assign neg_p1_shift = (need_p1i)? ({1'b1,~p1_PRE,1'b1} + 1):0;
|
||||
assign neg_q1_shift = (need_q1i)? ({1'b1,~q1_PRE,1'b1} + 1):0;
|
||||
assign delta_p1i_tmp = (need_p1i)? (p2_PRE + p0_q0_sum[8:1] + neg_p1_shift):0;
|
||||
assign delta_q1i_tmp = (need_q1i)? (q2_PRE + p0_q0_sum[8:1] + neg_q1_shift):0;
|
||||
assign delta_p1i = delta_p1i_tmp[9:1];
|
||||
assign delta_q1i = delta_q1i_tmp[9:1];
|
||||
|
||||
wire [8:0] clip_to_c_0_delta,clip_to_c_p1_delta,clip_to_c_q1_delta;
|
||||
wire [4:0] clip_to_c_0_c,clip_to_c_p1_c,clip_to_c_q1_c;
|
||||
wire [5:0] clip_to_c_0_out,clip_to_c_p1_out,clip_to_c_q1_out;
|
||||
clip_to_c clip_to_c_0 (.delta(clip_to_c_0_delta),.c(clip_to_c_0_c),.out(clip_to_c_0_out));
|
||||
clip_to_c clip_to_c_p1 (.delta(clip_to_c_p1_delta),.c(clip_to_c_p1_c),.out(clip_to_c_p1_out));
|
||||
clip_to_c clip_to_c_q1 (.delta(clip_to_c_q1_delta),.c(clip_to_c_q1_c),.out(clip_to_c_q1_out));
|
||||
|
||||
assign clip_to_c_0_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? delta_0i:0;
|
||||
assign clip_to_c_0_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? c0:0;
|
||||
assign clip_to_c_p1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? delta_p1i:0;
|
||||
assign clip_to_c_p1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? c1:0;
|
||||
assign clip_to_c_q1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? delta_q1i:0;
|
||||
assign clip_to_c_q1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? c1:0;
|
||||
|
||||
// Pipelined parameters
|
||||
reg [5:0] delta_0,delta_p1,delta_q1;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin delta_0 <= 0; delta_p1 <= 0; delta_q1 <= 0; end
|
||||
else if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)
|
||||
begin
|
||||
delta_0 <= clip_to_c_0_out;
|
||||
delta_p1 <= (p2_m_p0_less_beta)? clip_to_c_p1_out:0;
|
||||
delta_q1 <= (q2_m_q0_less_beta)? clip_to_c_q1_out:0;
|
||||
end
|
||||
|
||||
reg p2_m_p0_less_beta_FIR,q2_m_q0_less_beta_FIR,p0_m_q0_less_alpha_shift_FIR;
|
||||
reg lumaEdgeFlag_FIR,chromaEdgeFlag_FIR;
|
||||
reg [2:0] bs_curr_FIR;
|
||||
reg [5:0] DF_edge_counter_FIR;
|
||||
reg [1:0] one_edge_counter_FIR;
|
||||
reg [7:0] p0_FIR,p1_FIR,p2_FIR,p3_FIR;
|
||||
reg [7:0] q0_FIR,q1_FIR,q2_FIR,q3_FIR;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
p2_m_p0_less_beta_FIR <= 0; q2_m_q0_less_beta_FIR <= 0;
|
||||
p0_m_q0_less_alpha_shift_FIR <= 0;
|
||||
bs_curr_FIR <= 0;
|
||||
lumaEdgeFlag_FIR <= 0; chromaEdgeFlag_FIR <= 0;
|
||||
DF_edge_counter_FIR <= 6'd48; one_edge_counter_FIR <= 2'd3;
|
||||
p0_FIR <= 0; p1_FIR <= 0; p2_FIR <= 0; p3_FIR <= 0;
|
||||
q0_FIR <= 0; q1_FIR <= 0; q2_FIR <= 0; q3_FIR <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
p2_m_p0_less_beta_FIR <= p2_m_p0_less_beta;
|
||||
q2_m_q0_less_beta_FIR <= q2_m_q0_less_beta;
|
||||
p0_m_q0_less_alpha_shift_FIR <= p0_m_q0_less_alpha_shift;
|
||||
bs_curr_FIR <= bs_curr_PRE;
|
||||
lumaEdgeFlag_FIR <= lumaEdgeFlag_PRE; chromaEdgeFlag_FIR <= chromaEdgeFlag_PRE;
|
||||
DF_edge_counter_FIR <= DF_edge_counter_PRE; one_edge_counter_FIR <= one_edge_counter_PRE;
|
||||
p0_FIR <= p0_PRE; p1_FIR <= p1_PRE; p2_FIR <= p2_PRE; p3_FIR <= p3_PRE;
|
||||
q0_FIR <= q0_PRE; q1_FIR <= q1_PRE; q2_FIR <= q2_PRE; q3_FIR <= q3_PRE;
|
||||
end
|
||||
//---------------------------------------------------------------------
|
||||
//4.FIR: filtering
|
||||
//---------------------------------------------------------------------
|
||||
reg [7:0] bs4_strong_FIR_p0,bs4_strong_FIR_p1,bs4_strong_FIR_p2,bs4_strong_FIR_p3;
|
||||
reg [7:0] bs4_strong_FIR_q0,bs4_strong_FIR_q1,bs4_strong_FIR_q2,bs4_strong_FIR_q3;
|
||||
wire [7:0] bs4_strong_FIR_p0_out,bs4_strong_FIR_p1_out,bs4_strong_FIR_p2_out;
|
||||
wire [7:0] bs4_strong_FIR_q0_out,bs4_strong_FIR_q1_out,bs4_strong_FIR_q2_out;
|
||||
bs4_strong_FIR bs4_strong_FIR (
|
||||
.p0(bs4_strong_FIR_p0),.p1(bs4_strong_FIR_p1),.p2(bs4_strong_FIR_p2),.p3(bs4_strong_FIR_p3),
|
||||
.q0(bs4_strong_FIR_q0),.q1(bs4_strong_FIR_q1),.q2(bs4_strong_FIR_q2),.q3(bs4_strong_FIR_q3),
|
||||
.p0_out(bs4_strong_FIR_p0_out),.p1_out(bs4_strong_FIR_p1_out),.p2_out(bs4_strong_FIR_p2_out),
|
||||
.q0_out(bs4_strong_FIR_q0_out),.q1_out(bs4_strong_FIR_q1_out),.q2_out(bs4_strong_FIR_q2_out)
|
||||
);
|
||||
reg [7:0] bs4_weak_FIR0_a,bs4_weak_FIR0_b,bs4_weak_FIR0_c;
|
||||
reg [7:0] bs4_weak_FIR1_a,bs4_weak_FIR1_b,bs4_weak_FIR1_c;
|
||||
wire [7:0] bs4_weak_FIR0_out,bs4_weak_FIR1_out;
|
||||
bs4_weak_FIR bs4_weak_FIR0 (.a(bs4_weak_FIR0_a),.b(bs4_weak_FIR0_b),.c(bs4_weak_FIR0_c),.out(bs4_weak_FIR0_out));
|
||||
bs4_weak_FIR bs4_weak_FIR1 (.a(bs4_weak_FIR1_a),.b(bs4_weak_FIR1_b),.c(bs4_weak_FIR1_c),.out(bs4_weak_FIR1_out));
|
||||
// bs = 4
|
||||
always @ (bs_curr_FIR or lumaEdgeFlag_FIR or p0_m_q0_less_alpha_shift_FIR
|
||||
or p2_m_p0_less_beta_FIR or q2_m_q0_less_beta_FIR
|
||||
or p0_FIR or p1_FIR or p2_FIR or p3_FIR or q0_FIR or q1_FIR or q2_FIR or q3_FIR)
|
||||
if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1 && p0_m_q0_less_alpha_shift_FIR
|
||||
&& (p2_m_p0_less_beta_FIR || q2_m_q0_less_beta_FIR))
|
||||
begin
|
||||
bs4_strong_FIR_p0 <= p0_FIR; bs4_strong_FIR_p1 <= p1_FIR;
|
||||
bs4_strong_FIR_p2 <= p2_FIR; bs4_strong_FIR_p3 <= p3_FIR;
|
||||
bs4_strong_FIR_q0 <= q0_FIR; bs4_strong_FIR_q1 <= q1_FIR;
|
||||
bs4_strong_FIR_q2 <= q2_FIR; bs4_strong_FIR_q3 <= q3_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs4_strong_FIR_p0 <= 0; bs4_strong_FIR_p1 <= 0; bs4_strong_FIR_p2 <= 0; bs4_strong_FIR_p3 <= 0;
|
||||
bs4_strong_FIR_q0 <= 0; bs4_strong_FIR_q1 <= 0; bs4_strong_FIR_q2 <= 0; bs4_strong_FIR_q3 <= 0;
|
||||
end
|
||||
always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR
|
||||
or p2_m_p0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR
|
||||
or p1_FIR or p0_FIR or q1_FIR)
|
||||
if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1)
|
||||
begin
|
||||
if (!p2_m_p0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR)
|
||||
begin
|
||||
bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0;
|
||||
end
|
||||
end
|
||||
else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1)
|
||||
begin
|
||||
bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0;
|
||||
end
|
||||
always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR
|
||||
or q2_m_q0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR
|
||||
or q1_FIR or q0_FIR or p1_FIR)
|
||||
if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1)
|
||||
begin
|
||||
if (!q2_m_q0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR)
|
||||
begin
|
||||
bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0;
|
||||
end
|
||||
end
|
||||
else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1)
|
||||
begin
|
||||
bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0;
|
||||
end
|
||||
//bs = 1 ~ 3,for p0 and q0 filtering
|
||||
wire [9:0] p0_MW_tmp,q0_MW_tmp;
|
||||
wire [7:0] p0_MW_clipped,q0_MW_clipped;
|
||||
assign p0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,p0_FIR} + {{4{delta_0[5]}},delta_0}):0;
|
||||
assign q0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,q0_FIR} +
|
||||
{~delta_0[5],~delta_0[5],~delta_0[5],~delta_0[5],~delta_0} + 1):0;
|
||||
assign p0_MW_clipped = (p0_MW_tmp[9] == 1'b1)? 0:((p0_MW_tmp[8] == 1'b1)? 8'd255:p0_MW_tmp[7:0]);
|
||||
assign q0_MW_clipped = (q0_MW_tmp[9] == 1'b1)? 0:((q0_MW_tmp[8] == 1'b1)? 8'd255:q0_MW_tmp[7:0]);
|
||||
|
||||
// Pipelined parameters
|
||||
reg [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
|
||||
reg [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
p0_MW <= 0; p1_MW <= 0; p2_MW <= 0;
|
||||
q0_MW <= 0; q1_MW <= 0; q2_MW <= 0;
|
||||
end
|
||||
else if (bs_curr_FIR == 3'd4)
|
||||
begin
|
||||
if (lumaEdgeFlag_FIR)
|
||||
begin
|
||||
p0_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)?
|
||||
bs4_strong_FIR_p0_out:bs4_weak_FIR0_out;
|
||||
q0_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)?
|
||||
bs4_strong_FIR_q0_out:bs4_weak_FIR1_out;
|
||||
p1_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)?
|
||||
bs4_strong_FIR_p1_out:p1_FIR;
|
||||
q1_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)?
|
||||
bs4_strong_FIR_q1_out:q1_FIR;
|
||||
p2_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)?
|
||||
bs4_strong_FIR_p2_out:p2_FIR;
|
||||
q2_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)?
|
||||
bs4_strong_FIR_q2_out:q2_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
p0_MW <= bs4_weak_FIR0_out; q0_MW <= bs4_weak_FIR1_out;
|
||||
p1_MW <= p1_FIR; q1_MW <= q1_FIR;
|
||||
p2_MW <= p2_FIR; q2_MW <= q2_FIR;
|
||||
end
|
||||
end
|
||||
else if (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)
|
||||
begin
|
||||
p0_MW <= p0_MW_clipped;
|
||||
q0_MW <= q0_MW_clipped;
|
||||
p1_MW <= (lumaEdgeFlag_FIR)? ((p2_m_p0_less_beta_FIR)? (p1_FIR + {delta_p1[5],delta_p1[5],delta_p1}):p1_FIR):p1_FIR;
|
||||
q1_MW <= (lumaEdgeFlag_FIR)? ((q2_m_q0_less_beta_FIR)? (q1_FIR + {delta_q1[5],delta_q1[5],delta_q1}):q1_FIR):q1_FIR;
|
||||
p2_MW <= p2_FIR;
|
||||
q2_MW <= q2_FIR;
|
||||
end
|
||||
else
|
||||
begin
|
||||
p0_MW <= p0_FIR; p1_MW <= p1_FIR; p2_MW <= p2_FIR;
|
||||
q0_MW <= q0_FIR; q1_MW <= q1_FIR; q2_MW <= q2_FIR;
|
||||
end
|
||||
|
||||
reg [2:0] bs_curr_MW;
|
||||
reg [5:0] DF_edge_counter_MW;
|
||||
reg [1:0] one_edge_counter_MW;
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
DF_edge_counter_MW <= 6'd48; one_edge_counter_MW <= 2'd3;
|
||||
p3_MW <= 0; q3_MW <= 0;
|
||||
bs_curr_MW <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DF_edge_counter_MW <= DF_edge_counter_FIR; p3_MW <= p3_FIR;
|
||||
one_edge_counter_MW <= one_edge_counter_FIR; q3_MW <= q3_FIR;
|
||||
bs_curr_MW <= bs_curr_FIR;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module absolute (a,b,out);
|
||||
input [7:0] a,b;
|
||||
output [7:0] out;
|
||||
|
||||
assign out = (a > b)? (a - b):(b - a);
|
||||
endmodule
|
||||
|
||||
module clip_to_c (delta,c,out);
|
||||
input [8:0] delta;
|
||||
input [4:0] c; // 0 ~ 25, [4:0]
|
||||
output [5:0] out; // -25 ~ 25, [5:0]
|
||||
reg [5:0] out;
|
||||
|
||||
wire [5:0] neg_c; //-25 ~ 25,[5:0]
|
||||
assign neg_c = {1'b1,~c} + 1;
|
||||
|
||||
always @ (delta or c or neg_c)
|
||||
if (delta[8] == 1'b0) //delta is positive
|
||||
out <= (delta[7:0] > {3'b0,c})? {1'b0,c}:delta[5:0];
|
||||
else //delta is negtive
|
||||
out <= (delta[7:0] < {2'b11,neg_c})? {1'b1,neg_c}:delta[5:0];
|
||||
endmodule
|
||||
|
||||
module bs4_strong_FIR (p0,p1,p2,p3,q0,q1,q2,q3,p0_out,p1_out,p2_out,q0_out,q1_out,q2_out);
|
||||
input [7:0] p0,p1,p2,p3,q0,q1,q2,q3;
|
||||
output [7:0] p0_out,p1_out,p2_out,q0_out,q1_out,q2_out;
|
||||
|
||||
wire [8:0] sum_p2p3,sum_p1p2,sum_p0q0,sum_p1q1,sum_q1q2,sum_q2q3;
|
||||
assign sum_p2p3 = p2 + p3;
|
||||
assign sum_p1p2 = p1 + p2;
|
||||
assign sum_p0q0 = p0 + q0;
|
||||
assign sum_p1q1 = p1 + q1;
|
||||
assign sum_q1q2 = q1 + q2;
|
||||
assign sum_q2q3 = q2 + q3;
|
||||
|
||||
wire [9:0] sum_p2p3_x2,sum_q2q3_x2;
|
||||
assign sum_p2p3_x2 = {sum_p2p3,1'b0};
|
||||
assign sum_q2q3_x2 = {sum_q2q3,1'b0};
|
||||
|
||||
wire [9:0] sum_0,sum_1,sum_2;
|
||||
assign sum_0 = sum_p0q0 + sum_p1p2;
|
||||
assign sum_1 = sum_p0q0 + sum_p1q1;
|
||||
assign sum_2 = sum_p0q0 + sum_q1q2;
|
||||
|
||||
wire [10:0] p0_tmp,p2_tmp,q0_tmp,q2_tmp;
|
||||
assign p0_tmp = sum_0 + sum_1;
|
||||
assign p2_tmp = sum_p2p3_x2 + sum_0;
|
||||
assign q0_tmp = sum_1 + sum_2;
|
||||
assign q2_tmp = sum_q2q3_x2 + sum_2;
|
||||
|
||||
assign p0_out = (p0_tmp + 4) >> 3;
|
||||
assign p1_out = (sum_0 + 2) >> 2;
|
||||
assign p2_out = (p2_tmp + 4) >> 3;
|
||||
assign q0_out = (q0_tmp + 4) >> 3;
|
||||
assign q1_out = (sum_2 + 2) >> 2;
|
||||
assign q2_out = (q2_tmp + 4) >> 3;
|
||||
endmodule
|
||||
|
||||
module bs4_weak_FIR (a,b,c,out);
|
||||
input [7:0] a,b,c;
|
||||
output [7:0] out;
|
||||
|
||||
wire [8:0] a_x2;
|
||||
assign a_x2 = {a,1'b0};
|
||||
|
||||
wire [8:0] sum_bc;
|
||||
assign sum_bc = b + c;
|
||||
|
||||
wire [9:0] out_tmp;
|
||||
assign out_tmp = (a_x2 + sum_bc) + 2;
|
||||
assign out = out_tmp[9:2];
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,335 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : DF_reg_ctrl.v
|
||||
// Generated : Nov 27,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// buffer buf0 ~ buf3 & transpose reg t0 ~ t1 control
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module DF_reg_ctrl (gclk_DF,reset_n,DF_edge_counter_MW,one_edge_counter_MW,
|
||||
mb_num_h_DF,mb_num_v_DF,q0_MW,q1_MW,q2_MW,q3_MW,p0_MW,p1_MW,p2_MW,p3_MW,
|
||||
buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3,
|
||||
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3,
|
||||
t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3);
|
||||
input gclk_DF,reset_n;
|
||||
input [5:0] DF_edge_counter_MW;
|
||||
input [1:0] one_edge_counter_MW;
|
||||
input [3:0] mb_num_h_DF;
|
||||
input [3:0] mb_num_v_DF;
|
||||
input [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
|
||||
input [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
|
||||
|
||||
output [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
|
||||
output [31:0] buf1_0,buf1_1,buf1_2,buf1_3;
|
||||
output [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
|
||||
output [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
|
||||
output [31:0] t0_0,t0_1,t0_2,t0_3;
|
||||
output [31:0] t1_0,t1_1,t1_2,t1_3;
|
||||
output [31:0] t2_0,t2_1,t2_2,t2_3;
|
||||
|
||||
reg [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
|
||||
reg [31:0] buf1_0,buf1_1,buf1_2,buf1_3;
|
||||
reg [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
|
||||
reg [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
|
||||
reg [31:0] t0_0,t0_1,t0_2,t0_3;
|
||||
reg [31:0] t1_0,t1_1,t1_2,t1_3;
|
||||
reg [31:0] t2_0,t2_1,t2_2,t2_3;
|
||||
//------------------------------------------------------
|
||||
//buf0
|
||||
//------------------------------------------------------
|
||||
wire buf0_no_transpose; //buf0 updated without transpose
|
||||
wire buf0_transpose; //buf0 updated after transpose
|
||||
assign buf0_no_transpose = (
|
||||
DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd6 ||
|
||||
DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd20 ||
|
||||
DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd32 ||
|
||||
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd44);
|
||||
assign buf0_transpose = (
|
||||
DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd10 ||
|
||||
DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd26 ||
|
||||
DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd38 ||
|
||||
DF_edge_counter_MW == 6'd41 || DF_edge_counter_MW == 6'd46);
|
||||
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
buf0_0 <= 0; buf0_1 <= 0; buf0_2 <= 0; buf0_3 <= 0;
|
||||
end
|
||||
//no transpose update,always "q" position (right or down of the edge to be filtered)
|
||||
else if (buf0_no_transpose)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:buf0_0 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd1:buf0_1 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd2:buf0_2 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd3:buf0_3 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
endcase
|
||||
//transpose update,always "p" position (left or up of the edge to be filtered)
|
||||
else if (buf0_transpose)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf0_0[7:0] <= p3_MW; buf0_1[7:0] <= p2_MW;
|
||||
buf0_2[7:0] <= p1_MW; buf0_3[7:0] <= p0_MW; end
|
||||
2'd1:begin buf0_0[15:8] <= p3_MW; buf0_1[15:8] <= p2_MW;
|
||||
buf0_2[15:8] <= p1_MW; buf0_3[15:8] <= p0_MW; end
|
||||
2'd2:begin buf0_0[23:16] <= p3_MW; buf0_1[23:16] <= p2_MW;
|
||||
buf0_2[23:16] <= p1_MW; buf0_3[23:16] <= p0_MW; end
|
||||
2'd3:begin buf0_0[31:24] <= p3_MW; buf0_1[31:24] <= p2_MW;
|
||||
buf0_2[31:24] <= p1_MW; buf0_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
//------------------------------------------------------
|
||||
//buf1
|
||||
//------------------------------------------------------
|
||||
wire buf1_no_transpose; //buf1 updated without transpose
|
||||
wire buf1_transpose; //buf1 updated after transpose
|
||||
wire buf1_transpose_p; //buf1 transpose and buf1 stores "p" position pixels
|
||||
assign buf1_no_transpose = (
|
||||
DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd13 ||
|
||||
DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd24 || DF_edge_counter_MW == 6'd29 ||
|
||||
DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45);
|
||||
assign buf1_transpose = (
|
||||
DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd22 ||
|
||||
DF_edge_counter_MW == 6'd26 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd41);
|
||||
assign buf1_transpose_p = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd9
|
||||
|| DF_edge_counter_MW == 6'd22);
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
buf1_0 <= 0; buf1_1 <= 0; buf1_2 <= 0; buf1_3 <= 0;
|
||||
end
|
||||
//no transpose update,always "q" position (right or down of the edge to be filtered)
|
||||
else if (buf1_no_transpose)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:buf1_0 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd1:buf1_1 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd2:buf1_2 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd3:buf1_3 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
endcase
|
||||
//transpose update,"p":6/9/22,"q":10,26,33,41
|
||||
else if (buf1_transpose)
|
||||
begin
|
||||
if (buf1_transpose_p) // edge 6,22 "p"
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf1_0[7:0] <= p3_MW; buf1_1[7:0] <= p2_MW;
|
||||
buf1_2[7:0] <= p1_MW; buf1_3[7:0] <= p0_MW; end
|
||||
2'd1:begin buf1_0[15:8] <= p3_MW; buf1_1[15:8] <= p2_MW;
|
||||
buf1_2[15:8] <= p1_MW; buf1_3[15:8] <= p0_MW; end
|
||||
2'd2:begin buf1_0[23:16] <= p3_MW; buf1_1[23:16] <= p2_MW;
|
||||
buf1_2[23:16] <= p1_MW; buf1_3[23:16] <= p0_MW; end
|
||||
2'd3:begin buf1_0[31:24] <= p3_MW; buf1_1[31:24] <= p2_MW;
|
||||
buf1_2[31:24] <= p1_MW; buf1_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
else //edge 10,26,33,41 "q"
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf1_0[7:0] <= q0_MW; buf1_1[7:0] <= q1_MW;
|
||||
buf1_2[7:0] <= q2_MW; buf1_3[7:0] <= q3_MW; end
|
||||
2'd1:begin buf1_0[15:8] <= q0_MW; buf1_1[15:8] <= q1_MW;
|
||||
buf1_2[15:8] <= q2_MW; buf1_3[15:8] <= q3_MW; end
|
||||
2'd2:begin buf1_0[23:16] <= q0_MW; buf1_1[23:16] <= q1_MW;
|
||||
buf1_2[23:16] <= q2_MW; buf1_3[23:16] <= q3_MW; end
|
||||
2'd3:begin buf1_0[31:24] <= q0_MW; buf1_1[31:24] <= q1_MW;
|
||||
buf1_2[31:24] <= q2_MW; buf1_3[31:24] <= q3_MW; end
|
||||
endcase
|
||||
end
|
||||
//------------------------------------------------------
|
||||
//buf2
|
||||
//------------------------------------------------------
|
||||
wire buf2_no_transpose; //buf2 updated without transpose
|
||||
wire buf2_transpose; //buf2 updated after transpose
|
||||
wire buf2_transpose_p; //buf2 transpose and buf2 stores "p" position pixels
|
||||
assign buf2_no_transpose = (
|
||||
DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd18 ||
|
||||
DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42);
|
||||
assign buf2_transpose = (
|
||||
DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd19 ||
|
||||
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 ||
|
||||
DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd43 ||
|
||||
DF_edge_counter_MW == 6'd46);
|
||||
assign buf2_transpose_p = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11
|
||||
|| DF_edge_counter_MW == 6'd19 || DF_edge_counter_MW == 6'd27
|
||||
|| DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43);
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
buf2_0 <= 0; buf2_1 <= 0; buf2_2 <= 0; buf2_3 <= 0;
|
||||
end
|
||||
//no transpose update,always "q" position (right or down of the edge to be filtered)
|
||||
else if (buf2_no_transpose)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:buf2_0 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd1:buf2_1 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd2:buf2_2 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd3:buf2_3 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
endcase
|
||||
//transpose update,"p":3,11,19,27,35,43 "q":21,30,38,46
|
||||
else if (buf2_transpose)
|
||||
begin
|
||||
if (buf2_transpose_p) //"p":3,11,19,27,35,43
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf2_0[7:0] <= p3_MW; buf2_1[7:0] <= p2_MW;
|
||||
buf2_2[7:0] <= p1_MW; buf2_3[7:0] <= p0_MW; end
|
||||
2'd1:begin buf2_0[15:8] <= p3_MW; buf2_1[15:8] <= p2_MW;
|
||||
buf2_2[15:8] <= p1_MW; buf2_3[15:8] <= p0_MW; end
|
||||
2'd2:begin buf2_0[23:16] <= p3_MW; buf2_1[23:16] <= p2_MW;
|
||||
buf2_2[23:16] <= p1_MW; buf2_3[23:16] <= p0_MW; end
|
||||
2'd3:begin buf2_0[31:24] <= p3_MW; buf2_1[31:24] <= p2_MW;
|
||||
buf2_2[31:24] <= p1_MW; buf2_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
else //"q":21,30,38,46
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf2_0[7:0] <= q0_MW; buf2_1[7:0] <= q1_MW;
|
||||
buf2_2[7:0] <= q2_MW; buf2_3[7:0] <= q3_MW; end
|
||||
2'd1:begin buf2_0[15:8] <= q0_MW; buf2_1[15:8] <= q1_MW;
|
||||
buf2_2[15:8] <= q2_MW; buf2_3[15:8] <= q3_MW; end
|
||||
2'd2:begin buf2_0[23:16] <= q0_MW; buf2_1[23:16] <= q1_MW;
|
||||
buf2_2[23:16] <= q2_MW; buf2_3[23:16] <= q3_MW; end
|
||||
2'd3:begin buf2_0[31:24] <= q0_MW; buf2_1[31:24] <= q1_MW;
|
||||
buf2_2[31:24] <= q2_MW; buf2_3[31:24] <= q3_MW; end
|
||||
endcase
|
||||
end
|
||||
//------------------------------------------------------
|
||||
//buf3
|
||||
//------------------------------------------------------
|
||||
wire buf3_no_transpose; //buf3 updated without transpose
|
||||
wire buf3_transpose; //buf3 updated after transpose
|
||||
wire buf3_transpose_p; //buf3 transpose and buf1 stores "p" position pixels
|
||||
assign buf3_no_transpose = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd19);
|
||||
assign buf3_transpose = ( DF_edge_counter_MW == 6'd7 ||
|
||||
DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd27 ||
|
||||
DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43);
|
||||
assign buf3_transpose_p = (DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd23);
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
buf3_0 <= 0; buf3_1 <= 0; buf3_2 <= 0; buf3_3 <= 0;
|
||||
end
|
||||
//no transpose update,always "q" position (right or down of the edge to be filtered)
|
||||
else if (buf3_no_transpose)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:buf3_0 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd1:buf3_1 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd2:buf3_2 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
2'd3:buf3_3 <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
||||
endcase
|
||||
//transpose update,"p":7,23 "q":11,25,27,35,43
|
||||
else if (buf3_transpose)
|
||||
begin
|
||||
if (buf3_transpose_p) //"p":7,23
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf3_0[7:0] <= p3_MW; buf3_1[7:0] <= p2_MW;
|
||||
buf3_2[7:0] <= p1_MW; buf3_3[7:0] <= p0_MW; end
|
||||
2'd1:begin buf3_0[15:8] <= p3_MW; buf3_1[15:8] <= p2_MW;
|
||||
buf3_2[15:8] <= p1_MW; buf3_3[15:8] <= p0_MW; end
|
||||
2'd2:begin buf3_0[23:16] <= p3_MW; buf3_1[23:16] <= p2_MW;
|
||||
buf3_2[23:16] <= p1_MW; buf3_3[23:16] <= p0_MW; end
|
||||
2'd3:begin buf3_0[31:24] <= p3_MW; buf3_1[31:24] <= p2_MW;
|
||||
buf3_2[31:24] <= p1_MW; buf3_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
else //"q":11,25,35,43
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin buf3_0[7:0] <= q0_MW; buf3_1[7:0] <= q1_MW;
|
||||
buf3_2[7:0] <= q2_MW; buf3_3[7:0] <= q3_MW; end
|
||||
2'd1:begin buf3_0[15:8] <= q0_MW; buf3_1[15:8] <= q1_MW;
|
||||
buf3_2[15:8] <= q2_MW; buf3_3[15:8] <= q3_MW; end
|
||||
2'd2:begin buf3_0[23:16] <= q0_MW; buf3_1[23:16] <= q1_MW;
|
||||
buf3_2[23:16] <= q2_MW; buf3_3[23:16] <= q3_MW; end
|
||||
2'd3:begin buf3_0[31:24] <= q0_MW; buf3_1[31:24] <= q1_MW;
|
||||
buf3_2[31:24] <= q2_MW; buf3_3[31:24] <= q3_MW; end
|
||||
endcase
|
||||
end
|
||||
//------------------------------------------------------
|
||||
//T0:always updated after transpose,always "p" position
|
||||
//------------------------------------------------------
|
||||
wire t0_transpose; //t0 updated after transpose
|
||||
assign t0_transpose = (
|
||||
DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd36 ||
|
||||
DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd15 || DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd24 ||
|
||||
DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47);
|
||||
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
t0_0 <= 0; t0_1 <= 0; t0_2 <= 0; t0_3 <= 0;
|
||||
end
|
||||
//always transpose update for "p" position
|
||||
else if (t0_transpose)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin t0_0[7:0] <= p3_MW; t0_1[7:0] <= p2_MW;
|
||||
t0_2[7:0] <= p1_MW; t0_3[7:0] <= p0_MW; end
|
||||
2'd1:begin t0_0[15:8] <= p3_MW; t0_1[15:8] <= p2_MW;
|
||||
t0_2[15:8] <= p1_MW; t0_3[15:8] <= p0_MW; end
|
||||
2'd2:begin t0_0[23:16] <= p3_MW; t0_1[23:16] <= p2_MW;
|
||||
t0_2[23:16] <= p1_MW; t0_3[23:16] <= p0_MW; end
|
||||
2'd3:begin t0_0[31:24] <= p3_MW; t0_1[31:24] <= p2_MW;
|
||||
t0_2[31:24] <= p1_MW; t0_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
//------------------------------------------------------
|
||||
//T1:always updated after transpose
|
||||
//------------------------------------------------------
|
||||
wire t1_transpose; //t1 updated after transpose
|
||||
wire t1_transpose_q; //t1 transpose and t1 stores "q" position pixels
|
||||
assign t1_transpose = (
|
||||
DF_edge_counter_MW == 6'd13 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd9 ||
|
||||
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd31 ||
|
||||
DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47);
|
||||
|
||||
assign t1_transpose_q = (DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 ||
|
||||
DF_edge_counter_MW == 6'd47);
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
t1_0 <= 0; t1_1 <= 0; t1_2 <= 0; t1_3 <= 0;
|
||||
end
|
||||
else if (t1_transpose && !t1_transpose_q) //t1 transpose "p"
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin t1_0[7:0] <= p3_MW; t1_1[7:0] <= p2_MW;
|
||||
t1_2[7:0] <= p1_MW; t1_3[7:0] <= p0_MW; end
|
||||
2'd1:begin t1_0[15:8] <= p3_MW; t1_1[15:8] <= p2_MW;
|
||||
t1_2[15:8] <= p1_MW; t1_3[15:8] <= p0_MW; end
|
||||
2'd2:begin t1_0[23:16] <= p3_MW; t1_1[23:16] <= p2_MW;
|
||||
t1_2[23:16] <= p1_MW; t1_3[23:16] <= p0_MW; end
|
||||
2'd3:begin t1_0[31:24] <= p3_MW; t1_1[31:24] <= p2_MW;
|
||||
t1_2[31:24] <= p1_MW; t1_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
else if (t1_transpose) //t1 transpose "q"
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin t1_0[7:0] <= q0_MW; t1_1[7:0] <= q1_MW;
|
||||
t1_2[7:0] <= q2_MW; t1_3[7:0] <= q3_MW; end
|
||||
2'd1:begin t1_0[15:8] <= q0_MW; t1_1[15:8] <= q1_MW;
|
||||
t1_2[15:8] <= q2_MW; t1_3[15:8] <= q3_MW; end
|
||||
2'd2:begin t1_0[23:16] <= q0_MW; t1_1[23:16] <= q1_MW;
|
||||
t1_2[23:16] <= q2_MW; t1_3[23:16] <= q3_MW; end
|
||||
2'd3:begin t1_0[31:24] <= q0_MW; t1_1[31:24] <= q1_MW;
|
||||
t1_2[31:24] <= q2_MW; t1_3[31:24] <= q3_MW; end
|
||||
endcase
|
||||
//--------------------------------------------------------------------
|
||||
//T2:only used after filter edge 18/34/42 to update mbAddrB of left MB
|
||||
//--------------------------------------------------------------------
|
||||
wire t2_wr;
|
||||
assign t2_wr = ((mb_num_h_DF != 0 && mb_num_v_DF != 4'd8) &&
|
||||
(DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42));
|
||||
always @ (posedge gclk_DF or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
t2_0 <= 0; t2_1 <= 0; t2_2 <= 0; t2_3 <= 0;
|
||||
end
|
||||
else if (t2_wr)
|
||||
case (one_edge_counter_MW)
|
||||
2'd0:begin t2_0[7:0] <= p3_MW; t2_1[7:0] <= p2_MW;
|
||||
t2_2[7:0] <= p1_MW; t2_3[7:0] <= p0_MW; end
|
||||
2'd1:begin t2_0[15:8] <= p3_MW; t2_1[15:8] <= p2_MW;
|
||||
t2_2[15:8] <= p1_MW; t2_3[15:8] <= p0_MW; end
|
||||
2'd2:begin t2_0[23:16] <= p3_MW; t2_1[23:16] <= p2_MW;
|
||||
t2_2[23:16] <= p1_MW; t2_3[23:16] <= p0_MW; end
|
||||
2'd3:begin t2_0[31:24] <= p3_MW; t2_1[31:24] <= p2_MW;
|
||||
t2_2[31:24] <= p1_MW; t2_3[31:24] <= p0_MW; end
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,205 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : DF_top.v
|
||||
// Generated : Dec 30, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Top module of deblocking filter
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module DF_top (clk,reset_n,gclk_DF,gclk_end_of_MB_DEC,gclk_DF_mbAddrA_RF,gclk_DF_mbAddrB_RAM,
|
||||
end_of_BS_DEC,disable_DF,mb_num_h,mb_num_v,
|
||||
bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
|
||||
QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
|
||||
blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM_dout,
|
||||
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
||||
|
||||
DF_duration,end_of_MB_DF,DF_edge_counter_MR,one_edge_counter_MR,
|
||||
DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,
|
||||
dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din);
|
||||
input clk;
|
||||
input gclk_DF;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input gclk_DF_mbAddrA_RF;
|
||||
input gclk_DF_mbAddrB_RAM;
|
||||
input reset_n;
|
||||
input end_of_BS_DEC;
|
||||
input disable_DF;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
|
||||
input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
input [5:0] QPy,QPc;
|
||||
input [3:0] slice_alpha_c0_offset_div2;
|
||||
input [3:0] slice_beta_offset_div2;
|
||||
input [31:0] rec_DF_RAM_dout;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input [4:0] blk4x4_rec_counter_2_raster_order;
|
||||
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
|
||||
output DF_duration;
|
||||
output end_of_MB_DF;
|
||||
output [5:0] DF_edge_counter_MR;
|
||||
output [1:0] one_edge_counter_MR;
|
||||
output DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr;
|
||||
output DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
|
||||
output dis_frame_RAM_wr;
|
||||
output [13:0] dis_frame_RAM_wr_addr;
|
||||
output [31:0] dis_frame_RAM_din;
|
||||
|
||||
wire end_of_MB_DF;
|
||||
wire end_of_lastMB_DF;
|
||||
wire [3:0] mb_num_h_DF;
|
||||
wire [3:0] mb_num_v_DF;
|
||||
wire [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
|
||||
wire [1:0] one_edge_counter_MR,one_edge_counter_MW;
|
||||
wire [2:0] bs_curr_MR,bs_curr_MW;
|
||||
wire [7:0] q0_MW,q1_MW,q2_MW,q3_MW;
|
||||
wire [7:0] p0_MW,p1_MW,p2_MW,p3_MW;
|
||||
wire [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
|
||||
wire [31:0] buf1_0,buf1_1,buf1_2,buf1_3;
|
||||
wire [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
|
||||
wire [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
|
||||
wire [31:0] t0_0,t0_1,t0_2,t0_3;
|
||||
wire [31:0] t1_0,t1_1,t1_2,t1_3;
|
||||
wire [31:0] t2_0,t2_1,t2_2,t2_3;
|
||||
wire DF_mbAddrA_RF_rd;
|
||||
wire DF_mbAddrA_RF_wr;
|
||||
wire [4:0] DF_mbAddrA_RF_rd_addr;
|
||||
wire [4:0] DF_mbAddrA_RF_wr_addr;
|
||||
wire [31:0] DF_mbAddrA_RF_din;
|
||||
wire [31:0] DF_mbAddrA_RF_dout;
|
||||
wire DF_mbAddrB_RAM_rd;
|
||||
wire DF_mbAddrB_RAM_wr;
|
||||
wire [8:0] DF_mbAddrB_RAM_addr;
|
||||
wire [31:0] DF_mbAddrB_RAM_din;
|
||||
wire [31:0] DF_mbAddrB_RAM_dout;
|
||||
|
||||
DF_pipeline DF_pipeline (
|
||||
.clk(clk),
|
||||
.gclk_DF(gclk_DF),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.reset_n(reset_n),
|
||||
.disable_DF(disable_DF),
|
||||
.end_of_BS_DEC(end_of_BS_DEC),
|
||||
.end_of_MB_DF(end_of_MB_DF),
|
||||
.end_of_lastMB_DF(end_of_lastMB_DF),
|
||||
.bs_V0(bs_V0),.bs_V1(bs_V1),.bs_V2(bs_V2),.bs_V3(bs_V3),
|
||||
.bs_H0(bs_H0),.bs_H1(bs_H1),.bs_H2(bs_H2),.bs_H3(bs_H3),
|
||||
.QPy(QPy),
|
||||
.QPc(QPc),
|
||||
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
|
||||
.slice_beta_offset_div2(slice_beta_offset_div2),
|
||||
.DF_mbAddrA_RF_dout(DF_mbAddrA_RF_dout),
|
||||
.DF_mbAddrB_RAM_dout(DF_mbAddrB_RAM_dout),
|
||||
.rec_DF_RAM_dout(rec_DF_RAM_dout),
|
||||
.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
|
||||
.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3),
|
||||
.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
|
||||
.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
|
||||
|
||||
.DF_duration(DF_duration),
|
||||
.DF_edge_counter_MR(DF_edge_counter_MR),
|
||||
.DF_edge_counter_MW(DF_edge_counter_MW),
|
||||
.one_edge_counter_MR(one_edge_counter_MR),
|
||||
.one_edge_counter_MW(one_edge_counter_MW),
|
||||
.bs_curr_MR(bs_curr_MR),
|
||||
.bs_curr_MW(bs_curr_MW),
|
||||
.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
|
||||
.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW)
|
||||
);
|
||||
DF_reg_ctrl DF_reg_ctrl (
|
||||
.gclk_DF(gclk_DF),
|
||||
.reset_n(reset_n),
|
||||
.DF_edge_counter_MW(DF_edge_counter_MW),
|
||||
.one_edge_counter_MW(one_edge_counter_MW),
|
||||
.mb_num_h_DF(mb_num_h_DF),
|
||||
.mb_num_v_DF(mb_num_v_DF),
|
||||
|
||||
.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
|
||||
.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW),
|
||||
.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
|
||||
.buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3),
|
||||
.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
|
||||
.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
|
||||
.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3),
|
||||
.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3),
|
||||
.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3)
|
||||
);
|
||||
|
||||
DF_mem_ctrl DF_mem_ctrl (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.disable_DF(disable_DF),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.bs_curr_MR(bs_curr_MR),
|
||||
.bs_curr_MW(bs_curr_MW),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
||||
.DF_edge_counter_MR(DF_edge_counter_MR),
|
||||
.DF_edge_counter_MW(DF_edge_counter_MW),
|
||||
.one_edge_counter_MR(one_edge_counter_MR),
|
||||
.one_edge_counter_MW(one_edge_counter_MW),
|
||||
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
||||
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
||||
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
||||
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
||||
.q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW),
|
||||
.p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW),
|
||||
.buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3),
|
||||
.buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3),
|
||||
.buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3),
|
||||
.t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3),
|
||||
.t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3),
|
||||
.t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3),
|
||||
|
||||
.mb_num_h_DF(mb_num_h_DF),
|
||||
.mb_num_v_DF(mb_num_v_DF),
|
||||
.end_of_MB_DF(end_of_MB_DF),
|
||||
.end_of_lastMB_DF(end_of_lastMB_DF),
|
||||
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
|
||||
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
|
||||
.DF_mbAddrA_RF_rd_addr(DF_mbAddrA_RF_rd_addr),
|
||||
.DF_mbAddrA_RF_wr_addr(DF_mbAddrA_RF_wr_addr),
|
||||
.DF_mbAddrA_RF_din(DF_mbAddrA_RF_din),
|
||||
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
||||
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
||||
.DF_mbAddrB_RAM_addr(DF_mbAddrB_RAM_addr),
|
||||
.DF_mbAddrB_RAM_din(DF_mbAddrB_RAM_din),
|
||||
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
||||
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
||||
.dis_frame_RAM_din(dis_frame_RAM_din)
|
||||
);
|
||||
ram_sync_1r_sync_1w # (`DF_mbAddrA_RAM_data_width,`DF_mbAddrA_RAM_data_depth)
|
||||
DF_mbAddrA_RAM (
|
||||
.clk(gclk_DF_mbAddrA_RF),
|
||||
.rst_n(reset_n),
|
||||
.wr_n(~DF_mbAddrA_RF_wr),
|
||||
.rd_n(~DF_mbAddrA_RF_rd),
|
||||
.wr_addr(DF_mbAddrA_RF_wr_addr),
|
||||
.rd_addr(DF_mbAddrA_RF_rd_addr),
|
||||
.data_in(DF_mbAddrA_RF_din),
|
||||
.data_out(DF_mbAddrA_RF_dout)
|
||||
);
|
||||
ram_sync_1r_sync_1w # (`DF_mbAddrB_RAM_data_width,`DF_mbAddrB_RAM_data_depth)
|
||||
DF_mbAddrB_RAM (
|
||||
.clk(gclk_DF_mbAddrB_RAM),
|
||||
.rst_n(reset_n),
|
||||
.wr_n(~DF_mbAddrB_RAM_wr),
|
||||
.rd_n(~DF_mbAddrB_RAM_rd),
|
||||
.wr_addr(DF_mbAddrB_RAM_addr),
|
||||
.rd_addr(DF_mbAddrB_RAM_addr),
|
||||
.data_in(DF_mbAddrB_RAM_din),
|
||||
.data_out(DF_mbAddrB_RAM_dout)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,850 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : IQIT.v
|
||||
// Generated : June 18, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding the residual information
|
||||
// 1.The res_mb_bypass | DConly | allzero signals should be decoded first
|
||||
// 2.For DC coefficients,IDCT --> rescale
|
||||
// 3.For AC coefficients,rescale --> IDCT --> rounding
|
||||
// 4.coeffLevel:zig-zag order
|
||||
// OneD_output,TwoD_output,DC_output,rescale_output,rounding_output:raster-scan order
|
||||
// 5.Input coeffLevel_ext_0 ~ 15 are 2's complement,but with zig-zag order
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1.March 27,2006
|
||||
// DC_output: 0 ~ 15:for luma DC, 0 ~ 3:for Chroma Cb DC, 4 ~ 7:for Chroma Cr DC
|
||||
// 2.March 28,2006
|
||||
// 1)For Intra16x16ACLevel and chroma AC,the first coeff of IDCT is DC value, the following coeffLevel_ext_0 ~ 14 should be moved backward 1 space and coeffLevel_ext_15 is abandoned
|
||||
// 2)There are some blocks which have zero DC coeff but non-zero AC coeff. Additional signals as res_LumaDCBlk_IsZero,res_ChromaDCBlk_Cb_IsZero,res_ChromaDCBlk_Cr_IsZero are added to deal with such special case
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module IQIT (clk,reset_n,TotalCoeff,blk4x4_rec_counter,
|
||||
gclk_1D,gclk_2D,gclk_rescale,gclk_rounding,
|
||||
residual_state,cavlc_decoder_state,
|
||||
end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,
|
||||
QPy,QPc,i4x4_CbCr,
|
||||
coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3,
|
||||
coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7,
|
||||
coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11,
|
||||
coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15,
|
||||
|
||||
OneD_counter,TwoD_counter,rescale_counter,rounding_counter,
|
||||
curr_DC_IsZero,curr_DC_scaled,
|
||||
rounding_output_0,rounding_output_1,rounding_output_2,rounding_output_3,
|
||||
rounding_output_4,rounding_output_5,rounding_output_6,rounding_output_7,
|
||||
rounding_output_8,rounding_output_9,rounding_output_10,rounding_output_11,
|
||||
rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15,
|
||||
end_of_ACBlk4x4_IQIT,end_of_DCBlk_IQIT
|
||||
);
|
||||
input clk,reset_n;
|
||||
input [4:0] TotalCoeff;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input gclk_1D;
|
||||
input gclk_2D;
|
||||
input gclk_rescale;
|
||||
input gclk_rounding;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input end_of_one_residual_block;
|
||||
input end_of_NonZeroCoeff_CAVLC;
|
||||
input [5:0] QPy;
|
||||
input [5:0] QPc;
|
||||
input [1:0] i4x4_CbCr;
|
||||
input [15:0] coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3;
|
||||
input [15:0] coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7;
|
||||
input [15:0] coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11;
|
||||
input [15:0] coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15;
|
||||
|
||||
|
||||
output [2:0] OneD_counter;
|
||||
output [2:0] TwoD_counter;
|
||||
output [2:0] rescale_counter;
|
||||
output [2:0] rounding_counter;
|
||||
output curr_DC_IsZero;
|
||||
output [8:0] curr_DC_scaled;
|
||||
output [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3;
|
||||
output [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7;
|
||||
output [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11;
|
||||
output [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15;
|
||||
output end_of_ACBlk4x4_IQIT; //end of IQIT of one blk4x4 AC
|
||||
output end_of_DCBlk_IQIT; //end of IQIT of one blk4x4/blk2x2 DC
|
||||
|
||||
reg [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3;
|
||||
reg [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7;
|
||||
reg [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11;
|
||||
reg [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15;
|
||||
|
||||
reg [2:0] OneD_counter;
|
||||
reg [2:0] TwoD_counter;
|
||||
reg [2:0] rescale_counter;
|
||||
reg [2:0] rounding_counter;
|
||||
reg [4:0] LevelScale_DC;
|
||||
reg [4:0] LevelScale_AC [3:0];
|
||||
reg [15:0] butterfly_D0,butterfly_D1,butterfly_D2,butterfly_D3;
|
||||
reg [15:0] mult0_a,mult1_a,mult2_a,mult3_a;
|
||||
reg IsLeftShift;
|
||||
reg [3:0] shift_len;
|
||||
reg [15:0] OneD_output [15:0];
|
||||
reg [15:0] TwoD_output [3:0];
|
||||
reg [15:0] rescale_output [3:0];
|
||||
reg [15:0] DC_output [15:0];
|
||||
|
||||
wire IsHadamard;
|
||||
wire [5:0] QP;
|
||||
wire [2:0] QPmod6;
|
||||
wire [3:0] QPdiv6;
|
||||
wire [15:0] butterfly_F0,butterfly_F1,butterfly_F2,butterfly_F3;
|
||||
wire [4:0] LevelScale [3:0];
|
||||
wire [15:0] product0,product1,product2,product3;
|
||||
wire [15:0] shift_output0,shift_output1,shift_output2,shift_output3;
|
||||
wire [15:0] before_rounding0,before_rounding1,before_rounding2,before_rounding3;
|
||||
wire [9:0] rounding_sum0,rounding_sum1,rounding_sum2,rounding_sum3;
|
||||
|
||||
//-----------------------------------------------------------------------------------
|
||||
// Zero-block-aware decoding
|
||||
//-----------------------------------------------------------------------------------
|
||||
//Whether DC block is zero
|
||||
reg res_LumaDCBlk_IsZero;
|
||||
reg res_ChromaDCBlk_Cb_IsZero;
|
||||
reg res_ChromaDCBlk_Cr_IsZero;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
res_LumaDCBlk_IsZero <= 1'b0;
|
||||
res_ChromaDCBlk_Cb_IsZero <= 1'b0;
|
||||
res_ChromaDCBlk_Cr_IsZero <= 1'b0;
|
||||
end
|
||||
else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT)
|
||||
begin
|
||||
if (residual_state == `Intra16x16DCLevel_s)
|
||||
res_LumaDCBlk_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0;
|
||||
if (residual_state == `ChromaDCLevel_Cb_s)
|
||||
res_ChromaDCBlk_Cb_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0;
|
||||
if (residual_state == `ChromaDCLevel_Cr_s)
|
||||
res_ChromaDCBlk_Cr_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0;
|
||||
end
|
||||
|
||||
//Whether current DC from DC_output[15:0] is zero
|
||||
//If whole DC block are all zeros or current single DC is zero,curr_DC is assigned 0
|
||||
//If current blk4x4 doesn't need DC (e.g. LumaLevel_s), curr_DC is also assigned 0
|
||||
reg [15:0] curr_DC;
|
||||
reg [15:0] curr_DC_reg;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
curr_DC_reg <= 0;
|
||||
else
|
||||
curr_DC_reg <= curr_DC;
|
||||
|
||||
always @ (residual_state or TotalCoeff or blk4x4_rec_counter or end_of_one_residual_block
|
||||
or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero or curr_DC_reg
|
||||
or DC_output[0] or DC_output[1] or DC_output[2] or DC_output[3]
|
||||
or DC_output[4] or DC_output[5] or DC_output[6] or DC_output[7]
|
||||
or DC_output[8] or DC_output[9] or DC_output[10] or DC_output[11]
|
||||
or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15])
|
||||
if (residual_state == `Intra16x16ACLevel_0_s || (residual_state == `Intra16x16ACLevel_s && (end_of_one_residual_block && TotalCoeff == 0)))
|
||||
begin
|
||||
if (res_LumaDCBlk_IsZero == 1)
|
||||
curr_DC <= 0;
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
0 :curr_DC <= DC_output[0]; 1 :curr_DC <= DC_output[1];
|
||||
2 :curr_DC <= DC_output[2]; 3 :curr_DC <= DC_output[3];
|
||||
4 :curr_DC <= DC_output[4]; 5 :curr_DC <= DC_output[5];
|
||||
6 :curr_DC <= DC_output[6]; 7 :curr_DC <= DC_output[7];
|
||||
8 :curr_DC <= DC_output[8]; 9 :curr_DC <= DC_output[9];
|
||||
10:curr_DC <= DC_output[10];11:curr_DC <= DC_output[11];
|
||||
12:curr_DC <= DC_output[12];13:curr_DC <= DC_output[13];
|
||||
14:curr_DC <= DC_output[14];15:curr_DC <= DC_output[15];
|
||||
default:curr_DC <= curr_DC_reg;
|
||||
endcase
|
||||
end
|
||||
else if (residual_state == `ChromaACLevel_0_s || ((residual_state == `ChromaACLevel_Cb_s
|
||||
|| residual_state == `ChromaACLevel_Cr_s) && (end_of_one_residual_block && TotalCoeff == 0)))
|
||||
begin
|
||||
if (blk4x4_rec_counter < 20) //Cb
|
||||
begin
|
||||
if (res_ChromaDCBlk_Cb_IsZero == 1'b1)
|
||||
curr_DC <= 0;
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
16:curr_DC <= DC_output[0];17:curr_DC <= DC_output[1];
|
||||
18:curr_DC <= DC_output[2];19:curr_DC <= DC_output[3];
|
||||
default:curr_DC <= curr_DC_reg;
|
||||
endcase
|
||||
end
|
||||
else //Cr
|
||||
begin
|
||||
if (res_ChromaDCBlk_Cr_IsZero == 1'b1)
|
||||
curr_DC <= 0;
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
20:curr_DC <= DC_output[4];21:curr_DC <= DC_output[5];
|
||||
22:curr_DC <= DC_output[6];23:curr_DC <= DC_output[7];
|
||||
default:curr_DC <= curr_DC_reg;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else
|
||||
curr_DC <= curr_DC_reg;
|
||||
|
||||
wire curr_DC_IsZero;
|
||||
assign curr_DC_IsZero = (curr_DC == 0);
|
||||
|
||||
wire [15:0] curr_DC_tmp;
|
||||
wire [8:0] curr_DC_scaled;
|
||||
assign curr_DC_tmp = curr_DC + 32;
|
||||
assign curr_DC_scaled = curr_DC_tmp[14:6];
|
||||
|
||||
//-----------------------------------------------------------------------------------
|
||||
//residual type indicator
|
||||
//-----------------------------------------------------------------------------------
|
||||
wire res_DC;
|
||||
wire res_AC;
|
||||
wire res_luma;
|
||||
|
||||
assign res_DC = (residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s);
|
||||
assign res_AC = (residual_state != `rst_residual && !res_DC);
|
||||
assign res_luma = (residual_state == `Intra16x16DCLevel_s || residual_state == `Intra16x16ACLevel_s ||
|
||||
residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s);
|
||||
|
||||
//1.OneD_counter:control the step of 1D in IDCT,4 cycles
|
||||
// For ChromaDC IDCT,we combine the original 2x2 2D IDCT into a 4x4-like 1D IDCT
|
||||
// ChromaDC: 1 cycle
|
||||
// Others : 4 cycles
|
||||
always @ (posedge gclk_1D or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
OneD_counter <= 0;
|
||||
else if (OneD_counter == 0)
|
||||
OneD_counter <= (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)? 3'b001:3'b100;
|
||||
else
|
||||
OneD_counter <= OneD_counter - 1;
|
||||
|
||||
//2.TwoD_counter:control the step of 2D in IDCT,4 cycles
|
||||
// ChromaDC: 0 cycle (All ChromDC transform done at 1D-DCT)
|
||||
// Others : 4 cycles
|
||||
always @ (posedge gclk_2D or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
TwoD_counter <= 0;
|
||||
else
|
||||
TwoD_counter <= (TwoD_counter == 0)? 3'b100:TwoD_counter - 1;
|
||||
|
||||
//3.rescale_counter:control the step of rescale
|
||||
// ChromaDC: 1 cycle (only 4 ChromDC coefficients)
|
||||
// Others : 4 cycles(16 coefficients)
|
||||
always @ (posedge gclk_rescale or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
rescale_counter <= 0;
|
||||
else if (rescale_counter != 0)
|
||||
rescale_counter <= rescale_counter - 1;
|
||||
else if (end_of_NonZeroCoeff_CAVLC == 1'b1) // AC
|
||||
rescale_counter <= 3'b100;
|
||||
else if (OneD_counter == 3'b001 && (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)) //ChromaDC
|
||||
rescale_counter <= 3'b001;
|
||||
else if (TwoD_counter == 3'b100 && residual_state == `Intra16x16DCLevel_s) //LumaDC
|
||||
rescale_counter <= 3'b100;
|
||||
|
||||
//4.rounding_counter
|
||||
always @ (posedge gclk_rounding or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
rounding_counter <= 0;
|
||||
else
|
||||
rounding_counter <= (rounding_counter == 0)? 3'b100:(rounding_counter - 1);
|
||||
|
||||
//-----------------------------------------------------------------------------------
|
||||
//rescale
|
||||
//-----------------------------------------------------------------------------------
|
||||
|
||||
//butterfly IDCT
|
||||
//1D DC:from coeffLevel
|
||||
// Intra16x16 :(0,0) :from DC_output
|
||||
// others:from rescale_output
|
||||
// ChromaAC_Cb:(0,0) :from DC_output
|
||||
// others:from rescale_output
|
||||
// ChromaAC_Cr:(0,0) :from DC_output
|
||||
// others:from rescale_output
|
||||
// others :from rescale_output
|
||||
//
|
||||
//2D All from OneD_output
|
||||
assign IsHadamard = (res_DC == 1'b1 && (OneD_counter != 0 || TwoD_counter != 0))? 1'b1:1'b0;
|
||||
|
||||
butterfly butterfly (
|
||||
.D0(butterfly_D0),
|
||||
.D1(butterfly_D1),
|
||||
.D2(butterfly_D2),
|
||||
.D3(butterfly_D3),
|
||||
.F0(butterfly_F0),
|
||||
.F1(butterfly_F1),
|
||||
.F2(butterfly_F2),
|
||||
.F3(butterfly_F3),
|
||||
.IsHadamard(IsHadamard)
|
||||
);
|
||||
|
||||
always @ (i4x4_CbCr or OneD_counter or TwoD_counter or blk4x4_rec_counter[3:0] or residual_state or res_AC
|
||||
or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero
|
||||
or DC_output[0] or DC_output[1] or DC_output[2] or DC_output[3]
|
||||
or DC_output[4] or DC_output[5] or DC_output[6] or DC_output[7]
|
||||
or DC_output[8] or DC_output[9] or DC_output[10] or DC_output[11]
|
||||
or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15]
|
||||
or coeffLevel_ext_0 or coeffLevel_ext_1 or coeffLevel_ext_2 or coeffLevel_ext_3
|
||||
or coeffLevel_ext_4 or coeffLevel_ext_5 or coeffLevel_ext_6 or coeffLevel_ext_7
|
||||
or coeffLevel_ext_8 or coeffLevel_ext_9 or coeffLevel_ext_10 or coeffLevel_ext_11
|
||||
or coeffLevel_ext_12 or coeffLevel_ext_13 or coeffLevel_ext_14 or coeffLevel_ext_15
|
||||
or OneD_output[0] or OneD_output[1] or OneD_output[2] or OneD_output[3]
|
||||
or OneD_output[4] or OneD_output[5] or OneD_output[6] or OneD_output[7]
|
||||
or OneD_output[8] or OneD_output[9] or OneD_output[10] or OneD_output[11]
|
||||
or OneD_output[12] or OneD_output[13] or OneD_output[14] or OneD_output[15]
|
||||
or rescale_output[0] or rescale_output[1] or rescale_output[2] or rescale_output[3])
|
||||
if (OneD_counter != 0)
|
||||
case (OneD_counter)
|
||||
3'b100:
|
||||
begin
|
||||
case (residual_state)
|
||||
`Intra16x16ACLevel_s:
|
||||
if (res_LumaDCBlk_IsZero == 1'b1)
|
||||
butterfly_D0 <= 0;
|
||||
else
|
||||
case (blk4x4_rec_counter[3:0])
|
||||
4'b0000: butterfly_D0 <= DC_output[0];
|
||||
4'b0001: butterfly_D0 <= DC_output[1];
|
||||
4'b0010: butterfly_D0 <= DC_output[2];
|
||||
4'b0011: butterfly_D0 <= DC_output[3];
|
||||
4'b0100: butterfly_D0 <= DC_output[4];
|
||||
4'b0101: butterfly_D0 <= DC_output[5];
|
||||
4'b0110: butterfly_D0 <= DC_output[6];
|
||||
4'b0111: butterfly_D0 <= DC_output[7];
|
||||
4'b1000: butterfly_D0 <= DC_output[8];
|
||||
4'b1001: butterfly_D0 <= DC_output[9];
|
||||
4'b1010: butterfly_D0 <= DC_output[10];
|
||||
4'b1011: butterfly_D0 <= DC_output[11];
|
||||
4'b1100: butterfly_D0 <= DC_output[12];
|
||||
4'b1101: butterfly_D0 <= DC_output[13];
|
||||
4'b1110: butterfly_D0 <= DC_output[14];
|
||||
4'b1111: butterfly_D0 <= DC_output[15];
|
||||
endcase
|
||||
`ChromaACLevel_Cb_s:
|
||||
if(res_ChromaDCBlk_Cb_IsZero)
|
||||
butterfly_D0 <= 0;
|
||||
else
|
||||
case (i4x4_CbCr)
|
||||
2'b00:butterfly_D0 <= DC_output[0];
|
||||
2'b01:butterfly_D0 <= DC_output[1];
|
||||
2'b10:butterfly_D0 <= DC_output[2];
|
||||
2'b11:butterfly_D0 <= DC_output[3];
|
||||
endcase
|
||||
`ChromaACLevel_Cr_s:
|
||||
if(res_ChromaDCBlk_Cr_IsZero)
|
||||
butterfly_D0 <= 0;
|
||||
else
|
||||
case (i4x4_CbCr)
|
||||
2'b00:butterfly_D0 <= DC_output[4];
|
||||
2'b01:butterfly_D0 <= DC_output[5];
|
||||
2'b10:butterfly_D0 <= DC_output[6];
|
||||
2'b11:butterfly_D0 <= DC_output[7];
|
||||
endcase
|
||||
default: //luma DC,chroma DC,luma4x4 AC
|
||||
butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_0;
|
||||
endcase
|
||||
butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_1;
|
||||
butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_5;
|
||||
butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_6;
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_2;
|
||||
butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_4;
|
||||
butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_7;
|
||||
butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_12;
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_3;
|
||||
butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_8;
|
||||
butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_11;
|
||||
butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_13;
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
//luma DC
|
||||
if (residual_state == `Intra16x16DCLevel_s)
|
||||
begin
|
||||
butterfly_D0 <= coeffLevel_ext_9; butterfly_D1 <= coeffLevel_ext_10;
|
||||
butterfly_D2 <= coeffLevel_ext_14; butterfly_D3 <= coeffLevel_ext_15;
|
||||
end
|
||||
//chroma DC
|
||||
else if (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)
|
||||
begin
|
||||
butterfly_D0 <= coeffLevel_ext_0; butterfly_D1 <= coeffLevel_ext_1;
|
||||
butterfly_D2 <= coeffLevel_ext_2; butterfly_D3 <= coeffLevel_ext_3;
|
||||
end
|
||||
//AC
|
||||
else
|
||||
begin
|
||||
butterfly_D0 <= rescale_output[0]; butterfly_D1 <= rescale_output[1];
|
||||
butterfly_D2 <= rescale_output[2]; butterfly_D3 <= rescale_output[3];
|
||||
end
|
||||
end
|
||||
default:
|
||||
begin
|
||||
butterfly_D0 <= 0; butterfly_D1 <= 0;
|
||||
butterfly_D2 <= 0; butterfly_D3 <= 0;
|
||||
end
|
||||
endcase
|
||||
else if (TwoD_counter != 0)
|
||||
case (TwoD_counter)
|
||||
3'b100:
|
||||
begin
|
||||
butterfly_D0 <= OneD_output[0];butterfly_D1 <= OneD_output[4];
|
||||
butterfly_D2 <= OneD_output[8];butterfly_D3 <= OneD_output[12];
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
butterfly_D0 <= OneD_output[1];butterfly_D1 <= OneD_output[5];
|
||||
butterfly_D2 <= OneD_output[9];butterfly_D3 <= OneD_output[13];
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
butterfly_D0 <= OneD_output[2]; butterfly_D1 <= OneD_output[6];
|
||||
butterfly_D2 <= OneD_output[10];butterfly_D3 <= OneD_output[14];
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
butterfly_D0 <= OneD_output[3]; butterfly_D1 <= OneD_output[7];
|
||||
butterfly_D2 <= OneD_output[11];butterfly_D3 <= OneD_output[15];
|
||||
end
|
||||
default:
|
||||
begin
|
||||
butterfly_D0 <= 0; butterfly_D1 <= 0;
|
||||
butterfly_D2 <= 0; butterfly_D3 <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
butterfly_D0 <= 0; butterfly_D1 <= 0;
|
||||
butterfly_D2 <= 0; butterfly_D3 <= 0;
|
||||
end
|
||||
|
||||
assign QP = (res_luma == 1'b1)? QPy:QPc;
|
||||
mod6 mod6 (
|
||||
.qp(QP),
|
||||
.mod(QPmod6)
|
||||
);
|
||||
|
||||
// Specify LevelScale parameter: LevelScale_DC & LevelScale_AC
|
||||
always @ (rescale_counter or res_DC or QPmod6)
|
||||
if (rescale_counter != 0 && res_DC == 1'b1)
|
||||
case (QPmod6)
|
||||
0:LevelScale_DC <= 10;
|
||||
1:LevelScale_DC <= 11;
|
||||
2:LevelScale_DC <= 13;
|
||||
3:LevelScale_DC <= 14;
|
||||
4:LevelScale_DC <= 16;
|
||||
5:LevelScale_DC <= 18;
|
||||
default:LevelScale_DC <= 0;
|
||||
endcase
|
||||
else
|
||||
LevelScale_DC <= 0;
|
||||
|
||||
always @ (rescale_counter or res_AC or QPmod6)
|
||||
if (rescale_counter != 0 && res_AC == 1'b1)
|
||||
case (rescale_counter)
|
||||
3'b100,3'b010: //1 & 3 row
|
||||
case (QPmod6)
|
||||
3'b000:begin LevelScale_AC[0] <= 10; LevelScale_AC[1] <= 13; LevelScale_AC[2] <= 10; LevelScale_AC[3] <= 13; end
|
||||
3'b001:begin LevelScale_AC[0] <= 11; LevelScale_AC[1] <= 14; LevelScale_AC[2] <= 11; LevelScale_AC[3] <= 14; end
|
||||
3'b010:begin LevelScale_AC[0] <= 13; LevelScale_AC[1] <= 16; LevelScale_AC[2] <= 13; LevelScale_AC[3] <= 16; end
|
||||
3'b011:begin LevelScale_AC[0] <= 14; LevelScale_AC[1] <= 18; LevelScale_AC[2] <= 14; LevelScale_AC[3] <= 18; end
|
||||
3'b100:begin LevelScale_AC[0] <= 16; LevelScale_AC[1] <= 20; LevelScale_AC[2] <= 16; LevelScale_AC[3] <= 20; end
|
||||
3'b101:begin LevelScale_AC[0] <= 18; LevelScale_AC[1] <= 23; LevelScale_AC[2] <= 18; LevelScale_AC[3] <= 23; end
|
||||
default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end
|
||||
endcase
|
||||
3'b011,3'b001: //2 & 4 row
|
||||
case (QPmod6)
|
||||
3'b000:begin LevelScale_AC[0] <= 13; LevelScale_AC[1] <= 16; LevelScale_AC[2] <= 13; LevelScale_AC[3] <= 16; end
|
||||
3'b001:begin LevelScale_AC[0] <= 14; LevelScale_AC[1] <= 18; LevelScale_AC[2] <= 14; LevelScale_AC[3] <= 18; end
|
||||
3'b010:begin LevelScale_AC[0] <= 16; LevelScale_AC[1] <= 20; LevelScale_AC[2] <= 16; LevelScale_AC[3] <= 20; end
|
||||
3'b011:begin LevelScale_AC[0] <= 18; LevelScale_AC[1] <= 23; LevelScale_AC[2] <= 18; LevelScale_AC[3] <= 23; end
|
||||
3'b100:begin LevelScale_AC[0] <= 20; LevelScale_AC[1] <= 25; LevelScale_AC[2] <= 20; LevelScale_AC[3] <= 25; end
|
||||
3'b101:begin LevelScale_AC[0] <= 23; LevelScale_AC[1] <= 29; LevelScale_AC[2] <= 23; LevelScale_AC[3] <= 29; end
|
||||
default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end
|
||||
endcase
|
||||
default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0;
|
||||
LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0;
|
||||
end
|
||||
|
||||
assign LevelScale[0] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[0]:LevelScale_DC);
|
||||
assign LevelScale[1] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[1]:LevelScale_DC);
|
||||
assign LevelScale[2] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[2]:LevelScale_DC);
|
||||
assign LevelScale[3] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[3]:LevelScale_DC);
|
||||
|
||||
// Specify rescale multiplier input
|
||||
always @ (residual_state or res_DC or rescale_counter
|
||||
or OneD_output[0] or OneD_output[1] or OneD_output[2] or OneD_output[3]
|
||||
or OneD_output[4] or OneD_output[5] or OneD_output[6] or OneD_output[7]
|
||||
or OneD_output[8] or OneD_output[9] or OneD_output[10] or OneD_output[11]
|
||||
or OneD_output[12] or OneD_output[13] or OneD_output[14] or OneD_output[15]
|
||||
or TwoD_output[0] or TwoD_output[1] or TwoD_output[2] or TwoD_output[3]
|
||||
or coeffLevel_ext_0 or coeffLevel_ext_1 or coeffLevel_ext_2 or coeffLevel_ext_3
|
||||
or coeffLevel_ext_4 or coeffLevel_ext_5 or coeffLevel_ext_6 or coeffLevel_ext_7
|
||||
or coeffLevel_ext_8 or coeffLevel_ext_9 or coeffLevel_ext_10 or coeffLevel_ext_11
|
||||
or coeffLevel_ext_12 or coeffLevel_ext_13 or coeffLevel_ext_14 or coeffLevel_ext_15)
|
||||
if (residual_state == `Intra16x16DCLevel_s && rescale_counter != 0) //Intra16x16DC
|
||||
begin
|
||||
mult0_a <= TwoD_output[0]; mult1_a <= TwoD_output[1];
|
||||
mult2_a <= TwoD_output[2]; mult3_a <= TwoD_output[3];
|
||||
end
|
||||
else if (res_DC == 1'b1 && rescale_counter != 0) //ChromaDC
|
||||
begin
|
||||
mult0_a <= OneD_output[12]; mult1_a <= OneD_output[15];
|
||||
mult2_a <= OneD_output[13]; mult3_a <= OneD_output[14];
|
||||
end
|
||||
else if (rescale_counter != 0) //AC
|
||||
case (rescale_counter)
|
||||
3'b100:
|
||||
begin
|
||||
mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_0:0;
|
||||
mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_1:coeffLevel_ext_0;
|
||||
mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_5:coeffLevel_ext_4;
|
||||
mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_6:coeffLevel_ext_5;
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_2:coeffLevel_ext_1;
|
||||
mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_4:coeffLevel_ext_3;
|
||||
mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_7:coeffLevel_ext_6;
|
||||
mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_12:coeffLevel_ext_11;
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_3:coeffLevel_ext_2;
|
||||
mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_8:coeffLevel_ext_7;
|
||||
mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_11:coeffLevel_ext_10;
|
||||
mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_13:coeffLevel_ext_12;
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_9:coeffLevel_ext_8;
|
||||
mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_10:coeffLevel_ext_9;
|
||||
mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_14:coeffLevel_ext_13;
|
||||
mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_15:coeffLevel_ext_14;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
mult0_a <= 0; mult1_a <= 0;
|
||||
mult2_a <= 0; mult3_a <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
mult0_a <= 0; mult1_a <= 0;
|
||||
mult2_a <= 0; mult3_a <= 0;
|
||||
end
|
||||
|
||||
//rescale multiplier
|
||||
assign product0 = (rescale_counter == 0)? 0:mult0_a * {1'b0,LevelScale[0]};
|
||||
assign product1 = (rescale_counter == 0)? 0:mult1_a * {1'b0,LevelScale[1]};
|
||||
assign product2 = (rescale_counter == 0)? 0:mult2_a * {1'b0,LevelScale[2]};
|
||||
assign product3 = (rescale_counter == 0)? 0:mult3_a * {1'b0,LevelScale[3]};
|
||||
|
||||
always @ (res_AC or res_luma or QPy or QPc)
|
||||
if (res_AC == 1'b1)
|
||||
IsLeftShift <= 1'b1;
|
||||
else if (res_luma == 1'b1)
|
||||
IsLeftShift <= (QPy < 12)? 1'b0:1'b1;
|
||||
else
|
||||
IsLeftShift <= (QPc < 6)? 1'b0:1'b1;
|
||||
|
||||
div6 div6 (
|
||||
.qp(QP),
|
||||
.div(QPdiv6)
|
||||
);
|
||||
|
||||
always @ (residual_state or res_DC or QPdiv6)
|
||||
if (residual_state == `Intra16x16DCLevel_s) //Intra16x16DC
|
||||
case (QPdiv6)
|
||||
4'b0000:shift_len <= 2;
|
||||
4'b0001:shift_len <= 1;
|
||||
default:shift_len <= QPdiv6 - 2;
|
||||
endcase
|
||||
else if (res_DC) //ChromaDC
|
||||
case (QPdiv6)
|
||||
4'b0000:shift_len <= 1;
|
||||
default:shift_len <= QPdiv6 - 1;
|
||||
endcase
|
||||
else //AC
|
||||
shift_len <= QPdiv6;
|
||||
|
||||
rescale_shift rescale_shift0 (
|
||||
.IsLeftShift(IsLeftShift),
|
||||
.shift_input(product0),
|
||||
.shift_len(shift_len),
|
||||
.shift_output(shift_output0)
|
||||
);
|
||||
rescale_shift rescale_shift1 (
|
||||
.IsLeftShift(IsLeftShift),
|
||||
.shift_input(product1),
|
||||
.shift_len(shift_len),
|
||||
.shift_output(shift_output1)
|
||||
);
|
||||
rescale_shift rescale_shift2 (
|
||||
.IsLeftShift(IsLeftShift),
|
||||
.shift_input(product2),
|
||||
.shift_len(shift_len),
|
||||
.shift_output(shift_output2)
|
||||
);
|
||||
rescale_shift rescale_shift3 (
|
||||
.IsLeftShift(IsLeftShift),
|
||||
.shift_input(product3),
|
||||
.shift_len(shift_len),
|
||||
.shift_output(shift_output3)
|
||||
);
|
||||
//-----------------------------------------------------------------------
|
||||
//rounding
|
||||
//-----------------------------------------------------------------------
|
||||
assign before_rounding0 = (rounding_counter != 0)? TwoD_output[0]:0;
|
||||
assign before_rounding1 = (rounding_counter != 0)? TwoD_output[1]:0;
|
||||
assign before_rounding2 = (rounding_counter != 0)? TwoD_output[2]:0;
|
||||
assign before_rounding3 = (rounding_counter != 0)? TwoD_output[3]:0;
|
||||
|
||||
assign rounding_sum0 = before_rounding0[14:5] + 1;
|
||||
assign rounding_sum1 = before_rounding1[14:5] + 1;
|
||||
assign rounding_sum2 = before_rounding2[14:5] + 1;
|
||||
assign rounding_sum3 = before_rounding3[14:5] + 1;
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Strore results
|
||||
//-----------------------------------------------------------------------
|
||||
//1. Store OneD_output
|
||||
integer i;
|
||||
always @ (posedge gclk_1D or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
for (i=0;i<16;i=i+1)
|
||||
OneD_output[i] <= 0;
|
||||
else if (OneD_counter != 0)
|
||||
case (OneD_counter)
|
||||
3'b100:
|
||||
begin
|
||||
OneD_output[0] <= butterfly_F0;OneD_output[1] <= butterfly_F1;
|
||||
OneD_output[2] <= butterfly_F2;OneD_output[3] <= butterfly_F3;
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
OneD_output[4] <= butterfly_F0;OneD_output[5] <= butterfly_F1;
|
||||
OneD_output[6] <= butterfly_F2;OneD_output[7] <= butterfly_F3;
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
OneD_output[8] <= butterfly_F0;OneD_output[9] <= butterfly_F1;
|
||||
OneD_output[10] <= butterfly_F2;OneD_output[11] <= butterfly_F3;
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
OneD_output[12] <= butterfly_F0;OneD_output[13] <= butterfly_F1;
|
||||
OneD_output[14] <= butterfly_F2;OneD_output[15] <= butterfly_F3;
|
||||
end
|
||||
endcase
|
||||
|
||||
//2. Store TwoD_output
|
||||
integer j;
|
||||
always @ (posedge gclk_2D or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
for (j=0;j<4;j=j+1)
|
||||
TwoD_output[j] <= 0;
|
||||
else if (TwoD_counter != 0)
|
||||
begin
|
||||
TwoD_output[0] <= butterfly_F0; TwoD_output[1] <= butterfly_F1;
|
||||
TwoD_output[2] <= butterfly_F2; TwoD_output[3] <= butterfly_F3;
|
||||
end
|
||||
|
||||
//3.1 Store rescale_output as DC_output
|
||||
integer m;
|
||||
always @ (posedge gclk_rescale or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
for (m=0;m<16;m=m+1)
|
||||
DC_output[m] <= 0;
|
||||
else if (res_DC == 1'b1)
|
||||
case (rescale_counter)
|
||||
3'b100:
|
||||
begin
|
||||
DC_output[0] <= shift_output0; DC_output[2] <= shift_output1;
|
||||
DC_output[8] <= shift_output2; DC_output[10] <= shift_output3;
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
DC_output[1] <= shift_output0; DC_output[3] <= shift_output1;
|
||||
DC_output[9] <= shift_output2; DC_output[11] <= shift_output3;
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
DC_output[4] <= shift_output0; DC_output[6] <= shift_output1;
|
||||
DC_output[12] <= shift_output2; DC_output[14] <= shift_output3;
|
||||
end
|
||||
3'b001:
|
||||
if (residual_state == `ChromaDCLevel_Cb_s)
|
||||
begin
|
||||
DC_output[0] <= shift_output0; DC_output[1] <= shift_output1;
|
||||
DC_output[2] <= shift_output2; DC_output[3] <= shift_output3;
|
||||
end
|
||||
else if (residual_state == `ChromaDCLevel_Cr_s)
|
||||
begin
|
||||
DC_output[4] <= shift_output0; DC_output[5] <= shift_output1;
|
||||
DC_output[6] <= shift_output2; DC_output[7] <= shift_output3;
|
||||
end
|
||||
else
|
||||
begin
|
||||
DC_output[5] <= shift_output0; DC_output[7] <= shift_output1;
|
||||
DC_output[13] <= shift_output2; DC_output[15] <= shift_output3;
|
||||
end
|
||||
endcase
|
||||
|
||||
//3.2 Store rescale_output as AC_output
|
||||
integer n;
|
||||
always @ (posedge gclk_rescale or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
for (n=0;n<4;n=n+1)
|
||||
rescale_output[n] <= 0;
|
||||
else if (res_AC == 1'b1 && rescale_counter != 0)
|
||||
begin
|
||||
rescale_output[0] <= shift_output0; rescale_output[1] <= shift_output1;
|
||||
rescale_output[2] <= shift_output2; rescale_output[3] <= shift_output3;
|
||||
end
|
||||
|
||||
//4. Store rounding_output
|
||||
always @ (posedge gclk_rounding or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
rounding_output_0 <= 0;rounding_output_1 <= 0;rounding_output_2 <= 0;rounding_output_3 <= 0;
|
||||
rounding_output_4 <= 0;rounding_output_5 <= 0;rounding_output_6 <= 0;rounding_output_7 <= 0;
|
||||
rounding_output_8 <= 0;rounding_output_9 <= 0;rounding_output_10 <= 0;rounding_output_11 <= 0;
|
||||
rounding_output_12 <= 0;rounding_output_13 <= 0;rounding_output_14 <= 0;rounding_output_15 <= 0;
|
||||
end
|
||||
else
|
||||
case (rounding_counter)
|
||||
3'b100:
|
||||
begin
|
||||
rounding_output_0 <= rounding_sum0[9:1];
|
||||
rounding_output_4 <= rounding_sum1[9:1];
|
||||
rounding_output_8 <= rounding_sum2[9:1];
|
||||
rounding_output_12 <= rounding_sum3[9:1];
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
rounding_output_1 <= rounding_sum0[9:1];
|
||||
rounding_output_5 <= rounding_sum1[9:1];
|
||||
rounding_output_9 <= rounding_sum2[9:1];
|
||||
rounding_output_13 <= rounding_sum3[9:1];
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
rounding_output_2 <= rounding_sum0[9:1];
|
||||
rounding_output_6 <= rounding_sum1[9:1];
|
||||
rounding_output_10 <= rounding_sum2[9:1];
|
||||
rounding_output_14 <= rounding_sum3[9:1];
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
rounding_output_3 <= rounding_sum0[9:1];
|
||||
rounding_output_7 <= rounding_sum1[9:1];
|
||||
rounding_output_11 <= rounding_sum2[9:1];
|
||||
rounding_output_15 <= rounding_sum3[9:1];
|
||||
end
|
||||
endcase
|
||||
assign end_of_ACBlk4x4_IQIT = (rounding_counter == 3'b001)? 1'b1:1'b0;
|
||||
assign end_of_DCBlk_IQIT = ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
|
||||
residual_state == `ChromaDCLevel_Cr_s) && rescale_counter == 3'b001)? 1'b1:1'b0;
|
||||
endmodule
|
||||
|
||||
module butterfly (D0,D1,D2,D3,F0,F1,F2,F3,IsHadamard);
|
||||
input [15:0] D0,D1,D2,D3;
|
||||
input IsHadamard;
|
||||
output [15:0] F0,F1,F2,F3;
|
||||
|
||||
wire [15:0] T0,T1,T2,T3;
|
||||
wire [15:0] D1_scale,D3_scale;
|
||||
|
||||
assign D1_scale = (IsHadamard == 1'b1)? D1:{D1[15],D1[15:1]};
|
||||
assign D3_scale = (IsHadamard == 1'b1)? D3:{D3[15],D3[15:1]};
|
||||
|
||||
assign T0 = D0 + D2;
|
||||
assign T1 = D0 - D2;
|
||||
assign T2 = D1_scale - D3;
|
||||
assign T3 = D1 + D3_scale;
|
||||
|
||||
assign F0 = T0 + T3;
|
||||
assign F1 = T1 + T2;
|
||||
assign F2 = T1 - T2;
|
||||
assign F3 = T0 - T3;
|
||||
endmodule
|
||||
|
||||
module mod6 (qp,mod);
|
||||
input [5:0] qp;
|
||||
output [2:0] mod;
|
||||
reg [2:0] mod;
|
||||
always @ (qp)
|
||||
case (qp)
|
||||
0, 6,12,18,24,30,36,42,48:mod <= 3'b000;
|
||||
1, 7,13,19,25,31,37,43,49:mod <= 3'b001;
|
||||
2, 8,14,20,26,32,38,44,50:mod <= 3'b010;
|
||||
3, 9,15,21,27,33,39,45,51:mod <= 3'b011;
|
||||
4,10,16,22,28,34,40,46 :mod <= 3'b100;
|
||||
5,11,17,23,29,35,41,47 :mod <= 3'b101;
|
||||
default :mod <= 3'b000;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module div6 (qp,div);
|
||||
input [5:0] qp;
|
||||
output [3:0] div;
|
||||
reg [3:0] div;
|
||||
always @ (qp)
|
||||
case (qp)
|
||||
0, 1, 2, 3, 4, 5 :div <= 4'b0000;
|
||||
6, 7, 8, 9, 10,11:div <= 4'b0001;
|
||||
12,13,14,15,16,17:div <= 4'b0010;
|
||||
18,19,20,21,22,23:div <= 4'b0011;
|
||||
24,25,26,27,28,29:div <= 4'b0100;
|
||||
30,31,32,33,34,35:div <= 4'b0101;
|
||||
36,37,38,39,40,41:div <= 4'b0110;
|
||||
42,43,44,45,46,47:div <= 4'b0111;
|
||||
48,49,50,51 :div <= 4'b1000;
|
||||
default :div <= 0;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module rescale_shift (IsLeftShift,shift_input,shift_len,shift_output);
|
||||
input IsLeftShift;
|
||||
input signed [15:0] shift_input;
|
||||
input [3:0] shift_len;
|
||||
output signed [15:0] shift_output;
|
||||
|
||||
assign shift_output = (IsLeftShift == 1'b1)? (shift_input <<< shift_len):(shift_input >>> shift_len);
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Inter_pred_CPE.v
|
||||
// Generated : Oct 14, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Processing Element for Inter prediction of Chroma pixels
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Inter_pred_CPE (xFracC,yFracC,
|
||||
Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0,
|
||||
Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1,
|
||||
Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2,
|
||||
CPE0_out,CPE1_out,CPE2_out,CPE3_out);
|
||||
input [2:0] xFracC,yFracC;
|
||||
input [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0;
|
||||
input [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1;
|
||||
input [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2;
|
||||
output [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out;
|
||||
|
||||
wire [3:0] xFracC_n,yFracC_n;
|
||||
assign xFracC_n = 4'b1000 - xFracC;
|
||||
assign yFracC_n = 4'b1000 - yFracC;
|
||||
|
||||
CPE CPE0 (
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.xFracC_n(xFracC_n),
|
||||
.yFracC_n(yFracC_n),
|
||||
.a(Inter_C_window_0_0),
|
||||
.b(Inter_C_window_1_0),
|
||||
.c(Inter_C_window_0_1),
|
||||
.d(Inter_C_window_1_1),
|
||||
.out(CPE0_out)
|
||||
);
|
||||
CPE CPE1 (
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.xFracC_n(xFracC_n),
|
||||
.yFracC_n(yFracC_n),
|
||||
.a(Inter_C_window_1_0),
|
||||
.b(Inter_C_window_2_0),
|
||||
.c(Inter_C_window_1_1),
|
||||
.d(Inter_C_window_2_1),
|
||||
.out(CPE1_out)
|
||||
);
|
||||
CPE CPE2 (
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.xFracC_n(xFracC_n),
|
||||
.yFracC_n(yFracC_n),
|
||||
.a(Inter_C_window_0_1),
|
||||
.b(Inter_C_window_1_1),
|
||||
.c(Inter_C_window_0_2),
|
||||
.d(Inter_C_window_1_2),
|
||||
.out(CPE2_out)
|
||||
);
|
||||
CPE CPE3 (
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.xFracC_n(xFracC_n),
|
||||
.yFracC_n(yFracC_n),
|
||||
.a(Inter_C_window_1_1),
|
||||
.b(Inter_C_window_2_1),
|
||||
.c(Inter_C_window_1_2),
|
||||
.d(Inter_C_window_2_2),
|
||||
.out(CPE3_out)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module CPE (xFracC,yFracC,xFracC_n,yFracC_n,a,b,c,d,out);
|
||||
input [2:0] xFracC,yFracC;
|
||||
input [3:0] xFracC_n,yFracC_n;
|
||||
input [7:0] a,b,c,d;
|
||||
output [7:0] out;
|
||||
|
||||
wire [13:0] CPE_base0_out,CPE_base1_out,CPE_base2_out,CPE_base3_out;
|
||||
wire [13:0] out_tmp;
|
||||
|
||||
CPE_base CPE_base0 (
|
||||
.x(xFracC_n),
|
||||
.y(yFracC_n),
|
||||
.Int_pel(a),
|
||||
.out(CPE_base0_out)
|
||||
);
|
||||
CPE_base CPE_base1 (
|
||||
.x({1'b0,xFracC}),
|
||||
.y(yFracC_n),
|
||||
.Int_pel(b),
|
||||
.out(CPE_base1_out)
|
||||
);
|
||||
CPE_base CPE_base2 (
|
||||
.x(xFracC_n),
|
||||
.y({1'b0,yFracC}),
|
||||
.Int_pel(c),
|
||||
.out(CPE_base2_out)
|
||||
);
|
||||
CPE_base CPE_base3 (
|
||||
.x({1'b0,xFracC}),
|
||||
.y({1'b0,yFracC}),
|
||||
.Int_pel(d),
|
||||
.out(CPE_base3_out)
|
||||
);
|
||||
assign out_tmp = (CPE_base0_out + CPE_base1_out) + (CPE_base2_out + CPE_base3_out) + 32;
|
||||
assign out = out_tmp[13:6];
|
||||
endmodule
|
||||
|
||||
module CPE_base (x,y,Int_pel,out);
|
||||
input [3:0] x;
|
||||
input [3:0] y;
|
||||
input [7:0] Int_pel;
|
||||
output [13:0] out;
|
||||
|
||||
wire [10:0] sum_x3;
|
||||
wire [9:0] sum_x2;
|
||||
wire [8:0] sum_x1;
|
||||
wire [7:0] sum_x0;
|
||||
wire [10:0] sum_x;
|
||||
|
||||
wire [13:0] sum_y3;
|
||||
wire [12:0] sum_y2;
|
||||
wire [11:0] sum_y1;
|
||||
wire [10:0] sum_y0;
|
||||
|
||||
assign sum_x3 = (x[3] == 1'b1)? {Int_pel,3'b0}:0;
|
||||
assign sum_x2 = (x[2] == 1'b1)? {Int_pel,2'b0}:0;
|
||||
assign sum_x1 = (x[1] == 1'b1)? {Int_pel,1'b0}:0;
|
||||
assign sum_x0 = (x[0] == 1'b1)? Int_pel:0;
|
||||
assign sum_x = (sum_x3 + sum_x2) + (sum_x1 + sum_x0);
|
||||
|
||||
assign sum_y3 = (y[3] == 1'b1)? {sum_x,3'b0}:0;
|
||||
assign sum_y2 = (y[2] == 1'b1)? {sum_x,2'b0}:0;
|
||||
assign sum_y1 = (y[1] == 1'b1)? {sum_x,1'b0}:0;
|
||||
assign sum_y0 = (y[0] == 1'b1)? sum_x:0;
|
||||
assign out = (sum_y3 + sum_y2) + (sum_y1 + sum_y0);
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,591 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Inter_pred_LPE.v
|
||||
// Generated : Oct 11, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Processing Element for Inter prediction of Luma pixels
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Inter_pred_LPE (clk,reset_n,pos_FracL,IsInterLuma,
|
||||
blk4x4_inter_calculate_counter,
|
||||
Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0,
|
||||
Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1,
|
||||
Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2,
|
||||
Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3,
|
||||
Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4,
|
||||
Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5,
|
||||
Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6,
|
||||
Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7,
|
||||
Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8,
|
||||
Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4,
|
||||
Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8,
|
||||
Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3,
|
||||
|
||||
LPE0_out,LPE1_out,LPE2_out,LPE3_out
|
||||
);
|
||||
input clk,reset_n;
|
||||
input [3:0] pos_FracL;
|
||||
input IsInterLuma;
|
||||
input [3:0] blk4x4_inter_calculate_counter;
|
||||
|
||||
input [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0;
|
||||
input [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1;
|
||||
input [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2;
|
||||
input [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3;
|
||||
input [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4;
|
||||
input [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5;
|
||||
input [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6;
|
||||
input [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7;
|
||||
input [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8;
|
||||
input [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4;
|
||||
input [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8;
|
||||
input [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3;
|
||||
|
||||
output [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out;
|
||||
|
||||
reg [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out;
|
||||
|
||||
reg [14:0] b0_raw_reg,b1_raw_reg,b2_raw_reg,b3_raw_reg,b4_raw_reg,b5_raw_reg,b6_raw_reg,b7_raw_reg,b8_raw_reg;
|
||||
reg [7:0] b0_reg,b1_reg,b2_reg,b3_reg;
|
||||
reg [7:0] h0_reg,h1_reg,h2_reg,h3_reg;
|
||||
//------------------------
|
||||
//Vertical 6tap filter
|
||||
//------------------------
|
||||
wire Is_V_jfqik; //Is_V_jfqik: whether read from original [7:0] integer pixels and round as +16 >> 5 or read from b_raw[14:0] and round as +512 >> 10
|
||||
wire [14:0] V_6tapfilter0_A,V_6tapfilter0_B,V_6tapfilter0_C,V_6tapfilter0_D,V_6tapfilter0_E,V_6tapfilter0_F;
|
||||
wire [14:0] V_6tapfilter1_A,V_6tapfilter1_B,V_6tapfilter1_C,V_6tapfilter1_D,V_6tapfilter1_E,V_6tapfilter1_F;
|
||||
wire [14:0] V_6tapfilter2_A,V_6tapfilter2_B,V_6tapfilter2_C,V_6tapfilter2_D,V_6tapfilter2_E,V_6tapfilter2_F;
|
||||
wire [14:0] V_6tapfilter3_A,V_6tapfilter3_B,V_6tapfilter3_C,V_6tapfilter3_D,V_6tapfilter3_E,V_6tapfilter3_F;
|
||||
wire [7:0] V_6tapfilter0_round_out,V_6tapfilter1_round_out,V_6tapfilter2_round_out,V_6tapfilter3_round_out;
|
||||
filterV_6tap V_6tapfilter0 (
|
||||
.A(V_6tapfilter0_A),
|
||||
.B(V_6tapfilter0_B),
|
||||
.C(V_6tapfilter0_C),
|
||||
.D(V_6tapfilter0_D),
|
||||
.E(V_6tapfilter0_E),
|
||||
.F(V_6tapfilter0_F),
|
||||
.Is_jfqik(Is_V_jfqik),
|
||||
.round_out(V_6tapfilter0_round_out)
|
||||
);
|
||||
filterV_6tap V_6tapfilter1 (
|
||||
.A(V_6tapfilter1_A),
|
||||
.B(V_6tapfilter1_B),
|
||||
.C(V_6tapfilter1_C),
|
||||
.D(V_6tapfilter1_D),
|
||||
.E(V_6tapfilter1_E),
|
||||
.F(V_6tapfilter1_F),
|
||||
.Is_jfqik(Is_V_jfqik),
|
||||
.round_out(V_6tapfilter1_round_out)
|
||||
);
|
||||
filterV_6tap V_6tapfilter2 (
|
||||
.A(V_6tapfilter2_A),
|
||||
.B(V_6tapfilter2_B),
|
||||
.C(V_6tapfilter2_C),
|
||||
.D(V_6tapfilter2_D),
|
||||
.E(V_6tapfilter2_E),
|
||||
.F(V_6tapfilter2_F),
|
||||
.Is_jfqik(Is_V_jfqik),
|
||||
.round_out(V_6tapfilter2_round_out)
|
||||
);
|
||||
filterV_6tap V_6tapfilter3 (
|
||||
.A(V_6tapfilter3_A),
|
||||
.B(V_6tapfilter3_B),
|
||||
.C(V_6tapfilter3_C),
|
||||
.D(V_6tapfilter3_D),
|
||||
.E(V_6tapfilter3_E),
|
||||
.F(V_6tapfilter3_F),
|
||||
.Is_jfqik(Is_V_jfqik),
|
||||
.round_out(V_6tapfilter3_round_out)
|
||||
);
|
||||
assign Is_V_jfqik = (
|
||||
(pos_FracL == `pos_j && (
|
||||
blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 ||
|
||||
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) ||
|
||||
((pos_FracL == `pos_f || pos_FracL == `pos_q) && (
|
||||
blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 ||
|
||||
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) ||
|
||||
((pos_FracL == `pos_i || pos_FracL == `pos_k) && (
|
||||
blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 ||
|
||||
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)))? 1'b1:1'b0;
|
||||
|
||||
assign V_6tapfilter0_A = (Is_V_jfqik)? b0_raw_reg:{7'b0,Inter_V_window_0};
|
||||
assign V_6tapfilter0_B = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1};
|
||||
assign V_6tapfilter0_C = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2};
|
||||
assign V_6tapfilter0_D = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3};
|
||||
assign V_6tapfilter0_E = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4};
|
||||
assign V_6tapfilter0_F = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5};
|
||||
|
||||
assign V_6tapfilter1_A = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1};
|
||||
assign V_6tapfilter1_B = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2};
|
||||
assign V_6tapfilter1_C = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3};
|
||||
assign V_6tapfilter1_D = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4};
|
||||
assign V_6tapfilter1_E = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5};
|
||||
assign V_6tapfilter1_F = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6};
|
||||
|
||||
assign V_6tapfilter2_A = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2};
|
||||
assign V_6tapfilter2_B = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3};
|
||||
assign V_6tapfilter2_C = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4};
|
||||
assign V_6tapfilter2_D = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5};
|
||||
assign V_6tapfilter2_E = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6};
|
||||
assign V_6tapfilter2_F = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7};
|
||||
|
||||
assign V_6tapfilter3_A = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3};
|
||||
assign V_6tapfilter3_B = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4};
|
||||
assign V_6tapfilter3_C = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5};
|
||||
assign V_6tapfilter3_D = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6};
|
||||
assign V_6tapfilter3_E = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7};
|
||||
assign V_6tapfilter3_F = (Is_V_jfqik)? b8_raw_reg:{7'b0,Inter_V_window_8};
|
||||
|
||||
//------------------------
|
||||
//Horizontal 6tap filter
|
||||
//------------------------
|
||||
wire H_need_round;
|
||||
wire [14:0] H_6tapfilter0_raw_out;
|
||||
wire [14:0] H_6tapfilter1_raw_out;
|
||||
wire [14:0] H_6tapfilter2_raw_out;
|
||||
wire [14:0] H_6tapfilter3_raw_out;
|
||||
wire [14:0] H_6tapfilter4_raw_out;
|
||||
wire [14:0] H_6tapfilter5_raw_out;
|
||||
wire [14:0] H_6tapfilter6_raw_out;
|
||||
wire [14:0] H_6tapfilter7_raw_out;
|
||||
wire [14:0] H_6tapfilter8_raw_out;
|
||||
wire [7:0] H_6tapfilter0_round_out;
|
||||
wire [7:0] H_6tapfilter1_round_out;
|
||||
wire [7:0] H_6tapfilter2_round_out;
|
||||
wire [7:0] H_6tapfilter3_round_out;
|
||||
wire [7:0] H_6tapfilter4_round_out;
|
||||
wire [7:0] H_6tapfilter5_round_out;
|
||||
wire [7:0] H_6tapfilter6_round_out;
|
||||
wire [7:0] H_6tapfilter7_round_out;
|
||||
wire [7:0] H_6tapfilter8_round_out;
|
||||
|
||||
assign H_need_round = (blk4x4_inter_calculate_counter != 0 && pos_FracL != `pos_Int && pos_FracL != `pos_i
|
||||
&& pos_FracL != `pos_j && pos_FracL != `pos_k && pos_FracL != `pos_d && pos_FracL != `pos_n);
|
||||
|
||||
filterH_6tap H_6tapfilter0 (
|
||||
.A(Inter_H_window_0_0),
|
||||
.B(Inter_H_window_1_0),
|
||||
.C(Inter_H_window_2_0),
|
||||
.D(Inter_H_window_3_0),
|
||||
.E(Inter_H_window_4_0),
|
||||
.F(Inter_H_window_5_0),
|
||||
.H_need_round(1'b0),
|
||||
.raw_out(H_6tapfilter0_raw_out),
|
||||
.round_out(H_6tapfilter0_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter1 (
|
||||
.A(Inter_H_window_0_1),
|
||||
.B(Inter_H_window_1_1),
|
||||
.C(Inter_H_window_2_1),
|
||||
.D(Inter_H_window_3_1),
|
||||
.E(Inter_H_window_4_1),
|
||||
.F(Inter_H_window_5_1),
|
||||
.H_need_round(1'b0),
|
||||
.raw_out(H_6tapfilter1_raw_out),
|
||||
.round_out(H_6tapfilter1_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter2 (
|
||||
.A(Inter_H_window_0_2),
|
||||
.B(Inter_H_window_1_2),
|
||||
.C(Inter_H_window_2_2),
|
||||
.D(Inter_H_window_3_2),
|
||||
.E(Inter_H_window_4_2),
|
||||
.F(Inter_H_window_5_2),
|
||||
.H_need_round(H_need_round),
|
||||
.raw_out(H_6tapfilter2_raw_out),
|
||||
.round_out(H_6tapfilter2_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter3 (
|
||||
.A(Inter_H_window_0_3),
|
||||
.B(Inter_H_window_1_3),
|
||||
.C(Inter_H_window_2_3),
|
||||
.D(Inter_H_window_3_3),
|
||||
.E(Inter_H_window_4_3),
|
||||
.F(Inter_H_window_5_3),
|
||||
.H_need_round(H_need_round),
|
||||
.raw_out(H_6tapfilter3_raw_out),
|
||||
.round_out(H_6tapfilter3_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter4 (
|
||||
.A(Inter_H_window_0_4),
|
||||
.B(Inter_H_window_1_4),
|
||||
.C(Inter_H_window_2_4),
|
||||
.D(Inter_H_window_3_4),
|
||||
.E(Inter_H_window_4_4),
|
||||
.F(Inter_H_window_5_4),
|
||||
.H_need_round(H_need_round),
|
||||
.raw_out(H_6tapfilter4_raw_out),
|
||||
.round_out(H_6tapfilter4_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter5 (
|
||||
.A(Inter_H_window_0_5),
|
||||
.B(Inter_H_window_1_5),
|
||||
.C(Inter_H_window_2_5),
|
||||
.D(Inter_H_window_3_5),
|
||||
.E(Inter_H_window_4_5),
|
||||
.F(Inter_H_window_5_5),
|
||||
.H_need_round(H_need_round),
|
||||
.raw_out(H_6tapfilter5_raw_out),
|
||||
.round_out(H_6tapfilter5_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter6 (
|
||||
.A(Inter_H_window_0_6),
|
||||
.B(Inter_H_window_1_6),
|
||||
.C(Inter_H_window_2_6),
|
||||
.D(Inter_H_window_3_6),
|
||||
.E(Inter_H_window_4_6),
|
||||
.F(Inter_H_window_5_6),
|
||||
.H_need_round(H_need_round),
|
||||
.raw_out(H_6tapfilter6_raw_out),
|
||||
.round_out(H_6tapfilter6_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter7 (
|
||||
.A(Inter_H_window_0_7),
|
||||
.B(Inter_H_window_1_7),
|
||||
.C(Inter_H_window_2_7),
|
||||
.D(Inter_H_window_3_7),
|
||||
.E(Inter_H_window_4_7),
|
||||
.F(Inter_H_window_5_7),
|
||||
.H_need_round(1'b0),
|
||||
.raw_out(H_6tapfilter7_raw_out),
|
||||
.round_out(H_6tapfilter7_round_out)
|
||||
);
|
||||
filterH_6tap H_6tapfilter8 (
|
||||
.A(Inter_H_window_0_8),
|
||||
.B(Inter_H_window_1_8),
|
||||
.C(Inter_H_window_2_8),
|
||||
.D(Inter_H_window_3_8),
|
||||
.E(Inter_H_window_4_8),
|
||||
.F(Inter_H_window_5_8),
|
||||
.H_need_round(1'b0),
|
||||
.raw_out(H_6tapfilter8_raw_out),
|
||||
.round_out(H_6tapfilter8_round_out)
|
||||
);
|
||||
|
||||
//--------------------
|
||||
//bilinear filter
|
||||
//--------------------
|
||||
reg [7:0] bilinear0_A,bilinear0_B;
|
||||
reg [7:0] bilinear1_A,bilinear1_B;
|
||||
reg [7:0] bilinear2_A,bilinear2_B;
|
||||
reg [7:0] bilinear3_A,bilinear3_B;
|
||||
wire [7:0] bilinear0_out;
|
||||
wire [7:0] bilinear1_out;
|
||||
wire [7:0] bilinear2_out;
|
||||
wire [7:0] bilinear3_out;
|
||||
bilinear bilinear0 (
|
||||
.A(bilinear0_A),
|
||||
.B(bilinear0_B),
|
||||
.bilinear_out(bilinear0_out)
|
||||
);
|
||||
bilinear bilinear1 (
|
||||
.A(bilinear1_A),
|
||||
.B(bilinear1_B),
|
||||
.bilinear_out(bilinear1_out)
|
||||
);
|
||||
bilinear bilinear2 (
|
||||
.A(bilinear2_A),
|
||||
.B(bilinear2_B),
|
||||
.bilinear_out(bilinear2_out)
|
||||
);
|
||||
bilinear bilinear3 (
|
||||
.A(bilinear3_A),
|
||||
.B(bilinear3_B),
|
||||
.bilinear_out(bilinear3_out)
|
||||
);
|
||||
always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter
|
||||
or Inter_bi_window_0 or Inter_bi_window_1 or Inter_bi_window_2 or Inter_bi_window_3
|
||||
or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out
|
||||
or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out
|
||||
or b0_reg or b1_reg or b2_reg or b3_reg or h0_reg or h1_reg or h2_reg or h3_reg)
|
||||
if (IsInterLuma)
|
||||
case ({pos_FracL})
|
||||
`pos_a,`pos_c:
|
||||
if (blk4x4_inter_calculate_counter != 4'd0)
|
||||
begin
|
||||
bilinear0_A <= Inter_bi_window_0; bilinear0_B <= H_6tapfilter2_round_out;
|
||||
bilinear1_A <= Inter_bi_window_1; bilinear1_B <= H_6tapfilter3_round_out;
|
||||
bilinear2_A <= Inter_bi_window_2; bilinear2_B <= H_6tapfilter4_round_out;
|
||||
bilinear3_A <= Inter_bi_window_3; bilinear3_B <= H_6tapfilter5_round_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
`pos_d,`pos_n:
|
||||
if (blk4x4_inter_calculate_counter != 4'd0)
|
||||
begin
|
||||
bilinear0_A <= Inter_bi_window_0; bilinear0_B <= V_6tapfilter0_round_out;
|
||||
bilinear1_A <= Inter_bi_window_1; bilinear1_B <= V_6tapfilter1_round_out;
|
||||
bilinear2_A <= Inter_bi_window_2; bilinear2_B <= V_6tapfilter2_round_out;
|
||||
bilinear3_A <= Inter_bi_window_3; bilinear3_B <= V_6tapfilter3_round_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
`pos_e,`pos_g,`pos_p,`pos_r:
|
||||
if (blk4x4_inter_calculate_counter != 4'd0)
|
||||
begin
|
||||
bilinear0_A <= H_6tapfilter2_round_out; bilinear0_B <= V_6tapfilter0_round_out;
|
||||
bilinear1_A <= H_6tapfilter3_round_out; bilinear1_B <= V_6tapfilter1_round_out;
|
||||
bilinear2_A <= H_6tapfilter4_round_out; bilinear2_B <= V_6tapfilter2_round_out;
|
||||
bilinear3_A <= H_6tapfilter5_round_out; bilinear3_B <= V_6tapfilter3_round_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
`pos_i,`pos_k:
|
||||
if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 ||
|
||||
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)
|
||||
begin
|
||||
bilinear0_A <= h0_reg; bilinear0_B <= V_6tapfilter0_round_out;
|
||||
bilinear1_A <= h1_reg; bilinear1_B <= V_6tapfilter1_round_out;
|
||||
bilinear2_A <= h2_reg; bilinear2_B <= V_6tapfilter2_round_out;
|
||||
bilinear3_A <= h3_reg; bilinear3_B <= V_6tapfilter3_round_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
`pos_f,`pos_q:
|
||||
if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 4'd0)
|
||||
begin
|
||||
bilinear0_A <= b0_reg; bilinear0_B <= V_6tapfilter0_round_out;
|
||||
bilinear1_A <= b1_reg; bilinear1_B <= V_6tapfilter1_round_out;
|
||||
bilinear2_A <= b2_reg; bilinear2_B <= V_6tapfilter2_round_out;
|
||||
bilinear3_A <= b3_reg; bilinear3_B <= V_6tapfilter3_round_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0;
|
||||
bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0;
|
||||
end
|
||||
|
||||
//------------------------------------------------------------------------------------------
|
||||
//only "b","h" and "j" of half-pel positions need to be stored to predict quater-pel samples
|
||||
//------------------------------------------------------------------------------------------
|
||||
|
||||
//b0_raw_reg0 ~ b8_raw_reg:update after j/f/q/i/k horizontal filtering
|
||||
wire b_raw_reg_ena;
|
||||
assign b_raw_reg_ena = (IsInterLuma &&
|
||||
((pos_FracL == `pos_j && blk4x4_inter_calculate_counter != 4'd1 && blk4x4_inter_calculate_counter != 4'd0) ||
|
||||
((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 ||
|
||||
blk4x4_inter_calculate_counter == 4'd4 ||
|
||||
blk4x4_inter_calculate_counter == 4'd3 ||
|
||||
blk4x4_inter_calculate_counter == 4'd2)) ||
|
||||
((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 ||
|
||||
blk4x4_inter_calculate_counter == 4'd6 ||
|
||||
blk4x4_inter_calculate_counter == 4'd4 ||
|
||||
blk4x4_inter_calculate_counter == 4'd2))));
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
b0_raw_reg <= 0; b1_raw_reg <= 0; b2_raw_reg <= 0; b3_raw_reg <= 0; b4_raw_reg <= 0;
|
||||
b5_raw_reg <= 0; b6_raw_reg <= 0; b7_raw_reg <= 0; b8_raw_reg <= 0;
|
||||
end
|
||||
else if (b_raw_reg_ena)
|
||||
begin
|
||||
b0_raw_reg <= H_6tapfilter0_raw_out;b1_raw_reg <= H_6tapfilter1_raw_out;b2_raw_reg <= H_6tapfilter2_raw_out;
|
||||
b3_raw_reg <= H_6tapfilter3_raw_out;b4_raw_reg <= H_6tapfilter4_raw_out;b5_raw_reg <= H_6tapfilter5_raw_out;
|
||||
b6_raw_reg <= H_6tapfilter6_raw_out;b7_raw_reg <= H_6tapfilter7_raw_out;b8_raw_reg <= H_6tapfilter8_raw_out;
|
||||
end
|
||||
|
||||
//b0_reg ~ b3_reg:update for decoding f,q
|
||||
//Note:position q needs "b" of next line
|
||||
wire b_reg_ena;
|
||||
assign b_reg_ena = (IsInterLuma && ((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 ||
|
||||
blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd2)));
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
b0_reg <= 0; b1_reg <= 0; b2_reg <= 0; b3_reg <= 0;
|
||||
end
|
||||
else if (b_reg_ena)
|
||||
begin
|
||||
if (pos_FracL == `pos_q)
|
||||
begin
|
||||
b0_reg <= H_6tapfilter3_round_out; b1_reg <= H_6tapfilter4_round_out;
|
||||
b2_reg <= H_6tapfilter5_round_out; b3_reg <= H_6tapfilter6_round_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
b0_reg <= H_6tapfilter2_round_out; b1_reg <= H_6tapfilter3_round_out;
|
||||
b2_reg <= H_6tapfilter4_round_out; b3_reg <= H_6tapfilter5_round_out;
|
||||
end
|
||||
end
|
||||
|
||||
//h0_reg ~ h3_reg:update for decoding i,k
|
||||
wire h_reg_ena;
|
||||
assign h_reg_ena = (IsInterLuma && ((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 ||
|
||||
blk4x4_inter_calculate_counter == 4'd6 || blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd2)));
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
h0_reg <= 0; h1_reg <= 0; h2_reg <= 0; h3_reg <= 0;
|
||||
end
|
||||
else if (h_reg_ena)
|
||||
begin
|
||||
h0_reg <= V_6tapfilter0_round_out; h1_reg <= V_6tapfilter1_round_out;
|
||||
h2_reg <= V_6tapfilter2_round_out; h3_reg <= V_6tapfilter3_round_out;
|
||||
end
|
||||
//------------------------------------------------------------------------------------------
|
||||
//LPE output
|
||||
//------------------------------------------------------------------------------------------
|
||||
always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter
|
||||
or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out
|
||||
or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out
|
||||
or bilinear0_out or bilinear1_out or bilinear2_out or bilinear3_out)
|
||||
if (IsInterLuma)
|
||||
case (pos_FracL)
|
||||
//pos_Int: directly bypassed by Inter_pix_copy0 ~ Inter_pix_copy3
|
||||
`pos_b:
|
||||
if (blk4x4_inter_calculate_counter != 0)
|
||||
begin
|
||||
LPE0_out <= H_6tapfilter2_round_out; LPE1_out <= H_6tapfilter3_round_out;
|
||||
LPE2_out <= H_6tapfilter4_round_out; LPE3_out <= H_6tapfilter5_round_out;
|
||||
end
|
||||
else
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
`pos_h:
|
||||
if (blk4x4_inter_calculate_counter != 0)
|
||||
begin
|
||||
LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out;
|
||||
LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out;
|
||||
end
|
||||
else
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
`pos_j:
|
||||
if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 0)
|
||||
begin
|
||||
LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out;
|
||||
LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out;
|
||||
end
|
||||
else
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
`pos_a,`pos_c,`pos_d,`pos_e,`pos_g,`pos_n,`pos_p,`pos_r,`pos_f,`pos_q:
|
||||
if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 ||
|
||||
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)
|
||||
begin
|
||||
LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out;
|
||||
LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out;
|
||||
end
|
||||
else
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
`pos_i,`pos_k:
|
||||
if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 ||
|
||||
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)
|
||||
begin
|
||||
LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out;
|
||||
LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out;
|
||||
end
|
||||
else
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
default:
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
endcase
|
||||
else
|
||||
begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end
|
||||
|
||||
endmodule
|
||||
|
||||
module filterH_6tap(A,B,C,D,E,F,H_need_round,raw_out,round_out);
|
||||
input [7:0] A,B,C,D,E,F;
|
||||
input H_need_round;
|
||||
output [14:0] raw_out; //always output
|
||||
output [7:0] round_out;
|
||||
|
||||
wire [8:0] sum_AF;
|
||||
wire [8:0] sum_BE;
|
||||
wire [8:0] sum_CD;
|
||||
wire [10:0] sum_4CD;
|
||||
wire [11:0] sum_1;
|
||||
wire [12:0] sum_2;
|
||||
wire [13:0] sum_3;
|
||||
wire [14:0] sum_round;
|
||||
wire [9:0] round_tmp;
|
||||
|
||||
assign sum_AF = A + F;
|
||||
assign sum_BE = B + E;
|
||||
assign sum_CD = C + D;
|
||||
assign sum_4CD = {sum_CD,2'b0};
|
||||
assign sum_1 = {1'b0,sum_4CD} + {3'b111,~sum_BE} + 1;
|
||||
assign sum_2 = {4'b0,sum_AF} + {sum_1[11],sum_1};
|
||||
assign sum_3 = {sum_1,2'b0};
|
||||
assign raw_out = {{2{sum_2[12]}},sum_2} + {sum_3[13],sum_3};
|
||||
//round
|
||||
assign sum_round = (H_need_round)? (raw_out + 16):0;
|
||||
assign round_tmp = (H_need_round)? sum_round[14:5]:0;
|
||||
assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]);
|
||||
endmodule
|
||||
|
||||
module filterV_6tap(A,B,C,D,E,F,Is_jfqik,round_out);
|
||||
input [14:0] A,B,C,D,E,F;
|
||||
input Is_jfqik;
|
||||
output [7:0] round_out;
|
||||
|
||||
wire [15:0] sum_AF;
|
||||
wire [15:0] sum_BE;
|
||||
wire [15:0] sum_CD;
|
||||
wire [17:0] sum_4CD;
|
||||
wire [17:0] sum_1;
|
||||
wire [17:0] sum_2;
|
||||
wire [19:0] sum_3;
|
||||
wire [19:0] raw_out;
|
||||
|
||||
wire [19:0] sum_round;
|
||||
wire [9:0] round_tmp;
|
||||
|
||||
assign sum_AF = {A[14],A} + {F[14],F};
|
||||
assign sum_BE = {B[14],B} + {E[14],E};
|
||||
assign sum_CD = {C[14],C} + {D[14],D};
|
||||
assign sum_4CD = {sum_CD,2'b0};
|
||||
assign sum_1 = sum_4CD + {~sum_BE[15],~sum_BE[15],~sum_BE} + 1;
|
||||
assign sum_2 = {{2{sum_AF[15]}},sum_AF} + sum_1;
|
||||
assign sum_3 = {sum_1,2'b0};
|
||||
assign raw_out = {{2{sum_2[17]}},sum_2} + sum_3;
|
||||
//round
|
||||
assign sum_round = (Is_jfqik)? (raw_out + 512):(raw_out + 16);
|
||||
assign round_tmp = (Is_jfqik)? sum_round[19:10]:sum_round[14:5];
|
||||
assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]);
|
||||
endmodule
|
||||
|
||||
module bilinear (A,B,bilinear_out);
|
||||
input [7:0] A,B;
|
||||
output [7:0] bilinear_out;
|
||||
wire [8:0] sum_AB;
|
||||
|
||||
assign sum_AB = A + B + 1; //here A and B should NOT extend as {A[7],A}
|
||||
assign bilinear_out = sum_AB[8:1];
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,782 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Inter_pred_pipeline.v
|
||||
// Generated : Oct 4, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Inter prediction pipeline
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1.July 23,2006
|
||||
// Change the ext_frame_RAM from async read to sync read.Therefore,blk4x4_inter_preload_counter has to +1 for all the cases
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Inter_pred_pipeline (clk,reset_n,
|
||||
mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter,mb_type_general_bit3,
|
||||
mv_is16x16,mv_below8x8,
|
||||
mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,
|
||||
mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
|
||||
Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3,
|
||||
LPE0_out,LPE1_out,LPE2_out,LPE3_out,
|
||||
CPE0_out,CPE1_out,CPE2_out,CPE3_out,
|
||||
|
||||
mv_below8x8_curr,blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter,
|
||||
end_of_one_blk4x4_inter,IsInterLuma,IsInterChroma,Is_InterChromaCopy,
|
||||
xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC,
|
||||
Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,Inter_blk4x4_pred_output_valid,
|
||||
ref_frame_RAM_rd,ref_frame_RAM_rd_addr);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input [3:0] mb_num_h,mb_num_v;
|
||||
input trigger_blk4x4_inter_pred;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input mb_type_general_bit3;
|
||||
input mv_is16x16;
|
||||
input [3:0] mv_below8x8;
|
||||
input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
input [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3;
|
||||
input [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out;
|
||||
input [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out;
|
||||
|
||||
output mv_below8x8_curr;
|
||||
output [5:0] blk4x4_inter_preload_counter;
|
||||
output [3:0] blk4x4_inter_calculate_counter;
|
||||
output [1:0] Inter_chroma2x2_counter;
|
||||
output end_of_one_blk4x4_inter;
|
||||
output IsInterLuma,IsInterChroma;
|
||||
output Is_InterChromaCopy;
|
||||
output [8:0] xInt_addr_unclip;
|
||||
output [1:0] xInt_org_unclip_1to0;
|
||||
output [3:0] pos_FracL;
|
||||
output [2:0] xFracC,yFracC;
|
||||
output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
|
||||
output [1:0] Inter_blk4x4_pred_output_valid; //2'b01:luma output valid 2'b10:chroma output valid
|
||||
output ref_frame_RAM_rd;
|
||||
output [13:0] ref_frame_RAM_rd_addr;
|
||||
|
||||
reg [5:0] blk4x4_inter_preload_counter;
|
||||
reg [3:0] blk4x4_inter_calculate_counter;
|
||||
reg mv_below8x8_curr;
|
||||
reg [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
|
||||
reg [1:0] Inter_blk4x4_pred_output_valid;
|
||||
wire ref_frame_RAM_rd;
|
||||
wire IsInterLuma;
|
||||
wire IsInterChroma;
|
||||
wire [1:0] xFracL;
|
||||
wire [1:0] yFracL;
|
||||
wire [2:0] xFracC;
|
||||
wire [2:0] yFracC;
|
||||
wire [13:0] ref_frame_RAM_rd_addr;
|
||||
|
||||
assign IsInterLuma = (!mb_type_general_bit3 && blk4x4_rec_counter < 16)? 1'b1:1'b0;
|
||||
assign IsInterChroma = (!mb_type_general_bit3 && blk4x4_rec_counter > 15)? 1'b1:1'b0;
|
||||
//-------------------------------------------------------------------------
|
||||
//mv_below8x8_curr for each 2x2 Inter Chroma prediction
|
||||
//-------------------------------------------------------------------------
|
||||
always @ (IsInterLuma or IsInterChroma or blk4x4_rec_counter[3:0] or mv_below8x8)
|
||||
if (IsInterLuma)
|
||||
case (blk4x4_rec_counter[3:2])
|
||||
2'b00:mv_below8x8_curr <= mv_below8x8[0];
|
||||
2'b01:mv_below8x8_curr <= mv_below8x8[1];
|
||||
2'b10:mv_below8x8_curr <= mv_below8x8[2];
|
||||
2'b11:mv_below8x8_curr <= mv_below8x8[3];
|
||||
endcase
|
||||
else if (IsInterChroma)
|
||||
case (blk4x4_rec_counter[1:0])
|
||||
2'b00:mv_below8x8_curr <= mv_below8x8[0];
|
||||
2'b01:mv_below8x8_curr <= mv_below8x8[1];
|
||||
2'b10:mv_below8x8_curr <= mv_below8x8[2];
|
||||
2'b11:mv_below8x8_curr <= mv_below8x8[3];
|
||||
endcase
|
||||
else
|
||||
mv_below8x8_curr <= 0;
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Inter_chroma2x2_counter to guide the prediction of 2x2 chroma blocks
|
||||
//2'b11 -> 2'b10 -> 2'b01 -> 2'b00
|
||||
//----------------------------------------------------------------------------------------
|
||||
reg [1:0] Inter_chroma2x2_counter;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
Inter_chroma2x2_counter <= 0;
|
||||
//mv_below8x8_curr == 1'b1 includes the condition that "blk4x4_rec_counter > 15"
|
||||
else if (IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr)
|
||||
Inter_chroma2x2_counter <= 2'b11;
|
||||
else if (blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0)
|
||||
Inter_chroma2x2_counter <= Inter_chroma2x2_counter - 1;
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//trigger_blk2x2_inter_pred:only for chroma 2x2 decoding
|
||||
//We introduce this additional signal since we need Inter_chroma2x2_counter to update
|
||||
//one cycle before blk4x4_inter_calculate_counter
|
||||
//----------------------------------------------------------------------------------------
|
||||
reg trigger_blk2x2_inter_pred;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
trigger_blk2x2_inter_pred <= 0;
|
||||
else if ((IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) ||
|
||||
(blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0))
|
||||
trigger_blk2x2_inter_pred <= 1'b1;
|
||||
else
|
||||
trigger_blk2x2_inter_pred <= 1'b0;
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Inter motion vector for current 4x4 luma/chroma block or 2x2 chroma block
|
||||
// Inter_blk_mvx,Inter_blk_mvy
|
||||
//----------------------------------------------------------------------------------------
|
||||
reg [7:0] Inter_blk_mvx,Inter_blk_mvy;
|
||||
always @ (blk4x4_rec_counter or mv_below8x8_curr or Inter_chroma2x2_counter
|
||||
or IsInterLuma or IsInterChroma or mv_is16x16
|
||||
or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
||||
or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3)
|
||||
//Inter luma
|
||||
if (IsInterLuma)
|
||||
begin
|
||||
if (mv_is16x16)
|
||||
begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end
|
||||
else
|
||||
case (mv_below8x8_curr)
|
||||
1'b0:
|
||||
case (blk4x4_rec_counter[3:2])
|
||||
2'b00:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end
|
||||
2'b01:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end
|
||||
2'b10:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end
|
||||
2'b11:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end
|
||||
endcase
|
||||
1'b1:
|
||||
case (blk4x4_rec_counter)
|
||||
0 :begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end
|
||||
1 :begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end
|
||||
2 :begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end
|
||||
3 :begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end
|
||||
4 :begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end
|
||||
5 :begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end
|
||||
6 :begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end
|
||||
7 :begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end
|
||||
8 :begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end
|
||||
9 :begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end
|
||||
10:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end
|
||||
11:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end
|
||||
12:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end
|
||||
13:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end
|
||||
14:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end
|
||||
15:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end
|
||||
default:begin Inter_blk_mvx <= 0;Inter_blk_mvy <= 0; end
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
//Inter chroma
|
||||
else if (IsInterChroma)
|
||||
begin
|
||||
if (mv_is16x16)
|
||||
begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end
|
||||
else
|
||||
case (blk4x4_rec_counter[1:0])
|
||||
2'b00:
|
||||
if (mv_below8x8_curr) //chroma2x2 prediction
|
||||
case (Inter_chroma2x2_counter)
|
||||
3:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end
|
||||
2:begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end
|
||||
1:begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end
|
||||
0:begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end
|
||||
endcase
|
||||
else //chroma 4x4 prediction
|
||||
begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end
|
||||
2'b01:
|
||||
if (mv_below8x8_curr) //need chroma2x2 prediction
|
||||
case (Inter_chroma2x2_counter)
|
||||
3:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end
|
||||
2:begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end
|
||||
1:begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end
|
||||
0:begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end
|
||||
endcase
|
||||
else //chroma 4x4 prediction
|
||||
begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end
|
||||
2'b10:
|
||||
if (mv_below8x8_curr) //chroma2x2 prediction
|
||||
case (Inter_chroma2x2_counter)
|
||||
3:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end
|
||||
2:begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end
|
||||
1:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end
|
||||
0:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end
|
||||
endcase
|
||||
else //chroma 4x4 prediction
|
||||
begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end
|
||||
2'b11:
|
||||
if (mv_below8x8_curr) //chroma2x2 prediction
|
||||
case (Inter_chroma2x2_counter)
|
||||
3:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end
|
||||
2:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end
|
||||
1:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end
|
||||
0:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end
|
||||
endcase
|
||||
else //chroma 4x4 prediction
|
||||
begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin Inter_blk_mvx <= 0; Inter_blk_mvy <= 0; end
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Describes the offset of each blk4x4 inside a MB
|
||||
//----------------------------------------------------------------------------------------
|
||||
// xOffset = 0 for 0,2,8, 10 yOffset = 0 for 0, 1, 4, 5
|
||||
// xOffset = 4 for 1,3,9, 11 yOffset = 4 for 2, 3, 6, 7
|
||||
// xOffset = 8 for 4,6,12,14 yOffset = 8 for 8, 9, 12,13
|
||||
// xOffset = 12 for 5,7,13,15 yOffset = 12 for 10,11,14,15
|
||||
reg [3:0] xOffsetL,yOffsetL;
|
||||
always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[2] or blk4x4_rec_counter[0])
|
||||
if (IsInterLuma)
|
||||
begin
|
||||
if (!mv_below8x8_curr)
|
||||
xOffsetL <= (blk4x4_rec_counter[2])? 4'd8:4'd0;
|
||||
else
|
||||
case ({blk4x4_rec_counter[2],blk4x4_rec_counter[0]})
|
||||
2'b00:xOffsetL <= 4'd0;
|
||||
2'b01:xOffsetL <= 4'd4;
|
||||
2'b10:xOffsetL <= 4'd8;
|
||||
2'b11:xOffsetL <= 4'd12;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
xOffsetL <= 0;
|
||||
|
||||
always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[3] or blk4x4_rec_counter[1])
|
||||
if (IsInterLuma)
|
||||
begin
|
||||
if (!mv_below8x8_curr)
|
||||
yOffsetL <= (blk4x4_rec_counter[3])? 4'd8:4'd0;
|
||||
else
|
||||
case ({blk4x4_rec_counter[3],blk4x4_rec_counter[1]})
|
||||
2'b00:yOffsetL <= 4'd0;
|
||||
2'b01:yOffsetL <= 4'd4;
|
||||
2'b10:yOffsetL <= 4'd8;
|
||||
2'b11:yOffsetL <= 4'd12;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
yOffsetL <= 0;
|
||||
|
||||
reg [2:0] xOffsetC,yOffsetC;
|
||||
always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[0] or Inter_chroma2x2_counter[0])
|
||||
if (IsInterChroma)
|
||||
begin
|
||||
if (mv_below8x8_curr == 1'b0)
|
||||
xOffsetC <= (blk4x4_rec_counter[0] == 1'b0)? 3'd0:3'd4;
|
||||
else
|
||||
case (blk4x4_rec_counter[0])
|
||||
1'b0:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd0:3'd2;
|
||||
1'b1:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd4:3'd6;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
xOffsetC <= 0;
|
||||
|
||||
always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[1] or Inter_chroma2x2_counter[1])
|
||||
if (IsInterChroma)
|
||||
begin
|
||||
if (mv_below8x8_curr == 1'b0)
|
||||
yOffsetC <= (blk4x4_rec_counter[1] == 1'b0)? 3'd0:3'd4;
|
||||
else
|
||||
case (blk4x4_rec_counter[1])
|
||||
1'b0:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd0:3'd2;
|
||||
1'b1:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd4:3'd6;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
yOffsetC <= 3'd0;
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Integer position of each left-up-most pixel of a 8x8/4x4/2x2 blk
|
||||
//----------------------------------------------------------------------------------------
|
||||
wire [8:0] xIntL_unclip,yIntL_unclip; // 2's complement,bit[8] is the sign bit
|
||||
wire [7:0] xIntC_unclip,yIntC_unclip; // 2's complement,bit[7] is the sign bit
|
||||
assign xIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_h,4'b0} + xOffsetL + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:2]}):0;
|
||||
assign yIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_v,4'b0} + yOffsetL + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:2]}):0;
|
||||
assign xIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_h,3'b0} + xOffsetC + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:3]}):0;
|
||||
assign yIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_v,3'b0} + yOffsetC + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:3]}):0;
|
||||
|
||||
wire [8:0] xInt_org_unclip;
|
||||
wire [8:0] yInt_org_unclip;
|
||||
assign xInt_org_unclip = (IsInterLuma)? xIntL_unclip:{xIntC_unclip[7],xIntC_unclip};
|
||||
assign yInt_org_unclip = (IsInterLuma)? yIntL_unclip:{yIntC_unclip[7],yIntC_unclip};
|
||||
assign xInt_org_unclip_1to0 = xInt_org_unclip[1:0];
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Fractional motion vector for both luma and chroma
|
||||
//----------------------------------------------------------------------------------------
|
||||
wire [3:0] pos_FracL;
|
||||
wire Is_InterChromaCopy;//If chroma is predicted by direct copy,calculate cycle would reduce
|
||||
//from 16 cycles to 4 cycles
|
||||
|
||||
assign xFracL = (IsInterLuma)? Inter_blk_mvx[1:0]:0;
|
||||
assign yFracL = (IsInterLuma)? Inter_blk_mvy[1:0]:0;
|
||||
assign xFracC = (IsInterChroma)? Inter_blk_mvx[2:0]:0;
|
||||
assign yFracC = (IsInterChroma)? Inter_blk_mvy[2:0]:0;
|
||||
assign pos_FracL = {xFracL,yFracL};
|
||||
assign Is_InterChromaCopy = (IsInterChroma && xFracC == 0 && yFracC == 0)? 1'b1:1'b0;
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Inter prediction step control counter
|
||||
//----------------------------------------------------------------------------------------
|
||||
//1.Preload integer pels counter
|
||||
// If block partition equals 8x8 or above,preload only at first 4x4 block of each 8x8block
|
||||
// If block partition is 8x4,4x8 or 4x4, preload at each 4x4 block
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_inter_preload_counter <= 0;
|
||||
//luma
|
||||
else if (trigger_blk4x4_inter_pred && IsInterLuma)
|
||||
begin
|
||||
if (!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00)
|
||||
case (pos_FracL)
|
||||
`pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd17:6'd25;
|
||||
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd53;
|
||||
`pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd27:6'd40;
|
||||
`pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd33;
|
||||
`pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd49;
|
||||
endcase
|
||||
else if (mv_below8x8_curr) //partition below 8x8block
|
||||
case (pos_FracL)
|
||||
`pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9;
|
||||
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd28;
|
||||
`pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd10:6'd19;
|
||||
`pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd13;
|
||||
`pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd24;
|
||||
endcase
|
||||
end
|
||||
//chroma
|
||||
else if (trigger_blk4x4_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b0)
|
||||
begin
|
||||
if (xFracC == 0 && yFracC == 0)
|
||||
blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9;
|
||||
else
|
||||
blk4x4_inter_preload_counter <= 6'd11;
|
||||
end
|
||||
else if (trigger_blk2x2_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b1)
|
||||
begin
|
||||
if (xFracC == 0 && yFracC == 0)
|
||||
blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b11)? 6'd5:6'd3;
|
||||
else
|
||||
blk4x4_inter_preload_counter <= (xInt_org_unclip[1] == 1'b0 )? 6'd4:6'd7;
|
||||
end
|
||||
else if (blk4x4_inter_preload_counter != 0)
|
||||
blk4x4_inter_preload_counter <= blk4x4_inter_preload_counter - 1;
|
||||
|
||||
//2.Calculate counter
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_inter_calculate_counter <= 0;
|
||||
//luma
|
||||
else if (IsInterLuma && ((!mv_below8x8_curr && (
|
||||
(blk4x4_rec_counter[1:0] == 2'b00 && blk4x4_inter_preload_counter == 1) ||
|
||||
(blk4x4_rec_counter[1:0] != 2'b00 && trigger_blk4x4_inter_pred))) ||
|
||||
(mv_below8x8_curr && blk4x4_inter_preload_counter == 1)))
|
||||
case (pos_FracL)
|
||||
`pos_j,`pos_f,`pos_q:blk4x4_inter_calculate_counter <= 4'd5;
|
||||
`pos_i,`pos_k :blk4x4_inter_calculate_counter <= 4'd8;
|
||||
default :blk4x4_inter_calculate_counter <= 4'd4;
|
||||
endcase
|
||||
//chroma
|
||||
else if (blk4x4_inter_preload_counter == 1 && IsInterChroma == 1'b1)
|
||||
case (mv_below8x8_curr)
|
||||
1'b0:blk4x4_inter_calculate_counter <= 4'd4;
|
||||
1'b1:blk4x4_inter_calculate_counter <= 4'd1;
|
||||
endcase
|
||||
else if (blk4x4_inter_calculate_counter != 0)
|
||||
blk4x4_inter_calculate_counter <= blk4x4_inter_calculate_counter - 1;
|
||||
|
||||
assign end_of_one_blk4x4_inter = (blk4x4_inter_calculate_counter == 4'd1 &&
|
||||
((IsInterChroma && mv_below8x8_curr && Inter_chroma2x2_counter == 2'b00) ||
|
||||
!(IsInterChroma && mv_below8x8_curr)));
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Inter prediction reference frame RAM read control
|
||||
//----------------------------------------------------------------------------------------
|
||||
assign ref_frame_RAM_rd = ((IsInterLuma || IsInterChroma) && blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1);
|
||||
|
||||
//compared with blk4x4_inter_preload_counter,blk4x4_inter_preload_counter_m2 has some advantages
|
||||
//during some pos_FracL for vertical memory address decoding
|
||||
wire [5:0] blk4x4_inter_preload_counter_m2;
|
||||
assign blk4x4_inter_preload_counter_m2 = (blk4x4_inter_preload_counter == 6'd0 || blk4x4_inter_preload_counter == 6'd1)?
|
||||
6'd0:(blk4x4_inter_preload_counter - 2);
|
||||
|
||||
//xInt_curr_offset: offset from the left-upper most pixel of current block,ranging -2 ~ +10.
|
||||
//After each preload cycle,xInt_curr_offset will increase 4
|
||||
reg [4:0] xInt_curr_offset;
|
||||
always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC
|
||||
or xInt_org_unclip[1:0] or blk4x4_inter_preload_counter_m2 or blk4x4_inter_preload_counter)
|
||||
if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1)
|
||||
begin
|
||||
if (IsInterLuma)
|
||||
begin
|
||||
if (!mv_below8x8_curr)
|
||||
case (pos_FracL)
|
||||
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:
|
||||
case (blk4x4_inter_preload_counter_m2[1:0])
|
||||
2'b00:xInt_curr_offset <= 5'b01010; //+10
|
||||
2'b01:xInt_curr_offset <= 5'b00110; //+6
|
||||
2'b10:xInt_curr_offset <= 5'b00010; //+2
|
||||
2'b11:xInt_curr_offset <= 5'b11110; //-2
|
||||
endcase
|
||||
`pos_d,`pos_h,`pos_n:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 4'b0:4'b0100; //+0 or +4
|
||||
else
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd38,6'd35,6'd32,6'd29,6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2:
|
||||
xInt_curr_offset <= 5'b0; //+0
|
||||
6'd37,6'd34,6'd31,6'd28,6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1:
|
||||
xInt_curr_offset <= 5'b00100; //+4
|
||||
default:xInt_curr_offset <= 5'b01000;//+8
|
||||
endcase
|
||||
`pos_a,`pos_b,`pos_c:
|
||||
case (blk4x4_inter_preload_counter_m2[1:0])
|
||||
2'b00:xInt_curr_offset <= 5'b01010; //+10
|
||||
2'b01:xInt_curr_offset <= 5'b00110; //+6
|
||||
2'b10:xInt_curr_offset <= 5'b00010; //+2
|
||||
2'b11:xInt_curr_offset <= 5'b11110; //-2
|
||||
endcase
|
||||
`pos_Int:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b0100; //+0 or +4
|
||||
else
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2:
|
||||
xInt_curr_offset <= 5'b00000; //+0
|
||||
6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1:
|
||||
xInt_curr_offset <= 5'b00100; //+4
|
||||
default:xInt_curr_offset <= 5'b01000;//+8
|
||||
endcase
|
||||
`pos_e,`pos_g,`pos_p,`pos_r:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd47,6'd44,6'd5,6'd2:
|
||||
xInt_curr_offset <= 5'b00000; //+0
|
||||
6'd46,6'd43,6'd4,6'd1:
|
||||
xInt_curr_offset <= 5'b00100; //+4
|
||||
6'd45,6'd42,6'd3,6'd0:
|
||||
xInt_curr_offset <= 5'b01000; //+8
|
||||
default:
|
||||
case (blk4x4_inter_preload_counter_m2[1:0])
|
||||
2'b00:xInt_curr_offset <= 5'b00010; //+2
|
||||
2'b01:xInt_curr_offset <= 5'b11110; //-2
|
||||
2'b10:xInt_curr_offset <= 5'b01010; //+10
|
||||
2'b11:xInt_curr_offset <= 5'b00110; //+6
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
else //block partition below 8x8
|
||||
case (pos_FracL)
|
||||
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110;//-2
|
||||
6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010;//+2
|
||||
default:xInt_curr_offset <= 5'b00110; //+6
|
||||
endcase
|
||||
`pos_d,`pos_h,`pos_n:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
xInt_curr_offset <= 5'b0; //+0
|
||||
else
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100;//+0 or +4
|
||||
`pos_a,`pos_b,`pos_c:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110; //-2
|
||||
6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010; //+2
|
||||
default:xInt_curr_offset <= 5'b00110; //+6
|
||||
endcase
|
||||
`pos_Int:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
xInt_curr_offset <= 5'b0; //+0
|
||||
else
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100; //+0 or +4
|
||||
`pos_e,`pos_g,`pos_p,`pos_r:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd22,6'd20,6'd3,6'd1:xInt_curr_offset <= 5'b0; //+0
|
||||
6'd21,6'd19,6'd2,6'd0:xInt_curr_offset <= 5'b00100; //+4
|
||||
6'd18,6'd15,6'd12,6'd9,6'd6:xInt_curr_offset <= 5'b11110;//-2
|
||||
6'd17,6'd14,6'd11,6'd8,6'd5:xInt_curr_offset <= 5'b00010;//+2
|
||||
6'd16,6'd13,6'd10,6'd7,6'd4:xInt_curr_offset <= 5'b00110;//+6
|
||||
default:xInt_curr_offset <= 5'b0;
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
else //IsInterChroma
|
||||
begin
|
||||
if (!mv_below8x8_curr)
|
||||
begin
|
||||
if (xFracC == 0 && yFracC == 0)
|
||||
begin
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
xInt_curr_offset <= 5'b0;
|
||||
else
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100;
|
||||
end
|
||||
else
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100;
|
||||
end
|
||||
else //mv_below8x8_curr == 1'b1
|
||||
begin
|
||||
if (xFracC == 0 && yFracC == 0)
|
||||
begin
|
||||
if (xInt_org_unclip[1:0] == 2'b11) // 4 preload cycles
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100;
|
||||
else
|
||||
xInt_curr_offset <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (xInt_org_unclip[1] == 1'b0)
|
||||
xInt_curr_offset <= 0;
|
||||
else
|
||||
xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
else //blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1
|
||||
xInt_curr_offset <= 5'b0;
|
||||
|
||||
//Derive unclipped x pos for each preload cycle
|
||||
wire [8:0] xInt_addr_unclip;
|
||||
assign xInt_addr_unclip = xInt_org_unclip + {{4{xInt_curr_offset[4]}},xInt_curr_offset};
|
||||
|
||||
//x addr clipped:x address in pixels
|
||||
reg [7:0] xInt_addr;
|
||||
always @ (xInt_addr_unclip or IsInterLuma or IsInterChroma)
|
||||
if (xInt_addr_unclip[8] == 1'b1) //negative
|
||||
xInt_addr <= 0;
|
||||
else if (IsInterLuma)
|
||||
xInt_addr <= (xInt_addr_unclip[7:0] > (`pic_width - 4))? 8'd172:xInt_addr_unclip[7:0];
|
||||
else if (IsInterChroma)
|
||||
xInt_addr <= (xInt_addr_unclip[7:0] > (`half_pic_width - 4))? 8'd84:xInt_addr_unclip[7:0];
|
||||
else
|
||||
xInt_addr <= 0;
|
||||
|
||||
//yInt_p1:when loading from Xth line to (X-1)th line,yInt_p1 is set to 1'b1 at the last
|
||||
//loading cycle of current Xth line
|
||||
reg yInt_p1;
|
||||
always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC
|
||||
or blk4x4_inter_preload_counter or blk4x4_inter_preload_counter_m2 or xInt_org_unclip[1:0] or xInt_org_unclip[1])
|
||||
if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1)
|
||||
begin
|
||||
if (IsInterLuma)
|
||||
case (mv_below8x8_curr)
|
||||
1'b0:
|
||||
case (pos_FracL)
|
||||
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0;
|
||||
`pos_d,`pos_h,`pos_n:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
else
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd36,6'd33,6'd30,6'd27,6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:
|
||||
yInt_p1 <= 1'b1;
|
||||
default:yInt_p1 <= 1'b0;
|
||||
endcase
|
||||
`pos_a,`pos_b,`pos_c:
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0;
|
||||
`pos_Int:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
else
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1;
|
||||
default: yInt_p1 <= 1'b0;
|
||||
endcase
|
||||
`pos_e,`pos_g,`pos_p,`pos_r:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd45,6'd42,6'd3,6'd0:yInt_p1 <= 1'b1;
|
||||
6'd6,6'd10,6'd14,6'd18,6'd22,6'd26,6'd30,6'd34,6'd38:yInt_p1 <= 1'b1;
|
||||
default:yInt_p1 <= 1'b0;
|
||||
endcase
|
||||
endcase
|
||||
1'b1: //block partition below 8x8
|
||||
case (pos_FracL)
|
||||
`pos_f,`pos_q,`pos_i,`pos_k,`pos_j:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1;
|
||||
default:yInt_p1 <= 1'b0;
|
||||
endcase
|
||||
`pos_d,`pos_h,`pos_n:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
yInt_p1 <= 1'b1;
|
||||
else
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
`pos_a,`pos_b,`pos_c:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
5'd9,5'd6,5'd3,5'd0 :yInt_p1 <= 1'b1;
|
||||
default :yInt_p1 <= 1'b0;
|
||||
endcase
|
||||
`pos_Int:
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
yInt_p1 <= 1'b1;
|
||||
else
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
`pos_e,`pos_g,`pos_p,`pos_r:
|
||||
case (blk4x4_inter_preload_counter_m2)
|
||||
6'd21,6'd19,6'd2,6'd0 :yInt_p1 <= 1'b1;
|
||||
6'd4,6'd7,6'd10,6'd13,6'd16 :yInt_p1 <= 1'b1;
|
||||
default :yInt_p1 <= 1'b0;
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
else //IsInterChroma
|
||||
case (mv_below8x8_curr)
|
||||
1'b0:
|
||||
if (xFracC == 0 && yFracC == 0)
|
||||
begin
|
||||
if (xInt_org_unclip[1:0] == 2'b00)
|
||||
yInt_p1 <= 1'b1;
|
||||
else
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
end
|
||||
else
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
1'b1:
|
||||
if (xFracC == 0 && yFracC == 0)
|
||||
begin
|
||||
if (xInt_org_unclip[1:0] != 2'b11)
|
||||
yInt_p1 <= 1'b1;
|
||||
else
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (xInt_org_unclip[1] == 1'b0)
|
||||
yInt_p1 <= 1'b1;
|
||||
else
|
||||
yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else // blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1
|
||||
yInt_p1 <= 1'b0;
|
||||
|
||||
//Derive unclipped y pos for each preload cycle
|
||||
reg [8:0] yInt_addr_unclip;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
yInt_addr_unclip <= 0;
|
||||
else if ((IsInterLuma && (trigger_blk4x4_inter_pred && (mv_below8x8_curr ||
|
||||
(!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00)))) ||
|
||||
(IsInterChroma && (!mv_below8x8_curr && trigger_blk4x4_inter_pred) ||
|
||||
(mv_below8x8_curr && trigger_blk2x2_inter_pred)))
|
||||
begin
|
||||
if (IsInterLuma) //Luma
|
||||
case (pos_FracL)
|
||||
`pos_a,`pos_b,`pos_c,`pos_Int:
|
||||
yInt_addr_unclip <= yInt_org_unclip;
|
||||
default: //need -2 here
|
||||
yInt_addr_unclip <= yInt_org_unclip + 9'b111111110;
|
||||
endcase
|
||||
else //Chroma
|
||||
yInt_addr_unclip <= yInt_org_unclip;
|
||||
end
|
||||
else if (blk4x4_inter_preload_counter_m2 != 0 && yInt_p1 == 1'b1)
|
||||
yInt_addr_unclip <= yInt_addr_unclip + 1;
|
||||
|
||||
//y addr clipped
|
||||
reg [7:0] yInt_addr;
|
||||
always @ (yInt_addr_unclip or IsInterLuma or IsInterChroma)
|
||||
if (yInt_addr_unclip[8] == 1'b1) //negative
|
||||
yInt_addr <= 0;
|
||||
else if (IsInterLuma)
|
||||
yInt_addr <= (yInt_addr_unclip[7:0] > (`pic_height - 1))? 8'd143:yInt_addr_unclip[7:0];
|
||||
else if (IsInterChroma)
|
||||
yInt_addr <= (yInt_addr_unclip[7:0] > (`half_pic_height - 1))? 8'd71:yInt_addr_unclip[7:0];
|
||||
else
|
||||
yInt_addr <= 0;
|
||||
|
||||
wire [12:0] offset_constant;
|
||||
wire [10:0] yInt_addr_x11;
|
||||
wire [12:0] offset_yInt_addr;
|
||||
assign offset_constant = (IsInterLuma)? 0:((IsInterChroma)? ((blk4x4_rec_counter < 5'd20)? 13'd6336:13'd7920):0);
|
||||
assign yInt_addr_x11 = {yInt_addr,3'b0} + {2'b0,yInt_addr,1'b0} + {3'b0,yInt_addr};
|
||||
assign offset_yInt_addr = (IsInterLuma)? {yInt_addr_x11,2'b0}:{1'b0,yInt_addr_x11,1'b0};
|
||||
assign ref_frame_RAM_rd_addr = (offset_constant + {8'b0,xInt_addr[7:2]}) + {1'b0,offset_yInt_addr};
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Inter prediction output control: from LPE or from CPE
|
||||
//----------------------------------------------------------------------------------------
|
||||
always @ (IsInterLuma or IsInterChroma or Is_InterChromaCopy
|
||||
or blk4x4_inter_calculate_counter or pos_FracL
|
||||
or Inter_pix_copy0 or Inter_pix_copy1 or Inter_pix_copy2 or Inter_pix_copy3
|
||||
or LPE0_out or LPE1_out or LPE2_out or LPE3_out
|
||||
or CPE0_out or CPE1_out or CPE2_out or CPE3_out)
|
||||
if (IsInterLuma && blk4x4_inter_calculate_counter != 0)
|
||||
begin
|
||||
Inter_blk4x4_pred_output_valid <= 2'b01;
|
||||
case (pos_FracL)
|
||||
`pos_Int:
|
||||
begin
|
||||
Inter_pred_out0 <= Inter_pix_copy0;Inter_pred_out1 <= Inter_pix_copy1;
|
||||
Inter_pred_out2 <= Inter_pix_copy2;Inter_pred_out3 <= Inter_pix_copy3;
|
||||
end
|
||||
`pos_i,`pos_k:
|
||||
if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 ||
|
||||
blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)
|
||||
begin
|
||||
Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out;
|
||||
Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0;
|
||||
end
|
||||
default:
|
||||
if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 ||
|
||||
blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)
|
||||
begin
|
||||
Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out;
|
||||
Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if (IsInterChroma && blk4x4_inter_calculate_counter != 0)
|
||||
begin
|
||||
Inter_pred_out0 <= (Is_InterChromaCopy)? Inter_pix_copy0:CPE0_out;
|
||||
Inter_pred_out1 <= (Is_InterChromaCopy)? Inter_pix_copy1:CPE1_out;
|
||||
Inter_pred_out2 <= (Is_InterChromaCopy)? Inter_pix_copy2:CPE2_out;
|
||||
Inter_pred_out3 <= (Is_InterChromaCopy)? Inter_pix_copy3:CPE3_out;
|
||||
Inter_blk4x4_pred_output_valid <= 2'b10;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0;
|
||||
Inter_blk4x4_pred_output_valid <= 2'b00;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,703 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Inter_pred_top.v
|
||||
// Generated : Oct 28, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Top module of Inter prediction, including
|
||||
// Inter_pred_pipeline.v
|
||||
// Inter_pred_reg_control.v
|
||||
// Inter_pred_sliding_window.v
|
||||
// Inter_pred_LPE.v
|
||||
// Inter_pred_CPE.v
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Inter_pred_top (clk,gclk_Inter_ref_rf,reset_n,mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter,
|
||||
mb_type_general_bit3,mv_is16x16,mv_below8x8,mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,
|
||||
mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,ref_frame_RAM_dout,
|
||||
|
||||
Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,
|
||||
blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter,
|
||||
mv_below8x8_curr,pos_FracL,end_of_one_blk4x4_inter,Inter_blk4x4_pred_output_valid,
|
||||
ref_frame_RAM_rd,ref_frame_RAM_rd_addr);
|
||||
input clk;
|
||||
input gclk_Inter_ref_rf;
|
||||
input reset_n;
|
||||
input [3:0] mb_num_h,mb_num_v;
|
||||
input trigger_blk4x4_inter_pred;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input mb_type_general_bit3;
|
||||
input mv_is16x16;
|
||||
input [3:0] mv_below8x8;
|
||||
input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
input [31:0] ref_frame_RAM_dout;
|
||||
|
||||
output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
|
||||
output [5:0] blk4x4_inter_preload_counter;
|
||||
output [3:0] blk4x4_inter_calculate_counter;
|
||||
output [1:0] Inter_chroma2x2_counter;
|
||||
output mv_below8x8_curr;
|
||||
output [3:0] pos_FracL;
|
||||
output end_of_one_blk4x4_inter;
|
||||
output [1:0] Inter_blk4x4_pred_output_valid;
|
||||
output ref_frame_RAM_rd;
|
||||
output [13:0] ref_frame_RAM_rd_addr;
|
||||
|
||||
wire [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out;
|
||||
wire [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out;
|
||||
wire [5:0] blk4x4_inter_preload_counter;
|
||||
wire mv_below8x8_curr;
|
||||
wire IsInterLuma,IsInterChroma;
|
||||
wire Is_InterChromaCopy;
|
||||
wire [8:0] xInt_addr_unclip;
|
||||
wire [1:0] xInt_org_unclip_1to0;
|
||||
wire [2:0] xFracC,yFracC;
|
||||
|
||||
wire [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00;
|
||||
wire [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00;
|
||||
wire [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01;
|
||||
wire [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01;
|
||||
wire [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02;
|
||||
wire [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02;
|
||||
wire [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03;
|
||||
wire [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03;
|
||||
wire [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04;
|
||||
wire [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04;
|
||||
wire [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05;
|
||||
wire [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05;
|
||||
wire [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06;
|
||||
wire [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06;
|
||||
wire [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07;
|
||||
wire [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07;
|
||||
wire [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08;
|
||||
wire [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08;
|
||||
wire [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09;
|
||||
wire [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09;
|
||||
wire [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10;
|
||||
wire [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10;
|
||||
wire [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11;
|
||||
wire [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11;
|
||||
wire [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12;
|
||||
wire [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12;
|
||||
|
||||
wire [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3;
|
||||
wire [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0;
|
||||
wire [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1;
|
||||
wire [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2;
|
||||
wire [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3;
|
||||
wire [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4;
|
||||
wire [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5;
|
||||
wire [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6;
|
||||
wire [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7;
|
||||
wire [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8;
|
||||
wire [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4;
|
||||
wire [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8;
|
||||
wire [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0;
|
||||
wire [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1;
|
||||
wire [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2;
|
||||
wire [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3;
|
||||
|
||||
Inter_pred_pipeline Inter_pred_pipeline(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.mb_type_general_bit3(mb_type_general_bit3),
|
||||
.mv_is16x16(mv_is16x16),
|
||||
.mv_below8x8(mv_below8x8),
|
||||
.mvx_CurrMb0(mvx_CurrMb0),
|
||||
.mvx_CurrMb1(mvx_CurrMb1),
|
||||
.mvx_CurrMb2(mvx_CurrMb2),
|
||||
.mvx_CurrMb3(mvx_CurrMb3),
|
||||
.mvy_CurrMb0(mvy_CurrMb0),
|
||||
.mvy_CurrMb1(mvy_CurrMb1),
|
||||
.mvy_CurrMb2(mvy_CurrMb2),
|
||||
.mvy_CurrMb3(mvy_CurrMb3),
|
||||
.Inter_pix_copy0(Inter_pix_copy0),
|
||||
.Inter_pix_copy1(Inter_pix_copy1),
|
||||
.Inter_pix_copy2(Inter_pix_copy2),
|
||||
.Inter_pix_copy3(Inter_pix_copy3),
|
||||
.LPE0_out(LPE0_out),
|
||||
.LPE1_out(LPE1_out),
|
||||
.LPE2_out(LPE2_out),
|
||||
.LPE3_out(LPE3_out),
|
||||
.CPE0_out(CPE0_out),
|
||||
.CPE1_out(CPE1_out),
|
||||
.CPE2_out(CPE2_out),
|
||||
.CPE3_out(CPE3_out),
|
||||
|
||||
.mv_below8x8_curr(mv_below8x8_curr),
|
||||
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter),
|
||||
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
||||
.Inter_chroma2x2_counter(Inter_chroma2x2_counter),
|
||||
.end_of_one_blk4x4_inter(end_of_one_blk4x4_inter),
|
||||
.IsInterLuma(IsInterLuma),
|
||||
.IsInterChroma(IsInterChroma),
|
||||
.Is_InterChromaCopy(Is_InterChromaCopy),
|
||||
.xInt_addr_unclip(xInt_addr_unclip),
|
||||
.xInt_org_unclip_1to0(xInt_org_unclip_1to0),
|
||||
.pos_FracL(pos_FracL),
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.Inter_pred_out0(Inter_pred_out0),
|
||||
.Inter_pred_out1(Inter_pred_out1),
|
||||
.Inter_pred_out2(Inter_pred_out2),
|
||||
.Inter_pred_out3(Inter_pred_out3),
|
||||
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
|
||||
.ref_frame_RAM_rd(ref_frame_RAM_rd),
|
||||
.ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr)
|
||||
);
|
||||
|
||||
Inter_pred_reg_ctrl Inter_pred_reg_ctrl (
|
||||
.gclk_Inter_ref_rf(gclk_Inter_ref_rf),
|
||||
.reset_n(reset_n),
|
||||
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter),
|
||||
.ref_frame_RAM_dout(ref_frame_RAM_dout),
|
||||
.IsInterLuma(IsInterLuma),
|
||||
.IsInterChroma(IsInterChroma),
|
||||
.xInt_addr_unclip(xInt_addr_unclip),
|
||||
.xInt_org_unclip_1to0(xInt_org_unclip_1to0),
|
||||
.pos_FracL(pos_FracL),
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.mv_below8x8_curr(mv_below8x8_curr),
|
||||
|
||||
.Inter_ref_00_00(Inter_ref_00_00),
|
||||
.Inter_ref_01_00(Inter_ref_01_00),
|
||||
.Inter_ref_02_00(Inter_ref_02_00),
|
||||
.Inter_ref_03_00(Inter_ref_03_00),
|
||||
.Inter_ref_04_00(Inter_ref_04_00),
|
||||
.Inter_ref_05_00(Inter_ref_05_00),
|
||||
.Inter_ref_06_00(Inter_ref_06_00),
|
||||
.Inter_ref_07_00(Inter_ref_07_00),
|
||||
.Inter_ref_08_00(Inter_ref_08_00),
|
||||
.Inter_ref_09_00(Inter_ref_09_00),
|
||||
.Inter_ref_10_00(Inter_ref_10_00),
|
||||
.Inter_ref_11_00(Inter_ref_11_00),
|
||||
.Inter_ref_12_00(Inter_ref_12_00),
|
||||
.Inter_ref_00_01(Inter_ref_00_01),
|
||||
.Inter_ref_01_01(Inter_ref_01_01),
|
||||
.Inter_ref_02_01(Inter_ref_02_01),
|
||||
.Inter_ref_03_01(Inter_ref_03_01),
|
||||
.Inter_ref_04_01(Inter_ref_04_01),
|
||||
.Inter_ref_05_01(Inter_ref_05_01),
|
||||
.Inter_ref_06_01(Inter_ref_06_01),
|
||||
.Inter_ref_07_01(Inter_ref_07_01),
|
||||
.Inter_ref_08_01(Inter_ref_08_01),
|
||||
.Inter_ref_09_01(Inter_ref_09_01),
|
||||
.Inter_ref_10_01(Inter_ref_10_01),
|
||||
.Inter_ref_11_01(Inter_ref_11_01),
|
||||
.Inter_ref_12_01(Inter_ref_12_01),
|
||||
.Inter_ref_00_02(Inter_ref_00_02),
|
||||
.Inter_ref_01_02(Inter_ref_01_02),
|
||||
.Inter_ref_02_02(Inter_ref_02_02),
|
||||
.Inter_ref_03_02(Inter_ref_03_02),
|
||||
.Inter_ref_04_02(Inter_ref_04_02),
|
||||
.Inter_ref_05_02(Inter_ref_05_02),
|
||||
.Inter_ref_06_02(Inter_ref_06_02),
|
||||
.Inter_ref_07_02(Inter_ref_07_02),
|
||||
.Inter_ref_08_02(Inter_ref_08_02),
|
||||
.Inter_ref_09_02(Inter_ref_09_02),
|
||||
.Inter_ref_10_02(Inter_ref_10_02),
|
||||
.Inter_ref_11_02(Inter_ref_11_02),
|
||||
.Inter_ref_12_02(Inter_ref_12_02),
|
||||
.Inter_ref_00_03(Inter_ref_00_03),
|
||||
.Inter_ref_01_03(Inter_ref_01_03),
|
||||
.Inter_ref_02_03(Inter_ref_02_03),
|
||||
.Inter_ref_03_03(Inter_ref_03_03),
|
||||
.Inter_ref_04_03(Inter_ref_04_03),
|
||||
.Inter_ref_05_03(Inter_ref_05_03),
|
||||
.Inter_ref_06_03(Inter_ref_06_03),
|
||||
.Inter_ref_07_03(Inter_ref_07_03),
|
||||
.Inter_ref_08_03(Inter_ref_08_03),
|
||||
.Inter_ref_09_03(Inter_ref_09_03),
|
||||
.Inter_ref_10_03(Inter_ref_10_03),
|
||||
.Inter_ref_11_03(Inter_ref_11_03),
|
||||
.Inter_ref_12_03(Inter_ref_12_03),
|
||||
.Inter_ref_00_04(Inter_ref_00_04),
|
||||
.Inter_ref_01_04(Inter_ref_01_04),
|
||||
.Inter_ref_02_04(Inter_ref_02_04),
|
||||
.Inter_ref_03_04(Inter_ref_03_04),
|
||||
.Inter_ref_04_04(Inter_ref_04_04),
|
||||
.Inter_ref_05_04(Inter_ref_05_04),
|
||||
.Inter_ref_06_04(Inter_ref_06_04),
|
||||
.Inter_ref_07_04(Inter_ref_07_04),
|
||||
.Inter_ref_08_04(Inter_ref_08_04),
|
||||
.Inter_ref_09_04(Inter_ref_09_04),
|
||||
.Inter_ref_10_04(Inter_ref_10_04),
|
||||
.Inter_ref_11_04(Inter_ref_11_04),
|
||||
.Inter_ref_12_04(Inter_ref_12_04),
|
||||
.Inter_ref_00_05(Inter_ref_00_05),
|
||||
.Inter_ref_01_05(Inter_ref_01_05),
|
||||
.Inter_ref_02_05(Inter_ref_02_05),
|
||||
.Inter_ref_03_05(Inter_ref_03_05),
|
||||
.Inter_ref_04_05(Inter_ref_04_05),
|
||||
.Inter_ref_05_05(Inter_ref_05_05),
|
||||
.Inter_ref_06_05(Inter_ref_06_05),
|
||||
.Inter_ref_07_05(Inter_ref_07_05),
|
||||
.Inter_ref_08_05(Inter_ref_08_05),
|
||||
.Inter_ref_09_05(Inter_ref_09_05),
|
||||
.Inter_ref_10_05(Inter_ref_10_05),
|
||||
.Inter_ref_11_05(Inter_ref_11_05),
|
||||
.Inter_ref_12_05(Inter_ref_12_05),
|
||||
.Inter_ref_00_06(Inter_ref_00_06),
|
||||
.Inter_ref_01_06(Inter_ref_01_06),
|
||||
.Inter_ref_02_06(Inter_ref_02_06),
|
||||
.Inter_ref_03_06(Inter_ref_03_06),
|
||||
.Inter_ref_04_06(Inter_ref_04_06),
|
||||
.Inter_ref_05_06(Inter_ref_05_06),
|
||||
.Inter_ref_06_06(Inter_ref_06_06),
|
||||
.Inter_ref_07_06(Inter_ref_07_06),
|
||||
.Inter_ref_08_06(Inter_ref_08_06),
|
||||
.Inter_ref_09_06(Inter_ref_09_06),
|
||||
.Inter_ref_10_06(Inter_ref_10_06),
|
||||
.Inter_ref_11_06(Inter_ref_11_06),
|
||||
.Inter_ref_12_06(Inter_ref_12_06),
|
||||
.Inter_ref_00_07(Inter_ref_00_07),
|
||||
.Inter_ref_01_07(Inter_ref_01_07),
|
||||
.Inter_ref_02_07(Inter_ref_02_07),
|
||||
.Inter_ref_03_07(Inter_ref_03_07),
|
||||
.Inter_ref_04_07(Inter_ref_04_07),
|
||||
.Inter_ref_05_07(Inter_ref_05_07),
|
||||
.Inter_ref_06_07(Inter_ref_06_07),
|
||||
.Inter_ref_07_07(Inter_ref_07_07),
|
||||
.Inter_ref_08_07(Inter_ref_08_07),
|
||||
.Inter_ref_09_07(Inter_ref_09_07),
|
||||
.Inter_ref_10_07(Inter_ref_10_07),
|
||||
.Inter_ref_11_07(Inter_ref_11_07),
|
||||
.Inter_ref_12_07(Inter_ref_12_07),
|
||||
.Inter_ref_00_08(Inter_ref_00_08),
|
||||
.Inter_ref_01_08(Inter_ref_01_08),
|
||||
.Inter_ref_02_08(Inter_ref_02_08),
|
||||
.Inter_ref_03_08(Inter_ref_03_08),
|
||||
.Inter_ref_04_08(Inter_ref_04_08),
|
||||
.Inter_ref_05_08(Inter_ref_05_08),
|
||||
.Inter_ref_06_08(Inter_ref_06_08),
|
||||
.Inter_ref_07_08(Inter_ref_07_08),
|
||||
.Inter_ref_08_08(Inter_ref_08_08),
|
||||
.Inter_ref_09_08(Inter_ref_09_08),
|
||||
.Inter_ref_10_08(Inter_ref_10_08),
|
||||
.Inter_ref_11_08(Inter_ref_11_08),
|
||||
.Inter_ref_12_08(Inter_ref_12_08),
|
||||
.Inter_ref_00_09(Inter_ref_00_09),
|
||||
.Inter_ref_01_09(Inter_ref_01_09),
|
||||
.Inter_ref_02_09(Inter_ref_02_09),
|
||||
.Inter_ref_03_09(Inter_ref_03_09),
|
||||
.Inter_ref_04_09(Inter_ref_04_09),
|
||||
.Inter_ref_05_09(Inter_ref_05_09),
|
||||
.Inter_ref_06_09(Inter_ref_06_09),
|
||||
.Inter_ref_07_09(Inter_ref_07_09),
|
||||
.Inter_ref_08_09(Inter_ref_08_09),
|
||||
.Inter_ref_09_09(Inter_ref_09_09),
|
||||
.Inter_ref_10_09(Inter_ref_10_09),
|
||||
.Inter_ref_11_09(Inter_ref_11_09),
|
||||
.Inter_ref_12_09(Inter_ref_12_09),
|
||||
.Inter_ref_00_10(Inter_ref_00_10),
|
||||
.Inter_ref_01_10(Inter_ref_01_10),
|
||||
.Inter_ref_02_10(Inter_ref_02_10),
|
||||
.Inter_ref_03_10(Inter_ref_03_10),
|
||||
.Inter_ref_04_10(Inter_ref_04_10),
|
||||
.Inter_ref_05_10(Inter_ref_05_10),
|
||||
.Inter_ref_06_10(Inter_ref_06_10),
|
||||
.Inter_ref_07_10(Inter_ref_07_10),
|
||||
.Inter_ref_08_10(Inter_ref_08_10),
|
||||
.Inter_ref_09_10(Inter_ref_09_10),
|
||||
.Inter_ref_10_10(Inter_ref_10_10),
|
||||
.Inter_ref_11_10(Inter_ref_11_10),
|
||||
.Inter_ref_12_10(Inter_ref_12_10),
|
||||
.Inter_ref_00_11(Inter_ref_00_11),
|
||||
.Inter_ref_01_11(Inter_ref_01_11),
|
||||
.Inter_ref_02_11(Inter_ref_02_11),
|
||||
.Inter_ref_03_11(Inter_ref_03_11),
|
||||
.Inter_ref_04_11(Inter_ref_04_11),
|
||||
.Inter_ref_05_11(Inter_ref_05_11),
|
||||
.Inter_ref_06_11(Inter_ref_06_11),
|
||||
.Inter_ref_07_11(Inter_ref_07_11),
|
||||
.Inter_ref_08_11(Inter_ref_08_11),
|
||||
.Inter_ref_09_11(Inter_ref_09_11),
|
||||
.Inter_ref_10_11(Inter_ref_10_11),
|
||||
.Inter_ref_11_11(Inter_ref_11_11),
|
||||
.Inter_ref_12_11(Inter_ref_12_11),
|
||||
.Inter_ref_00_12(Inter_ref_00_12),
|
||||
.Inter_ref_01_12(Inter_ref_01_12),
|
||||
.Inter_ref_02_12(Inter_ref_02_12),
|
||||
.Inter_ref_03_12(Inter_ref_03_12),
|
||||
.Inter_ref_04_12(Inter_ref_04_12),
|
||||
.Inter_ref_05_12(Inter_ref_05_12),
|
||||
.Inter_ref_06_12(Inter_ref_06_12),
|
||||
.Inter_ref_07_12(Inter_ref_07_12),
|
||||
.Inter_ref_08_12(Inter_ref_08_12),
|
||||
.Inter_ref_09_12(Inter_ref_09_12),
|
||||
.Inter_ref_10_12(Inter_ref_10_12),
|
||||
.Inter_ref_11_12(Inter_ref_11_12),
|
||||
.Inter_ref_12_12(Inter_ref_12_12)
|
||||
);
|
||||
Inter_pred_sliding_window Inter_pred_sliding_window (
|
||||
.IsInterLuma(IsInterLuma),
|
||||
.IsInterChroma(IsInterChroma),
|
||||
.Is_InterChromaCopy(Is_InterChromaCopy),
|
||||
.mv_below8x8_curr(mv_below8x8_curr),
|
||||
.pos_FracL(pos_FracL),
|
||||
.blk4x4_rec_counter_1to0(blk4x4_rec_counter[1:0]),
|
||||
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
||||
.Inter_ref_00_00(Inter_ref_00_00),
|
||||
.Inter_ref_01_00(Inter_ref_01_00),
|
||||
.Inter_ref_02_00(Inter_ref_02_00),
|
||||
.Inter_ref_03_00(Inter_ref_03_00),
|
||||
.Inter_ref_04_00(Inter_ref_04_00),
|
||||
.Inter_ref_05_00(Inter_ref_05_00),
|
||||
.Inter_ref_06_00(Inter_ref_06_00),
|
||||
.Inter_ref_07_00(Inter_ref_07_00),
|
||||
.Inter_ref_08_00(Inter_ref_08_00),
|
||||
.Inter_ref_09_00(Inter_ref_09_00),
|
||||
.Inter_ref_10_00(Inter_ref_10_00),
|
||||
.Inter_ref_11_00(Inter_ref_11_00),
|
||||
.Inter_ref_12_00(Inter_ref_12_00),
|
||||
.Inter_ref_00_01(Inter_ref_00_01),
|
||||
.Inter_ref_01_01(Inter_ref_01_01),
|
||||
.Inter_ref_02_01(Inter_ref_02_01),
|
||||
.Inter_ref_03_01(Inter_ref_03_01),
|
||||
.Inter_ref_04_01(Inter_ref_04_01),
|
||||
.Inter_ref_05_01(Inter_ref_05_01),
|
||||
.Inter_ref_06_01(Inter_ref_06_01),
|
||||
.Inter_ref_07_01(Inter_ref_07_01),
|
||||
.Inter_ref_08_01(Inter_ref_08_01),
|
||||
.Inter_ref_09_01(Inter_ref_09_01),
|
||||
.Inter_ref_10_01(Inter_ref_10_01),
|
||||
.Inter_ref_11_01(Inter_ref_11_01),
|
||||
.Inter_ref_12_01(Inter_ref_12_01),
|
||||
.Inter_ref_00_02(Inter_ref_00_02),
|
||||
.Inter_ref_01_02(Inter_ref_01_02),
|
||||
.Inter_ref_02_02(Inter_ref_02_02),
|
||||
.Inter_ref_03_02(Inter_ref_03_02),
|
||||
.Inter_ref_04_02(Inter_ref_04_02),
|
||||
.Inter_ref_05_02(Inter_ref_05_02),
|
||||
.Inter_ref_06_02(Inter_ref_06_02),
|
||||
.Inter_ref_07_02(Inter_ref_07_02),
|
||||
.Inter_ref_08_02(Inter_ref_08_02),
|
||||
.Inter_ref_09_02(Inter_ref_09_02),
|
||||
.Inter_ref_10_02(Inter_ref_10_02),
|
||||
.Inter_ref_11_02(Inter_ref_11_02),
|
||||
.Inter_ref_12_02(Inter_ref_12_02),
|
||||
.Inter_ref_00_03(Inter_ref_00_03),
|
||||
.Inter_ref_01_03(Inter_ref_01_03),
|
||||
.Inter_ref_02_03(Inter_ref_02_03),
|
||||
.Inter_ref_03_03(Inter_ref_03_03),
|
||||
.Inter_ref_04_03(Inter_ref_04_03),
|
||||
.Inter_ref_05_03(Inter_ref_05_03),
|
||||
.Inter_ref_06_03(Inter_ref_06_03),
|
||||
.Inter_ref_07_03(Inter_ref_07_03),
|
||||
.Inter_ref_08_03(Inter_ref_08_03),
|
||||
.Inter_ref_09_03(Inter_ref_09_03),
|
||||
.Inter_ref_10_03(Inter_ref_10_03),
|
||||
.Inter_ref_11_03(Inter_ref_11_03),
|
||||
.Inter_ref_12_03(Inter_ref_12_03),
|
||||
.Inter_ref_00_04(Inter_ref_00_04),
|
||||
.Inter_ref_01_04(Inter_ref_01_04),
|
||||
.Inter_ref_02_04(Inter_ref_02_04),
|
||||
.Inter_ref_03_04(Inter_ref_03_04),
|
||||
.Inter_ref_04_04(Inter_ref_04_04),
|
||||
.Inter_ref_05_04(Inter_ref_05_04),
|
||||
.Inter_ref_06_04(Inter_ref_06_04),
|
||||
.Inter_ref_07_04(Inter_ref_07_04),
|
||||
.Inter_ref_08_04(Inter_ref_08_04),
|
||||
.Inter_ref_09_04(Inter_ref_09_04),
|
||||
.Inter_ref_10_04(Inter_ref_10_04),
|
||||
.Inter_ref_11_04(Inter_ref_11_04),
|
||||
.Inter_ref_12_04(Inter_ref_12_04),
|
||||
.Inter_ref_00_05(Inter_ref_00_05),
|
||||
.Inter_ref_01_05(Inter_ref_01_05),
|
||||
.Inter_ref_02_05(Inter_ref_02_05),
|
||||
.Inter_ref_03_05(Inter_ref_03_05),
|
||||
.Inter_ref_04_05(Inter_ref_04_05),
|
||||
.Inter_ref_05_05(Inter_ref_05_05),
|
||||
.Inter_ref_06_05(Inter_ref_06_05),
|
||||
.Inter_ref_07_05(Inter_ref_07_05),
|
||||
.Inter_ref_08_05(Inter_ref_08_05),
|
||||
.Inter_ref_09_05(Inter_ref_09_05),
|
||||
.Inter_ref_10_05(Inter_ref_10_05),
|
||||
.Inter_ref_11_05(Inter_ref_11_05),
|
||||
.Inter_ref_12_05(Inter_ref_12_05),
|
||||
.Inter_ref_00_06(Inter_ref_00_06),
|
||||
.Inter_ref_01_06(Inter_ref_01_06),
|
||||
.Inter_ref_02_06(Inter_ref_02_06),
|
||||
.Inter_ref_03_06(Inter_ref_03_06),
|
||||
.Inter_ref_04_06(Inter_ref_04_06),
|
||||
.Inter_ref_05_06(Inter_ref_05_06),
|
||||
.Inter_ref_06_06(Inter_ref_06_06),
|
||||
.Inter_ref_07_06(Inter_ref_07_06),
|
||||
.Inter_ref_08_06(Inter_ref_08_06),
|
||||
.Inter_ref_09_06(Inter_ref_09_06),
|
||||
.Inter_ref_10_06(Inter_ref_10_06),
|
||||
.Inter_ref_11_06(Inter_ref_11_06),
|
||||
.Inter_ref_12_06(Inter_ref_12_06),
|
||||
.Inter_ref_00_07(Inter_ref_00_07),
|
||||
.Inter_ref_01_07(Inter_ref_01_07),
|
||||
.Inter_ref_02_07(Inter_ref_02_07),
|
||||
.Inter_ref_03_07(Inter_ref_03_07),
|
||||
.Inter_ref_04_07(Inter_ref_04_07),
|
||||
.Inter_ref_05_07(Inter_ref_05_07),
|
||||
.Inter_ref_06_07(Inter_ref_06_07),
|
||||
.Inter_ref_07_07(Inter_ref_07_07),
|
||||
.Inter_ref_08_07(Inter_ref_08_07),
|
||||
.Inter_ref_09_07(Inter_ref_09_07),
|
||||
.Inter_ref_10_07(Inter_ref_10_07),
|
||||
.Inter_ref_11_07(Inter_ref_11_07),
|
||||
.Inter_ref_12_07(Inter_ref_12_07),
|
||||
.Inter_ref_00_08(Inter_ref_00_08),
|
||||
.Inter_ref_01_08(Inter_ref_01_08),
|
||||
.Inter_ref_02_08(Inter_ref_02_08),
|
||||
.Inter_ref_03_08(Inter_ref_03_08),
|
||||
.Inter_ref_04_08(Inter_ref_04_08),
|
||||
.Inter_ref_05_08(Inter_ref_05_08),
|
||||
.Inter_ref_06_08(Inter_ref_06_08),
|
||||
.Inter_ref_07_08(Inter_ref_07_08),
|
||||
.Inter_ref_08_08(Inter_ref_08_08),
|
||||
.Inter_ref_09_08(Inter_ref_09_08),
|
||||
.Inter_ref_10_08(Inter_ref_10_08),
|
||||
.Inter_ref_11_08(Inter_ref_11_08),
|
||||
.Inter_ref_12_08(Inter_ref_12_08),
|
||||
.Inter_ref_00_09(Inter_ref_00_09),
|
||||
.Inter_ref_01_09(Inter_ref_01_09),
|
||||
.Inter_ref_02_09(Inter_ref_02_09),
|
||||
.Inter_ref_03_09(Inter_ref_03_09),
|
||||
.Inter_ref_04_09(Inter_ref_04_09),
|
||||
.Inter_ref_05_09(Inter_ref_05_09),
|
||||
.Inter_ref_06_09(Inter_ref_06_09),
|
||||
.Inter_ref_07_09(Inter_ref_07_09),
|
||||
.Inter_ref_08_09(Inter_ref_08_09),
|
||||
.Inter_ref_09_09(Inter_ref_09_09),
|
||||
.Inter_ref_10_09(Inter_ref_10_09),
|
||||
.Inter_ref_11_09(Inter_ref_11_09),
|
||||
.Inter_ref_12_09(Inter_ref_12_09),
|
||||
.Inter_ref_00_10(Inter_ref_00_10),
|
||||
.Inter_ref_01_10(Inter_ref_01_10),
|
||||
.Inter_ref_02_10(Inter_ref_02_10),
|
||||
.Inter_ref_03_10(Inter_ref_03_10),
|
||||
.Inter_ref_04_10(Inter_ref_04_10),
|
||||
.Inter_ref_05_10(Inter_ref_05_10),
|
||||
.Inter_ref_06_10(Inter_ref_06_10),
|
||||
.Inter_ref_07_10(Inter_ref_07_10),
|
||||
.Inter_ref_08_10(Inter_ref_08_10),
|
||||
.Inter_ref_09_10(Inter_ref_09_10),
|
||||
.Inter_ref_10_10(Inter_ref_10_10),
|
||||
.Inter_ref_11_10(Inter_ref_11_10),
|
||||
.Inter_ref_12_10(Inter_ref_12_10),
|
||||
.Inter_ref_00_11(Inter_ref_00_11),
|
||||
.Inter_ref_01_11(Inter_ref_01_11),
|
||||
.Inter_ref_02_11(Inter_ref_02_11),
|
||||
.Inter_ref_03_11(Inter_ref_03_11),
|
||||
.Inter_ref_04_11(Inter_ref_04_11),
|
||||
.Inter_ref_05_11(Inter_ref_05_11),
|
||||
.Inter_ref_06_11(Inter_ref_06_11),
|
||||
.Inter_ref_07_11(Inter_ref_07_11),
|
||||
.Inter_ref_08_11(Inter_ref_08_11),
|
||||
.Inter_ref_09_11(Inter_ref_09_11),
|
||||
.Inter_ref_10_11(Inter_ref_10_11),
|
||||
.Inter_ref_11_11(Inter_ref_11_11),
|
||||
.Inter_ref_12_11(Inter_ref_12_11),
|
||||
.Inter_ref_00_12(Inter_ref_00_12),
|
||||
.Inter_ref_01_12(Inter_ref_01_12),
|
||||
.Inter_ref_02_12(Inter_ref_02_12),
|
||||
.Inter_ref_03_12(Inter_ref_03_12),
|
||||
.Inter_ref_04_12(Inter_ref_04_12),
|
||||
.Inter_ref_05_12(Inter_ref_05_12),
|
||||
.Inter_ref_06_12(Inter_ref_06_12),
|
||||
.Inter_ref_07_12(Inter_ref_07_12),
|
||||
.Inter_ref_08_12(Inter_ref_08_12),
|
||||
.Inter_ref_09_12(Inter_ref_09_12),
|
||||
.Inter_ref_10_12(Inter_ref_10_12),
|
||||
.Inter_ref_11_12(Inter_ref_11_12),
|
||||
.Inter_ref_12_12(Inter_ref_12_12),
|
||||
|
||||
.Inter_pix_copy0(Inter_pix_copy0),
|
||||
.Inter_pix_copy1(Inter_pix_copy1),
|
||||
.Inter_pix_copy2(Inter_pix_copy2),
|
||||
.Inter_pix_copy3(Inter_pix_copy3),
|
||||
.Inter_H_window_0_0(Inter_H_window_0_0),
|
||||
.Inter_H_window_1_0(Inter_H_window_1_0),
|
||||
.Inter_H_window_2_0(Inter_H_window_2_0),
|
||||
.Inter_H_window_3_0(Inter_H_window_3_0),
|
||||
.Inter_H_window_4_0(Inter_H_window_4_0),
|
||||
.Inter_H_window_5_0(Inter_H_window_5_0),
|
||||
.Inter_H_window_0_1(Inter_H_window_0_1),
|
||||
.Inter_H_window_1_1(Inter_H_window_1_1),
|
||||
.Inter_H_window_2_1(Inter_H_window_2_1),
|
||||
.Inter_H_window_3_1(Inter_H_window_3_1),
|
||||
.Inter_H_window_4_1(Inter_H_window_4_1),
|
||||
.Inter_H_window_5_1(Inter_H_window_5_1),
|
||||
.Inter_H_window_0_2(Inter_H_window_0_2),
|
||||
.Inter_H_window_1_2(Inter_H_window_1_2),
|
||||
.Inter_H_window_2_2(Inter_H_window_2_2),
|
||||
.Inter_H_window_3_2(Inter_H_window_3_2),
|
||||
.Inter_H_window_4_2(Inter_H_window_4_2),
|
||||
.Inter_H_window_5_2(Inter_H_window_5_2),
|
||||
.Inter_H_window_0_3(Inter_H_window_0_3),
|
||||
.Inter_H_window_1_3(Inter_H_window_1_3),
|
||||
.Inter_H_window_2_3(Inter_H_window_2_3),
|
||||
.Inter_H_window_3_3(Inter_H_window_3_3),
|
||||
.Inter_H_window_4_3(Inter_H_window_4_3),
|
||||
.Inter_H_window_5_3(Inter_H_window_5_3),
|
||||
.Inter_H_window_0_4(Inter_H_window_0_4),
|
||||
.Inter_H_window_1_4(Inter_H_window_1_4),
|
||||
.Inter_H_window_2_4(Inter_H_window_2_4),
|
||||
.Inter_H_window_3_4(Inter_H_window_3_4),
|
||||
.Inter_H_window_4_4(Inter_H_window_4_4),
|
||||
.Inter_H_window_5_4(Inter_H_window_5_4),
|
||||
.Inter_H_window_0_5(Inter_H_window_0_5),
|
||||
.Inter_H_window_1_5(Inter_H_window_1_5),
|
||||
.Inter_H_window_2_5(Inter_H_window_2_5),
|
||||
.Inter_H_window_3_5(Inter_H_window_3_5),
|
||||
.Inter_H_window_4_5(Inter_H_window_4_5),
|
||||
.Inter_H_window_5_5(Inter_H_window_5_5),
|
||||
.Inter_H_window_0_6(Inter_H_window_0_6),
|
||||
.Inter_H_window_1_6(Inter_H_window_1_6),
|
||||
.Inter_H_window_2_6(Inter_H_window_2_6),
|
||||
.Inter_H_window_3_6(Inter_H_window_3_6),
|
||||
.Inter_H_window_4_6(Inter_H_window_4_6),
|
||||
.Inter_H_window_5_6(Inter_H_window_5_6),
|
||||
.Inter_H_window_0_7(Inter_H_window_0_7),
|
||||
.Inter_H_window_1_7(Inter_H_window_1_7),
|
||||
.Inter_H_window_2_7(Inter_H_window_2_7),
|
||||
.Inter_H_window_3_7(Inter_H_window_3_7),
|
||||
.Inter_H_window_4_7(Inter_H_window_4_7),
|
||||
.Inter_H_window_5_7(Inter_H_window_5_7),
|
||||
.Inter_H_window_0_8(Inter_H_window_0_8),
|
||||
.Inter_H_window_1_8(Inter_H_window_1_8),
|
||||
.Inter_H_window_2_8(Inter_H_window_2_8),
|
||||
.Inter_H_window_3_8(Inter_H_window_3_8),
|
||||
.Inter_H_window_4_8(Inter_H_window_4_8),
|
||||
.Inter_H_window_5_8(Inter_H_window_5_8),
|
||||
.Inter_V_window_0(Inter_V_window_0),
|
||||
.Inter_V_window_1(Inter_V_window_1),
|
||||
.Inter_V_window_2(Inter_V_window_2),
|
||||
.Inter_V_window_3(Inter_V_window_3),
|
||||
.Inter_V_window_4(Inter_V_window_4),
|
||||
.Inter_V_window_5(Inter_V_window_5),
|
||||
.Inter_V_window_6(Inter_V_window_6),
|
||||
.Inter_V_window_7(Inter_V_window_7),
|
||||
.Inter_V_window_8(Inter_V_window_8),
|
||||
.Inter_C_window_0_0(Inter_C_window_0_0),
|
||||
.Inter_C_window_1_0(Inter_C_window_1_0),
|
||||
.Inter_C_window_2_0(Inter_C_window_2_0),
|
||||
.Inter_C_window_0_1(Inter_C_window_0_1),
|
||||
.Inter_C_window_1_1(Inter_C_window_1_1),
|
||||
.Inter_C_window_2_1(Inter_C_window_2_1),
|
||||
.Inter_C_window_0_2(Inter_C_window_0_2),
|
||||
.Inter_C_window_1_2(Inter_C_window_1_2),
|
||||
.Inter_C_window_2_2(Inter_C_window_2_2),
|
||||
.Inter_bi_window_0(Inter_bi_window_0),
|
||||
.Inter_bi_window_1(Inter_bi_window_1),
|
||||
.Inter_bi_window_2(Inter_bi_window_2),
|
||||
.Inter_bi_window_3(Inter_bi_window_3)
|
||||
);
|
||||
|
||||
Inter_pred_LPE Inter_pred_LPE (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.pos_FracL(pos_FracL),
|
||||
.IsInterLuma(IsInterLuma),
|
||||
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
||||
.Inter_H_window_0_0(Inter_H_window_0_0),
|
||||
.Inter_H_window_1_0(Inter_H_window_1_0),
|
||||
.Inter_H_window_2_0(Inter_H_window_2_0),
|
||||
.Inter_H_window_3_0(Inter_H_window_3_0),
|
||||
.Inter_H_window_4_0(Inter_H_window_4_0),
|
||||
.Inter_H_window_5_0(Inter_H_window_5_0),
|
||||
.Inter_H_window_0_1(Inter_H_window_0_1),
|
||||
.Inter_H_window_1_1(Inter_H_window_1_1),
|
||||
.Inter_H_window_2_1(Inter_H_window_2_1),
|
||||
.Inter_H_window_3_1(Inter_H_window_3_1),
|
||||
.Inter_H_window_4_1(Inter_H_window_4_1),
|
||||
.Inter_H_window_5_1(Inter_H_window_5_1),
|
||||
.Inter_H_window_0_2(Inter_H_window_0_2),
|
||||
.Inter_H_window_1_2(Inter_H_window_1_2),
|
||||
.Inter_H_window_2_2(Inter_H_window_2_2),
|
||||
.Inter_H_window_3_2(Inter_H_window_3_2),
|
||||
.Inter_H_window_4_2(Inter_H_window_4_2),
|
||||
.Inter_H_window_5_2(Inter_H_window_5_2),
|
||||
.Inter_H_window_0_3(Inter_H_window_0_3),
|
||||
.Inter_H_window_1_3(Inter_H_window_1_3),
|
||||
.Inter_H_window_2_3(Inter_H_window_2_3),
|
||||
.Inter_H_window_3_3(Inter_H_window_3_3),
|
||||
.Inter_H_window_4_3(Inter_H_window_4_3),
|
||||
.Inter_H_window_5_3(Inter_H_window_5_3),
|
||||
.Inter_H_window_0_4(Inter_H_window_0_4),
|
||||
.Inter_H_window_1_4(Inter_H_window_1_4),
|
||||
.Inter_H_window_2_4(Inter_H_window_2_4),
|
||||
.Inter_H_window_3_4(Inter_H_window_3_4),
|
||||
.Inter_H_window_4_4(Inter_H_window_4_4),
|
||||
.Inter_H_window_5_4(Inter_H_window_5_4),
|
||||
.Inter_H_window_0_5(Inter_H_window_0_5),
|
||||
.Inter_H_window_1_5(Inter_H_window_1_5),
|
||||
.Inter_H_window_2_5(Inter_H_window_2_5),
|
||||
.Inter_H_window_3_5(Inter_H_window_3_5),
|
||||
.Inter_H_window_4_5(Inter_H_window_4_5),
|
||||
.Inter_H_window_5_5(Inter_H_window_5_5),
|
||||
.Inter_H_window_0_6(Inter_H_window_0_6),
|
||||
.Inter_H_window_1_6(Inter_H_window_1_6),
|
||||
.Inter_H_window_2_6(Inter_H_window_2_6),
|
||||
.Inter_H_window_3_6(Inter_H_window_3_6),
|
||||
.Inter_H_window_4_6(Inter_H_window_4_6),
|
||||
.Inter_H_window_5_6(Inter_H_window_5_6),
|
||||
.Inter_H_window_0_7(Inter_H_window_0_7),
|
||||
.Inter_H_window_1_7(Inter_H_window_1_7),
|
||||
.Inter_H_window_2_7(Inter_H_window_2_7),
|
||||
.Inter_H_window_3_7(Inter_H_window_3_7),
|
||||
.Inter_H_window_4_7(Inter_H_window_4_7),
|
||||
.Inter_H_window_5_7(Inter_H_window_5_7),
|
||||
.Inter_H_window_0_8(Inter_H_window_0_8),
|
||||
.Inter_H_window_1_8(Inter_H_window_1_8),
|
||||
.Inter_H_window_2_8(Inter_H_window_2_8),
|
||||
.Inter_H_window_3_8(Inter_H_window_3_8),
|
||||
.Inter_H_window_4_8(Inter_H_window_4_8),
|
||||
.Inter_H_window_5_8(Inter_H_window_5_8),
|
||||
.Inter_V_window_0(Inter_V_window_0),
|
||||
.Inter_V_window_1(Inter_V_window_1),
|
||||
.Inter_V_window_2(Inter_V_window_2),
|
||||
.Inter_V_window_3(Inter_V_window_3),
|
||||
.Inter_V_window_4(Inter_V_window_4),
|
||||
.Inter_V_window_5(Inter_V_window_5),
|
||||
.Inter_V_window_6(Inter_V_window_6),
|
||||
.Inter_V_window_7(Inter_V_window_7),
|
||||
.Inter_V_window_8(Inter_V_window_8),
|
||||
.Inter_bi_window_0(Inter_bi_window_0),
|
||||
.Inter_bi_window_1(Inter_bi_window_1),
|
||||
.Inter_bi_window_2(Inter_bi_window_2),
|
||||
.Inter_bi_window_3(Inter_bi_window_3),
|
||||
|
||||
.LPE0_out(LPE0_out),
|
||||
.LPE1_out(LPE1_out),
|
||||
.LPE2_out(LPE2_out),
|
||||
.LPE3_out(LPE3_out)
|
||||
);
|
||||
Inter_pred_CPE Inter_pred_CPE (
|
||||
.xFracC(xFracC),
|
||||
.yFracC(yFracC),
|
||||
.Inter_C_window_0_0(Inter_C_window_0_0),
|
||||
.Inter_C_window_1_0(Inter_C_window_1_0),
|
||||
.Inter_C_window_2_0(Inter_C_window_2_0),
|
||||
.Inter_C_window_0_1(Inter_C_window_0_1),
|
||||
.Inter_C_window_1_1(Inter_C_window_1_1),
|
||||
.Inter_C_window_2_1(Inter_C_window_2_1),
|
||||
.Inter_C_window_0_2(Inter_C_window_0_2),
|
||||
.Inter_C_window_1_2(Inter_C_window_1_2),
|
||||
.Inter_C_window_2_2(Inter_C_window_2_2),
|
||||
.CPE0_out(CPE0_out),
|
||||
.CPE1_out(CPE1_out),
|
||||
.CPE2_out(CPE2_out),
|
||||
.CPE3_out(CPE3_out)
|
||||
);
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,333 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Intra4x4_PredMode_decoding.v
|
||||
// Generated : May 31, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding the prediction mode for Intra4x4
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v,
|
||||
MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag,
|
||||
rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout,
|
||||
|
||||
Intra4x4PredMode_CurrMb,
|
||||
Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr,
|
||||
Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din
|
||||
);
|
||||
input clk,reset_n;
|
||||
input [2:0] mb_pred_state;
|
||||
input [3:0] luma4x4BlkIdx;
|
||||
input [3:0] mb_num_h,mb_num_v;
|
||||
input [1:0] MBTypeGen_mbAddrA;
|
||||
input [21:0] MBTypeGen_mbAddrB_reg;
|
||||
input constrained_intra_pred_flag;
|
||||
input [2:0] rem_intra4x4_pred_mode;
|
||||
input prev_intra4x4_pred_mode_flag;
|
||||
input [15:0] Intra4x4PredMode_mbAddrB_dout;
|
||||
//input [8:0] pic_num;
|
||||
|
||||
output [63:0] Intra4x4PredMode_CurrMb;
|
||||
output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
|
||||
output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
|
||||
output [15:0] Intra4x4PredMode_mbAddrB_din;
|
||||
|
||||
reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
|
||||
reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
|
||||
reg [15:0] Intra4x4PredMode_mbAddrB_din;
|
||||
|
||||
wire mbAddrA_availability;
|
||||
wire mbAddrB_availability;
|
||||
wire mbAddrA;
|
||||
wire mbAddrB;
|
||||
wire [3:0] predIntra4x4PredMode; //prediction mode obtained at `prev_intra4x4_pred_mode_flag_s
|
||||
reg dcOnlyPredictionFlag;
|
||||
reg [15:0] Intra4x4PredMode_mbAddrA;
|
||||
reg [63:0] Intra4x4PredMode_CurrMb;
|
||||
reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB;
|
||||
|
||||
reg [3:0] rem_Intra4x4PredMode; //prediction mode obtained at `rem_intra4x4_pred_mode_s
|
||||
reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode
|
||||
|
||||
|
||||
reg [1:0] MBTypeGen_mbAddrB;
|
||||
always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
|
||||
case (mb_num_h)
|
||||
0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
|
||||
1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
|
||||
2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
|
||||
3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
|
||||
4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
|
||||
5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
|
||||
6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
|
||||
7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
|
||||
8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
|
||||
9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
|
||||
10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
|
||||
default:MBTypeGen_mbAddrB <= 0;
|
||||
endcase
|
||||
|
||||
//neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order
|
||||
assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2
|
||||
|| luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1;
|
||||
|
||||
assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1
|
||||
|| luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1;
|
||||
|
||||
assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8
|
||||
|| luma4x4BlkIdx == 10)? 1'b0:1'b1; //0:left MB;1:curr MB
|
||||
|
||||
assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4
|
||||
|| luma4x4BlkIdx == 5)? 1'b0:1'b1; //0:upper MB;1:curr MB
|
||||
|
||||
//dcOnlyPredictionFlag
|
||||
always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or
|
||||
MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag)
|
||||
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
||||
begin
|
||||
if (mbAddrA_availability == 0)
|
||||
dcOnlyPredictionFlag <= 1;
|
||||
else if (mbAddrB_availability == 0)
|
||||
dcOnlyPredictionFlag <= 1;
|
||||
else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1)
|
||||
dcOnlyPredictionFlag <= 1;
|
||||
else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1)
|
||||
dcOnlyPredictionFlag <= 1;
|
||||
else
|
||||
dcOnlyPredictionFlag <= 0;
|
||||
end
|
||||
else
|
||||
dcOnlyPredictionFlag <= 0;
|
||||
//Intra4x4PredModeA
|
||||
always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA
|
||||
or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
|
||||
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
||||
begin
|
||||
if (dcOnlyPredictionFlag == 1)
|
||||
Intra4x4PredModeA <= 2;
|
||||
else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4
|
||||
Intra4x4PredModeA <= 2;
|
||||
else
|
||||
case (luma4x4BlkIdx)
|
||||
0 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[3:0];
|
||||
1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0];
|
||||
2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4];
|
||||
3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8];
|
||||
4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4];
|
||||
5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16];
|
||||
6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12];
|
||||
7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24];
|
||||
8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8];
|
||||
9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32];
|
||||
10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12];
|
||||
11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40];
|
||||
12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36];
|
||||
13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48];
|
||||
14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44];
|
||||
15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56];
|
||||
endcase
|
||||
end
|
||||
else
|
||||
Intra4x4PredModeA <= 0;
|
||||
//Intra4x4PredModeB
|
||||
always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB
|
||||
or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
|
||||
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
||||
begin
|
||||
if (dcOnlyPredictionFlag == 1)
|
||||
Intra4x4PredModeB <= 2;
|
||||
else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4) //not coded in Intra4x4
|
||||
Intra4x4PredModeB <= 2;
|
||||
else
|
||||
case (luma4x4BlkIdx)
|
||||
0 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[15:12];
|
||||
1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8];
|
||||
2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0];
|
||||
3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4];
|
||||
4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4];
|
||||
5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0];
|
||||
6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16];
|
||||
7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20];
|
||||
8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8];
|
||||
9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12];
|
||||
10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32];
|
||||
11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36];
|
||||
12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24];
|
||||
13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28];
|
||||
14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48];
|
||||
15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52];
|
||||
endcase
|
||||
end
|
||||
else
|
||||
Intra4x4PredModeB <= 0;
|
||||
//obtain prediction mode at prev_intra4x4_pred_mode_flag_s
|
||||
assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
predIntra4x4PredMode_reg <= 0;
|
||||
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0)
|
||||
predIntra4x4PredMode_reg <= predIntra4x4PredMode;
|
||||
//obtain prediction mode at rem_intra4x4_pred_mode_s
|
||||
always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg)
|
||||
if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
||||
rem_Intra4x4PredMode <= ({1'b0,rem_intra4x4_pred_mode} < predIntra4x4PredMode_reg)?
|
||||
{1'b0,rem_intra4x4_pred_mode}:(rem_intra4x4_pred_mode + 1);
|
||||
else
|
||||
rem_Intra4x4PredMode <= 0;
|
||||
//-----------------------------
|
||||
//Intra4x4PredMode_CurrMb write
|
||||
//-----------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
Intra4x4PredMode_CurrMb <= 0;
|
||||
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
||||
case (luma4x4BlkIdx)
|
||||
0 :Intra4x4PredMode_CurrMb[3:0] <= predIntra4x4PredMode;
|
||||
1 :Intra4x4PredMode_CurrMb[7:4] <= predIntra4x4PredMode;
|
||||
2 :Intra4x4PredMode_CurrMb[11:8] <= predIntra4x4PredMode;
|
||||
3 :Intra4x4PredMode_CurrMb[15:12] <= predIntra4x4PredMode;
|
||||
4 :Intra4x4PredMode_CurrMb[19:16] <= predIntra4x4PredMode;
|
||||
5 :Intra4x4PredMode_CurrMb[23:20] <= predIntra4x4PredMode;
|
||||
6 :Intra4x4PredMode_CurrMb[27:24] <= predIntra4x4PredMode;
|
||||
7 :Intra4x4PredMode_CurrMb[31:28] <= predIntra4x4PredMode;
|
||||
8 :Intra4x4PredMode_CurrMb[35:32] <= predIntra4x4PredMode;
|
||||
9 :Intra4x4PredMode_CurrMb[39:36] <= predIntra4x4PredMode;
|
||||
10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode;
|
||||
11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode;
|
||||
12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode;
|
||||
13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode;
|
||||
14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode;
|
||||
15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode;
|
||||
endcase
|
||||
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
||||
case (luma4x4BlkIdx)
|
||||
0 :Intra4x4PredMode_CurrMb[3:0] <= rem_Intra4x4PredMode;
|
||||
1 :Intra4x4PredMode_CurrMb[7:4] <= rem_Intra4x4PredMode;
|
||||
2 :Intra4x4PredMode_CurrMb[11:8] <= rem_Intra4x4PredMode;
|
||||
3 :Intra4x4PredMode_CurrMb[15:12] <= rem_Intra4x4PredMode;
|
||||
4 :Intra4x4PredMode_CurrMb[19:16] <= rem_Intra4x4PredMode;
|
||||
5 :Intra4x4PredMode_CurrMb[23:20] <= rem_Intra4x4PredMode;
|
||||
6 :Intra4x4PredMode_CurrMb[27:24] <= rem_Intra4x4PredMode;
|
||||
7 :Intra4x4PredMode_CurrMb[31:28] <= rem_Intra4x4PredMode;
|
||||
8 :Intra4x4PredMode_CurrMb[35:32] <= rem_Intra4x4PredMode;
|
||||
9 :Intra4x4PredMode_CurrMb[39:36] <= rem_Intra4x4PredMode;
|
||||
10 :Intra4x4PredMode_CurrMb[43:40] <= rem_Intra4x4PredMode;
|
||||
11 :Intra4x4PredMode_CurrMb[47:44] <= rem_Intra4x4PredMode;
|
||||
12 :Intra4x4PredMode_CurrMb[51:48] <= rem_Intra4x4PredMode;
|
||||
13 :Intra4x4PredMode_CurrMb[55:52] <= rem_Intra4x4PredMode;
|
||||
14 :Intra4x4PredMode_CurrMb[59:56] <= rem_Intra4x4PredMode;
|
||||
15 :Intra4x4PredMode_CurrMb[63:60] <= rem_Intra4x4PredMode;
|
||||
endcase
|
||||
//------------------------------
|
||||
//Intra4x4PredMode_mbAddrA write
|
||||
//------------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
Intra4x4PredMode_mbAddrA <= 0;
|
||||
else if (mb_num_h != 10) //mb_num_h == 10,no need to store mbAddrA
|
||||
begin
|
||||
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
||||
case (luma4x4BlkIdx)
|
||||
5: Intra4x4PredMode_mbAddrA[3:0] <= predIntra4x4PredMode;
|
||||
7: Intra4x4PredMode_mbAddrA[7:4] <= predIntra4x4PredMode;
|
||||
13:Intra4x4PredMode_mbAddrA[11:8] <= predIntra4x4PredMode;
|
||||
15:Intra4x4PredMode_mbAddrA[15:12] <= predIntra4x4PredMode;
|
||||
endcase
|
||||
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
||||
case (luma4x4BlkIdx)
|
||||
5: Intra4x4PredMode_mbAddrA[3:0] <= rem_Intra4x4PredMode;
|
||||
7: Intra4x4PredMode_mbAddrA[7:4] <= rem_Intra4x4PredMode;
|
||||
13:Intra4x4PredMode_mbAddrA[11:8] <= rem_Intra4x4PredMode;
|
||||
15:Intra4x4PredMode_mbAddrA[15:12] <= rem_Intra4x4PredMode;
|
||||
endcase
|
||||
end
|
||||
//----------------------------------------
|
||||
//Intra4x4PredMode_mbAddrB RF read & write
|
||||
//----------------------------------------
|
||||
always @ (reset_n or mb_num_v or mb_num_h or luma4x4BlkIdx or mb_pred_state or prev_intra4x4_pred_mode_flag
|
||||
or Intra4x4PredMode_CurrMb or predIntra4x4PredMode or rem_Intra4x4PredMode)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
||||
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
||||
Intra4x4PredMode_mbAddrB_din <= 0;
|
||||
end
|
||||
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
||||
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
||||
if (prev_intra4x4_pred_mode_flag == 1 && luma4x4BlkIdx == 15 && mb_num_v != 8)//write is conditional when mb_num_v != 8
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
||||
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
||||
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
||||
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],predIntra4x4PredMode};
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
||||
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
||||
Intra4x4PredMode_mbAddrB_din <= 0;
|
||||
end
|
||||
end
|
||||
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
||||
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
||||
if (luma4x4BlkIdx == 15 && mb_num_v != 8) //write is conditional when mb_num_v != 8
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
||||
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
||||
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
||||
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],rem_Intra4x4PredMode};
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
||||
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
||||
Intra4x4PredMode_mbAddrB_din <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
||||
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
||||
Intra4x4PredMode_mbAddrB_din <= 0;
|
||||
end
|
||||
|
||||
/*
|
||||
// synopsys translate_off
|
||||
integer tracefile;
|
||||
wire [6:0] mb_num;
|
||||
assign mb_num = mb_num_v * 11 + mb_num_h;
|
||||
|
||||
initial
|
||||
begin
|
||||
tracefile = $fopen("intra_4x4_trace.txt");
|
||||
end
|
||||
always @ (posedge clk)
|
||||
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
||||
begin
|
||||
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
||||
pic_num,mb_num,luma4x4BlkIdx,predIntra4x4PredMode);
|
||||
if (luma4x4BlkIdx == 15)
|
||||
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
||||
end
|
||||
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
||||
begin
|
||||
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
||||
pic_num,mb_num,luma4x4BlkIdx,rem_Intra4x4PredMode);
|
||||
if (luma4x4BlkIdx == 15)
|
||||
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
||||
end
|
||||
// synopsys translate_on
|
||||
*/
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,743 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Intra_pred_pipeline.v
|
||||
// Generated : Aug 4, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Intra16x16,Intra4x4 prediction pipeline
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Intra_pred_pipeline (clk,reset_n,mb_type_general,blk4x4_rec_counter,
|
||||
trigger_blk4x4_intra_pred,mb_num_v,mb_num_h,blk4x4_sum_counter,NextMB_IsSkip,
|
||||
Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
|
||||
|
||||
Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
|
||||
Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
|
||||
Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
|
||||
Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
|
||||
|
||||
Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
|
||||
Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
|
||||
Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
|
||||
Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
|
||||
Intra_mbAddrD_window,
|
||||
|
||||
Intra4x4_predmode,blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,
|
||||
blk4x4_intra_calculate_counter,end_of_one_blk4x4_intra,
|
||||
blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability,mbAddrC_availability,
|
||||
main_seed,plane_b_reg,plane_c_reg,
|
||||
Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_rd_addr
|
||||
);
|
||||
input clk,reset_n;
|
||||
input [3:0] mb_type_general;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input trigger_blk4x4_intra_pred;
|
||||
input [3:0] mb_num_v,mb_num_h;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input NextMB_IsSkip;
|
||||
input [1:0] Intra16x16_predmode;
|
||||
input [63:0] Intra4x4_predmode_CurrMb;
|
||||
input [1:0] Intra_chroma_predmode;
|
||||
|
||||
input [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
|
||||
input [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
|
||||
input [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
|
||||
input [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
|
||||
|
||||
input [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
|
||||
input [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
|
||||
input [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
|
||||
input [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
|
||||
input [7:0] Intra_mbAddrD_window;
|
||||
|
||||
output [3:0] Intra4x4_predmode;
|
||||
output [2:0] blk4x4_intra_preload_counter;
|
||||
output [3:0] blk4x4_intra_precompute_counter;
|
||||
output [2:0] blk4x4_intra_calculate_counter;
|
||||
output end_of_one_blk4x4_intra;
|
||||
output blkAddrA_availability,blkAddrB_availability;
|
||||
output mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
|
||||
output [15:0] main_seed;
|
||||
output [11:0] plane_b_reg,plane_c_reg;
|
||||
output Intra_mbAddrB_RAM_rd;
|
||||
output [6:0] Intra_mbAddrB_RAM_rd_addr;
|
||||
|
||||
reg [3:0] Intra4x4_predmode;
|
||||
reg [2:0] blk4x4_intra_preload_counter;
|
||||
reg [3:0] blk4x4_intra_precompute_counter;
|
||||
reg [2:0] blk4x4_intra_calculate_counter;
|
||||
|
||||
reg [11:0] plane_b_reg,plane_c_reg;
|
||||
wire Intra_mbAddrB_RAM_rd;
|
||||
wire [6:0] Intra_mbAddrB_RAM_rd_addr;
|
||||
wire end_of_one_blk4x4_intra;
|
||||
wire blkAddrA_availability,blkAddrB_availability;
|
||||
wire mbAddrA_availability,mbAddrB_availability;
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Intra4x4 prediction mode for current 4x4 block
|
||||
//----------------------------------------------------------------------------------------
|
||||
always @ (Intra4x4_predmode_CurrMb or blk4x4_rec_counter or mb_type_general)
|
||||
if (mb_type_general == `MB_Intra4x4)
|
||||
case (blk4x4_rec_counter)
|
||||
0 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[3:0];
|
||||
1 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[7:4];
|
||||
2 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[11:8];
|
||||
3 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[15:12];
|
||||
4 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[19:16];
|
||||
5 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[23:20];
|
||||
6 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[27:24];
|
||||
7 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[31:28];
|
||||
8 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[35:32];
|
||||
9 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[39:36];
|
||||
10:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[43:40];
|
||||
11:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[47:44];
|
||||
12:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[51:48];
|
||||
13:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[55:52];
|
||||
14:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[59:56];
|
||||
15:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[63:60];
|
||||
default:Intra4x4_predmode <= 4'b1111;
|
||||
endcase
|
||||
else
|
||||
Intra4x4_predmode <= 4'b1111;
|
||||
|
||||
//availability for intra4x4 predmode = Intra4x4_DC only
|
||||
assign blkAddrA_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC &&
|
||||
blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8 ||
|
||||
blk4x4_rec_counter == 10) && mb_num_h == 0))? 1'b0:1'b1;
|
||||
|
||||
assign blkAddrB_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC &&
|
||||
blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 ||
|
||||
blk4x4_rec_counter == 5) && mb_num_v == 0))? 1'b0:1'b1;
|
||||
|
||||
//availability for whole intra predicted MB (both intra16x16 & intra4x4)
|
||||
//assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0;
|
||||
//assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0;
|
||||
assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0;
|
||||
assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0;
|
||||
assign mbAddrC_availability = (mb_type_general[3] && mb_num_v != 0 && mb_num_h != 10)? 1'b1:1'b0;
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//Intra prediction step control counter
|
||||
//----------------------------------------------------------------------------------------
|
||||
//1.Preload upper pels counter
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_intra_preload_counter <= 0;
|
||||
else if (trigger_blk4x4_intra_pred)
|
||||
begin
|
||||
//Chroma
|
||||
if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20))
|
||||
case (Intra_chroma_predmode)
|
||||
`Intra_chroma_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b011:3'b000;
|
||||
`Intra_chroma_Horizontal:blk4x4_intra_preload_counter <= 3'b000;
|
||||
`Intra_chroma_Vertical :blk4x4_intra_preload_counter <= 3'b011;
|
||||
`Intra_chroma_Plane :blk4x4_intra_preload_counter <= 3'b011;
|
||||
endcase
|
||||
//Luma
|
||||
// Intra16x16
|
||||
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter == 0)
|
||||
case (Intra16x16_predmode)
|
||||
`Intra16x16_Vertical :blk4x4_intra_preload_counter <= 3'b101;
|
||||
`Intra16x16_Horizontal:blk4x4_intra_preload_counter <= 3'b000;
|
||||
`Intra16x16_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b101:3'b000;
|
||||
`Intra16x16_Plane :blk4x4_intra_preload_counter <= 3'b101;
|
||||
endcase
|
||||
// Intra4x4
|
||||
else if (mb_type_general[3:2] == 2'b11 && (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1
|
||||
|| blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5))
|
||||
case (Intra4x4_predmode)
|
||||
`Intra4x4_Vertical :blk4x4_intra_preload_counter <= 3'b010;
|
||||
`Intra4x4_Horizontal :blk4x4_intra_preload_counter <= 3'b000;
|
||||
`Intra4x4_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b010:3'b000;
|
||||
`Intra4x4_Diagonal_Down_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC
|
||||
`Intra4x4_Diagonal_Down_Right:blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD
|
||||
`Intra4x4_Vertical_Right :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD
|
||||
`Intra4x4_Horizontal_Down :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD
|
||||
`Intra4x4_Vertical_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC
|
||||
`Intra4x4_Horizontal_Up :blk4x4_intra_preload_counter <= 3'b000;
|
||||
endcase
|
||||
end
|
||||
else if (blk4x4_intra_preload_counter != 0)
|
||||
blk4x4_intra_preload_counter <= blk4x4_intra_preload_counter - 1;
|
||||
|
||||
//2.Precomputation for plane mode counter
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_intra_precompute_counter <= 0;
|
||||
//Intra16x16 plane mode: 10 cycle + 1 cycle (seed)
|
||||
else if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_precompute_counter <= 4'b1011;
|
||||
//Chroma8x8 plane mode: 6 cycle + 1 cycle (seed)
|
||||
else if ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_precompute_counter <= 4'b0111;
|
||||
else if (blk4x4_intra_precompute_counter != 0)
|
||||
blk4x4_intra_precompute_counter <= blk4x4_intra_precompute_counter - 1;
|
||||
|
||||
//3.Intra prediction calculation counter
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_intra_calculate_counter <= 0;
|
||||
//Intra16x16 Luma
|
||||
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
||||
begin
|
||||
if (blk4x4_rec_counter == 0)
|
||||
case (Intra16x16_predmode)
|
||||
`Intra16x16_Vertical:
|
||||
if (blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra16x16_Horizontal:
|
||||
if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra16x16_DC:
|
||||
if (mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (!mbAddrB_availability && trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra16x16_Plane:
|
||||
if (blk4x4_intra_precompute_counter == 4'b0001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
end
|
||||
end
|
||||
//Intra4x4 Luma
|
||||
else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
||||
begin
|
||||
if (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 ||
|
||||
blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5)
|
||||
case (Intra4x4_predmode)
|
||||
`Intra4x4_Horizontal,`Intra4x4_Horizontal_Up://Intra4x4 prediction modes do NOT need preload
|
||||
if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra4x4_DC: //Intra4x4 prediction modes may or may NOT need preload
|
||||
if (mbAddrB_availability == 1'b1) //need reload
|
||||
begin
|
||||
if (blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
end
|
||||
else //do not need reload
|
||||
begin
|
||||
if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
end
|
||||
default: //other Intra4x4 prediction modes that needs preload
|
||||
if (blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
endcase
|
||||
else if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
end
|
||||
//Chroma
|
||||
else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)
|
||||
case (Intra_chroma_predmode)
|
||||
`Intra_chroma_DC:
|
||||
if ((mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) || (!mbAddrB_availability && trigger_blk4x4_intra_pred))
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra_chroma_Horizontal:
|
||||
if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra_chroma_Vertical:
|
||||
if (blk4x4_intra_preload_counter == 3'b001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
`Intra_chroma_Plane: //plane
|
||||
if (blk4x4_intra_precompute_counter == 4'b0001)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
if (trigger_blk4x4_intra_pred)
|
||||
blk4x4_intra_calculate_counter <= 3'b100;
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
||||
end
|
||||
|
||||
assign end_of_one_blk4x4_intra = (blk4x4_intra_calculate_counter == 3'd1)? 1'b1:1'b0;
|
||||
//----------------------------------------------------------------------------------------
|
||||
//1.Preload
|
||||
// For intra4x4,preload_counter == 3'b010 means preload mbAddrC or mbAddrD
|
||||
// preload_counter == 3'b001 means preload mbAddrB
|
||||
//----------------------------------------------------------------------------------------
|
||||
wire [6:0] Intra_mbAddrB_RAM_addr_bp;
|
||||
reg [5:0] Intra_mbAddrB_RAM_addr_sp;
|
||||
reg [1:0] Intra_mbAddrB_RAM_addr_ip;
|
||||
|
||||
wire Intra_mbAddrB_RAM_rd_for_mbAddrD;
|
||||
assign Intra_mbAddrB_RAM_rd_for_mbAddrD = (blk4x4_sum_counter == 3'b0 &&
|
||||
(blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23) &&
|
||||
mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip)? 1'b1:1'b0;
|
||||
|
||||
assign Intra_mbAddrB_RAM_rd = ((blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) || Intra_mbAddrB_RAM_rd_for_mbAddrD)? 1'b1:1'b0;
|
||||
|
||||
// base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr
|
||||
assign Intra_mbAddrB_RAM_addr_bp = (Intra_mbAddrB_RAM_rd)? ((blk4x4_rec_counter > 15)? ((blk4x4_rec_counter > 19)? 7'd66:7'd44):0):0;
|
||||
|
||||
// shift pointer,x2 for chroma,x4 for luma
|
||||
always @ (Intra_mbAddrB_RAM_rd_for_mbAddrD or Intra_mbAddrB_RAM_rd or mb_num_h or
|
||||
blk4x4_rec_counter or Intra4x4_predmode or blk4x4_intra_preload_counter)
|
||||
if (Intra_mbAddrB_RAM_rd_for_mbAddrD)
|
||||
Intra_mbAddrB_RAM_addr_sp <= (blk4x4_rec_counter < 16)? {mb_num_h,2'b0}:{1'b0,mb_num_h,1'b0};
|
||||
else if (Intra_mbAddrB_RAM_rd)
|
||||
begin
|
||||
if (blk4x4_rec_counter < 16)
|
||||
Intra_mbAddrB_RAM_addr_sp <= ((Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left
|
||||
|| Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter == 5
|
||||
&& blk4x4_intra_preload_counter == 3'b011)? //read for mbAddrC
|
||||
{(mb_num_h + 1),2'b0}:{mb_num_h,2'b0};
|
||||
else
|
||||
Intra_mbAddrB_RAM_addr_sp <= {1'b0,mb_num_h,1'b0};
|
||||
end
|
||||
else
|
||||
Intra_mbAddrB_RAM_addr_sp <= 0;
|
||||
|
||||
// pointer for relative address of each 4x4 block inside a MB
|
||||
always @ (Intra_mbAddrB_RAM_rd or blk4x4_rec_counter or blk4x4_intra_preload_counter or
|
||||
mb_type_general[3:2] or Intra4x4_predmode or Intra_mbAddrB_RAM_rd_for_mbAddrD)
|
||||
if (blk4x4_rec_counter < 16 && Intra_mbAddrB_RAM_rd) //luma
|
||||
begin
|
||||
if (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)
|
||||
begin
|
||||
if (mb_type_general[3:2] == 2'b10) //Intra16x16
|
||||
case (blk4x4_intra_preload_counter)
|
||||
3'b101:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
3'b100:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
||||
3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
||||
3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
||||
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
endcase
|
||||
else //Intra4x4
|
||||
begin
|
||||
if (blk4x4_intra_preload_counter == 3'b010) //For mbAddrB
|
||||
case (blk4x4_rec_counter)
|
||||
0:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
1:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
||||
4:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
||||
5:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
||||
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
endcase
|
||||
else if (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left
|
||||
|| Intra4x4_predmode == `Intra4x4_Vertical_Left) //For mbAddrC
|
||||
case (blk4x4_rec_counter)
|
||||
0:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
||||
1:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
||||
4:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
||||
5:Intra_mbAddrB_RAM_addr_ip <= 2'b00;
|
||||
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
endcase
|
||||
else //For mbAddrD
|
||||
case (blk4x4_rec_counter)
|
||||
1:Intra_mbAddrB_RAM_addr_ip <= 2'b00;
|
||||
4:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
||||
5:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
||||
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else if (Intra_mbAddrB_RAM_rd_for_mbAddrD)
|
||||
Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
||||
else
|
||||
Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
end
|
||||
else if (Intra_mbAddrB_RAM_rd) //chroma
|
||||
Intra_mbAddrB_RAM_addr_ip <= (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)? {1'b0,~blk4x4_intra_preload_counter[0]}:2'b01;
|
||||
else
|
||||
Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
|
||||
// pointer for each 4x4 block
|
||||
assign Intra_mbAddrB_RAM_rd_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip;
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//2.Precomputation
|
||||
// For Intra16x16 Luma Plane
|
||||
// cycle11: x1 + x3 |
|
||||
// cycle10: x2 + x5 |
|
||||
// cycle9 : x4 + x6 |
|
||||
// cycle8 : x8 + x7 | Vertical,V For Intra Chroma Plane
|
||||
// cycle7 : calculate c cycle7: x1 + x3 |
|
||||
// cycle6 : x1 + x3 | cycle6: x2 + x4 | Vertical,V
|
||||
// cycle5 : x2 + x5 | cycle5: calculate c
|
||||
// cycle4 : x4 + x6 | cycle4: x1 + x3 |
|
||||
// cycle3 : x8 + x7 | Horizontal,H cycle3: x2 + x4 | Horizontal,H
|
||||
// cycle2 : calculate a & b cycle2 : calculate a & b
|
||||
// cycle1 : seed cycle1 : seed
|
||||
//----------------------------------------------------------------------------------------
|
||||
// 2.1 precomputation for HV:
|
||||
reg [14:0] plane_HV_prev_in;
|
||||
reg [7:0] plane_HV_A1,plane_HV_A2,plane_HV_B1,plane_HV_B2;
|
||||
reg [1:0] plane_HV_shifter1_len,plane_HV_shifter2_len;
|
||||
reg plane_HV_mux1_sel,plane_HV_mux2_sel;
|
||||
reg plane_HV_Is7;
|
||||
wire [14:0] plane_HV_out;
|
||||
reg [14:0] plane_HV_out_reg;
|
||||
|
||||
plane_HV_precomputation plane_HV_precomputation (
|
||||
.prev_in(plane_HV_prev_in),
|
||||
.A1(plane_HV_A1),
|
||||
.A2(plane_HV_A2),
|
||||
.B1(plane_HV_B1),
|
||||
.B2(plane_HV_B2),
|
||||
.shifter1_len(plane_HV_shifter1_len),
|
||||
.shifter2_len(plane_HV_shifter2_len),
|
||||
.mux1_sel(plane_HV_mux1_sel),
|
||||
.mux2_sel(plane_HV_mux2_sel),
|
||||
.Is7(plane_HV_Is7),
|
||||
.HV_out(plane_HV_out)
|
||||
);
|
||||
always @ (blk4x4_intra_precompute_counter or mb_type_general[2] or blk4x4_rec_counter or plane_HV_out_reg
|
||||
or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
|
||||
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
||||
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
||||
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
||||
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3
|
||||
or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7
|
||||
or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
||||
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
||||
or Intra_mbAddrD_window)
|
||||
//Intra16x16 plane
|
||||
if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0)
|
||||
case (blk4x4_intra_precompute_counter)
|
||||
11,6: // x1,x3
|
||||
begin
|
||||
plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0;
|
||||
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg8 :Intra_mbAddrB_reg8;
|
||||
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg6 :Intra_mbAddrB_reg6;
|
||||
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg10:Intra_mbAddrB_reg10;
|
||||
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg4 :Intra_mbAddrB_reg4;
|
||||
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01;
|
||||
plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0;
|
||||
end
|
||||
10,5 : // x2,x5
|
||||
begin
|
||||
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0;
|
||||
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg9 :Intra_mbAddrB_reg9;
|
||||
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg5 :Intra_mbAddrB_reg5;
|
||||
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg12:Intra_mbAddrB_reg12;
|
||||
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg2 :Intra_mbAddrB_reg2;
|
||||
plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b10;
|
||||
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0;
|
||||
end
|
||||
9,4 : // x4,x6
|
||||
begin
|
||||
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0;
|
||||
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg11:Intra_mbAddrB_reg11;
|
||||
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg3 :Intra_mbAddrB_reg3;
|
||||
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg13:Intra_mbAddrB_reg13;
|
||||
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg1 :Intra_mbAddrB_reg1;
|
||||
plane_HV_shifter1_len <= 2'b10; plane_HV_shifter2_len <= 2'b10;
|
||||
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1;
|
||||
end
|
||||
8,3 : // x8,x7
|
||||
begin
|
||||
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b1;
|
||||
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg15:Intra_mbAddrB_reg15;
|
||||
plane_HV_A2 <= Intra_mbAddrD_window;
|
||||
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg14:Intra_mbAddrB_reg14;
|
||||
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg0 :Intra_mbAddrB_reg0;
|
||||
plane_HV_shifter1_len <= 2'b11; plane_HV_shifter2_len <= 2'b11;
|
||||
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
plane_HV_prev_in <= 0; plane_HV_Is7 <= 0;
|
||||
plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0;
|
||||
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0;
|
||||
plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0;
|
||||
end
|
||||
endcase
|
||||
//Chroma Cb/Cr plane
|
||||
else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)
|
||||
case (blk4x4_intra_precompute_counter)
|
||||
7,4: //x1,x3
|
||||
begin
|
||||
plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0;
|
||||
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg4:Intra_mbAddrB_reg4;
|
||||
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg2:Intra_mbAddrB_reg2;
|
||||
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg6:Intra_mbAddrB_reg6;
|
||||
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg0:Intra_mbAddrB_reg0;
|
||||
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01;
|
||||
plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0;
|
||||
end
|
||||
6,3: //x2,x4
|
||||
begin
|
||||
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0;
|
||||
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg5:Intra_mbAddrB_reg5;
|
||||
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg1:Intra_mbAddrB_reg1;
|
||||
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg7:Intra_mbAddrB_reg7;
|
||||
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrD_window :Intra_mbAddrD_window;
|
||||
plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b01;
|
||||
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
plane_HV_prev_in <= 0; plane_HV_Is7 <= 0;
|
||||
plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0;
|
||||
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0;
|
||||
plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
plane_HV_prev_in <= 0; plane_HV_Is7 <= 0;
|
||||
plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0;
|
||||
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0;
|
||||
plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0;
|
||||
end
|
||||
|
||||
wire Is_HV_latch;
|
||||
assign Is_HV_latch = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter != 7 && blk4x4_intra_precompute_counter != 2 &&
|
||||
blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0) || (
|
||||
(blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && (blk4x4_intra_precompute_counter != 5 &&
|
||||
blk4x4_intra_precompute_counter != 2 && blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0)));
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
plane_HV_out_reg <= 0;
|
||||
else if (Is_HV_latch)
|
||||
plane_HV_out_reg <= plane_HV_out;
|
||||
|
||||
// 2.2 precomputation for b,c
|
||||
reg [14:0] plane_bc_in;
|
||||
reg plane_bc_IsLuma;
|
||||
wire [11:0] plane_bc;
|
||||
plane_bc_precomputation plane_bc_precomputation (
|
||||
.HV_in(plane_bc_in),
|
||||
.IsLuma(plane_bc_IsLuma),
|
||||
.bc_out(plane_bc)
|
||||
);
|
||||
always @ (mb_type_general[3:2] or Intra16x16_predmode or blk4x4_rec_counter or blk4x4_intra_precompute_counter or plane_HV_out_reg)
|
||||
//Intra16x16 plane
|
||||
if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_rec_counter == 0)
|
||||
case (blk4x4_intra_precompute_counter)
|
||||
7,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b1; end
|
||||
default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end
|
||||
endcase
|
||||
//Chroma Cb,Cr plane
|
||||
else if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20))
|
||||
case (blk4x4_intra_precompute_counter)
|
||||
5,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b0; end
|
||||
default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end
|
||||
endcase
|
||||
else
|
||||
begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end
|
||||
|
||||
wire c_latch_ena;
|
||||
assign c_latch_ena = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 7) ||
|
||||
((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 5));
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
plane_c_reg <= 0;
|
||||
else if (c_latch_ena)
|
||||
plane_c_reg <= plane_bc;
|
||||
// 2.3 precomputation for a,and latch a & b at the same time at cycle 2
|
||||
reg [7:0] plane_a_pix_in1,plane_a_pix_in2;
|
||||
wire [13:0] plane_a;
|
||||
reg [13:0] plane_a_reg;
|
||||
|
||||
plane_a_precomputation plane_a_precomputation(
|
||||
.pix_in1(plane_a_pix_in1),
|
||||
.pix_in2(plane_a_pix_in2),
|
||||
.a_out(plane_a)
|
||||
);
|
||||
always @ (blk4x4_rec_counter or blk4x4_intra_precompute_counter or Intra_mbAddrA_reg15
|
||||
or Intra_mbAddrB_reg15 or Intra_mbAddrA_reg7 or Intra_mbAddrB_reg7)
|
||||
//Intra16x16
|
||||
if (blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 2)
|
||||
begin
|
||||
plane_a_pix_in1 <= Intra_mbAddrA_reg15;
|
||||
plane_a_pix_in2 <= Intra_mbAddrB_reg15;
|
||||
end
|
||||
//Chroma
|
||||
else if((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 2)
|
||||
begin
|
||||
plane_a_pix_in1 <= Intra_mbAddrA_reg7;
|
||||
plane_a_pix_in2 <= Intra_mbAddrB_reg7;
|
||||
end
|
||||
else
|
||||
begin
|
||||
plane_a_pix_in1 <= 0;
|
||||
plane_a_pix_in2 <= 0;
|
||||
end
|
||||
|
||||
wire ab_latch_ena;
|
||||
assign ab_latch_ena = (blk4x4_intra_precompute_counter == 2);
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
plane_a_reg <= 0;
|
||||
plane_b_reg <= 0;
|
||||
end
|
||||
else if (ab_latch_ena)
|
||||
begin
|
||||
plane_a_reg <= plane_a;
|
||||
plane_b_reg <= plane_bc;
|
||||
end
|
||||
// 2.4 precomputation for main seed @ blk4x4_intra_precompute_counter == 1
|
||||
wire [13:0] main_seed_a;
|
||||
wire [11:0] main_seed_b,main_seed_c;
|
||||
wire main_seed_IsIntra16x16;
|
||||
|
||||
main_seed_precomputation main_seed_precomputation (
|
||||
.a(main_seed_a),
|
||||
.b(main_seed_b),
|
||||
.c(main_seed_c),
|
||||
.IsIntra16x16(main_seed_IsIntra16x16),
|
||||
.main_seed(main_seed)
|
||||
);
|
||||
assign main_seed_a = (blk4x4_intra_precompute_counter == 1)? plane_a_reg:0;
|
||||
assign main_seed_b = (blk4x4_intra_precompute_counter == 1)? plane_b_reg:0;
|
||||
assign main_seed_c = (blk4x4_intra_precompute_counter == 1)? plane_c_reg:0;
|
||||
assign main_seed_IsIntra16x16 = (blk4x4_intra_precompute_counter == 1)? ((blk4x4_rec_counter == 0)? 1'b1:1'b0):1'b0;
|
||||
|
||||
//----------------------------------------------------------------------------------------
|
||||
//3.calculation: by Intra_pred_PE.v
|
||||
//----------------------------------------------------------------------------------------
|
||||
|
||||
endmodule
|
||||
|
||||
module plane_a_precomputation (pix_in1,pix_in2,a_out);
|
||||
input [7:0] pix_in1,pix_in2;
|
||||
output [13:0] a_out;
|
||||
|
||||
wire [8:0] sum;
|
||||
assign sum = pix_in1 + pix_in2;
|
||||
assign a_out = {1'b0,sum,4'b0};
|
||||
endmodule
|
||||
|
||||
module plane_bc_precomputation (HV_in,IsLuma,bc_out);
|
||||
input [14:0] HV_in;
|
||||
input IsLuma;
|
||||
output [11:0] bc_out;
|
||||
|
||||
wire [16:0] multiply_4or16;
|
||||
wire [16:0] product;
|
||||
wire [5:0] addend;
|
||||
wire [16:0] sum;
|
||||
|
||||
assign multiply_4or16 = (IsLuma)? {HV_in,2'b0}:{HV_in[12:0],4'b0};
|
||||
assign product = multiply_4or16 + {{2{HV_in[14]}},HV_in};
|
||||
assign addend = (IsLuma)? 6'b100000:6'b010000; //32 for luma,16 for chroma
|
||||
assign sum = product + addend;
|
||||
assign bc_out = (IsLuma)? {sum[16],sum[16:6]}:sum[16:5];
|
||||
|
||||
endmodule
|
||||
|
||||
module plane_HV_precomputation (prev_in,A1,A2,B1,B2,shifter1_len,shifter2_len,mux1_sel,mux2_sel,Is7,HV_out);
|
||||
input [14:0] prev_in;
|
||||
input [7:0] A1,A2,B1,B2;
|
||||
input [1:0] shifter1_len,shifter2_len;
|
||||
input mux1_sel,mux2_sel;
|
||||
input Is7;
|
||||
output [14:0] HV_out;
|
||||
|
||||
wire [7:0] neg_A2;
|
||||
wire signed [8:0] A1_minus_A2;
|
||||
wire signed [11:0] shifter1_out;
|
||||
wire [11:0] mux1_out;
|
||||
wire [14:0] adder1_out;
|
||||
wire [7:0] neg_B2;
|
||||
wire signed [8:0] B1_minus_B2;
|
||||
wire signed [11:0] shifter2_out;
|
||||
wire [9:0] mux2_out;
|
||||
wire [9:0] neg_mux2_out;
|
||||
wire [11:0] adder2_out;
|
||||
//Left part,multiply by 1,2,4,8
|
||||
assign neg_A2 = ~A2;
|
||||
assign A1_minus_A2 = {1'b0,A1} + {1'b1,neg_A2} + 1;
|
||||
assign shifter1_out = A1_minus_A2 <<< shifter1_len;
|
||||
assign mux1_out = (mux1_sel == 1'b0)? {{3{A1_minus_A2[8]}},A1_minus_A2}:shifter1_out;
|
||||
assign adder1_out = prev_in + {{3{mux1_out[11]}},mux1_out};
|
||||
//Right part,multiply by 3,5,6,7
|
||||
assign neg_B2 = ~B2;
|
||||
assign B1_minus_B2 = {1'b0,B1} + {1'b1,neg_B2} + 1;
|
||||
assign shifter2_out = B1_minus_B2 <<< shifter2_len;
|
||||
assign mux2_out = (mux2_sel == 1'b0)? {B1_minus_B2[8],B1_minus_B2}:{B1_minus_B2,1'b0};
|
||||
assign neg_mux2_out = (Is7 == 1'b1)? (~mux2_out + 1):mux2_out;
|
||||
assign adder2_out = shifter2_out + {{2{neg_mux2_out[9]}},neg_mux2_out};
|
||||
assign HV_out = adder1_out + {{3{adder2_out[11]}},adder2_out};
|
||||
endmodule
|
||||
|
||||
module main_seed_precomputation (a,b,c,IsIntra16x16,main_seed);
|
||||
input [13:0] a;
|
||||
input [11:0] b,c;
|
||||
input IsIntra16x16;
|
||||
output [15:0] main_seed;
|
||||
|
||||
wire [14:0] b_x8_or_x4;
|
||||
wire [14:0] c_x8_or_x4;
|
||||
wire [11:0] neg_b;
|
||||
wire [14:0] b_x7_or_x3;
|
||||
wire [15:0] neg_b_x7_or_x3;
|
||||
wire [15:0] neg_c_x8_or_x4;
|
||||
|
||||
assign b_x8_or_x4 = (IsIntra16x16)? {b[11:0],3'b0}:{b[11],b[11:0],2'b0};
|
||||
assign c_x8_or_x4 = (IsIntra16x16)? {c[11:0],3'b0}:{c[11],c[11:0],2'b0};
|
||||
assign neg_b = ~ b;
|
||||
assign b_x7_or_x3 = b_x8_or_x4 + {{3{neg_b[11]}},neg_b} + 1;
|
||||
assign neg_b_x7_or_x3 = {~b_x7_or_x3[14],~b_x7_or_x3} + 1;
|
||||
assign neg_c_x8_or_x4 = {~c_x8_or_x4[14],~c_x8_or_x4} + 1;
|
||||
assign main_seed = {a[13],a[13],a} + (neg_c_x8_or_x4 + neg_b_x7_or_x3);
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,839 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Intra_pred_reg_ctrl.v
|
||||
// Generated : Sep 25, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Prepare the appropriate registers for PE0 ~ PE3
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Intra_pred_reg_ctrl (reset_n,gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,
|
||||
gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
|
||||
mbAddrA_availability,mbAddrC_availability,blk4x4_rec_counter,blk4x4_sum_counter,
|
||||
blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
|
||||
mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
|
||||
|
||||
Intra_mbAddrB_RAM_dout,sum_right_column_reg,
|
||||
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
||||
main_seed,PE0_sum_out,PE3_sum_out,
|
||||
|
||||
Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3,
|
||||
Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
|
||||
Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
|
||||
Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
|
||||
Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
|
||||
|
||||
Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3,
|
||||
Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
|
||||
Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
|
||||
Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
|
||||
Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
|
||||
|
||||
Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,Intra_mbAddrD_window,
|
||||
seed);
|
||||
input reset_n;
|
||||
input gclk_intra_mbAddrA_luma;
|
||||
input gclk_intra_mbAddrA_Cb;
|
||||
input gclk_intra_mbAddrA_Cr;
|
||||
input gclk_intra_mbAddrB;
|
||||
input gclk_intra_mbAddrC_luma;
|
||||
input gclk_intra_mbAddrD;
|
||||
input gclk_seed;
|
||||
input mbAddrA_availability;
|
||||
input mbAddrC_availability;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input [2:0] blk4x4_intra_preload_counter;
|
||||
input [3:0] blk4x4_intra_precompute_counter;
|
||||
input [2:0] blk4x4_intra_calculate_counter;
|
||||
input [3:0] mb_type_general;
|
||||
input [3:0] Intra4x4_predmode;
|
||||
input [1:0] Intra16x16_predmode;
|
||||
input [1:0] Intra_chroma_predmode;
|
||||
input [31:0] Intra_mbAddrB_RAM_dout;
|
||||
input [23:0] sum_right_column_reg;
|
||||
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
input [15:0] main_seed;
|
||||
input [15:0] PE0_sum_out,PE3_sum_out;
|
||||
|
||||
output [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
|
||||
output [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
|
||||
output [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
|
||||
output [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
|
||||
output [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
|
||||
|
||||
output [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
|
||||
output [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
|
||||
output [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
|
||||
output [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
|
||||
output [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
|
||||
|
||||
output [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
|
||||
output [7:0] Intra_mbAddrD_window;
|
||||
output [15:0] seed;
|
||||
|
||||
reg [7:0] Intra_mbAddrA_luma_reg0, Intra_mbAddrA_luma_reg1, Intra_mbAddrA_luma_reg2, Intra_mbAddrA_luma_reg3;
|
||||
reg [7:0] Intra_mbAddrA_luma_reg4, Intra_mbAddrA_luma_reg5, Intra_mbAddrA_luma_reg6, Intra_mbAddrA_luma_reg7;
|
||||
reg [7:0] Intra_mbAddrA_luma_reg8, Intra_mbAddrA_luma_reg9, Intra_mbAddrA_luma_reg10,Intra_mbAddrA_luma_reg11;
|
||||
reg [7:0] Intra_mbAddrA_luma_reg12,Intra_mbAddrA_luma_reg13,Intra_mbAddrA_luma_reg14,Intra_mbAddrA_luma_reg15;
|
||||
reg [7:0] Intra_mbAddrA_Cb_reg0,Intra_mbAddrA_Cb_reg1,Intra_mbAddrA_Cb_reg2,Intra_mbAddrA_Cb_reg3;
|
||||
reg [7:0] Intra_mbAddrA_Cb_reg4,Intra_mbAddrA_Cb_reg5,Intra_mbAddrA_Cb_reg6,Intra_mbAddrA_Cb_reg7;
|
||||
reg [7:0] Intra_mbAddrA_Cr_reg0,Intra_mbAddrA_Cr_reg1,Intra_mbAddrA_Cr_reg2,Intra_mbAddrA_Cr_reg3;
|
||||
reg [7:0] Intra_mbAddrA_Cr_reg4,Intra_mbAddrA_Cr_reg5,Intra_mbAddrA_Cr_reg6,Intra_mbAddrA_Cr_reg7;
|
||||
reg [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
|
||||
reg [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
|
||||
reg [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
|
||||
reg [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
|
||||
reg [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
|
||||
|
||||
reg [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
|
||||
reg [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
|
||||
reg [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
|
||||
reg [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
|
||||
reg [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
|
||||
|
||||
reg [7:0] Intra_mbAddrC_reg0,Intra_mbAddrC_reg1,Intra_mbAddrC_reg2,Intra_mbAddrC_reg3;
|
||||
reg [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
|
||||
|
||||
reg [7:0] Intra_mbAddrD_reg0,Intra_mbAddrD_reg1,Intra_mbAddrD_reg2;
|
||||
reg [7:0] Intra_mbAddrD_reg3,Intra_mbAddrD_reg4;
|
||||
reg [7:0] Intra_mbAddrD_LeftMB_luma_reg,Intra_mbAddrD_LeftMB_Cb_reg,Intra_mbAddrD_LeftMB_Cr_reg;
|
||||
reg [7:0] Intra_mbAddrD_window;
|
||||
|
||||
reg [15:0] seed_0,seed_1,seed_2,seed_3;
|
||||
reg [15:0] seed;
|
||||
//---------------------------------------------------------------------
|
||||
//Intra_mbAddrA_luma_reg0 ~ 15
|
||||
//Intra_mbAddrA_Cb_reg0 ~ 7
|
||||
//Intra_mbAddrA_Cr_reg0 ~ 7
|
||||
//---------------------------------------------------------------------
|
||||
always @ (posedge gclk_intra_mbAddrA_luma or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
Intra_mbAddrA_luma_reg0 <= 0; Intra_mbAddrA_luma_reg1 <= 0; Intra_mbAddrA_luma_reg2 <= 0;
|
||||
Intra_mbAddrA_luma_reg3 <= 0; Intra_mbAddrA_luma_reg4 <= 0; Intra_mbAddrA_luma_reg5 <= 0;
|
||||
Intra_mbAddrA_luma_reg6 <= 0; Intra_mbAddrA_luma_reg7 <= 0; Intra_mbAddrA_luma_reg8 <= 0;
|
||||
Intra_mbAddrA_luma_reg9 <= 0; Intra_mbAddrA_luma_reg10 <= 0; Intra_mbAddrA_luma_reg11 <= 0;
|
||||
Intra_mbAddrA_luma_reg12 <= 0; Intra_mbAddrA_luma_reg13 <= 0; Intra_mbAddrA_luma_reg14 <= 0;
|
||||
Intra_mbAddrA_luma_reg15 <= 0;
|
||||
end
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
0,1,4,5:
|
||||
begin
|
||||
Intra_mbAddrA_luma_reg0 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_luma_reg1 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_luma_reg2 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_luma_reg3 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
2,3,6,7:
|
||||
begin
|
||||
Intra_mbAddrA_luma_reg4 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_luma_reg5 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_luma_reg6 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_luma_reg7 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
8,9,12,13:
|
||||
begin
|
||||
Intra_mbAddrA_luma_reg8 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_luma_reg9 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_luma_reg10 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_luma_reg11 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
10,11,14,15:
|
||||
begin
|
||||
Intra_mbAddrA_luma_reg12 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_luma_reg13 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_luma_reg14 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_luma_reg15 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
endcase
|
||||
|
||||
always @ (posedge gclk_intra_mbAddrA_Cb or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
Intra_mbAddrA_Cb_reg0 <= 0; Intra_mbAddrA_Cb_reg1 <= 0; Intra_mbAddrA_Cb_reg2 <= 0;
|
||||
Intra_mbAddrA_Cb_reg3 <= 0; Intra_mbAddrA_Cb_reg4 <= 0; Intra_mbAddrA_Cb_reg5 <= 0;
|
||||
Intra_mbAddrA_Cb_reg6 <= 0; Intra_mbAddrA_Cb_reg7 <= 0;
|
||||
end
|
||||
else if (blk4x4_rec_counter == 17)
|
||||
begin
|
||||
Intra_mbAddrA_Cb_reg0 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_Cb_reg1 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_Cb_reg2 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_Cb_reg3 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrA_Cb_reg4 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_Cb_reg5 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_Cb_reg6 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_Cb_reg7 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
|
||||
always @ (posedge gclk_intra_mbAddrA_Cr or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
Intra_mbAddrA_Cr_reg0 <= 0; Intra_mbAddrA_Cr_reg1 <= 0; Intra_mbAddrA_Cr_reg2 <= 0;
|
||||
Intra_mbAddrA_Cr_reg3 <= 0; Intra_mbAddrA_Cr_reg4 <= 0; Intra_mbAddrA_Cr_reg5 <= 0;
|
||||
Intra_mbAddrA_Cr_reg6 <= 0; Intra_mbAddrA_Cr_reg7 <= 0;
|
||||
end
|
||||
else if (blk4x4_rec_counter == 21)
|
||||
begin
|
||||
Intra_mbAddrA_Cr_reg0 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_Cr_reg1 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_Cr_reg2 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_Cr_reg3 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrA_Cr_reg4 <= sum_right_column_reg[7:0];
|
||||
Intra_mbAddrA_Cr_reg5 <= sum_right_column_reg[15:8];
|
||||
Intra_mbAddrA_Cr_reg6 <= sum_right_column_reg[23:16];
|
||||
Intra_mbAddrA_Cr_reg7 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
//---------------------------------------------------------------------
|
||||
//Intra_mbAddrB_reg0 ~ 15
|
||||
//---------------------------------------------------------------------
|
||||
always @ (posedge gclk_intra_mbAddrB or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
Intra_mbAddrB_reg0 <= 0; Intra_mbAddrB_reg1 <= 0; Intra_mbAddrB_reg2 <= 0;
|
||||
Intra_mbAddrB_reg3 <= 0; Intra_mbAddrB_reg4 <= 0; Intra_mbAddrB_reg5 <= 0;
|
||||
Intra_mbAddrB_reg6 <= 0; Intra_mbAddrB_reg7 <= 0; Intra_mbAddrB_reg8 <= 0;
|
||||
Intra_mbAddrB_reg9 <= 0; Intra_mbAddrB_reg10 <= 0; Intra_mbAddrB_reg11 <= 0;
|
||||
Intra_mbAddrB_reg12 <= 0; Intra_mbAddrB_reg13 <= 0; Intra_mbAddrB_reg14 <= 0;
|
||||
Intra_mbAddrB_reg15 <= 0;
|
||||
end
|
||||
//Intra4x4
|
||||
else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
||||
begin
|
||||
// blk 0,1,4,5,load from RAM
|
||||
if (blk4x4_intra_preload_counter == 3'b001)
|
||||
case (blk4x4_rec_counter)
|
||||
0:
|
||||
begin
|
||||
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
1:
|
||||
begin
|
||||
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
4:
|
||||
begin
|
||||
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
5:
|
||||
begin
|
||||
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
endcase
|
||||
//other blocks,from blk4x4_sum output
|
||||
else if ((blk4x4_rec_counter != 10 || blk4x4_rec_counter != 11 || blk4x4_rec_counter != 14 ||
|
||||
blk4x4_rec_counter != 15) && blk4x4_sum_counter == 3'd3)
|
||||
case (blk4x4_rec_counter)
|
||||
0,2,8:
|
||||
begin
|
||||
Intra_mbAddrB_reg0 <= blk4x4_sum_PE0_out;
|
||||
Intra_mbAddrB_reg1 <= blk4x4_sum_PE1_out;
|
||||
Intra_mbAddrB_reg2 <= blk4x4_sum_PE2_out;
|
||||
Intra_mbAddrB_reg3 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
1,3,9:
|
||||
begin
|
||||
Intra_mbAddrB_reg4 <= blk4x4_sum_PE0_out;
|
||||
Intra_mbAddrB_reg5 <= blk4x4_sum_PE1_out;
|
||||
Intra_mbAddrB_reg6 <= blk4x4_sum_PE2_out;
|
||||
Intra_mbAddrB_reg7 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
4,6,12:
|
||||
begin
|
||||
Intra_mbAddrB_reg8 <= blk4x4_sum_PE0_out;
|
||||
Intra_mbAddrB_reg9 <= blk4x4_sum_PE1_out;
|
||||
Intra_mbAddrB_reg10 <= blk4x4_sum_PE2_out;
|
||||
Intra_mbAddrB_reg11 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
5,7,13:
|
||||
begin
|
||||
Intra_mbAddrB_reg12 <= blk4x4_sum_PE0_out;
|
||||
Intra_mbAddrB_reg13 <= blk4x4_sum_PE1_out;
|
||||
Intra_mbAddrB_reg14 <= blk4x4_sum_PE2_out;
|
||||
Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
//Intra16x16
|
||||
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
||||
case (blk4x4_intra_preload_counter)
|
||||
3'b100:
|
||||
begin
|
||||
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
3'b010:
|
||||
begin
|
||||
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
endcase
|
||||
//Chroma
|
||||
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
||||
begin
|
||||
if (blk4x4_intra_preload_counter == 3'b010)
|
||||
begin
|
||||
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
else if (blk4x4_intra_preload_counter == 3'b001)
|
||||
begin
|
||||
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
end
|
||||
//--------------------------------------------------------
|
||||
//Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with
|
||||
// blkIdx = 0/1/4/5
|
||||
//--------------------------------------------------------
|
||||
|
||||
always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
Intra_mbAddrC_reg0 <= 0; Intra_mbAddrC_reg1 <= 0;
|
||||
Intra_mbAddrC_reg2 <= 0; Intra_mbAddrC_reg3 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrC_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
||||
Intra_mbAddrC_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
||||
Intra_mbAddrC_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
||||
Intra_mbAddrC_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
end
|
||||
//--------------------------------------------------------
|
||||
//Intra_mbAddrD_reg0 ~ 5
|
||||
//Intra_mbAddrD_LeftMB_reg
|
||||
//--------------------------------------------------------
|
||||
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
Intra_mbAddrD_LeftMB_luma_reg <= 0;
|
||||
else if (blk4x4_rec_counter == 15)
|
||||
Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3) //Intra4x4
|
||||
case (blk4x4_rec_counter)
|
||||
0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3;
|
||||
2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7;
|
||||
8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11;
|
||||
endcase
|
||||
|
||||
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
Intra_mbAddrD_LeftMB_Cb_reg <= 0;
|
||||
else if (blk4x4_rec_counter == 19)
|
||||
Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
|
||||
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
Intra_mbAddrD_LeftMB_Cr_reg <= 0;
|
||||
else if (blk4x4_rec_counter == 23)
|
||||
Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
|
||||
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0;
|
||||
Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0;
|
||||
end
|
||||
else if (mb_type_general[3:2] == 2'b11)
|
||||
begin
|
||||
//load from Intra_mbAddrB_RAM for blk 1/4/5
|
||||
if (blk4x4_intra_preload_counter == 3'b010)
|
||||
case (blk4x4_rec_counter)
|
||||
1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24];
|
||||
endcase
|
||||
//update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4
|
||||
//After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7
|
||||
//After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13
|
||||
//After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out;
|
||||
1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out;
|
||||
2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out;
|
||||
3 :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out;
|
||||
4,9 :Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out;
|
||||
endcase
|
||||
end
|
||||
//---------------------------
|
||||
//sliding window output
|
||||
//---------------------------
|
||||
//Intra_mbAddrA_reg0 ~ 15
|
||||
always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or
|
||||
blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode
|
||||
or mbAddrA_availability
|
||||
|
||||
or Intra_mbAddrA_luma_reg0 or Intra_mbAddrA_luma_reg1 or Intra_mbAddrA_luma_reg2
|
||||
or Intra_mbAddrA_luma_reg3 or Intra_mbAddrA_luma_reg4 or Intra_mbAddrA_luma_reg5
|
||||
or Intra_mbAddrA_luma_reg6 or Intra_mbAddrA_luma_reg7 or Intra_mbAddrA_luma_reg8
|
||||
or Intra_mbAddrA_luma_reg9 or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11
|
||||
or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14
|
||||
or Intra_mbAddrA_luma_reg15
|
||||
|
||||
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2
|
||||
or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5
|
||||
or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
||||
|
||||
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2
|
||||
or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5
|
||||
or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
||||
if (mb_type_general[3] == 1'b1)
|
||||
begin
|
||||
//Intra4x4
|
||||
//Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane
|
||||
if (blk4x4_rec_counter < 16 &&
|
||||
(mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && (
|
||||
(Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
||||
(Intra16x16_predmode == `Intra16x16_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
||||
(Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_precompute_counter != 0)))))
|
||||
begin
|
||||
Intra_mbAddrA_reg0 <= Intra_mbAddrA_luma_reg0;
|
||||
Intra_mbAddrA_reg1 <= Intra_mbAddrA_luma_reg1;
|
||||
Intra_mbAddrA_reg2 <= Intra_mbAddrA_luma_reg2;
|
||||
Intra_mbAddrA_reg3 <= Intra_mbAddrA_luma_reg3;
|
||||
Intra_mbAddrA_reg4 <= Intra_mbAddrA_luma_reg4;
|
||||
Intra_mbAddrA_reg5 <= Intra_mbAddrA_luma_reg5;
|
||||
Intra_mbAddrA_reg6 <= Intra_mbAddrA_luma_reg6;
|
||||
Intra_mbAddrA_reg7 <= Intra_mbAddrA_luma_reg7;
|
||||
Intra_mbAddrA_reg8 <= Intra_mbAddrA_luma_reg8;
|
||||
Intra_mbAddrA_reg9 <= Intra_mbAddrA_luma_reg9;
|
||||
Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10;
|
||||
Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11;
|
||||
Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12;
|
||||
Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13;
|
||||
Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14;
|
||||
Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15;
|
||||
end
|
||||
//Chroma Cb
|
||||
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && (
|
||||
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
||||
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
||||
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
||||
begin
|
||||
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cb_reg0;
|
||||
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cb_reg1;
|
||||
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cb_reg2;
|
||||
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cb_reg3;
|
||||
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cb_reg4;
|
||||
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cb_reg5;
|
||||
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cb_reg6;
|
||||
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cb_reg7;
|
||||
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
||||
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
||||
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
||||
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
||||
end
|
||||
//Chroma Cr
|
||||
else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && (
|
||||
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
||||
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
||||
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
||||
begin
|
||||
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cr_reg0;
|
||||
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cr_reg1;
|
||||
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cr_reg2;
|
||||
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cr_reg3;
|
||||
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cr_reg4;
|
||||
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cr_reg5;
|
||||
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cr_reg6;
|
||||
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cr_reg7;
|
||||
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
||||
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
||||
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
||||
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
||||
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
||||
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
||||
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
||||
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
||||
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
||||
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
||||
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
||||
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
||||
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
||||
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
||||
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
||||
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
||||
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
||||
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
||||
end
|
||||
//Intra_mbAddrA_window0 ~ 3
|
||||
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
||||
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability
|
||||
|
||||
or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
|
||||
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
||||
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
||||
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
||||
|
||||
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3
|
||||
or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
||||
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3
|
||||
or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
||||
if (mb_type_general[3] == 1'b1)
|
||||
begin
|
||||
//Intra4x4 && Intra16x16_horizontal
|
||||
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
||||
(mb_type_general[2] == 1'b1 || (
|
||||
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal))))
|
||||
case (blk4x4_rec_counter)
|
||||
0,1,4,5:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3;
|
||||
end
|
||||
2,3,6,7:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7;
|
||||
end
|
||||
8,9,12,13:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11;
|
||||
end
|
||||
10,11,14,15:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
||||
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
||||
end
|
||||
endcase
|
||||
//Chroma Cb/Cr Horizontal & DC
|
||||
else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 &&
|
||||
(Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability)))
|
||||
case (blk4x4_rec_counter)
|
||||
16,17:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0;
|
||||
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2;
|
||||
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3;
|
||||
end
|
||||
18,19:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4;
|
||||
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6;
|
||||
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7;
|
||||
end
|
||||
20,21:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0;
|
||||
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2;
|
||||
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3;
|
||||
end
|
||||
22,23:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4;
|
||||
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5;
|
||||
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6;
|
||||
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
||||
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
||||
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
||||
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
||||
end
|
||||
|
||||
|
||||
//Intra_mbAddrB_window0 ~ 3
|
||||
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
||||
or blk4x4_intra_calculate_counter or blk4x4_rec_counter
|
||||
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2
|
||||
or Intra_mbAddrB_reg3 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5
|
||||
or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8
|
||||
or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
||||
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14
|
||||
or Intra_mbAddrB_reg15)
|
||||
if (mb_type_general[3] == 1'b1)
|
||||
begin
|
||||
//Intra4x4 && Intra16x16_Vertical
|
||||
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
||||
(mb_type_general[2] == 1'b1 || (
|
||||
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical))))
|
||||
case (blk4x4_rec_counter)
|
||||
0,2,8,10:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
||||
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
||||
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
||||
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
||||
end
|
||||
1,3,9,11:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
||||
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
||||
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
||||
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
||||
end
|
||||
4,6,12,14:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8;
|
||||
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9;
|
||||
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10;
|
||||
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11;
|
||||
end
|
||||
5,7,13,15:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12;
|
||||
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13;
|
||||
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14;
|
||||
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
||||
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
||||
end
|
||||
endcase
|
||||
//Chroma Cb/Cr Vertical and DC
|
||||
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 &&
|
||||
(Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0)
|
||||
case (blk4x4_rec_counter)
|
||||
16,18,20,22:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
||||
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
||||
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
||||
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
||||
end
|
||||
17,19,21,23:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
||||
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
||||
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
||||
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
||||
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
||||
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
||||
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
||||
end
|
||||
//Intra_mbAddrC_window0 ~ 3
|
||||
always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode
|
||||
or Intra_mbAddrC_reg0 or Intra_mbAddrC_reg1 or Intra_mbAddrC_reg2 or Intra_mbAddrC_reg3
|
||||
or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7
|
||||
or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
||||
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
||||
or mbAddrC_availability or Intra_mbAddrB_window3)
|
||||
if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && (
|
||||
Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16)
|
||||
case (blk4x4_rec_counter)
|
||||
0,1,4:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0;
|
||||
Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1;
|
||||
Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2;
|
||||
Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3;
|
||||
end
|
||||
5:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15;
|
||||
Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15;
|
||||
Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15;
|
||||
Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15;
|
||||
end
|
||||
2,8,10:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg4;
|
||||
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg5;
|
||||
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg6;
|
||||
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg7;
|
||||
end
|
||||
9:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg8;
|
||||
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg9;
|
||||
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg10;
|
||||
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg11;
|
||||
end
|
||||
6,12,14:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg12;
|
||||
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg13;
|
||||
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg14;
|
||||
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg15;
|
||||
end
|
||||
3,11,7,13,15:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= Intra_mbAddrB_window3;
|
||||
Intra_mbAddrC_window1 <= Intra_mbAddrB_window3;
|
||||
Intra_mbAddrC_window2 <= Intra_mbAddrB_window3;
|
||||
Intra_mbAddrC_window3 <= Intra_mbAddrB_window3;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
||||
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
||||
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
||||
end
|
||||
|
||||
//Intra_mbAddrD_window
|
||||
always @ (mb_type_general[3:2] or blk4x4_rec_counter
|
||||
or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter
|
||||
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
||||
or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2
|
||||
or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4
|
||||
or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg)
|
||||
//Intra
|
||||
if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0))
|
||||
begin
|
||||
//Intra luma
|
||||
if (blk4x4_rec_counter[4] == 1'b0)
|
||||
begin
|
||||
//Intra4x4 luma
|
||||
if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right ||
|
||||
Intra4x4_predmode == `Intra4x4_Vertical_Right ||
|
||||
Intra4x4_predmode == `Intra4x4_Horizontal_Down))
|
||||
case (blk4x4_rec_counter[3:0])
|
||||
0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg;
|
||||
3,5,13 :Intra_mbAddrD_window <= Intra_mbAddrD_reg0;
|
||||
1,6,11 :Intra_mbAddrD_window <= Intra_mbAddrD_reg1;
|
||||
9,15 :Intra_mbAddrD_window <= Intra_mbAddrD_reg2;
|
||||
12 :Intra_mbAddrD_window <= Intra_mbAddrD_reg3;
|
||||
4,7,14 :Intra_mbAddrD_window <= Intra_mbAddrD_reg4;
|
||||
endcase
|
||||
//Intra16x16
|
||||
else
|
||||
Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0;
|
||||
end
|
||||
//Intra chroma
|
||||
else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane)
|
||||
Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg;
|
||||
else
|
||||
Intra_mbAddrD_window <= 0;
|
||||
end
|
||||
//Inter
|
||||
else
|
||||
Intra_mbAddrD_window <= 0;
|
||||
|
||||
//seed
|
||||
always @ (posedge gclk_seed or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
seed_0 <= 0; seed_1 <= 0; seed_2 <= 0;
|
||||
end
|
||||
else if (blk4x4_intra_precompute_counter == 1)
|
||||
seed_0 <= main_seed;
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
0,2,8,16,20 :seed_0 <= PE3_sum_out;
|
||||
1,9 :seed_1 <= PE0_sum_out;
|
||||
3,11 :seed_2 <= PE0_sum_out;
|
||||
endcase
|
||||
|
||||
always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode
|
||||
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2)
|
||||
if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16)
|
||||
case (blk4x4_rec_counter)
|
||||
0,2,8,10:seed <= seed_0;
|
||||
4,12 :seed <= seed_1;
|
||||
6,14 :seed <= seed_2;
|
||||
default :seed <= 0;
|
||||
endcase
|
||||
else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15)
|
||||
if (blk4x4_rec_counter[0] == 1'b0) //16,18,20,22
|
||||
seed <= seed_0;
|
||||
else
|
||||
seed <= 0;
|
||||
else
|
||||
seed <= 0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,334 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : Intra_pred_top.v
|
||||
// Generated : Sep 30,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Top module of Intra prediction
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module Intra_pred_top (clk,reset_n,
|
||||
gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,
|
||||
gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,gclk_Intra_mbAddrB_RAM,
|
||||
mb_num_h,mb_num_v,mb_type_general,NextMB_IsSkip,
|
||||
Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
|
||||
blk4x4_rec_counter,trigger_blk4x4_intra_pred,blk4x4_sum_counter,
|
||||
sum_right_column_reg,blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
||||
blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
|
||||
blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
|
||||
blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
|
||||
blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
|
||||
Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din,
|
||||
|
||||
PE0_out,PE1_out,PE2_out,PE3_out,Intra4x4_predmode,
|
||||
blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
|
||||
end_of_one_blk4x4_intra,Intra_mbAddrB_RAM_rd
|
||||
);
|
||||
input clk,reset_n;
|
||||
input gclk_intra_mbAddrA_luma;
|
||||
input gclk_intra_mbAddrA_Cb;
|
||||
input gclk_intra_mbAddrA_Cr;
|
||||
input gclk_intra_mbAddrB;
|
||||
input gclk_intra_mbAddrC_luma;
|
||||
input gclk_intra_mbAddrD;
|
||||
input gclk_seed;
|
||||
input gclk_Intra_mbAddrB_RAM;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [3:0] mb_type_general;
|
||||
input NextMB_IsSkip;
|
||||
input [1:0] Intra16x16_predmode;
|
||||
input [63:0] Intra4x4_predmode_CurrMb;
|
||||
input [1:0] Intra_chroma_predmode;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input trigger_blk4x4_intra_pred;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input [23:0] sum_right_column_reg;
|
||||
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
input [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
|
||||
input [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
|
||||
input [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
|
||||
input [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
|
||||
input Intra_mbAddrB_RAM_wr;
|
||||
input [6:0] Intra_mbAddrB_RAM_wr_addr;
|
||||
input [31:0] Intra_mbAddrB_RAM_din;
|
||||
|
||||
output [7:0] PE0_out;
|
||||
output [7:0] PE1_out;
|
||||
output [7:0] PE2_out;
|
||||
output [7:0] PE3_out;
|
||||
output [3:0] Intra4x4_predmode;
|
||||
output [2:0] blk4x4_intra_preload_counter;
|
||||
output [3:0] blk4x4_intra_precompute_counter;
|
||||
output [2:0] blk4x4_intra_calculate_counter;
|
||||
output end_of_one_blk4x4_intra;
|
||||
output Intra_mbAddrB_RAM_rd;
|
||||
|
||||
wire blkAddrA_availability,blkAddrB_availability;
|
||||
wire mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
|
||||
wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
wire [15:0] PE0_sum_out,PE3_sum_out;
|
||||
wire Intra_mbAddrB_RAM_rd;
|
||||
wire [6:0] Intra_mbAddrB_RAM_rd_addr;
|
||||
wire [31:0] Intra_mbAddrB_RAM_dout;
|
||||
|
||||
wire [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
|
||||
wire [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
|
||||
wire [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
|
||||
wire [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
|
||||
wire [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
|
||||
|
||||
wire [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
|
||||
wire [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
|
||||
wire [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
|
||||
wire [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
|
||||
wire [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
|
||||
|
||||
wire [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
|
||||
wire [7:0] Intra_mbAddrD_window;
|
||||
wire [15:0] main_seed,seed;
|
||||
wire [11:0] plane_b_reg,plane_c_reg;
|
||||
|
||||
Intra_pred_pipeline Intra_pred_pipeline (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_type_general(mb_type_general),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
|
||||
.mb_num_v(mb_num_v),
|
||||
.mb_num_h(mb_num_h),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.NextMB_IsSkip(NextMB_IsSkip),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0),
|
||||
.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1),
|
||||
.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2),
|
||||
.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
|
||||
.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4),
|
||||
.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5),
|
||||
.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6),
|
||||
.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
|
||||
.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8),
|
||||
.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9),
|
||||
.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
|
||||
.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
|
||||
.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
|
||||
.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
|
||||
.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
|
||||
.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
|
||||
.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0),
|
||||
.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1),
|
||||
.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2),
|
||||
.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
|
||||
.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4),
|
||||
.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5),
|
||||
.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6),
|
||||
.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
|
||||
.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8),
|
||||
.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9),
|
||||
.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
|
||||
.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
|
||||
.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
|
||||
.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
|
||||
.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
|
||||
.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
|
||||
.Intra_mbAddrD_window(Intra_mbAddrD_window),
|
||||
|
||||
.Intra4x4_predmode(Intra4x4_predmode),
|
||||
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
||||
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
||||
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
||||
.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
|
||||
.blkAddrA_availability(blkAddrA_availability),
|
||||
.blkAddrB_availability(blkAddrB_availability),
|
||||
.mbAddrA_availability(mbAddrA_availability),
|
||||
.mbAddrB_availability(mbAddrB_availability),
|
||||
.mbAddrC_availability(mbAddrC_availability),
|
||||
.main_seed(main_seed),
|
||||
.plane_b_reg(plane_b_reg),
|
||||
.plane_c_reg(plane_c_reg),
|
||||
.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd),
|
||||
.Intra_mbAddrB_RAM_rd_addr(Intra_mbAddrB_RAM_rd_addr)
|
||||
);
|
||||
|
||||
Intra_pred_reg_ctrl Intra_pred_reg_ctrl (
|
||||
.reset_n(reset_n),
|
||||
.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
|
||||
.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
|
||||
.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
|
||||
.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
|
||||
.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
|
||||
.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
|
||||
.gclk_seed(gclk_seed),
|
||||
.mbAddrA_availability(mbAddrA_availability),
|
||||
.mbAddrC_availability(mbAddrC_availability),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
||||
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
||||
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
||||
.mb_type_general(mb_type_general),
|
||||
.Intra4x4_predmode(Intra4x4_predmode),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.Intra_mbAddrB_RAM_dout(Intra_mbAddrB_RAM_dout),
|
||||
.sum_right_column_reg(sum_right_column_reg),
|
||||
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
||||
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
||||
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
||||
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
||||
.main_seed(main_seed),
|
||||
.PE0_sum_out(PE0_sum_out),
|
||||
.PE3_sum_out(PE3_sum_out),
|
||||
|
||||
.Intra_mbAddrA_window0(Intra_mbAddrA_window0),
|
||||
.Intra_mbAddrA_window1(Intra_mbAddrA_window1),
|
||||
.Intra_mbAddrA_window2(Intra_mbAddrA_window2),
|
||||
.Intra_mbAddrA_window3(Intra_mbAddrA_window3),
|
||||
.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0),
|
||||
.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1),
|
||||
.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2),
|
||||
.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
|
||||
.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4),
|
||||
.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5),
|
||||
.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6),
|
||||
.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
|
||||
.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8),
|
||||
.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9),
|
||||
.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
|
||||
.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
|
||||
.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
|
||||
.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
|
||||
.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
|
||||
.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
|
||||
.Intra_mbAddrB_window0(Intra_mbAddrB_window0),
|
||||
.Intra_mbAddrB_window1(Intra_mbAddrB_window1),
|
||||
.Intra_mbAddrB_window2(Intra_mbAddrB_window2),
|
||||
.Intra_mbAddrB_window3(Intra_mbAddrB_window3),
|
||||
.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0),
|
||||
.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1),
|
||||
.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2),
|
||||
.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
|
||||
.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4),
|
||||
.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5),
|
||||
.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6),
|
||||
.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
|
||||
.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8),
|
||||
.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9),
|
||||
.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
|
||||
.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
|
||||
.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
|
||||
.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
|
||||
.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
|
||||
.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
|
||||
.Intra_mbAddrC_window0(Intra_mbAddrC_window0),
|
||||
.Intra_mbAddrC_window1(Intra_mbAddrC_window1),
|
||||
.Intra_mbAddrC_window2(Intra_mbAddrC_window2),
|
||||
.Intra_mbAddrC_window3(Intra_mbAddrC_window3),
|
||||
.Intra_mbAddrD_window(Intra_mbAddrD_window),
|
||||
.seed(seed)
|
||||
);
|
||||
|
||||
Intra_pred_PE Intra_pred_PE (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_type_general(mb_type_general),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
||||
.Intra4x4_predmode(Intra4x4_predmode),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.blkAddrA_availability(blkAddrA_availability),
|
||||
.blkAddrB_availability(blkAddrB_availability),
|
||||
.mbAddrA_availability(mbAddrA_availability),
|
||||
.mbAddrB_availability(mbAddrB_availability),
|
||||
.Intra_mbAddrA_window0({8'b0,Intra_mbAddrA_window0}),
|
||||
.Intra_mbAddrA_window1({8'b0,Intra_mbAddrA_window1}),
|
||||
.Intra_mbAddrA_window2({8'b0,Intra_mbAddrA_window2}),
|
||||
.Intra_mbAddrA_window3({8'b0,Intra_mbAddrA_window3}),
|
||||
.Intra_mbAddrB_window0({8'b0,Intra_mbAddrB_window0}),
|
||||
.Intra_mbAddrB_window1({8'b0,Intra_mbAddrB_window1}),
|
||||
.Intra_mbAddrB_window2({8'b0,Intra_mbAddrB_window2}),
|
||||
.Intra_mbAddrB_window3({8'b0,Intra_mbAddrB_window3}),
|
||||
.Intra_mbAddrC_window0({8'b0,Intra_mbAddrC_window0}),
|
||||
.Intra_mbAddrC_window1({8'b0,Intra_mbAddrC_window1}),
|
||||
.Intra_mbAddrC_window2({8'b0,Intra_mbAddrC_window2}),
|
||||
.Intra_mbAddrC_window3({8'b0,Intra_mbAddrC_window3}),
|
||||
.Intra_mbAddrD_window({8'b0,Intra_mbAddrD_window}),
|
||||
.Intra_mbAddrA_reg0({8'b0,Intra_mbAddrA_reg0}),
|
||||
.Intra_mbAddrA_reg1({8'b0,Intra_mbAddrA_reg1}),
|
||||
.Intra_mbAddrA_reg2({8'b0,Intra_mbAddrA_reg2}),
|
||||
.Intra_mbAddrA_reg3({8'b0,Intra_mbAddrA_reg3}),
|
||||
.Intra_mbAddrA_reg4({8'b0,Intra_mbAddrA_reg4}),
|
||||
.Intra_mbAddrA_reg5({8'b0,Intra_mbAddrA_reg5}),
|
||||
.Intra_mbAddrA_reg6({8'b0,Intra_mbAddrA_reg6}),
|
||||
.Intra_mbAddrA_reg7({8'b0,Intra_mbAddrA_reg7}),
|
||||
.Intra_mbAddrA_reg8({8'b0,Intra_mbAddrA_reg8}),
|
||||
.Intra_mbAddrA_reg9({8'b0,Intra_mbAddrA_reg9}),
|
||||
.Intra_mbAddrA_reg10({8'b0,Intra_mbAddrA_reg10}),
|
||||
.Intra_mbAddrA_reg11({8'b0,Intra_mbAddrA_reg11}),
|
||||
.Intra_mbAddrA_reg12({8'b0,Intra_mbAddrA_reg12}),
|
||||
.Intra_mbAddrA_reg13({8'b0,Intra_mbAddrA_reg13}),
|
||||
.Intra_mbAddrA_reg14({8'b0,Intra_mbAddrA_reg14}),
|
||||
.Intra_mbAddrA_reg15({8'b0,Intra_mbAddrA_reg15}),
|
||||
.Intra_mbAddrB_reg0({8'b0,Intra_mbAddrB_reg0}),
|
||||
.Intra_mbAddrB_reg1({8'b0,Intra_mbAddrB_reg1}),
|
||||
.Intra_mbAddrB_reg2({8'b0,Intra_mbAddrB_reg2}),
|
||||
.Intra_mbAddrB_reg3({8'b0,Intra_mbAddrB_reg3}),
|
||||
.Intra_mbAddrB_reg4({8'b0,Intra_mbAddrB_reg4}),
|
||||
.Intra_mbAddrB_reg5({8'b0,Intra_mbAddrB_reg5}),
|
||||
.Intra_mbAddrB_reg6({8'b0,Intra_mbAddrB_reg6}),
|
||||
.Intra_mbAddrB_reg7({8'b0,Intra_mbAddrB_reg7}),
|
||||
.Intra_mbAddrB_reg8({8'b0,Intra_mbAddrB_reg8}),
|
||||
.Intra_mbAddrB_reg9({8'b0,Intra_mbAddrB_reg9}),
|
||||
.Intra_mbAddrB_reg10({8'b0,Intra_mbAddrB_reg10}),
|
||||
.Intra_mbAddrB_reg11({8'b0,Intra_mbAddrB_reg11}),
|
||||
.Intra_mbAddrB_reg12({8'b0,Intra_mbAddrB_reg12}),
|
||||
.Intra_mbAddrB_reg13({8'b0,Intra_mbAddrB_reg13}),
|
||||
.Intra_mbAddrB_reg14({8'b0,Intra_mbAddrB_reg14}),
|
||||
.Intra_mbAddrB_reg15({8'b0,Intra_mbAddrB_reg15}),
|
||||
.blk4x4_pred_output0({8'b0,blk4x4_pred_output0}),
|
||||
.blk4x4_pred_output1({8'b0,blk4x4_pred_output1}),
|
||||
.blk4x4_pred_output2({8'b0,blk4x4_pred_output2}),
|
||||
.blk4x4_pred_output4({8'b0,blk4x4_pred_output4}),
|
||||
.blk4x4_pred_output5({8'b0,blk4x4_pred_output5}),
|
||||
.blk4x4_pred_output6({8'b0,blk4x4_pred_output6}),
|
||||
.blk4x4_pred_output8({8'b0,blk4x4_pred_output8}),
|
||||
.blk4x4_pred_output9({8'b0,blk4x4_pred_output9}),
|
||||
.blk4x4_pred_output10({8'b0,blk4x4_pred_output10}),
|
||||
.blk4x4_pred_output12({8'b0,blk4x4_pred_output12}),
|
||||
.blk4x4_pred_output13({8'b0,blk4x4_pred_output13}),
|
||||
.blk4x4_pred_output14({8'b0,blk4x4_pred_output14}),
|
||||
.seed(seed),
|
||||
.b(plane_b_reg),
|
||||
.c(plane_c_reg),
|
||||
|
||||
.PE0_out(PE0_out),
|
||||
.PE1_out(PE1_out),
|
||||
.PE2_out(PE2_out),
|
||||
.PE3_out(PE3_out),
|
||||
.PE0_sum_out(PE0_sum_out),
|
||||
.PE3_sum_out(PE3_sum_out)
|
||||
);
|
||||
ram_sync_1r_sync_1w #(`Intra_mbAddrB_RAM_data_width,`Intra_mbAddrB_RAM_data_depth)
|
||||
Intra_mbAddrB_RAM (
|
||||
.clk(gclk_Intra_mbAddrB_RAM),
|
||||
.rst_n(reset_n),
|
||||
.wr_n(~Intra_mbAddrB_RAM_wr),
|
||||
.rd_n(~Intra_mbAddrB_RAM_rd),
|
||||
.wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
||||
.rd_addr(Intra_mbAddrB_RAM_rd_addr),
|
||||
.data_in(Intra_mbAddrB_RAM_din),
|
||||
.data_out(Intra_mbAddrB_RAM_dout)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,678 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : NumCoeffTrailingOnes_decoding.v
|
||||
// Generated : June 8, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding for Table 9-5 on Page159 of H.264/AVC standard 2003
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module NumCoeffTrailingOnes_decoding (clk,reset_n,cavlc_decoder_state,heading_one_pos,BitStream_buffer_output,
|
||||
nC,TrailingOnes,TotalCoeff,NumCoeffTrailingOnes_len);
|
||||
input clk,reset_n;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [3:0] heading_one_pos;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
input [4:0] nC;
|
||||
output [1:0] TrailingOnes;
|
||||
output [4:0] TotalCoeff;
|
||||
output [4:0] NumCoeffTrailingOnes_len;
|
||||
reg [1:0] TrailingOnes;
|
||||
reg [4:0] TotalCoeff;
|
||||
reg [4:0] NumCoeffTrailingOnes_len;
|
||||
|
||||
reg [1:0] TrailingOnes_reg;
|
||||
reg [4:0] TotalCoeff_reg;
|
||||
|
||||
wire nC_0to2,nC_2to4,nC_4to8,nC_n1,nC_GE8;
|
||||
wire nC_0to2_t0,nC_0to2_t1,nC_0to2_t2,nC_0to2_t3;
|
||||
wire nC_2to4_t0,nC_2to4_t1,nC_2to4_t2,nC_2to4_t3;
|
||||
wire nC_4to8_t0,nC_4to8_t1;
|
||||
wire nC_n1_t0;
|
||||
//Select nC values to choose table
|
||||
assign nC_0to2 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd0 || nC == 5'd1));
|
||||
assign nC_2to4 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd2 || nC == 5'd3));
|
||||
assign nC_4to8 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd4 || nC == 5'd5 || nC == 5'd6 || nC == 5'd7));
|
||||
assign nC_n1 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd31));
|
||||
assign nC_GE8 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && !nC_0to2 && !nC_2to4 && !nC_4to8 && !nC_n1);
|
||||
|
||||
//1.nC_0to2 t0 ~ t4 sub-table selection
|
||||
assign nC_0to2_t0 = (nC_0to2 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1 || heading_one_pos == 4'd2));
|
||||
assign nC_0to2_t1 = (nC_0to2 && (heading_one_pos == 4'd3 || heading_one_pos == 4'd4));
|
||||
assign nC_0to2_t2 = (nC_0to2 && (heading_one_pos == 4'd5 || heading_one_pos == 4'd6 || heading_one_pos == 4'd7 || heading_one_pos == 4'd8));
|
||||
assign nC_0to2_t3 = (nC_0to2 && (heading_one_pos == 4'd9 || heading_one_pos == 4'd10));
|
||||
//2.nC_2to4 t0 ~ t4 sub-table selection
|
||||
assign nC_2to4_t0 = (nC_2to4 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1));
|
||||
assign nC_2to4_t1 = (nC_2to4 && (heading_one_pos == 4'd2 || heading_one_pos == 4'd3));
|
||||
assign nC_2to4_t2 = (nC_2to4 && (heading_one_pos == 4'd4 || heading_one_pos == 4'd5 || heading_one_pos == 4'd6));
|
||||
assign nC_2to4_t3 = (nC_2to4 && (heading_one_pos == 4'd7 || heading_one_pos == 4'd8));
|
||||
//3.nC_4to8 t0 ~ t2 sub-table selection
|
||||
assign nC_4to8_t0 = (nC_4to8 && heading_one_pos == 4'd0);
|
||||
assign nC_4to8_t1 = (nC_4to8 && (heading_one_pos == 4'd1 || heading_one_pos == 4'd2 || heading_one_pos == 4'd3 || heading_one_pos == 4'd4));
|
||||
//4.nC_GE8:single table, NO sub-table selection
|
||||
//5.nC_n1 t0 ~ t1 sub-table selection
|
||||
assign nC_n1_t0 = (nC_n1 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1 || heading_one_pos == 4'd2));
|
||||
|
||||
//NumCoeffTrailingOnes_len
|
||||
always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_GE8 or nC_n1 or heading_one_pos or BitStream_buffer_output)
|
||||
if (nC_0to2)
|
||||
case (heading_one_pos)
|
||||
0 :NumCoeffTrailingOnes_len <= 5'd1;
|
||||
1 :NumCoeffTrailingOnes_len <= 5'd2;
|
||||
2 :NumCoeffTrailingOnes_len <= 5'd3;
|
||||
3 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[11] == 1)? 5'd5:5'd6;
|
||||
4 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[10] == 1)? 5'd6:5'd7;
|
||||
5 :NumCoeffTrailingOnes_len <= 5'd8;
|
||||
6 :NumCoeffTrailingOnes_len <= 5'd9;
|
||||
7 :NumCoeffTrailingOnes_len <= 5'd10;
|
||||
8 :NumCoeffTrailingOnes_len <= 5'd11;
|
||||
9 :NumCoeffTrailingOnes_len <= 5'd13;
|
||||
10:NumCoeffTrailingOnes_len <= 5'd14;
|
||||
11:NumCoeffTrailingOnes_len <= 5'd15;
|
||||
12:NumCoeffTrailingOnes_len <= 5'd16;
|
||||
13:NumCoeffTrailingOnes_len <= 5'd16;
|
||||
14:NumCoeffTrailingOnes_len <= 5'd15;
|
||||
default:NumCoeffTrailingOnes_len <= 5'd0;
|
||||
endcase
|
||||
else if (nC_2to4)
|
||||
case (heading_one_pos)
|
||||
0 :NumCoeffTrailingOnes_len <= 5'd2;
|
||||
1 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[13] == 1)? 5'd3:5'd4;
|
||||
2 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[12] == 1)? 5'd5:5'd6;
|
||||
3 :NumCoeffTrailingOnes_len <= 5'd6;
|
||||
4 :NumCoeffTrailingOnes_len <= 5'd7;
|
||||
5 :NumCoeffTrailingOnes_len <= 5'd8;
|
||||
6 :NumCoeffTrailingOnes_len <= 5'd9;
|
||||
7 :NumCoeffTrailingOnes_len <= 5'd11;
|
||||
8 :NumCoeffTrailingOnes_len <= 5'd12;
|
||||
9 :NumCoeffTrailingOnes_len <= 5'd13;
|
||||
10:NumCoeffTrailingOnes_len <= (BitStream_buffer_output[4] == 1)? 5'd13:5'd14;
|
||||
11:NumCoeffTrailingOnes_len <= 5'd14;
|
||||
12:NumCoeffTrailingOnes_len <= 5'd13;
|
||||
default:NumCoeffTrailingOnes_len <= 5'd0;
|
||||
endcase
|
||||
else if (nC_n1)
|
||||
case (heading_one_pos)
|
||||
0:NumCoeffTrailingOnes_len <= 5'd1;
|
||||
1:NumCoeffTrailingOnes_len <= 5'd2;
|
||||
2:NumCoeffTrailingOnes_len <= 5'd3;
|
||||
3:NumCoeffTrailingOnes_len <= 5'd6;
|
||||
4:NumCoeffTrailingOnes_len <= 5'd6;
|
||||
5:NumCoeffTrailingOnes_len <= 5'd7;
|
||||
6:NumCoeffTrailingOnes_len <= 5'd8;
|
||||
default:NumCoeffTrailingOnes_len <= 5'd7;
|
||||
endcase
|
||||
else if (nC_4to8)
|
||||
case (heading_one_pos)
|
||||
0 :NumCoeffTrailingOnes_len <= 5'd4;
|
||||
1 :NumCoeffTrailingOnes_len <= 5'd5;
|
||||
2 :NumCoeffTrailingOnes_len <= 5'd6;
|
||||
3 :NumCoeffTrailingOnes_len <= 5'd7;
|
||||
4 :NumCoeffTrailingOnes_len <= 5'd8;
|
||||
5 :NumCoeffTrailingOnes_len <= 5'd9;
|
||||
6 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[8:7] == 2'b11)? 5'd9:5'd10;
|
||||
7 :NumCoeffTrailingOnes_len <= 5'd10;
|
||||
8 :NumCoeffTrailingOnes_len <= 5'd10;
|
||||
9 :NumCoeffTrailingOnes_len <= 5'd10;
|
||||
10:NumCoeffTrailingOnes_len <= 5'd10;
|
||||
default:NumCoeffTrailingOnes_len <= 5'd0;
|
||||
endcase
|
||||
else if (nC_GE8)
|
||||
NumCoeffTrailingOnes_len <= 5'd6;
|
||||
else
|
||||
NumCoeffTrailingOnes_len <= 0;
|
||||
|
||||
|
||||
//TrailingOnes
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
TrailingOnes_reg <= 0;
|
||||
else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT)
|
||||
TrailingOnes_reg <= TrailingOnes;
|
||||
|
||||
always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_n1 or nC_GE8
|
||||
or nC_0to2_t0 or nC_0to2_t1 or nC_0to2_t2 or nC_0to2_t3
|
||||
or nC_2to4_t0 or nC_2to4_t1 or nC_2to4_t2 or nC_2to4_t3
|
||||
or nC_4to8_t0 or nC_4to8_t1 or nC_n1_t0
|
||||
or TrailingOnes_reg or heading_one_pos or BitStream_buffer_output)
|
||||
if (nC_0to2)
|
||||
begin
|
||||
if (nC_0to2_t0)
|
||||
TrailingOnes <= heading_one_pos[1:0];
|
||||
else if (nC_0to2_t1)
|
||||
begin
|
||||
if (heading_one_pos == 4'd3 && !BitStream_buffer_output[11])
|
||||
TrailingOnes <= (BitStream_buffer_output[10])? 2'd0:2'd1;
|
||||
else if (heading_one_pos == 4'd4 && BitStream_buffer_output[10:9] == 2'b01)
|
||||
TrailingOnes <= 2'd2;
|
||||
else
|
||||
TrailingOnes <= 2'd3;
|
||||
end
|
||||
else if (nC_0to2_t2)
|
||||
begin
|
||||
if (heading_one_pos == 4'd5)
|
||||
case (BitStream_buffer_output[9:8])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd6)
|
||||
case (BitStream_buffer_output[8:7])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd7)
|
||||
case (BitStream_buffer_output[7:6])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[6:5])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
end
|
||||
else if (nC_0to2_t3)
|
||||
begin
|
||||
if (heading_one_pos == 4'd9)
|
||||
case (BitStream_buffer_output[4:3])
|
||||
2'b00:TrailingOnes <= (BitStream_buffer_output[5])? 2'd3:2'd0;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[3:2])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b11) ||
|
||||
(heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b11) ||
|
||||
(heading_one_pos == 4'd13 && (BitStream_buffer_output[1:0] == 2'b00 || BitStream_buffer_output[1:0] == 2'b11)))
|
||||
TrailingOnes <= 2'd0;
|
||||
else if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b10) ||
|
||||
(heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b10) ||
|
||||
(heading_one_pos == 4'd13 && BitStream_buffer_output[1:0] == 2'b10) ||
|
||||
heading_one_pos == 4'd14)
|
||||
TrailingOnes <= 2'd1;
|
||||
else if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b01) ||
|
||||
(heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b01) ||
|
||||
(heading_one_pos == 4'd13 && BitStream_buffer_output[1:0] == 2'b01))
|
||||
TrailingOnes <= 2'd2;
|
||||
else
|
||||
TrailingOnes <= 2'd3;
|
||||
end
|
||||
end
|
||||
else if (nC_2to4)
|
||||
begin
|
||||
if (nC_2to4_t0)
|
||||
begin
|
||||
if (heading_one_pos == 4'd0)
|
||||
TrailingOnes <= {1'b0,~BitStream_buffer_output[14]};
|
||||
else
|
||||
TrailingOnes <= (BitStream_buffer_output[13])? 2'd2:2'd3;
|
||||
end
|
||||
else if (nC_2to4_t1)
|
||||
begin
|
||||
if ((heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b011) ||
|
||||
(heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b11))
|
||||
TrailingOnes <= 2'd0;
|
||||
else if ((heading_one_pos == 4'd2 && (BitStream_buffer_output[12:11] == 2'b11 || BitStream_buffer_output[12:10] == 3'b010)) ||
|
||||
(heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b10))
|
||||
TrailingOnes <= 2'd1;
|
||||
else if ((heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b001) ||
|
||||
(heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b01))
|
||||
TrailingOnes <= 2'd2;
|
||||
else
|
||||
TrailingOnes <= 2'd3;
|
||||
end
|
||||
else if (nC_2to4_t2)
|
||||
begin
|
||||
if (heading_one_pos == 4'd4)
|
||||
case (BitStream_buffer_output[10:9])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd5)
|
||||
case (BitStream_buffer_output[9:8])
|
||||
2'b00:TrailingOnes <= 2'd0;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[8:7])
|
||||
2'b00:TrailingOnes <= 2'd3;
|
||||
2'b01:TrailingOnes <= 2'd2;
|
||||
2'b10:TrailingOnes <= 2'd1;
|
||||
2'b11:TrailingOnes <= 2'd0;
|
||||
endcase
|
||||
end
|
||||
else if (nC_2to4_t3)
|
||||
begin
|
||||
if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b11) ||
|
||||
(heading_one_pos == 4'd8 && (BitStream_buffer_output[5:4] == 2'b11 || BitStream_buffer_output[6:4] == 3'b000)))
|
||||
TrailingOnes <= 2'd0;
|
||||
else if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b10) ||
|
||||
(heading_one_pos == 4'd8 && BitStream_buffer_output[5:4] == 2'b10))
|
||||
TrailingOnes <= 2'd1;
|
||||
else if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b01) ||
|
||||
(heading_one_pos == 4'd8 && BitStream_buffer_output[5:4] == 2'b01))
|
||||
TrailingOnes <= 2'd2;
|
||||
else
|
||||
TrailingOnes <= 2'd3;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b11) ||
|
||||
(heading_one_pos == 4'd10 && (BitStream_buffer_output[4:3] == 2'b11 || BitStream_buffer_output[4:2] == 3'b001)) ||
|
||||
(heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b11))
|
||||
TrailingOnes <= 2'd0;
|
||||
else if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b10) ||
|
||||
(heading_one_pos == 4'd10 && (BitStream_buffer_output[4:2] == 3'b000 || BitStream_buffer_output[4:2] == 3'b011)) ||
|
||||
(heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b10))
|
||||
TrailingOnes <= 2'd1;
|
||||
else if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b01) ||
|
||||
(heading_one_pos == 4'd10 && (BitStream_buffer_output[4:3] == 2'b10 || BitStream_buffer_output[4:2] == 3'b010)) ||
|
||||
(heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b01))
|
||||
TrailingOnes <= 2'd2;
|
||||
else
|
||||
TrailingOnes <= 2'd3;
|
||||
end
|
||||
end
|
||||
else if (nC_n1)
|
||||
begin
|
||||
if (nC_n1_t0)
|
||||
begin
|
||||
if (BitStream_buffer_output[15]) TrailingOnes <= 2'd1;
|
||||
else if (BitStream_buffer_output[14]) TrailingOnes <= 2'd0;
|
||||
else TrailingOnes <= 2'd2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((heading_one_pos == 4'd3 && (BitStream_buffer_output[11:10] == 2'b00 || BitStream_buffer_output[11:10] == 2'b11)) ||
|
||||
heading_one_pos == 4'd4)
|
||||
TrailingOnes <= 2'd0;
|
||||
else if ((heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b10) ||
|
||||
(heading_one_pos == 4'd5 && BitStream_buffer_output[9]) ||
|
||||
(heading_one_pos == 4'd6 && BitStream_buffer_output[8]))
|
||||
TrailingOnes <= 2'd1;
|
||||
else if ((heading_one_pos == 4'd5 && !BitStream_buffer_output[9]) ||
|
||||
(heading_one_pos == 4'd6 && !BitStream_buffer_output[8]))
|
||||
TrailingOnes <= 2'd2;
|
||||
else
|
||||
TrailingOnes <= 2'd3;
|
||||
end
|
||||
end
|
||||
else if (nC_4to8)
|
||||
begin
|
||||
if (nC_4to8_t0)
|
||||
begin
|
||||
if (BitStream_buffer_output[14:12] == 3'b111) TrailingOnes <= 2'd0;
|
||||
else if (BitStream_buffer_output[14:12] == 3'b110) TrailingOnes <= 2'd1;
|
||||
else if (BitStream_buffer_output[14:12] == 3'b101) TrailingOnes <= 2'd2;
|
||||
else TrailingOnes <= 2'd3;
|
||||
end
|
||||
else if (nC_4to8_t1)
|
||||
begin
|
||||
if ((heading_one_pos == 4'd1 &&
|
||||
(BitStream_buffer_output[13:11] == 3'b000 || BitStream_buffer_output[13:11] == 3'b010 ||
|
||||
BitStream_buffer_output[13:11] == 3'b100 || BitStream_buffer_output[13:11] == 3'b111)) ||
|
||||
(heading_one_pos == 4'd2 && BitStream_buffer_output[11:10] == 2'b10 ) ||
|
||||
(heading_one_pos == 4'd3 && BitStream_buffer_output[11:9] == 3'b110) ||
|
||||
(heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b10 ))
|
||||
TrailingOnes <= 2'd1;
|
||||
else if (
|
||||
(heading_one_pos == 4'd1 && (BitStream_buffer_output[13:11] == 3'b001 || BitStream_buffer_output[13:11] == 3'b011 || BitStream_buffer_output[13:11] == 3'b110))||
|
||||
(heading_one_pos == 4'd2 && BitStream_buffer_output[11:10] == 2'b01) ||
|
||||
(heading_one_pos == 4'd3 && (BitStream_buffer_output[11:9] == 3'b010 || BitStream_buffer_output[11:9] == 3'b101))||
|
||||
(heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b01))
|
||||
TrailingOnes <= 2'd2;
|
||||
else if (
|
||||
(heading_one_pos == 4'd1 && BitStream_buffer_output[13:11] == 3'b101) ||
|
||||
(heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b100) ||
|
||||
(heading_one_pos == 4'd3 && BitStream_buffer_output[11:9] == 3'b100) ||
|
||||
(heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b00))
|
||||
TrailingOnes <= 2'd3;
|
||||
else
|
||||
TrailingOnes <= 2'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((heading_one_pos == 4'd5 && BitStream_buffer_output[8:7] == 2'b10) ||
|
||||
(heading_one_pos == 4'd6 && (BitStream_buffer_output[8:7] == 2'b11 || BitStream_buffer_output[7:6] == 2'b00)) ||
|
||||
(heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b00))
|
||||
TrailingOnes <= 2'd1;
|
||||
else if (
|
||||
(heading_one_pos == 4'd5 && BitStream_buffer_output[8:7] == 2'b01) ||
|
||||
(heading_one_pos == 4'd6 && BitStream_buffer_output[8:6] == 3'b011) ||
|
||||
(heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b11) ||
|
||||
(heading_one_pos == 4'd8 && BitStream_buffer_output[6]))
|
||||
TrailingOnes <= 2'd2;
|
||||
else if (
|
||||
(heading_one_pos == 4'd5 && BitStream_buffer_output[9:7] == 3'b100) ||
|
||||
(heading_one_pos == 4'd6 && BitStream_buffer_output[8:6] == 3'b010) ||
|
||||
(heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b10) ||
|
||||
(heading_one_pos == 4'd8 && !BitStream_buffer_output[6]))
|
||||
TrailingOnes <= 2'd3;
|
||||
else
|
||||
TrailingOnes <= 2'd0;
|
||||
end
|
||||
end
|
||||
else if (nC_GE8)
|
||||
begin
|
||||
if (BitStream_buffer_output[15:10] == 6'b0 || heading_one_pos == 4'd4)
|
||||
TrailingOnes <= 2'd0;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
TrailingOnes <= 2'd1;
|
||||
else
|
||||
TrailingOnes <= BitStream_buffer_output[11:10];
|
||||
end
|
||||
else
|
||||
TrailingOnes <= TrailingOnes_reg;
|
||||
|
||||
//TotalCoeff
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
TotalCoeff_reg <= 0;
|
||||
else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT)
|
||||
TotalCoeff_reg <= TotalCoeff;
|
||||
|
||||
always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_n1 or nC_GE8
|
||||
or nC_0to2_t0 or nC_0to2_t1 or nC_0to2_t2 or nC_0to2_t3
|
||||
or nC_2to4_t0 or nC_2to4_t1 or nC_2to4_t2 or nC_2to4_t3
|
||||
or nC_4to8_t0 or nC_4to8_t1 or nC_n1_t0
|
||||
or TotalCoeff_reg or heading_one_pos or BitStream_buffer_output)
|
||||
if (nC_0to2)
|
||||
begin
|
||||
if (nC_0to2_t0)
|
||||
TotalCoeff <= {3'b0,heading_one_pos[1:0]};
|
||||
else if (nC_0to2_t1)
|
||||
begin
|
||||
if (heading_one_pos == 4'd3)
|
||||
case (BitStream_buffer_output[11:10])
|
||||
2'b00 :TotalCoeff <= 5'd2;
|
||||
2'b01 :TotalCoeff <= 5'd1;
|
||||
default:TotalCoeff <= 5'd3;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[10:9])
|
||||
2'b00 :TotalCoeff <= 5'd5;
|
||||
2'b01 :TotalCoeff <= 5'd3;
|
||||
default:TotalCoeff <= 5'd4;
|
||||
endcase
|
||||
end
|
||||
else if (nC_0to2_t2)
|
||||
begin
|
||||
if (heading_one_pos == 4'd5)
|
||||
case (BitStream_buffer_output[9:8])
|
||||
2'b00:TotalCoeff <= 5'd6;
|
||||
2'b01:TotalCoeff <= 5'd4;
|
||||
2'b10:TotalCoeff <= 5'd3;
|
||||
2'b11:TotalCoeff <= 5'd2;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd6)
|
||||
case (BitStream_buffer_output[8:7])
|
||||
2'b00:TotalCoeff <= 5'd7;
|
||||
2'b01:TotalCoeff <= 5'd5;
|
||||
2'b10:TotalCoeff <= 5'd4;
|
||||
2'b11:TotalCoeff <= 5'd3;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd7)
|
||||
case (BitStream_buffer_output[7:6])
|
||||
2'b00:TotalCoeff <= 5'd8;
|
||||
2'b01:TotalCoeff <= 5'd6;
|
||||
2'b10:TotalCoeff <= 5'd5;
|
||||
2'b11:TotalCoeff <= 5'd4;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[6:5])
|
||||
2'b00:TotalCoeff <= 5'd9;
|
||||
2'b01:TotalCoeff <= 5'd7;
|
||||
2'b10:TotalCoeff <= 5'd6;
|
||||
2'b11:TotalCoeff <= 5'd5;
|
||||
endcase
|
||||
end
|
||||
else if (nC_0to2_t3)
|
||||
begin
|
||||
if (heading_one_pos == 4'd9)
|
||||
case (BitStream_buffer_output[5:3])
|
||||
3'b001 :TotalCoeff <= 5'd9;
|
||||
3'b011,3'b110:TotalCoeff <= 5'd7;
|
||||
3'b100 :TotalCoeff <= 5'd10;
|
||||
3'b111 :TotalCoeff <= 5'd6;
|
||||
default :TotalCoeff <= 5'd8;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[4:2])
|
||||
3'b000 :TotalCoeff <= 5'd12;
|
||||
3'b001,3'b100:TotalCoeff <= 5'd11;
|
||||
3'b110,3'b111:TotalCoeff <= 5'd9;
|
||||
default :TotalCoeff <= 5'd10;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (heading_one_pos == 4'd11)
|
||||
case (BitStream_buffer_output[3:1])
|
||||
3'b000 :TotalCoeff <= 5'd14;
|
||||
3'b001,3'b100:TotalCoeff <= 5'd13;
|
||||
3'b110,3'b111:TotalCoeff <= 5'd11;
|
||||
default :TotalCoeff <= 5'd12;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd12)
|
||||
case (BitStream_buffer_output[2:0])
|
||||
3'b000 :TotalCoeff <= 5'd16;
|
||||
3'b011,3'b101,3'b110:TotalCoeff <= 5'd14;
|
||||
3'b111 :TotalCoeff <= 5'd13;
|
||||
default :TotalCoeff <= 5'd15;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd13)
|
||||
TotalCoeff <= (BitStream_buffer_output[1:0] == 2'b11)? 5'd15:5'd16;
|
||||
else
|
||||
TotalCoeff <= 5'd13;
|
||||
end
|
||||
end
|
||||
else if (nC_2to4)
|
||||
begin
|
||||
if (nC_2to4_t0)
|
||||
begin
|
||||
if (heading_one_pos == 4'd0)
|
||||
TotalCoeff <= {4'b0,~BitStream_buffer_output[14]};
|
||||
else
|
||||
case (BitStream_buffer_output[13:12])
|
||||
2'b00 :TotalCoeff <= 5'd4;
|
||||
2'b01 :TotalCoeff <= 5'd3;
|
||||
default:TotalCoeff <= 5'd2;
|
||||
endcase
|
||||
end
|
||||
else if (nC_2to4_t1)
|
||||
begin
|
||||
if (heading_one_pos == 4'd2)
|
||||
case (BitStream_buffer_output[12:11])
|
||||
2'b00:TotalCoeff <= (BitStream_buffer_output[10])? 5'd3:5'd6;
|
||||
2'b01:TotalCoeff <= (BitStream_buffer_output[10])? 5'd1:5'd3;
|
||||
2'b10:TotalCoeff <= 5'd5;
|
||||
2'b11:TotalCoeff <= 5'd2;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[11:10])
|
||||
2'b00 :TotalCoeff <= 5'd7;
|
||||
2'b11 :TotalCoeff <= 5'd2;
|
||||
default:TotalCoeff <= 5'd4;
|
||||
endcase
|
||||
end
|
||||
else if (nC_2to4_t2)
|
||||
begin
|
||||
if (heading_one_pos == 4'd4)
|
||||
case (BitStream_buffer_output[10:9])
|
||||
2'b00 :TotalCoeff <= 5'd8;
|
||||
2'b11 :TotalCoeff <= 5'd3;
|
||||
default:TotalCoeff <= 5'd5;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd5)
|
||||
case (BitStream_buffer_output[9:8])
|
||||
2'b00 :TotalCoeff <= 5'd5;
|
||||
2'b11 :TotalCoeff <= 5'd4;
|
||||
default:TotalCoeff <= 5'd6;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[8:7])
|
||||
2'b00 :TotalCoeff <= 5'd9;
|
||||
2'b11 :TotalCoeff <= 5'd6;
|
||||
default:TotalCoeff <= 5'd7;
|
||||
endcase
|
||||
end
|
||||
else if (nC_2to4_t3)
|
||||
begin
|
||||
if (heading_one_pos == 4'd7)
|
||||
case (BitStream_buffer_output[7:5])
|
||||
3'b000 :TotalCoeff <= 5'd11;
|
||||
3'b001,3'b010:TotalCoeff <= 5'd9;
|
||||
3'b100 :TotalCoeff <= 5'd10;
|
||||
3'b111 :TotalCoeff <= 5'd7;
|
||||
default :TotalCoeff <= 5'd8;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[6:4])
|
||||
3'b000,3'b001,3'b010:TotalCoeff <= 5'd11;
|
||||
3'b100 :TotalCoeff <= 5'd12;
|
||||
3'b111 :TotalCoeff <= 5'd9;
|
||||
default :TotalCoeff <= 5'd10;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (heading_one_pos == 4'd9)
|
||||
case (BitStream_buffer_output[5:3])
|
||||
3'b000 :TotalCoeff <= 5'd14;
|
||||
3'b101,3'b110,3'b111:TotalCoeff <= 5'd12;
|
||||
default :TotalCoeff <= 5'd13;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd10)
|
||||
TotalCoeff <= (BitStream_buffer_output[4:2] == 3'b0 || BitStream_buffer_output[4:2] == 3'b001 || BitStream_buffer_output[4:2] == 3'b010)? 5'd15:5'd14;
|
||||
else if (heading_one_pos == 4'd11)
|
||||
TotalCoeff <= 5'd16;
|
||||
else
|
||||
TotalCoeff <= 5'd15;
|
||||
end
|
||||
end
|
||||
else if (nC_n1)
|
||||
begin
|
||||
if (nC_n1_t0)
|
||||
begin
|
||||
if (BitStream_buffer_output[15]) TotalCoeff <= 5'd1;
|
||||
else if (BitStream_buffer_output[14]) TotalCoeff <= 5'd0;
|
||||
else TotalCoeff <= 5'd2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (heading_one_pos == 4'd3)
|
||||
case (BitStream_buffer_output[11:10])
|
||||
2'b01 :TotalCoeff <= 5'd3;
|
||||
2'b11 :TotalCoeff <= 5'd1;
|
||||
default:TotalCoeff <= 5'd2;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd4)
|
||||
TotalCoeff <= (BitStream_buffer_output[10])? 5'd3:5'd4;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
TotalCoeff <= 5'd3;
|
||||
else
|
||||
TotalCoeff <= 5'd4;
|
||||
end
|
||||
end
|
||||
else if (nC_4to8)
|
||||
begin
|
||||
if (nC_4to8_t0)
|
||||
TotalCoeff <= {2'b0,~BitStream_buffer_output[14:12]};
|
||||
else if (nC_4to8_t1)
|
||||
begin
|
||||
if (heading_one_pos == 4'd1)
|
||||
case (BitStream_buffer_output[13:11])
|
||||
3'b000,3'b001:TotalCoeff <= 5'd5;
|
||||
3'b010,3'b011:TotalCoeff <= 5'd4;
|
||||
3'b101 :TotalCoeff <= 5'd8;
|
||||
3'b111 :TotalCoeff <= 5'd2;
|
||||
default :TotalCoeff <= 5'd3;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd2)
|
||||
case (BitStream_buffer_output[12:10])
|
||||
3'b000 :TotalCoeff <= 5'd3;
|
||||
3'b001,3'b010:TotalCoeff <= 5'd7;
|
||||
3'b011 :TotalCoeff <= 5'd2;
|
||||
3'b100 :TotalCoeff <= 5'd9;
|
||||
3'b111 :TotalCoeff <= 5'd1;
|
||||
default :TotalCoeff <= 5'd6;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd3)
|
||||
case (BitStream_buffer_output[11:9])
|
||||
3'b000 :TotalCoeff <= 5'd7;
|
||||
3'b001 :TotalCoeff <= 5'd6;
|
||||
3'b010 :TotalCoeff <= 5'd9;
|
||||
3'b011 :TotalCoeff <= 5'd5;
|
||||
3'b100 :TotalCoeff <= 5'd10;
|
||||
3'b111 :TotalCoeff <= 5'd4;
|
||||
default:TotalCoeff <= 5'd8;
|
||||
endcase
|
||||
else
|
||||
case (BitStream_buffer_output[10:8])
|
||||
3'b000 :TotalCoeff <= 5'd12;
|
||||
3'b001,3'b100:TotalCoeff <= 5'd11;
|
||||
3'b010,3'b101:TotalCoeff <= 5'd10;
|
||||
3'b111 :TotalCoeff <= 5'd8;
|
||||
default :TotalCoeff <= 5'd9;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (heading_one_pos == 4'd5)
|
||||
case (BitStream_buffer_output[9:7])
|
||||
3'b001,3'b100 :TotalCoeff <= 5'd13;
|
||||
3'b011,3'b110 :TotalCoeff <= 5'd11;
|
||||
3'b111 :TotalCoeff <= 5'd10;
|
||||
default :TotalCoeff <= 5'd12;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd6)
|
||||
case (BitStream_buffer_output[8:6])
|
||||
3'b000 :TotalCoeff <= 5'd15;
|
||||
3'b101,3'b110,3'b111:TotalCoeff <= 5'd13;
|
||||
default :TotalCoeff <= 5'd14;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd7)
|
||||
TotalCoeff <= (BitStream_buffer_output[7:6] == 2'b00)? 5'd16:5'd15;
|
||||
else
|
||||
TotalCoeff <= 5'd16;
|
||||
end
|
||||
end
|
||||
else if (nC_GE8)
|
||||
begin
|
||||
if (heading_one_pos == 4'd4)
|
||||
TotalCoeff <= 5'd0;
|
||||
else
|
||||
TotalCoeff <= BitStream_buffer_output[15:12] + 1;
|
||||
end
|
||||
else
|
||||
TotalCoeff <= TotalCoeff_reg;
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : QP_decoding.v
|
||||
// Generated : June 7, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// QPy:the luma quantisation parameter
|
||||
// QPi:the intermediate quantisation parameter derived from QPy
|
||||
// QPc:the chroma quantisation parameter derived from QPi on Table 8-13,Page136
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1. March 21,2006
|
||||
// Input signals slice_qp_delta and mb_qp_delta are removed, using
|
||||
// exp_golomb_decoding_output_5to0 instead since these two signals are latched at clock
|
||||
// rising edge which is too late for computation. So use exp_golomb_decoding_output_5to0 directly
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module QP_decoding (clk,reset_n,slice_header_state,slice_data_state,pic_init_qp_minus26,
|
||||
exp_golomb_decoding_output_5to0,chroma_qp_index_offset,QPy,QPc);
|
||||
input clk,reset_n;
|
||||
input [3:0] slice_header_state;
|
||||
input [3:0] slice_data_state;
|
||||
input [5:0] pic_init_qp_minus26;
|
||||
input [5:0] exp_golomb_decoding_output_5to0;
|
||||
input [4:0] chroma_qp_index_offset;
|
||||
output [5:0] QPy,QPc;
|
||||
reg [5:0] QPy,QPc;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
QPy <= 0;
|
||||
else if (slice_header_state == `slice_qp_delta_s)
|
||||
QPy <= 26 + pic_init_qp_minus26 + exp_golomb_decoding_output_5to0;
|
||||
else if (slice_data_state == `mb_qp_delta_s)
|
||||
QPy <= QPy + exp_golomb_decoding_output_5to0;
|
||||
|
||||
wire [5:0] QPi;
|
||||
assign QPi = QPy + {1'b0,chroma_qp_index_offset};
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
QPc <= 0;
|
||||
else
|
||||
begin
|
||||
if (QPi < 30)
|
||||
QPc <= QPi;
|
||||
else
|
||||
case (QPi)
|
||||
30 :QPc <= 29;
|
||||
31 :QPc <= 30;
|
||||
32 :QPc <= 31;
|
||||
33,34 :QPc <= 32;
|
||||
35 :QPc <= 33;
|
||||
36,37 :QPc <= 34;
|
||||
38,39 :QPc <= 35;
|
||||
40,41 :QPc <= 36;
|
||||
42,43,44:QPc <= 37;
|
||||
45,46,47:QPc <= 38;
|
||||
default :QPc <= 39;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,333 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : bitstream_gclk_gen.v
|
||||
// Generated : Jan 9,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Gated clock generation module for bitstream controller
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module bitstream_gclk_gen (clk,reset_n,freq_ctrl0,freq_ctrl1,parser_state,nal_unit_state,slice_layer_wo_partitioning_state,
|
||||
slice_header_state,slice_data_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state,
|
||||
mb_num,TotalCoeff,start_code_prefix_found,pc_2to0,deblocking_filter_control_present_flag,
|
||||
disable_deblocking_filter_idc,end_of_one_residual_block,
|
||||
Intra4x4PredMode_mbAddrB_cs_n,mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n,
|
||||
LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n,
|
||||
trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,disable_DF,bs_dec_counter,
|
||||
|
||||
gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps,
|
||||
gclk_slice_header,gclk_slice_data,gclk_residual,gclk_cavlc,
|
||||
gclk_Intra4x4PredMode_mbAddrB_RF,
|
||||
gclk_mvx_mbAddrB_RF,gclk_mvy_mbAddrB_RF,gclk_mvx_mbAddrC_RF,gclk_mvy_mbAddrC_RF,
|
||||
gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF,gclk_bs_dec,
|
||||
end_of_one_frame);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input freq_ctrl0;
|
||||
input freq_ctrl1;
|
||||
input [1:0] parser_state;
|
||||
input [2:0] nal_unit_state;
|
||||
input [1:0] slice_layer_wo_partitioning_state;
|
||||
input [3:0] slice_header_state;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] seq_parameter_set_state;
|
||||
input [3:0] pic_parameter_set_state;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [6:0] mb_num;
|
||||
input [4:0] TotalCoeff;
|
||||
input start_code_prefix_found;
|
||||
input [2:0] pc_2to0;
|
||||
input deblocking_filter_control_present_flag;
|
||||
input [1:0] disable_deblocking_filter_idc;
|
||||
input end_of_one_residual_block;
|
||||
input Intra4x4PredMode_mbAddrB_cs_n;
|
||||
input mvx_mbAddrB_cs_n;
|
||||
input mvy_mbAddrB_cs_n;
|
||||
input mvx_mbAddrC_cs_n;
|
||||
input mvy_mbAddrC_cs_n;
|
||||
input LumaLevel_mbAddrB_cs_n;
|
||||
input ChromaLevel_Cb_mbAddrB_cs_n;
|
||||
input ChromaLevel_Cr_mbAddrB_cs_n;
|
||||
input trigger_CAVLC;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input end_of_DCBlk_IQIT;
|
||||
input end_of_one_blk4x4_sum;
|
||||
input end_of_MB_DEC;
|
||||
input disable_DF;
|
||||
input [1:0] bs_dec_counter;
|
||||
|
||||
output gclk_parser;
|
||||
output gclk_nal;
|
||||
output gclk_slice;
|
||||
output gclk_sps;
|
||||
output gclk_pps;
|
||||
output gclk_slice_header;
|
||||
output gclk_slice_data;
|
||||
output gclk_residual;
|
||||
output gclk_cavlc;
|
||||
output gclk_Intra4x4PredMode_mbAddrB_RF;
|
||||
output gclk_mvx_mbAddrB_RF;
|
||||
output gclk_mvy_mbAddrB_RF;
|
||||
output gclk_mvx_mbAddrC_RF;
|
||||
output gclk_mvy_mbAddrC_RF;
|
||||
output gclk_LumaLevel_mbAddrB_RF;
|
||||
output gclk_ChromaLevel_Cb_mbAddrB_RF;
|
||||
output gclk_ChromaLevel_Cr_mbAddrB_RF;
|
||||
output gclk_bs_dec;
|
||||
output end_of_one_frame;
|
||||
|
||||
//Input pin freq_ctrl0 & freq_ctrl1 can be used to adjust frequency after the chip is fabricated
|
||||
reg [16:0] cycles_per_frame;
|
||||
always @ (freq_ctrl0 or freq_ctrl1)
|
||||
case ({freq_ctrl1,freq_ctrl0})
|
||||
2'b00:cycles_per_frame <= `cycles_per_frame0;
|
||||
2'b01:cycles_per_frame <= `cycles_per_frame1;
|
||||
2'b11:cycles_per_frame <= `cycles_per_frame3;
|
||||
default:cycles_per_frame <= `cycles_per_frame2;
|
||||
endcase
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
// decoding rate control
|
||||
//---------------------------------------------------------------------------------
|
||||
reg [16:0] frame_cycle_counter;
|
||||
reg end_of_one_frame;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
frame_cycle_counter <= 0;
|
||||
end_of_one_frame <= 1'b0;
|
||||
end
|
||||
else if (parser_state == `start_code_prefix)
|
||||
begin
|
||||
frame_cycle_counter <= 0;
|
||||
end_of_one_frame <= 1'b0;
|
||||
end
|
||||
else if (frame_cycle_counter < cycles_per_frame)
|
||||
begin
|
||||
frame_cycle_counter <= frame_cycle_counter + 1;
|
||||
end_of_one_frame <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
frame_cycle_counter <= 0;
|
||||
end_of_one_frame <= 1'b1;
|
||||
end
|
||||
//PPS and SPS doesn't need rate control,so after PPS/SPS decoding,bitstream parser should continue
|
||||
//without waiting for "end_of_one_frame" signal when parser_state == rst_parser.
|
||||
//PPS_SPS_complete is used to identify whether next nal_unit to be decoded is PPS/SPS or normal frame
|
||||
reg PPS_SPS_complete;
|
||||
always @ (posedge gclk_slice or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
PPS_SPS_complete <= 1'b0;
|
||||
else if (slice_layer_wo_partitioning_state == `slice_header)
|
||||
PPS_SPS_complete <= 1'b1;
|
||||
|
||||
//1.gclk_parser
|
||||
wire parser_ena;
|
||||
reg l_parser_ena;
|
||||
wire gclk_parser;
|
||||
assign parser_ena = (
|
||||
(parser_state == `rst_parser && (!PPS_SPS_complete || (PPS_SPS_complete && end_of_one_frame))) ||
|
||||
(parser_state == `start_code_prefix && start_code_prefix_found == 1'b1) ||
|
||||
(nal_unit_state == `rbsp_trailing_one_bit && pc_2to0 == 3'b000) ||
|
||||
nal_unit_state == `rbsp_trailing_zero_bits)? 1'b1:1'b0;
|
||||
always @ (clk or parser_ena)
|
||||
if (!clk) l_parser_ena <= parser_ena;
|
||||
assign gclk_parser = l_parser_ena & clk;
|
||||
|
||||
//2.gclk_nal
|
||||
//including rate control for end of one frame
|
||||
wire nal_ena;
|
||||
reg l_nal_ena;
|
||||
wire gclk_nal;
|
||||
assign nal_ena = (parser_state == `nal_unit && (
|
||||
nal_unit_state == `rst_nal_unit ||
|
||||
nal_unit_state == `forbidden_zero_bit_2_nal_unit_type ||
|
||||
(((slice_data_state == `skip_run_duration && end_of_MB_DEC)|| slice_data_state == `mb_num_update)
|
||||
&& mb_num == 98) ||
|
||||
seq_parameter_set_state == `vui_parameter_present_flag_s ||
|
||||
pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag ||
|
||||
nal_unit_state == `rbsp_trailing_one_bit ||
|
||||
nal_unit_state == `rbsp_trailing_zero_bits))? 1'b1:1'b0;
|
||||
always @ (clk or nal_ena)
|
||||
if (!clk) l_nal_ena <= nal_ena;
|
||||
assign gclk_nal = l_nal_ena & clk;
|
||||
|
||||
//3.gclk_slice:for slice_layer_wo_partitioning_state FSM
|
||||
wire slice_ena;
|
||||
reg l_slice_ena;
|
||||
wire gclk_slice;
|
||||
assign slice_ena = (
|
||||
(nal_unit_state == `slice_layer_non_IDR_rbsp || nal_unit_state == `slice_layer_IDR_rbsp) &&
|
||||
(slice_layer_wo_partitioning_state == `rst_slice_layer_wo_partitioning ||
|
||||
(slice_header_state == `slice_qp_delta_s && deblocking_filter_control_present_flag == 1'b0) ||
|
||||
(slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 2'b01) ||
|
||||
slice_header_state == `slice_beta_offset_div2_s ||
|
||||
(((slice_data_state == `skip_run_duration && end_of_MB_DEC) || slice_data_state == `mb_num_update)
|
||||
&& mb_num == 98)))? 1'b1:1'b0;
|
||||
always @ (clk or slice_ena)
|
||||
if (!clk) l_slice_ena <= slice_ena;
|
||||
assign gclk_slice = l_slice_ena & clk;
|
||||
|
||||
//4.gclk_sps
|
||||
wire sps_ena;
|
||||
reg l_sps_ena;
|
||||
wire gclk_sps;
|
||||
assign sps_ena = (nal_unit_state == `seq_parameter_set_rbsp)? 1'b1:1'b0;
|
||||
always @ (clk or sps_ena)
|
||||
if (!clk) l_sps_ena <= sps_ena;
|
||||
assign gclk_sps = l_sps_ena & clk;
|
||||
|
||||
//5.gclk_pps
|
||||
wire pps_ena;
|
||||
reg l_pps_ena;
|
||||
wire gclk_pps;
|
||||
|
||||
assign pps_ena = (nal_unit_state == `pic_parameter_set_rbsp)? 1'b1:1'b0;
|
||||
always @ (clk or pps_ena)
|
||||
if (!clk) l_pps_ena <= pps_ena;
|
||||
assign gclk_pps = l_pps_ena & clk;
|
||||
|
||||
//6.gclk_slice_header
|
||||
wire slice_header_ena;
|
||||
reg l_slice_header_ena;
|
||||
wire gclk_slice_header;
|
||||
assign slice_header_ena = (slice_layer_wo_partitioning_state == `slice_header)? 1'b1:1'b0;
|
||||
always @ (clk or slice_header_ena)
|
||||
if (!clk) l_slice_header_ena <= slice_header_ena;
|
||||
assign gclk_slice_header = l_slice_header_ena & clk;
|
||||
|
||||
//7.gclk_slice_data
|
||||
//including rate control for skipped macroblock:skip_run_duration
|
||||
//including rate control for normal macroblock:mb_num_update
|
||||
wire slice_data_ena;
|
||||
reg l_slice_data_ena;
|
||||
wire gclk_slice_data;
|
||||
assign slice_data_ena = (slice_layer_wo_partitioning_state == `slice_data && (
|
||||
(slice_data_state != `skip_run_duration && slice_data_state != `residual) ||
|
||||
(slice_data_state == `skip_run_duration && end_of_MB_DEC == 1'b1) ||
|
||||
(slice_data_state == `residual && end_of_MB_DEC == 1'b1)))? 1'b1:1'b0;
|
||||
always @ (clk or slice_data_ena)
|
||||
if (!clk) l_slice_data_ena <= slice_data_ena;
|
||||
assign gclk_slice_data = l_slice_data_ena & clk;
|
||||
|
||||
//8.gclk_residual
|
||||
wire residual_ena;
|
||||
reg l_residual_ena;
|
||||
wire gclk_residual;
|
||||
|
||||
assign residual_ena = (slice_data_state == `residual &&
|
||||
(residual_state == `rst_residual ||
|
||||
|
||||
((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s
|
||||
|| residual_state == `ChromaDCLevel_Cr_s) &&
|
||||
((end_of_one_residual_block == 1 && TotalCoeff == 0) || end_of_DCBlk_IQIT)) ||
|
||||
|
||||
((residual_state == `Intra16x16ACLevel_s || residual_state == `Intra16x16ACLevel_0_s
|
||||
|| residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s)
|
||||
&& blk4x4_rec_counter == 15 && end_of_one_blk4x4_sum == 1) ||
|
||||
(residual_state == `ChromaACLevel_Cb_s && blk4x4_rec_counter == 19 && end_of_one_blk4x4_sum == 1) ||
|
||||
(residual_state == `ChromaACLevel_Cr_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1) ||
|
||||
(residual_state == `ChromaACLevel_0_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1)))? 1'b1:1'b0;
|
||||
|
||||
always @ (clk or residual_ena)
|
||||
if (!clk) l_residual_ena <= residual_ena;
|
||||
assign gclk_residual = l_residual_ena & clk;
|
||||
|
||||
//9.gclk_cavlc
|
||||
wire cavlc_ena;
|
||||
reg l_cavlc_ena;
|
||||
wire gclk_cavlc;
|
||||
assign cavlc_ena = (slice_data_state == `residual && (cavlc_decoder_state != `rst_cavlc_decoder ||
|
||||
(cavlc_decoder_state == `rst_cavlc_decoder && trigger_CAVLC)))? 1'b1:1'b0;
|
||||
|
||||
always @ (clk or cavlc_ena)
|
||||
if (!clk) l_cavlc_ena <= cavlc_ena;
|
||||
assign gclk_cavlc = l_cavlc_ena & clk;
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
//gclk for bitstream controller register file
|
||||
//----------------------------------------------------------------------
|
||||
//1.gclk_Intra4x4PredMode_mbAddrB_RF
|
||||
reg l_Intra4x4PredMode_mbAddrB_RF_ena;
|
||||
wire gclk_Intra4x4PredMode_mbAddrB_RF;
|
||||
always @ (clk or Intra4x4PredMode_mbAddrB_cs_n)
|
||||
if (!clk) l_Intra4x4PredMode_mbAddrB_RF_ena <= ~Intra4x4PredMode_mbAddrB_cs_n;
|
||||
assign gclk_Intra4x4PredMode_mbAddrB_RF = clk & l_Intra4x4PredMode_mbAddrB_RF_ena;
|
||||
|
||||
//2.gclk_mvx_mbAddrB_RF
|
||||
reg l_mvx_mbAddrB_RF_ena;
|
||||
wire gclk_mvx_mbAddrB_RF;
|
||||
always @ (clk or mvx_mbAddrB_cs_n)
|
||||
if (!clk) l_mvx_mbAddrB_RF_ena <= ~mvx_mbAddrB_cs_n;
|
||||
assign gclk_mvx_mbAddrB_RF = clk & l_mvx_mbAddrB_RF_ena;
|
||||
|
||||
//3.gclk_mvy_mbAddrB_RF
|
||||
reg l_mvy_mbAddrB_RF_ena;
|
||||
wire gclk_mvy_mbAddrB_RF;
|
||||
always @ (clk or mvy_mbAddrB_cs_n)
|
||||
if (!clk) l_mvy_mbAddrB_RF_ena <= ~mvy_mbAddrB_cs_n;
|
||||
assign gclk_mvy_mbAddrB_RF = clk & l_mvy_mbAddrB_RF_ena;
|
||||
|
||||
//4.gclk_mvx_mbAddrC_RF
|
||||
reg l_mvx_mbAddrC_RF_ena;
|
||||
wire gclk_mvx_mbAddrC_RF;
|
||||
always @ (clk or mvx_mbAddrC_cs_n)
|
||||
if (!clk) l_mvx_mbAddrC_RF_ena <= ~mvx_mbAddrC_cs_n;
|
||||
assign gclk_mvx_mbAddrC_RF = clk & l_mvx_mbAddrC_RF_ena;
|
||||
|
||||
//5.gclk_mvy_mbAddrC_RF
|
||||
reg l_mvy_mbAddrC_RF_ena;
|
||||
wire gclk_mvy_mbAddrC_RF;
|
||||
always @ (clk or mvy_mbAddrC_cs_n)
|
||||
if (!clk) l_mvy_mbAddrC_RF_ena <= ~mvy_mbAddrC_cs_n;
|
||||
assign gclk_mvy_mbAddrC_RF = clk & l_mvy_mbAddrC_RF_ena;
|
||||
//----------------------------------------------------------------------
|
||||
//gclk for CAVLC_decoder related regfiles
|
||||
//----------------------------------------------------------------------
|
||||
//1.gclk_LumaLevel_mbAddrB_RF
|
||||
reg l_LumaLevel_mbAddrB_RF_ena;
|
||||
wire gclk_LumaLevel_mbAddrB_RF;
|
||||
always @ (clk or LumaLevel_mbAddrB_cs_n)
|
||||
if (!clk) l_LumaLevel_mbAddrB_RF_ena <= ~LumaLevel_mbAddrB_cs_n;
|
||||
assign gclk_LumaLevel_mbAddrB_RF = clk & l_LumaLevel_mbAddrB_RF_ena;
|
||||
|
||||
//2.gclk_ChromaLevel_Cb_mbAddrB_RF
|
||||
reg l_ChromaLevel_Cb_mbAddrB_RF_ena;
|
||||
wire gclk_ChromaLevel_Cb_mbAddrB_RF;
|
||||
always @ (clk or ChromaLevel_Cb_mbAddrB_cs_n)
|
||||
if (!clk) l_ChromaLevel_Cb_mbAddrB_RF_ena <= ~ChromaLevel_Cb_mbAddrB_cs_n;
|
||||
assign gclk_ChromaLevel_Cb_mbAddrB_RF = clk & l_ChromaLevel_Cb_mbAddrB_RF_ena;
|
||||
|
||||
//3.gclk_ChromaLevel_Cr_mbAddrB_RF
|
||||
reg l_ChromaLevel_Cr_mbAddrB_RF_ena;
|
||||
wire gclk_ChromaLevel_Cr_mbAddrB_RF;
|
||||
always @ (clk or ChromaLevel_Cr_mbAddrB_cs_n)
|
||||
if (!clk) l_ChromaLevel_Cr_mbAddrB_RF_ena <= ~ChromaLevel_Cr_mbAddrB_cs_n;
|
||||
assign gclk_ChromaLevel_Cr_mbAddrB_RF = clk & l_ChromaLevel_Cr_mbAddrB_RF_ena;
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
//gclk for boundary strength decoding
|
||||
//----------------------------------------------------------------------
|
||||
wire bs_dec_ena;
|
||||
reg l_bs_dec_ena;
|
||||
wire gclk_bs_dec;
|
||||
|
||||
assign bs_dec_ena = ((end_of_MB_DEC == 1'b1 && disable_DF == 1'b0) || bs_dec_counter != 0)? 1'b1:1'b0;
|
||||
always @ (clk or bs_dec_ena)
|
||||
if (!clk) l_bs_dec_ena <= bs_dec_ena;
|
||||
assign gclk_bs_dec = l_bs_dec_ena & clk;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,906 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : bs_decoding.v
|
||||
// Generated : Nov 17,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Deblocking Filter Boundary Strength decoding
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module bs_decoding (clk,reset_n,gclk_bs_dec,gclk_end_of_MB_DEC,end_of_MB_DEC,end_of_one_blk4x4_sum,mb_num_h,mb_num_v,
|
||||
disable_DF,blk4x4_rec_counter,CodedBlockPatternLuma,mb_type_general,slice_data_state,residual_state,
|
||||
MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,end_of_one_residual_block,TotalCoeff,
|
||||
curr_DC_IsZero,Is_skipMB_mv_calc,
|
||||
mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout,
|
||||
mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
|
||||
|
||||
bs_dec_counter,end_of_BS_DEC,mv_mbAddrB_rd_for_DF,
|
||||
bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3
|
||||
);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input gclk_bs_dec;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input end_of_MB_DEC;
|
||||
input end_of_one_blk4x4_sum;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input disable_DF;
|
||||
input [3:0] CodedBlockPatternLuma;
|
||||
input [3:0] mb_type_general;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] residual_state;
|
||||
input [1:0] MBTypeGen_mbAddrA;
|
||||
input [21:0] MBTypeGen_mbAddrB_reg;
|
||||
input end_of_one_residual_block;
|
||||
input [4:0] TotalCoeff;
|
||||
input curr_DC_IsZero;
|
||||
input Is_skipMB_mv_calc;
|
||||
input [31:0] mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout;
|
||||
input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
|
||||
output [1:0] bs_dec_counter;
|
||||
output end_of_BS_DEC;
|
||||
output mv_mbAddrB_rd_for_DF;
|
||||
output [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
|
||||
reg [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
|
||||
//-------------------------------------------
|
||||
//mb_type_general needs to be latched for DF
|
||||
//-------------------------------------------
|
||||
reg [3:0] mb_type_general_DF;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
mb_type_general_DF <= 4'b0;
|
||||
else if (!disable_DF && end_of_one_blk4x4_sum && blk4x4_rec_counter == 5'd22)
|
||||
mb_type_general_DF <= mb_type_general;
|
||||
|
||||
reg [1:0] MB_inter_size;
|
||||
always @ (mb_type_general_DF)
|
||||
if (mb_type_general_DF[3] == 1'b0)
|
||||
case (mb_type_general_DF[2:0])
|
||||
3'b000,3'b101:MB_inter_size <= `I16x16;
|
||||
3'b001 :MB_inter_size <= `I16x8;
|
||||
3'b010 :MB_inter_size <= `I8x16;
|
||||
default :MB_inter_size <= `I8x8;
|
||||
endcase
|
||||
else //Although it should be Intra,but we have no other choice
|
||||
MB_inter_size <= `I8x8;
|
||||
|
||||
reg [1:0] MBTypeGen_mbAddrB;
|
||||
always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
|
||||
case (mb_num_h)
|
||||
0: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
|
||||
1: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
|
||||
2: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
|
||||
3: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
|
||||
4: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
|
||||
5: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
|
||||
6: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
|
||||
7: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
|
||||
8: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
|
||||
9: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
|
||||
10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
|
||||
default:MBTypeGen_mbAddrB <= 0;
|
||||
endcase
|
||||
|
||||
reg [1:0] bs_dec_counter;
|
||||
always @ (posedge gclk_bs_dec or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
bs_dec_counter <= 0;
|
||||
else
|
||||
bs_dec_counter <= bs_dec_counter - 1;
|
||||
|
||||
assign end_of_BS_DEC = (bs_dec_counter == 2'd1)? 1'b1:1'b0;
|
||||
|
||||
wire mvx_V0_diff_GE4,mvx_V1_diff_GE4,mvx_V2_diff_GE4,mvx_V3_diff_GE4;
|
||||
wire mvy_V0_diff_GE4,mvy_V1_diff_GE4,mvy_V2_diff_GE4,mvy_V3_diff_GE4;
|
||||
wire mvx_H0_diff_GE4,mvx_H1_diff_GE4,mvx_H2_diff_GE4,mvx_H3_diff_GE4;
|
||||
wire mvy_H0_diff_GE4,mvy_H1_diff_GE4,mvy_H2_diff_GE4,mvy_H3_diff_GE4;
|
||||
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
//If current MB is Inter,derive current MB non-zero coeff information
|
||||
//No need to do this for P_skip or Intra.No need for chroma,either.
|
||||
//--------------------------------------------------------------------
|
||||
reg [15:0] currMB_coeff;//whether each 4x4blk of current MB has at least one non-zero transform coeff
|
||||
//currMB_coeff is organized in zig-zag order,according to blk4x4_rec_counter
|
||||
//= 1'b1:this 4x4blk has at least one non-zero transform coeff
|
||||
//= 1'b0:this 4x4blk has all 16 zero transform coeff
|
||||
//only useful for Inter (excluding P_skip) MB
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
currMB_coeff <= 16'd0;
|
||||
else if (!disable_DF)
|
||||
begin
|
||||
//need to be reset evey MB
|
||||
//Since only Inter MB needs currMB_coeff,we can use "coded_block_pattern_s" state as timing slot
|
||||
if (slice_data_state == `coded_block_pattern_s)
|
||||
currMB_coeff <= 16'd0;
|
||||
else if (mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101) //Inter but not P_skip
|
||||
case (residual_state)
|
||||
`Intra16x16ACLevel_s:
|
||||
if (end_of_one_residual_block)
|
||||
case (blk4x4_rec_counter[3:0])
|
||||
4'd0 :currMB_coeff[0] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd1 :currMB_coeff[1] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd2 :currMB_coeff[2] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd3 :currMB_coeff[3] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd4 :currMB_coeff[4] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd5 :currMB_coeff[5] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd6 :currMB_coeff[6] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd7 :currMB_coeff[7] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd8 :currMB_coeff[8] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd9 :currMB_coeff[9] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd10:currMB_coeff[10] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd11:currMB_coeff[11] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd12:currMB_coeff[12] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd13:currMB_coeff[13] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd14:currMB_coeff[14] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
4'd15:currMB_coeff[15] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
|
||||
endcase
|
||||
`Intra16x16ACLevel_0_s:
|
||||
case (blk4x4_rec_counter[3:0])
|
||||
4'd0:currMB_coeff[0] <= ~curr_DC_IsZero;
|
||||
4'd1:currMB_coeff[1] <= ~curr_DC_IsZero;
|
||||
4'd2:currMB_coeff[2] <= ~curr_DC_IsZero;
|
||||
4'd3:currMB_coeff[3] <= ~curr_DC_IsZero;
|
||||
4'd4:currMB_coeff[4] <= ~curr_DC_IsZero;
|
||||
4'd5:currMB_coeff[5] <= ~curr_DC_IsZero;
|
||||
4'd6:currMB_coeff[6] <= ~curr_DC_IsZero;
|
||||
4'd7:currMB_coeff[7] <= ~curr_DC_IsZero;
|
||||
4'd8:currMB_coeff[8] <= ~curr_DC_IsZero;
|
||||
4'd9:currMB_coeff[9] <= ~curr_DC_IsZero;
|
||||
4'd10:currMB_coeff[10] <= ~curr_DC_IsZero;
|
||||
4'd11:currMB_coeff[11] <= ~curr_DC_IsZero;
|
||||
4'd12:currMB_coeff[12] <= ~curr_DC_IsZero;
|
||||
4'd13:currMB_coeff[13] <= ~curr_DC_IsZero;
|
||||
4'd14:currMB_coeff[14] <= ~curr_DC_IsZero;
|
||||
4'd15:currMB_coeff[15] <= ~curr_DC_IsZero;
|
||||
endcase
|
||||
`LumaLevel_s:
|
||||
case (blk4x4_rec_counter[3:0])
|
||||
4'd0 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[0] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[0] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd1 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[1] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[1] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd2 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[2] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[2] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd3 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[3] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[3] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd4 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[4] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[4] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd5 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[5] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[5] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd6 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[6] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[6] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd7 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[7] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[7] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd8 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[8] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[8] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd9 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[9] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[9] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd10:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[10] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[10] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd11:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[11] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[11] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd12:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[12] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[12] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd13:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[13] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[13] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd14:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[14] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[14] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
4'd15:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[15] <= 1'b0;
|
||||
else if (end_of_one_residual_block) currMB_coeff[15] <= (TotalCoeff == 0)? 1'b0:1'b1;
|
||||
endcase
|
||||
`LumaLevel_0_s:currMB_coeff <= 16'd0;
|
||||
endcase
|
||||
end
|
||||
|
||||
//whether each 4x4blk of MB at mbAddrB has at least one non-zero transform coeff
|
||||
reg [43:0] mbAddrB_coeff_reg;
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
mbAddrB_coeff_reg <= 44'd0;
|
||||
else if (!disable_DF && mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101 && mb_num_v != 8) //Inter but not P_skip
|
||||
case (mb_num_h)
|
||||
4'd0 :mbAddrB_coeff_reg[3:0] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd1 :mbAddrB_coeff_reg[7:4] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd2 :mbAddrB_coeff_reg[11:8] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd3 :mbAddrB_coeff_reg[15:12] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd4 :mbAddrB_coeff_reg[19:16] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd5 :mbAddrB_coeff_reg[23:20] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd6 :mbAddrB_coeff_reg[27:24] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd7 :mbAddrB_coeff_reg[31:28] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd8 :mbAddrB_coeff_reg[35:32] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd9 :mbAddrB_coeff_reg[39:36] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
4'd10:mbAddrB_coeff_reg[43:40] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
|
||||
endcase
|
||||
//-------------------------------------------------
|
||||
//backup mbAddrA coding information to derive bs_V0
|
||||
//-------------------------------------------------
|
||||
reg [3:0] mbAddrA_coeff;
|
||||
reg [31:0] mbAddrA_mvx;
|
||||
reg [31:0] mbAddrA_mvy;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
mbAddrA_coeff <= 4'b0;
|
||||
mbAddrA_mvx <= 32'b0;
|
||||
mbAddrA_mvy <= 32'b0;
|
||||
end
|
||||
else if (!disable_DF && mb_num_h != 0 &&
|
||||
((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrA[1] == 1'b0) //Current MB is P_skip
|
||||
|| (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0))) //Current MB is Inter
|
||||
begin
|
||||
mbAddrA_mvx <= mvx_mbAddrA; mbAddrA_mvy <= mvy_mbAddrA;
|
||||
//if mbAddrA is Inter (not P_skip),back up non-zero residual coeff information
|
||||
if (MBTypeGen_mbAddrA[0] == 1'b0) mbAddrA_coeff <= {currMB_coeff[15],currMB_coeff[13],currMB_coeff[7],currMB_coeff[5]};
|
||||
end
|
||||
//-------------------------------------------------
|
||||
//backup mbAddrB coding information to derive bs_H0
|
||||
//-------------------------------------------------
|
||||
|
||||
//1)For P_skip,at "Is_skipMB_mv_calc", no matter DF is enabled or not,mvx_mbAddrB/mvy_mbAddrB should be read to
|
||||
// derive current motion vector
|
||||
//2)For Inter other than P_skip, mvx_mbAddrB/mvy_mbAddrB are read at mb_pred or sub_mb_pred state.So we add a new
|
||||
// signal "mv_mbAddrB_rd_for_DF" at "slice_data_state == `mb_type_s"
|
||||
assign mv_mbAddrB_rd_for_DF = (!disable_DF && slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0 && mb_num_v != 0);
|
||||
reg [3:0] mbAddrB_coeff;
|
||||
reg [31:0] mbAddrB_mvx;
|
||||
reg [31:0] mbAddrB_mvy;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
mbAddrB_coeff <= 4'b0;
|
||||
mbAddrB_mvx <= 32'b0;
|
||||
mbAddrB_mvy <= 32'b0;
|
||||
end
|
||||
else if (!disable_DF && mb_num_v != 0 &&
|
||||
((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrB[1] == 1'b0) //Current MB is P_skip
|
||||
|| (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0))) //Current MB is Inter
|
||||
begin
|
||||
mbAddrB_mvx <= mvx_mbAddrB_dout; mbAddrB_mvy <= mvy_mbAddrB_dout;
|
||||
//if mbAddrB is Inter (not P_skip),back up non-zero residual coeff information
|
||||
if (MBTypeGen_mbAddrB[0] == 1'b0)
|
||||
case (mb_num_h)
|
||||
4'd0 :mbAddrB_coeff <= mbAddrB_coeff_reg[3:0];
|
||||
4'd1 :mbAddrB_coeff <= mbAddrB_coeff_reg[7:4];
|
||||
4'd2 :mbAddrB_coeff <= mbAddrB_coeff_reg[11:8];
|
||||
4'd3 :mbAddrB_coeff <= mbAddrB_coeff_reg[15:12];
|
||||
4'd4 :mbAddrB_coeff <= mbAddrB_coeff_reg[19:16];
|
||||
4'd5 :mbAddrB_coeff <= mbAddrB_coeff_reg[23:20];
|
||||
4'd6 :mbAddrB_coeff <= mbAddrB_coeff_reg[27:24];
|
||||
4'd7 :mbAddrB_coeff <= mbAddrB_coeff_reg[31:28];
|
||||
4'd8 :mbAddrB_coeff <= mbAddrB_coeff_reg[35:32];
|
||||
4'd9 :mbAddrB_coeff <= mbAddrB_coeff_reg[39:36];
|
||||
4'd10:mbAddrB_coeff <= mbAddrB_coeff_reg[43:40];
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ (posedge gclk_bs_dec or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin
|
||||
bs_V0 <= 0; bs_V1 <= 0; bs_V2 <= 0; bs_V3 <= 0;
|
||||
bs_H0 <= 0; bs_H1 <= 0; bs_H2 <= 0; bs_H3 <= 0;
|
||||
end
|
||||
//-----------------------
|
||||
//Current MB is P_skip
|
||||
//-----------------------
|
||||
else if (mb_type_general_DF == `MB_P_skip)
|
||||
case (bs_dec_counter)
|
||||
2'b00:
|
||||
begin
|
||||
//V0
|
||||
if (mb_num_h == 0) //edge of frame,bs = 0
|
||||
bs_V0 <= 12'b0;
|
||||
else if (MBTypeGen_mbAddrA[1] == 1'b1) //mbAddrA is Intra,bs = 4
|
||||
bs_V0 <= 12'b100100100100;
|
||||
else if (MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip
|
||||
bs_V0 <= (mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 12'b001001001001:12'b0;
|
||||
else //mbAddrA is Inter
|
||||
begin
|
||||
bs_V0[2:0] <= (mbAddrA_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[5:3] <= (mbAddrA_coeff[1])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[8:6] <= (mbAddrA_coeff[2])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[11:9] <= (mbAddrA_coeff[3])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
//H0
|
||||
if (mb_num_v == 0) //edge of frame,bs = 0
|
||||
bs_H0 <= 12'b0;
|
||||
else if (MBTypeGen_mbAddrB[1] == 1'b1) //mbAddrB is Intra,bs=4
|
||||
bs_H0 <= 12'b100100100100;
|
||||
else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip
|
||||
bs_H0 <= (mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 12'b001001001001:12'b0;
|
||||
else
|
||||
begin
|
||||
bs_H0[2:0] <= (mbAddrB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[5:3] <= (mbAddrB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[8:6] <= (mbAddrB_coeff[2])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[11:9] <= (mbAddrB_coeff[3])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
end
|
||||
2'b11:begin bs_V1 <= 0; bs_H1 <= 0; end
|
||||
2'b10:begin bs_V2 <= 0; bs_H2 <= 0; end
|
||||
2'b01:begin bs_V3 <= 0; bs_H3 <= 0; end
|
||||
endcase
|
||||
//--------------------
|
||||
//Current MB is Intra
|
||||
//-----------------------
|
||||
else if (mb_type_general_DF[3] == 1'b1)
|
||||
case (bs_dec_counter)
|
||||
2'b00:
|
||||
begin
|
||||
bs_V0 <= (mb_num_h == 0)? 12'b0:12'b100100100100;
|
||||
bs_H0 <= (mb_num_v == 0)? 12'b0:12'b100100100100;
|
||||
end
|
||||
2'b11:begin bs_V1 <= 12'b011011011011; bs_H1 <= 12'b011011011011; end
|
||||
2'b10:begin bs_V2 <= 12'b011011011011; bs_H2 <= 12'b011011011011; end
|
||||
2'b01:begin bs_V3 <= 12'b011011011011; bs_H3 <= 12'b011011011011; end
|
||||
endcase
|
||||
//-----------------------
|
||||
//Current MB is Inter
|
||||
//-----------------------
|
||||
else
|
||||
case (bs_dec_counter)
|
||||
2'b00: //V0,H0
|
||||
begin
|
||||
//V0
|
||||
if (mb_num_h == 0) //edge of frame,bs = 0
|
||||
bs_V0 <= 12'b0;
|
||||
else if (MBTypeGen_mbAddrA[1] == 1'b1) //mbAddrA is Intra,bs = 4
|
||||
bs_V0 <= 12'b100100100100;
|
||||
else if (MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip
|
||||
begin
|
||||
bs_V0[2:0] <= (currMB_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[5:3] <= (currMB_coeff[2])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[8:6] <= (currMB_coeff[8])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[11:9] <= (currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
else //mbAddrA is Inter
|
||||
begin
|
||||
bs_V0[2:0] <= (mbAddrA_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[5:3] <= (mbAddrA_coeff[1] || currMB_coeff[2])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[8:6] <= (mbAddrA_coeff[2] || currMB_coeff[8])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_V0[11:9] <= (mbAddrA_coeff[3] || currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
//H0
|
||||
if (mb_num_v == 0) //edge of frame,bs = 0
|
||||
bs_H0 <= 12'b0;
|
||||
else if (MBTypeGen_mbAddrB[1] == 1'b1) //mbAddrB is Intra,bs = 4
|
||||
bs_H0 <= 12'b100100100100;
|
||||
else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip
|
||||
begin
|
||||
bs_H0[2:0] <= (currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[5:3] <= (currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[8:6] <= (currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[11:9] <= (currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
else //mbAddrB is Inter
|
||||
begin
|
||||
bs_H0[2:0] <= (mbAddrB_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[5:3] <= (mbAddrB_coeff[1] || currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[8:6] <= (mbAddrB_coeff[2] || currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H0[11:9] <= (mbAddrB_coeff[3] || currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
end
|
||||
2'b11://V1,H1
|
||||
begin
|
||||
bs_V1[2:0] <= (currMB_coeff[0] || currMB_coeff[1])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V1[5:3] <= (currMB_coeff[2] || currMB_coeff[3])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V1[8:6] <= (currMB_coeff[8] || currMB_coeff[9])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V1[11:9] <= (currMB_coeff[10] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H1[2:0] <= (currMB_coeff[0] || currMB_coeff[2])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H1[5:3] <= (currMB_coeff[1] || currMB_coeff[3])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H1[8:6] <= (currMB_coeff[4] || currMB_coeff[6])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
|
||||
bs_H1[11:9] <= (currMB_coeff[5] || currMB_coeff[7])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
2'b10://V2,H2
|
||||
begin
|
||||
bs_V2[2:0] <= (currMB_coeff[1] || currMB_coeff[4])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
|
||||
0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V2[5:3] <= (currMB_coeff[3] || currMB_coeff[6])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
|
||||
0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V2[8:6] <= (currMB_coeff[9] || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
|
||||
0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V2[11:9] <= (currMB_coeff[11] || currMB_coeff[14])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
|
||||
0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H2[2:0] <= (currMB_coeff[2] || currMB_coeff[8])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
|
||||
0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H2[5:3] <= (currMB_coeff[3] || currMB_coeff[9])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
|
||||
0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H2[8:6] <= (currMB_coeff[6] || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
|
||||
0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H2[11:9] <= (currMB_coeff[7] || currMB_coeff[13])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
|
||||
0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
2'b01://V3,H3
|
||||
begin
|
||||
bs_V3[2:0] <= (currMB_coeff[4] || currMB_coeff[5])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V3[5:3] <= (currMB_coeff[6] || currMB_coeff[7])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V3[8:6] <= (currMB_coeff[12] || currMB_coeff[13])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_V3[11:9] <= (currMB_coeff[14] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H3[2:0] <= (currMB_coeff[8] || currMB_coeff[10])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H3[5:3] <= (currMB_coeff[9] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H3[8:6] <= (currMB_coeff[12] || currMB_coeff[14])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
|
||||
|
||||
bs_H3[11:9] <= (currMB_coeff[13] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)?
|
||||
0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
|
||||
end
|
||||
endcase
|
||||
|
||||
reg [7:0] mvx_V0_diff_a,mvx_V0_diff_b;
|
||||
reg [7:0] mvx_V1_diff_a,mvx_V1_diff_b;
|
||||
reg [7:0] mvx_V2_diff_a,mvx_V2_diff_b;
|
||||
reg [7:0] mvx_V3_diff_a,mvx_V3_diff_b;
|
||||
reg [7:0] mvy_V0_diff_a,mvy_V0_diff_b;
|
||||
reg [7:0] mvy_V1_diff_a,mvy_V1_diff_b;
|
||||
reg [7:0] mvy_V2_diff_a,mvy_V2_diff_b;
|
||||
reg [7:0] mvy_V3_diff_a,mvy_V3_diff_b;
|
||||
|
||||
reg [7:0] mvx_H0_diff_a,mvx_H0_diff_b;
|
||||
reg [7:0] mvx_H1_diff_a,mvx_H1_diff_b;
|
||||
reg [7:0] mvx_H2_diff_a,mvx_H2_diff_b;
|
||||
reg [7:0] mvx_H3_diff_a,mvx_H3_diff_b;
|
||||
reg [7:0] mvy_H0_diff_a,mvy_H0_diff_b;
|
||||
reg [7:0] mvy_H1_diff_a,mvy_H1_diff_b;
|
||||
reg [7:0] mvy_H2_diff_a,mvy_H2_diff_b;
|
||||
reg [7:0] mvy_H3_diff_a,mvy_H3_diff_b;
|
||||
|
||||
mv_diff_GE4 mvx_V0_diff (.mv_a(mvx_V0_diff_a),.mv_b(mvx_V0_diff_b),.diff_GE4(mvx_V0_diff_GE4));
|
||||
mv_diff_GE4 mvx_V1_diff (.mv_a(mvx_V1_diff_a),.mv_b(mvx_V1_diff_b),.diff_GE4(mvx_V1_diff_GE4));
|
||||
mv_diff_GE4 mvx_V2_diff (.mv_a(mvx_V2_diff_a),.mv_b(mvx_V2_diff_b),.diff_GE4(mvx_V2_diff_GE4));
|
||||
mv_diff_GE4 mvx_V3_diff (.mv_a(mvx_V3_diff_a),.mv_b(mvx_V3_diff_b),.diff_GE4(mvx_V3_diff_GE4));
|
||||
mv_diff_GE4 mvy_V0_diff (.mv_a(mvy_V0_diff_a),.mv_b(mvy_V0_diff_b),.diff_GE4(mvy_V0_diff_GE4));
|
||||
mv_diff_GE4 mvy_V1_diff (.mv_a(mvy_V1_diff_a),.mv_b(mvy_V1_diff_b),.diff_GE4(mvy_V1_diff_GE4));
|
||||
mv_diff_GE4 mvy_V2_diff (.mv_a(mvy_V2_diff_a),.mv_b(mvy_V2_diff_b),.diff_GE4(mvy_V2_diff_GE4));
|
||||
mv_diff_GE4 mvy_V3_diff (.mv_a(mvy_V3_diff_a),.mv_b(mvy_V3_diff_b),.diff_GE4(mvy_V3_diff_GE4));
|
||||
|
||||
mv_diff_GE4 mvx_H0_diff (.mv_a(mvx_H0_diff_a),.mv_b(mvx_H0_diff_b),.diff_GE4(mvx_H0_diff_GE4));
|
||||
mv_diff_GE4 mvx_H1_diff (.mv_a(mvx_H1_diff_a),.mv_b(mvx_H1_diff_b),.diff_GE4(mvx_H1_diff_GE4));
|
||||
mv_diff_GE4 mvx_H2_diff (.mv_a(mvx_H2_diff_a),.mv_b(mvx_H2_diff_b),.diff_GE4(mvx_H2_diff_GE4));
|
||||
mv_diff_GE4 mvx_H3_diff (.mv_a(mvx_H3_diff_a),.mv_b(mvx_H3_diff_b),.diff_GE4(mvx_H3_diff_GE4));
|
||||
mv_diff_GE4 mvy_H0_diff (.mv_a(mvy_H0_diff_a),.mv_b(mvy_H0_diff_b),.diff_GE4(mvy_H0_diff_GE4));
|
||||
mv_diff_GE4 mvy_H1_diff (.mv_a(mvy_H1_diff_a),.mv_b(mvy_H1_diff_b),.diff_GE4(mvy_H1_diff_GE4));
|
||||
mv_diff_GE4 mvy_H2_diff (.mv_a(mvy_H2_diff_a),.mv_b(mvy_H2_diff_b),.diff_GE4(mvy_H2_diff_GE4));
|
||||
mv_diff_GE4 mvy_H3_diff (.mv_a(mvy_H3_diff_a),.mv_b(mvy_H3_diff_b),.diff_GE4(mvy_H3_diff_GE4));
|
||||
|
||||
always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF
|
||||
or mb_num_h or MB_inter_size or MBTypeGen_mbAddrA
|
||||
or mbAddrA_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
||||
or mbAddrA_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3)
|
||||
if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0)
|
||||
begin
|
||||
//-----------------------
|
||||
//Current MB is P_skip
|
||||
//-----------------------
|
||||
if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00)//V0
|
||||
begin
|
||||
if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip
|
||||
begin
|
||||
mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
|
||||
mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
|
||||
mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
|
||||
mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
|
||||
mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
|
||||
mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
|
||||
end
|
||||
else if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_Inter) //mbAddrA is Inter
|
||||
begin
|
||||
mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_V1_diff_a <= mbAddrA_mvx[15:8]; mvx_V1_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_V2_diff_a <= mbAddrA_mvx[23:16];mvx_V2_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_V3_diff_a <= mbAddrA_mvx[31:24];mvx_V3_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_V1_diff_a <= mbAddrA_mvy[15:8]; mvy_V1_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_V2_diff_a <= mbAddrA_mvy[23:16];mvy_V2_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_V3_diff_a <= mbAddrA_mvy[31:24];mvy_V3_diff_b <= mvy_CurrMb0[7:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
|
||||
mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
|
||||
mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
|
||||
mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
|
||||
mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
|
||||
mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
|
||||
mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
|
||||
mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
|
||||
end
|
||||
end
|
||||
//-----------------------
|
||||
//Current MB is Inter
|
||||
//-----------------------
|
||||
else if (mb_type_general_DF[3] == 1'b0)
|
||||
case (bs_dec_counter)
|
||||
2'b00: //V0
|
||||
if (mb_num_h != 0 && (MBTypeGen_mbAddrA[1] == 1'b0)) //mbAddrA is P_skip or Inter
|
||||
begin
|
||||
mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0];
|
||||
|
||||
mvx_V1_diff_a <= mbAddrA_mvx[15:8];
|
||||
mvx_V1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[23:16];
|
||||
|
||||
mvx_V2_diff_a <= mbAddrA_mvx[23:16];
|
||||
mvx_V2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[7:0];
|
||||
|
||||
mvx_V3_diff_a <= mbAddrA_mvx[31:24];
|
||||
mvx_V3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[23:16];
|
||||
|
||||
mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0];
|
||||
|
||||
mvy_V1_diff_a <= mbAddrA_mvy[15:8];
|
||||
mvy_V1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[23:16];
|
||||
|
||||
mvy_V2_diff_a <= mbAddrA_mvy[23:16];
|
||||
mvy_V2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[7:0];
|
||||
|
||||
mvy_V3_diff_a <= mbAddrA_mvy[31:24];
|
||||
mvy_V3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[23:16];
|
||||
end
|
||||
else
|
||||
begin
|
||||
mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
|
||||
mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
|
||||
mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
|
||||
mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
|
||||
mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
|
||||
mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
|
||||
mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
|
||||
mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
|
||||
end
|
||||
2'b11: //V1
|
||||
begin
|
||||
mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0];
|
||||
mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8];
|
||||
mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16];
|
||||
mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24];
|
||||
mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0];
|
||||
mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8];
|
||||
mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16];
|
||||
mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24];
|
||||
|
||||
mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0];
|
||||
mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8];
|
||||
mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16];
|
||||
mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24];
|
||||
mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0];
|
||||
mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8];
|
||||
mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16];
|
||||
mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24];
|
||||
end
|
||||
2'b10: //V2
|
||||
begin
|
||||
mvx_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[15:8];
|
||||
mvx_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[7:0];
|
||||
mvx_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[31:24];
|
||||
mvx_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[23:16];
|
||||
mvx_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[15:8];
|
||||
mvx_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[7:0];
|
||||
mvx_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[31:24];
|
||||
mvx_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[23:16];
|
||||
mvy_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[15:8];
|
||||
mvy_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[7:0];
|
||||
mvy_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[31:24];
|
||||
mvy_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[23:16];
|
||||
mvy_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[15:8];
|
||||
mvy_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[7:0];
|
||||
mvy_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[31:24];
|
||||
mvy_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[23:16];
|
||||
end
|
||||
2'b01: //V3
|
||||
begin
|
||||
mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0];
|
||||
mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8];
|
||||
mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16];
|
||||
mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24];
|
||||
mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0];
|
||||
mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8];
|
||||
mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16];
|
||||
mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24];
|
||||
|
||||
mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0];
|
||||
mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8];
|
||||
mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16];
|
||||
mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24];
|
||||
mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0];
|
||||
mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8];
|
||||
mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16];
|
||||
mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24];
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
|
||||
mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
|
||||
mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
|
||||
mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
|
||||
mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
|
||||
mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
|
||||
mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
|
||||
mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
|
||||
mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
|
||||
mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
|
||||
mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
|
||||
mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
|
||||
mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
|
||||
mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
|
||||
mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
|
||||
end
|
||||
|
||||
|
||||
always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF
|
||||
or mb_num_v or MBTypeGen_mbAddrB or MB_inter_size
|
||||
or mbAddrB_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
|
||||
or mbAddrB_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3)
|
||||
if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0)
|
||||
begin
|
||||
//-----------------------
|
||||
//Current MB is P_skip
|
||||
//-----------------------
|
||||
if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00) //H0
|
||||
begin
|
||||
if (mb_num_v != 0 && MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip
|
||||
begin
|
||||
mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
|
||||
mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
|
||||
mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
|
||||
mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
|
||||
mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
|
||||
mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
|
||||
end
|
||||
else if (mb_num_v != 0 && MBTypeGen_mbAddrB == 2'b00) //mbAddrB is Inter
|
||||
begin
|
||||
mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_H1_diff_a <= mbAddrB_mvx[23:16]; mvx_H1_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_H2_diff_a <= mbAddrB_mvx[15:8]; mvx_H2_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvx_H3_diff_a <= mbAddrB_mvx[7:0]; mvx_H3_diff_b <= mvx_CurrMb0[7:0];
|
||||
mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_H1_diff_a <= mbAddrB_mvy[23:16]; mvy_H1_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_H2_diff_a <= mbAddrB_mvy[15:8]; mvy_H2_diff_b <= mvy_CurrMb0[7:0];
|
||||
mvy_H3_diff_a <= mbAddrB_mvy[7:0]; mvy_H3_diff_b <= mvy_CurrMb0[7:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
|
||||
mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
|
||||
mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
|
||||
mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
|
||||
mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
|
||||
mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
|
||||
mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
|
||||
mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
|
||||
end
|
||||
end
|
||||
//-----------------------
|
||||
//Current MB is Inter
|
||||
//-----------------------
|
||||
else if (mb_type_general_DF[3] == 1'b0)
|
||||
case (bs_dec_counter)
|
||||
2'b00: //H0
|
||||
if (mb_num_v != 0 && (MBTypeGen_mbAddrB[1] == 1'b0))//mbAddrB is P_skip or Inter
|
||||
begin
|
||||
mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0];
|
||||
|
||||
mvx_H1_diff_a <= mbAddrB_mvx[23:16];
|
||||
mvx_H1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[15:8];
|
||||
|
||||
mvx_H2_diff_a <= mbAddrB_mvx[15:8];
|
||||
mvx_H2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[7:0];
|
||||
|
||||
mvx_H3_diff_a <= mbAddrB_mvx[7:0];
|
||||
mvx_H3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[15:8];
|
||||
|
||||
mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0];
|
||||
|
||||
mvy_H1_diff_a <= mbAddrB_mvy[23:16];
|
||||
mvy_H1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[15:8];
|
||||
|
||||
mvy_H2_diff_a <= mbAddrB_mvy[15:8];
|
||||
mvy_H2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[7:0];
|
||||
|
||||
mvy_H3_diff_a <= mbAddrB_mvy[7:0];
|
||||
mvy_H3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[15:8];
|
||||
end
|
||||
else
|
||||
begin
|
||||
mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
|
||||
mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
|
||||
mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
|
||||
mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
|
||||
mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
|
||||
mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
|
||||
mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
|
||||
mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
|
||||
end
|
||||
2'b11: //H1
|
||||
begin
|
||||
mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0];
|
||||
mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16];
|
||||
mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8];
|
||||
mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24];
|
||||
mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0];
|
||||
mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16];
|
||||
mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8];
|
||||
mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24];
|
||||
|
||||
mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0];
|
||||
mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16];
|
||||
mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8];
|
||||
mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24];
|
||||
mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0];
|
||||
mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16];
|
||||
mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8];
|
||||
mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24];
|
||||
end
|
||||
2'b10: //H2
|
||||
begin
|
||||
mvx_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[23:16];
|
||||
mvx_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[7:0];
|
||||
mvx_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[31:24];
|
||||
mvx_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[15:8];
|
||||
mvx_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[23:16];
|
||||
mvx_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[7:0];
|
||||
mvx_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[31:24];
|
||||
mvx_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[15:8];
|
||||
|
||||
mvy_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[23:16];
|
||||
mvy_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[7:0];
|
||||
mvy_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[31:24];
|
||||
mvy_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[15:8];
|
||||
mvy_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[23:16];
|
||||
mvy_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[7:0];
|
||||
mvy_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[31:24];
|
||||
mvy_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[15:8];
|
||||
|
||||
end
|
||||
2'b01: //H3
|
||||
begin
|
||||
mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0];
|
||||
mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16];
|
||||
mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8];
|
||||
mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24];
|
||||
mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0];
|
||||
mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16];
|
||||
mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8];
|
||||
mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24];
|
||||
|
||||
mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0];
|
||||
mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16];
|
||||
mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8];
|
||||
mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24];
|
||||
mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0];
|
||||
mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16];
|
||||
mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8];
|
||||
mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24];
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
|
||||
mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
|
||||
mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
|
||||
mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
|
||||
mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
|
||||
mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
|
||||
mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
|
||||
mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
|
||||
mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
|
||||
mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
|
||||
mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
|
||||
mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
|
||||
mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
|
||||
mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
|
||||
mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
|
||||
end
|
||||
/*
|
||||
// synopsys translate_off
|
||||
integer tracefile;
|
||||
integer pic_num;
|
||||
wire [6:0] mb_num;
|
||||
assign mb_num = mb_num_v * 11 + mb_num_h;
|
||||
|
||||
initial
|
||||
begin
|
||||
tracefile = $fopen("bs_trace.txt");
|
||||
end
|
||||
reg bs_dec_will_end;
|
||||
always @ (posedge clk)
|
||||
if (bs_dec_counter == 2'b01)
|
||||
bs_dec_will_end <= 1'b1;
|
||||
else
|
||||
bs_dec_will_end <= 1'b0;
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
pic_num <= 0;
|
||||
else if (bs_dec_will_end)
|
||||
begin
|
||||
$fdisplay (tracefile, "-------------------------------");
|
||||
if (mb_num == 0)
|
||||
$fdisplay (tracefile, " Pic_num = %3d,MB_num = 98",(pic_num - 1));
|
||||
else
|
||||
$fdisplay (tracefile, " Pic_num = %3d,MB_num = %3d",pic_num,(mb_num - 1));
|
||||
$fdisplay (tracefile, " Vertical Edge 0:Bs = %d,%d,%d,%d",bs_V0[2:0],bs_V0[5:3],bs_V0[8:6],bs_V0[11:9]);
|
||||
$fdisplay (tracefile, " Vertical Edge 1:Bs = %d,%d,%d,%d",bs_V1[2:0],bs_V1[5:3],bs_V1[8:6],bs_V1[11:9]);
|
||||
$fdisplay (tracefile, " Vertical Edge 2:Bs = %d,%d,%d,%d",bs_V2[2:0],bs_V2[5:3],bs_V2[8:6],bs_V2[11:9]);
|
||||
$fdisplay (tracefile, " Vertical Edge 3:Bs = %d,%d,%d,%d",bs_V3[2:0],bs_V3[5:3],bs_V3[8:6],bs_V3[11:9]);
|
||||
$fdisplay (tracefile, " Horizontal Edge 0:Bs = %d,%d,%d,%d",bs_H0[2:0],bs_H0[5:3],bs_H0[8:6],bs_H0[11:9]);
|
||||
$fdisplay (tracefile, " Horizontal Edge 1:Bs = %d,%d,%d,%d",bs_H1[2:0],bs_H1[5:3],bs_H1[8:6],bs_H1[11:9]);
|
||||
$fdisplay (tracefile, " Horizontal Edge 2:Bs = %d,%d,%d,%d",bs_H2[2:0],bs_H2[5:3],bs_H2[8:6],bs_H2[11:9]);
|
||||
$fdisplay (tracefile, " Horizontal Edge 3:Bs = %d,%d,%d,%d",bs_H3[2:0],bs_H3[5:3],bs_H3[8:6],bs_H3[11:9]);
|
||||
if (mb_num == 98)
|
||||
pic_num <= pic_num + 1;
|
||||
end
|
||||
// synopsys translate_on
|
||||
*/
|
||||
endmodule
|
||||
|
||||
module mv_diff_GE4 (mv_a,mv_b,diff_GE4);
|
||||
input [7:0] mv_a,mv_b;
|
||||
output diff_GE4;
|
||||
wire [7:0] diff_tmp;
|
||||
wire [6:0] diff;
|
||||
assign diff_tmp = mv_a + ~ mv_b + 1;
|
||||
assign diff = (diff_tmp[7] == 1'b1)? (~diff_tmp[6:0] + 1):diff_tmp[6:0];
|
||||
assign diff_GE4 = (diff[6:2] != 0)? 1'b1:1'b0;
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : cavlc_consumed_bits_decoding.v
|
||||
// Generated : June 12,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Calculate the consumed bit length of CAVLC decoder of each clock cycle
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module cavlc_consumed_bits_decoding (cavlc_decoder_state,NumCoeffTrailingOnes_len,TrailingOnes,
|
||||
heading_one_pos,levelSuffixSize,total_zeros_len,run_of_zeros_len,cavlc_consumed_bits_len);
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [4:0] NumCoeffTrailingOnes_len;
|
||||
input [1:0] TrailingOnes;
|
||||
input [3:0] heading_one_pos;
|
||||
input [3:0] levelSuffixSize;
|
||||
input [3:0] total_zeros_len;
|
||||
input [3:0] run_of_zeros_len;
|
||||
output [4:0] cavlc_consumed_bits_len;
|
||||
reg [4:0] cavlc_consumed_bits_len;
|
||||
|
||||
always @ (cavlc_decoder_state or NumCoeffTrailingOnes_len or TrailingOnes or heading_one_pos or
|
||||
levelSuffixSize or total_zeros_len or run_of_zeros_len)
|
||||
case (cavlc_decoder_state)
|
||||
`NumCoeffTrailingOnes_LUT:cavlc_consumed_bits_len <= NumCoeffTrailingOnes_len;
|
||||
`TrailingOnesSignFlag :cavlc_consumed_bits_len <= TrailingOnes;
|
||||
`LevelPrefix :cavlc_consumed_bits_len <= heading_one_pos + 1;
|
||||
`LevelSuffix :cavlc_consumed_bits_len <= levelSuffixSize;
|
||||
`total_zeros_LUT :cavlc_consumed_bits_len <= total_zeros_len;
|
||||
`run_before_LUT :cavlc_consumed_bits_len <= run_of_zeros_len;
|
||||
default :cavlc_consumed_bits_len <= 0;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,288 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : cavlc_decoder.v
|
||||
// Generated : June 12,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// cavlc_decoder top module
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module cavlc_decoder (clk,reset_n,gclk_end_of_MB_DEC,
|
||||
gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF,
|
||||
slice_data_state,residual_state,cavlc_decoder_state,mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr,
|
||||
i_level,i_run,i_TotalCoeff,coeffNum,
|
||||
heading_one_pos,BitStream_buffer_output,
|
||||
CodedBlockPatternLuma,CodedBlockPatternChroma,suffix_length_initialized,IsRunLoop,
|
||||
|
||||
Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA,LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3,
|
||||
LumaLevel_mbAddrB_dout,LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n,
|
||||
end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,
|
||||
cavlc_consumed_bits_len,TotalCoeff,TrailingOnes,maxNumCoeff,zerosLeft,run,
|
||||
coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7,
|
||||
coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15);
|
||||
input clk,reset_n;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input gclk_LumaLevel_mbAddrB_RF;
|
||||
input gclk_ChromaLevel_Cb_mbAddrB_RF;
|
||||
input gclk_ChromaLevel_Cr_mbAddrB_RF;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [1:0] i8x8;
|
||||
input [1:0] i4x4;
|
||||
input [1:0] i4x4_CbCr;
|
||||
input [3:0] i_level;
|
||||
input [3:0] i_run;
|
||||
input [3:0] i_TotalCoeff;
|
||||
input [3:0] coeffNum;
|
||||
input [3:0] heading_one_pos;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
input [3:0] CodedBlockPatternLuma;
|
||||
input [1:0] CodedBlockPatternChroma;
|
||||
input suffix_length_initialized;
|
||||
input IsRunLoop;
|
||||
|
||||
output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA;
|
||||
output [19:0] LumaLevel_mbAddrA;
|
||||
output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
|
||||
output [19:0] LumaLevel_mbAddrB_dout;
|
||||
output LumaLevel_mbAddrB_cs_n;
|
||||
output ChromaLevel_Cb_mbAddrB_cs_n;
|
||||
output ChromaLevel_Cr_mbAddrB_cs_n;
|
||||
output end_of_one_residual_block;
|
||||
output end_of_NonZeroCoeff_CAVLC;
|
||||
output [4:0] cavlc_consumed_bits_len;
|
||||
output [4:0] TotalCoeff;
|
||||
output [1:0] TrailingOnes;
|
||||
output [4:0] maxNumCoeff;
|
||||
output [3:0] zerosLeft;
|
||||
output [3:0] run;
|
||||
output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6;
|
||||
output [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13;
|
||||
output [8:0] coeffLevel_14,coeffLevel_15;
|
||||
|
||||
wire LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n;
|
||||
wire [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr;
|
||||
wire [19:0] LumaLevel_mbAddrB_din;
|
||||
wire [19:0] LumaLevel_mbAddrB_dout;
|
||||
wire ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n;
|
||||
wire [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr;
|
||||
wire [9:0] ChromaLevel_Cb_mbAddrB_din;
|
||||
wire [9:0] ChromaLevel_Cb_mbAddrB_dout;
|
||||
wire ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n;
|
||||
wire [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr;
|
||||
wire [9:0] ChromaLevel_Cr_mbAddrB_din;
|
||||
wire [9:0] ChromaLevel_Cr_mbAddrB_dout;
|
||||
wire [4:0] nC;
|
||||
wire [4:0] NumCoeffTrailingOnes_len;
|
||||
wire [3:0] levelSuffixSize;
|
||||
wire [8:0] level_0,level_1,level_2, level_3, level_4, level_5, level_6, level_7;
|
||||
wire [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15;
|
||||
wire [3:0] total_zeros;
|
||||
wire [3:0] total_zeros_len;
|
||||
wire [3:0] run_of_zeros_len;
|
||||
|
||||
nC_decoding nC_decoding (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.residual_state(residual_state),
|
||||
.slice_data_state(slice_data_state),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.i8x8(i8x8),
|
||||
.i4x4(i4x4),
|
||||
.i4x4_CbCr(i4x4_CbCr),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.LumaLevel_mbAddrB_dout(LumaLevel_mbAddrB_dout),
|
||||
.ChromaLevel_Cb_mbAddrB_dout(ChromaLevel_Cb_mbAddrB_dout),
|
||||
.ChromaLevel_Cr_mbAddrB_dout(ChromaLevel_Cr_mbAddrB_dout),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
|
||||
.nC(nC),
|
||||
.Luma_8x8_AllZeroCoeff_mbAddrA(Luma_8x8_AllZeroCoeff_mbAddrA),
|
||||
.LumaLevel_mbAddrA(LumaLevel_mbAddrA),
|
||||
.LumaLevel_CurrMb0(LumaLevel_CurrMb0),
|
||||
.LumaLevel_CurrMb1(LumaLevel_CurrMb1),
|
||||
.LumaLevel_CurrMb2(LumaLevel_CurrMb2),
|
||||
.LumaLevel_CurrMb3(LumaLevel_CurrMb3),
|
||||
.LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n),
|
||||
.LumaLevel_mbAddrB_wr_n(LumaLevel_mbAddrB_wr_n),
|
||||
.LumaLevel_mbAddrB_rd_addr(LumaLevel_mbAddrB_rd_addr),
|
||||
.LumaLevel_mbAddrB_wr_addr(LumaLevel_mbAddrB_wr_addr),
|
||||
.LumaLevel_mbAddrB_din(LumaLevel_mbAddrB_din),
|
||||
.ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n),
|
||||
.ChromaLevel_Cb_mbAddrB_wr_n(ChromaLevel_Cb_mbAddrB_wr_n),
|
||||
.ChromaLevel_Cb_mbAddrB_rd_addr(ChromaLevel_Cb_mbAddrB_rd_addr),
|
||||
.ChromaLevel_Cb_mbAddrB_wr_addr(ChromaLevel_Cb_mbAddrB_wr_addr),
|
||||
.ChromaLevel_Cb_mbAddrB_din(ChromaLevel_Cb_mbAddrB_din),
|
||||
.ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n),
|
||||
.ChromaLevel_Cr_mbAddrB_wr_n(ChromaLevel_Cr_mbAddrB_wr_n),
|
||||
.ChromaLevel_Cr_mbAddrB_rd_addr(ChromaLevel_Cr_mbAddrB_rd_addr),
|
||||
.ChromaLevel_Cr_mbAddrB_wr_addr(ChromaLevel_Cr_mbAddrB_wr_addr),
|
||||
.ChromaLevel_Cr_mbAddrB_din(ChromaLevel_Cr_mbAddrB_din)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`LumaLevel_mbAddrB_RF_data_width,`LumaLevel_mbAddrB_RF_data_depth)
|
||||
LumaLevel_mbAddrB_RF(
|
||||
.clk(gclk_LumaLevel_mbAddrB_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(LumaLevel_mbAddrB_cs_n),
|
||||
.wr_n(LumaLevel_mbAddrB_wr_n),
|
||||
.rd_addr(LumaLevel_mbAddrB_rd_addr),
|
||||
.wr_addr(LumaLevel_mbAddrB_wr_addr),
|
||||
.data_in(LumaLevel_mbAddrB_din),
|
||||
.data_out(LumaLevel_mbAddrB_dout)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`ChromaLevel_Cb_mbAddrB_RF_data_width,`ChromaLevel_Cb_mbAddrB_RF_data_depth)
|
||||
ChromaLevel_Cb_mbAddrB_RF(
|
||||
.clk(gclk_ChromaLevel_Cb_mbAddrB_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(ChromaLevel_Cb_mbAddrB_cs_n),
|
||||
.wr_n(ChromaLevel_Cb_mbAddrB_wr_n),
|
||||
.rd_addr(ChromaLevel_Cb_mbAddrB_rd_addr),
|
||||
.wr_addr(ChromaLevel_Cb_mbAddrB_wr_addr),
|
||||
.data_in(ChromaLevel_Cb_mbAddrB_din),
|
||||
.data_out(ChromaLevel_Cb_mbAddrB_dout)
|
||||
);
|
||||
ram_async_1r_sync_1w # (`ChromaLevel_Cr_mbAddrB_RF_data_width,`ChromaLevel_Cr_mbAddrB_RF_data_depth)
|
||||
ChromaLevel_Cr_mbAddrB_RF(
|
||||
.clk(gclk_ChromaLevel_Cr_mbAddrB_RF),
|
||||
.rst_n(reset_n),
|
||||
.cs_n(ChromaLevel_Cr_mbAddrB_cs_n),
|
||||
.wr_n(ChromaLevel_Cr_mbAddrB_wr_n),
|
||||
.rd_addr(ChromaLevel_Cr_mbAddrB_rd_addr),
|
||||
.wr_addr(ChromaLevel_Cr_mbAddrB_wr_addr),
|
||||
.data_in(ChromaLevel_Cr_mbAddrB_din),
|
||||
.data_out(ChromaLevel_Cr_mbAddrB_dout)
|
||||
);
|
||||
NumCoeffTrailingOnes_decoding NumCoeffTrailingOnes_decoding(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.heading_one_pos(heading_one_pos),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.nC(nC),
|
||||
.TrailingOnes(TrailingOnes),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.NumCoeffTrailingOnes_len(NumCoeffTrailingOnes_len)
|
||||
);
|
||||
level_decoding level_decoding(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.heading_one_pos(heading_one_pos),
|
||||
.suffix_length_initialized(suffix_length_initialized),
|
||||
.i_level(i_level),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.TrailingOnes(TrailingOnes),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.levelSuffixSize(levelSuffixSize),
|
||||
.level_0(level_0),
|
||||
.level_1(level_1),
|
||||
.level_2(level_2),
|
||||
.level_3(level_3),
|
||||
.level_4(level_4),
|
||||
.level_5(level_5),
|
||||
.level_6(level_6),
|
||||
.level_7(level_7),
|
||||
.level_8(level_8),
|
||||
.level_9(level_9),
|
||||
.level_10(level_10),
|
||||
.level_11(level_11),
|
||||
.level_12(level_12),
|
||||
.level_13(level_13),
|
||||
.level_14(level_14),
|
||||
.level_15(level_15)
|
||||
);
|
||||
total_zeros_decoding total_zeros_decoding(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.TotalCoeff_3to0(TotalCoeff[3:0]),
|
||||
.heading_one_pos(heading_one_pos),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.maxNumCoeff(maxNumCoeff),
|
||||
.total_zeros(total_zeros),
|
||||
.total_zeros_len(total_zeros_len)
|
||||
);
|
||||
run_decoding run_decoding(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.BitStream_buffer_output(BitStream_buffer_output),
|
||||
.total_zeros(total_zeros),
|
||||
.level_0(level_0),
|
||||
.level_1(level_1),
|
||||
.level_2(level_2),
|
||||
.level_3(level_3),
|
||||
.level_4(level_4),
|
||||
.level_5(level_5),
|
||||
.level_6(level_6),
|
||||
.level_7(level_7),
|
||||
.level_8(level_8),
|
||||
.level_9(level_9),
|
||||
.level_10(level_10),
|
||||
.level_11(level_11),
|
||||
.level_12(level_12),
|
||||
.level_13(level_13),
|
||||
.level_14(level_14),
|
||||
.level_15(level_15),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.i_run(i_run),
|
||||
.i_TotalCoeff(i_TotalCoeff),
|
||||
.coeffNum(coeffNum),
|
||||
.IsRunLoop(IsRunLoop),
|
||||
|
||||
.run_of_zeros_len(run_of_zeros_len),
|
||||
.zerosLeft(zerosLeft),
|
||||
.run(run),
|
||||
.coeffLevel_0(coeffLevel_0),
|
||||
.coeffLevel_1(coeffLevel_1),
|
||||
.coeffLevel_2(coeffLevel_2),
|
||||
.coeffLevel_3(coeffLevel_3),
|
||||
.coeffLevel_4(coeffLevel_4),
|
||||
.coeffLevel_5(coeffLevel_5),
|
||||
.coeffLevel_6(coeffLevel_6),
|
||||
.coeffLevel_7(coeffLevel_7),
|
||||
.coeffLevel_8(coeffLevel_8),
|
||||
.coeffLevel_9(coeffLevel_9),
|
||||
.coeffLevel_10(coeffLevel_10),
|
||||
.coeffLevel_11(coeffLevel_11),
|
||||
.coeffLevel_12(coeffLevel_12),
|
||||
.coeffLevel_13(coeffLevel_13),
|
||||
.coeffLevel_14(coeffLevel_14),
|
||||
.coeffLevel_15(coeffLevel_15)
|
||||
);
|
||||
end_of_blk_decoding end_of_blk_decoding(
|
||||
.reset_n(reset_n),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.i_TotalCoeff(i_TotalCoeff),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC)
|
||||
);
|
||||
cavlc_consumed_bits_decoding cavlc_consumed_bits_decoding(
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.NumCoeffTrailingOnes_len(NumCoeffTrailingOnes_len),
|
||||
.TrailingOnes(TrailingOnes),
|
||||
.heading_one_pos(heading_one_pos),
|
||||
.levelSuffixSize(levelSuffixSize),
|
||||
.total_zeros_len(total_zeros_len),
|
||||
.run_of_zeros_len(run_of_zeros_len),
|
||||
.cavlc_consumed_bits_len(cavlc_consumed_bits_len)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,55 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : dependent_variable_decoding.v
|
||||
// Generated : June 6,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// for u(v) decoding as frame_num,pic_order_cnt_lsb
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module dependent_variable_decoding (slice_header_state,log2_max_frame_num_minus4,
|
||||
log2_max_pic_order_cnt_lsb_minus4,BitStream_buffer_output,
|
||||
dependent_variable_len,dependent_variable_decoding_output);
|
||||
input [3:0] slice_header_state;
|
||||
input [3:0] log2_max_frame_num_minus4;
|
||||
input [3:0] log2_max_pic_order_cnt_lsb_minus4;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
output [3:0] dependent_variable_len;
|
||||
output [9:0] dependent_variable_decoding_output;
|
||||
reg [3:0] dependent_variable_len;
|
||||
reg [9:0] dependent_variable_decoding_output;
|
||||
|
||||
always @ (slice_header_state or log2_max_frame_num_minus4 or log2_max_pic_order_cnt_lsb_minus4)
|
||||
if (slice_header_state == `frame_num_s)
|
||||
dependent_variable_len <= log2_max_frame_num_minus4 + 4;
|
||||
else if (slice_header_state == `pic_order_cnt_lsb_s)
|
||||
dependent_variable_len <= log2_max_pic_order_cnt_lsb_minus4 + 4;
|
||||
else
|
||||
dependent_variable_len <= 0;
|
||||
|
||||
always @ (slice_header_state or dependent_variable_len or BitStream_buffer_output)
|
||||
if (slice_header_state == `frame_num_s || slice_header_state == `pic_order_cnt_lsb_s)
|
||||
case (dependent_variable_len)
|
||||
4 :dependent_variable_decoding_output <= {6'b0,BitStream_buffer_output[15:12]};
|
||||
5 :dependent_variable_decoding_output <= {5'b0,BitStream_buffer_output[15:11]};
|
||||
6 :dependent_variable_decoding_output <= {4'b0,BitStream_buffer_output[15:10]};
|
||||
7 :dependent_variable_decoding_output <= {3'b0,BitStream_buffer_output[15:9]};
|
||||
8 :dependent_variable_decoding_output <= {2'b0,BitStream_buffer_output[15:8]};
|
||||
9 :dependent_variable_decoding_output <= {1'b0,BitStream_buffer_output[15:7]};
|
||||
10:dependent_variable_decoding_output <= BitStream_buffer_output[15:6];
|
||||
default:dependent_variable_decoding_output <= 0;
|
||||
endcase
|
||||
else
|
||||
dependent_variable_decoding_output <= 0;
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : end_of_blk_decoding.v
|
||||
// Generated : June 12, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding end_of_one_residual_block signal for 1 cycle duration
|
||||
// 1)for BitStream_parser_FSM to update signals such as i4x4 and direct state switch
|
||||
// 2)for nC_decoding to update LumaLevel/ChromaLevel CurrMb,mbAddrA,mbAddrB
|
||||
// Decoding end_of_residual signal for 1 cycle duration
|
||||
// 1)for nC_decoding to update general control regs such as Luma_8x8_AllZeroCoeff_mbAddrA,Luma_8x8_AllZeroCoeff_mbAddrB_reg,Chroma_8x8_AllZeroCoeff_mbAddrA,Chroma_8x8_AllZeroCoeff_mbAddrB_reg
|
||||
// 2)Note:for P_skip MBs,their general control regs as *8x8_ALLZeroCoeff* are directly controlled by the state instead of end_of_residual signal
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1. March 24,2006
|
||||
// Add signal end_of_NonZeroCoeff_CAVLC for IQIT to update res_AC/res_DC/... signals.
|
||||
// end_of_NonZeroCoeff_CAVLC:combinational logic,active one cycle at the end of CAVLC decoding of one non zero coefficient residual.
|
||||
// 2. March 29,2006
|
||||
// Add signal lumaDC_IsAllZero,ChromaDC_Cb_IsAllZero,ChromaDC_Cr_IsAllZero to deal with special case:zero DC coeff,but non-zero AC coeff
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module end_of_blk_decoding (reset_n,cavlc_decoder_state,
|
||||
TotalCoeff,i_TotalCoeff,end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC
|
||||
);
|
||||
input reset_n;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [4:0] TotalCoeff;
|
||||
input [3:0] i_TotalCoeff;
|
||||
output end_of_one_residual_block;
|
||||
output end_of_NonZeroCoeff_CAVLC;
|
||||
|
||||
reg end_of_one_residual_block;
|
||||
reg end_of_NonZeroCoeff_CAVLC;
|
||||
reg lumaDC_IsAllZero;
|
||||
reg ChromaDC_Cb_IsAllZero;
|
||||
reg ChromaDC_Cr_IsAllZero;
|
||||
|
||||
always @ (reset_n or cavlc_decoder_state or TotalCoeff or i_TotalCoeff)
|
||||
if (reset_n == 0)
|
||||
end_of_one_residual_block <= 0;
|
||||
else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && TotalCoeff == 0)
|
||||
end_of_one_residual_block <= 1;
|
||||
else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0)
|
||||
end_of_one_residual_block <= 1;
|
||||
else
|
||||
end_of_one_residual_block <= 0;
|
||||
|
||||
always @ (reset_n or cavlc_decoder_state or i_TotalCoeff)
|
||||
if (reset_n == 0)
|
||||
end_of_NonZeroCoeff_CAVLC <= 0;
|
||||
else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0)
|
||||
end_of_NonZeroCoeff_CAVLC <= 1;
|
||||
else
|
||||
end_of_NonZeroCoeff_CAVLC <= 0;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,152 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : exp_golomb_decoding.v
|
||||
// Generated : June 6, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Exp-Golomb code decoding
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module exp_golomb_decoding (reset_n,heading_one_pos,BitStream_buffer_output,num_ref_idx_l0_active_minus1,
|
||||
slice_header_state,slice_data_state,mb_pred_state,sub_mb_pred_state,
|
||||
seq_parameter_set_state,pic_parameter_set_state,exp_golomb_decoding_output,exp_golomb_len);
|
||||
input reset_n;
|
||||
input [3:0] heading_one_pos;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
input [2:0] num_ref_idx_l0_active_minus1;
|
||||
input [3:0] slice_header_state;
|
||||
input [3:0] slice_data_state;
|
||||
input [2:0] mb_pred_state;
|
||||
input [1:0] sub_mb_pred_state;
|
||||
input [3:0] seq_parameter_set_state;
|
||||
input [3:0] pic_parameter_set_state;
|
||||
output [7:0] exp_golomb_decoding_output;
|
||||
output [3:0] exp_golomb_len;
|
||||
|
||||
reg [7:0] exp_golomb_decoding_output;
|
||||
reg [3:0] exp_golomb_len;
|
||||
|
||||
parameter rst_exp_golomb_sel = 2'b00;
|
||||
parameter ue = 2'b01;
|
||||
parameter se = 2'b10;
|
||||
parameter te = 2'b11;
|
||||
|
||||
reg [7:0] codeNum;
|
||||
reg [1:0] exp_golomb_sel;
|
||||
|
||||
always @ (exp_golomb_sel or heading_one_pos or BitStream_buffer_output)
|
||||
if (exp_golomb_sel != rst_exp_golomb_sel)
|
||||
case (heading_one_pos)
|
||||
0:codeNum <= 0;
|
||||
1:codeNum <= {6'b0,BitStream_buffer_output[14:13]} - 1;
|
||||
2:codeNum <= {5'b0,BitStream_buffer_output[13:11]} - 1;
|
||||
3:codeNum <= {4'b0,BitStream_buffer_output[12:9]} - 1;
|
||||
4:codeNum <= {3'b0,BitStream_buffer_output[11:7]} - 1;
|
||||
5:codeNum <= {2'b0,BitStream_buffer_output[10:5]} - 1;
|
||||
6:codeNum <= {1'b0,BitStream_buffer_output[9:3]} - 1;
|
||||
7:codeNum <= BitStream_buffer_output[8:1] - 1;
|
||||
default:codeNum <= 0;
|
||||
endcase
|
||||
else
|
||||
codeNum <= 0;
|
||||
|
||||
wire [2:0] te_range;
|
||||
assign te_range = num_ref_idx_l0_active_minus1 + 1;
|
||||
always @ (exp_golomb_sel or heading_one_pos or te_range)
|
||||
case (exp_golomb_sel)
|
||||
ue,se:exp_golomb_len <= (heading_one_pos << 1) + 1;
|
||||
te :exp_golomb_len <= (te_range == 2)? 1:((heading_one_pos << 1) + 1);
|
||||
default:exp_golomb_len <= 0;
|
||||
endcase
|
||||
|
||||
wire [7:0] codeNum_se_tmp;
|
||||
assign codeNum_se_tmp = codeNum >> 1;
|
||||
always @ (exp_golomb_sel or codeNum or codeNum_se_tmp or te_range)
|
||||
case (exp_golomb_sel)
|
||||
ue:exp_golomb_decoding_output <= codeNum;
|
||||
se:
|
||||
case (codeNum[0])
|
||||
1:exp_golomb_decoding_output <= (codeNum + 1) >> 1;
|
||||
0:exp_golomb_decoding_output <= ~codeNum_se_tmp + 1;
|
||||
endcase
|
||||
te:
|
||||
if (te_range == 2) exp_golomb_decoding_output <= (codeNum == 0)? 8'd0:8'd1;
|
||||
else exp_golomb_decoding_output <= codeNum;
|
||||
default:exp_golomb_decoding_output <= 0;
|
||||
endcase
|
||||
|
||||
always @ (reset_n or slice_header_state or slice_data_state or mb_pred_state or sub_mb_pred_state or
|
||||
seq_parameter_set_state or pic_parameter_set_state)
|
||||
if (reset_n == 0)
|
||||
exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
else if (slice_header_state != `rst_slice_header)
|
||||
case (slice_header_state)
|
||||
`first_mb_in_slice_s :exp_golomb_sel <= ue;
|
||||
`slice_type_s :exp_golomb_sel <= ue;
|
||||
`pic_parameter_set_id_slice_header_s:exp_golomb_sel <= ue;
|
||||
`idr_pic_id_s :exp_golomb_sel <= ue;
|
||||
`slice_qp_delta_s :exp_golomb_sel <= se;
|
||||
`disable_deblocking_filter_idc_s :exp_golomb_sel <= ue;
|
||||
`slice_alpha_c0_offset_div2_s :exp_golomb_sel <= se;
|
||||
`slice_beta_offset_div2_s :exp_golomb_sel <= ue;
|
||||
default :exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
endcase
|
||||
else if (slice_data_state != `rst_slice_data)
|
||||
case (slice_data_state)
|
||||
`mb_skip_run_s :exp_golomb_sel <= ue;
|
||||
`mb_type_s :exp_golomb_sel <= ue;
|
||||
`sub_mb_pred:
|
||||
case (sub_mb_pred_state)
|
||||
`sub_mb_type_s :exp_golomb_sel <= ue;
|
||||
`sub_ref_idx_l0_s:exp_golomb_sel <= te;
|
||||
`sub_mvd_l0_s :exp_golomb_sel <= se;
|
||||
default :exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
endcase
|
||||
`mb_pred:
|
||||
case (mb_pred_state)
|
||||
`intra_chroma_pred_mode_s:exp_golomb_sel <= ue;
|
||||
`ref_idx_l0_s :exp_golomb_sel <= te;
|
||||
`mvd_l0_s :exp_golomb_sel <= se;
|
||||
default :exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
endcase
|
||||
`coded_block_pattern_s :exp_golomb_sel <= ue;
|
||||
`mb_qp_delta_s :exp_golomb_sel <= se;
|
||||
default :exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
endcase
|
||||
else if (seq_parameter_set_state != `rst_seq_parameter_set)
|
||||
case (seq_parameter_set_state)
|
||||
`seq_parameter_set_id_sps_s :exp_golomb_sel <= ue;
|
||||
`log2_max_frame_num_minus4_s :exp_golomb_sel <= ue;
|
||||
`pic_order_cnt_type_s :exp_golomb_sel <= ue;
|
||||
`log2_max_pic_order_cnt_lsb_minus4_s:exp_golomb_sel <= ue;
|
||||
`num_ref_frames_s :exp_golomb_sel <= ue;
|
||||
`pic_width_in_mbs_minus1_s :exp_golomb_sel <= ue;
|
||||
`pic_height_in_map_units_minus1_s :exp_golomb_sel <= ue;
|
||||
default :exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
endcase
|
||||
else if (pic_parameter_set_state != `rst_pic_parameter_set)
|
||||
case (pic_parameter_set_state)
|
||||
`pic_parameter_set_id_pps_s :exp_golomb_sel <= ue;
|
||||
`seq_parameter_set_id_pps_s :exp_golomb_sel <= ue;
|
||||
`num_slice_groups_minus1_s :exp_golomb_sel <= ue;
|
||||
`num_ref_idx_l0_active_minus1_pps_s:exp_golomb_sel <= ue;
|
||||
`num_ref_idx_l1_active_minus1_pps_s:exp_golomb_sel <= ue;
|
||||
`pic_init_qp_minus26_s :exp_golomb_sel <= se;
|
||||
`pic_init_qs_minus26_s :exp_golomb_sel <= se;
|
||||
`chroma_qp_index_offset_s :exp_golomb_sel <= se;
|
||||
default :exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
endcase
|
||||
else
|
||||
exp_golomb_sel <= rst_exp_golomb_sel;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,97 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : ext_frame_RAM1_wrapper.v
|
||||
// Generated : Nov 28,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Controller for ext_frame_RAM
|
||||
// Rread as ref_frame_RAM before Inter Prediction
|
||||
// Write as dis_frame_RAM after Deblocking Filter
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module ext_RAM_ctrl (clk,reset_n,end_of_one_frame,ref_frame_RAM_rd,ref_frame_RAM_rd_addr,dis_frame_RAM_wr,
|
||||
dis_frame_RAM_wr_addr,ref_frame_RAM_dout,
|
||||
ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
|
||||
ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data);
|
||||
input clk,reset_n;
|
||||
input end_of_one_frame;
|
||||
input ref_frame_RAM_rd;
|
||||
input [13:0] ref_frame_RAM_rd_addr;
|
||||
input dis_frame_RAM_wr;
|
||||
input [13:0] dis_frame_RAM_wr_addr;
|
||||
//input [31:0] dis_frame_RAM_din;
|
||||
input [31:0] ext_frame_RAM0_data;
|
||||
input [31:0] ext_frame_RAM1_data;
|
||||
|
||||
output [31:0] ref_frame_RAM_dout;
|
||||
|
||||
output ext_frame_RAM0_cs_n;
|
||||
output ext_frame_RAM0_wr;
|
||||
output [13:0] ext_frame_RAM0_addr;
|
||||
|
||||
output ext_frame_RAM1_cs_n;
|
||||
output ext_frame_RAM1_wr;
|
||||
output [13:0] ext_frame_RAM1_addr;
|
||||
|
||||
reg ext_frame_RAM_sel; //0:ext_frame_RAM0 as dis_frame_RAM to be written
|
||||
//0:ext_frame_RAM1 as ref_frame_RAM to be read
|
||||
//1:ext_frame_RAM0 as ref_frame_RAM to be read
|
||||
//1:ext_frame_RAM1 as dis_frame_RAM to be written
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
ext_frame_RAM_sel <= 1'b0;
|
||||
else if (end_of_one_frame)
|
||||
ext_frame_RAM_sel <= ~ ext_frame_RAM_sel;
|
||||
|
||||
reg [31:0] ref_frame_RAM_dout;
|
||||
|
||||
reg ext_frame_RAM0_cs_n;
|
||||
reg ext_frame_RAM0_wr;
|
||||
reg [13:0] ext_frame_RAM0_addr;
|
||||
|
||||
reg ext_frame_RAM1_cs_n;
|
||||
reg ext_frame_RAM1_wr;
|
||||
reg [13:0] ext_frame_RAM1_addr;
|
||||
|
||||
always @ (ext_frame_RAM_sel or
|
||||
ref_frame_RAM_rd or ref_frame_RAM_rd_addr or ext_frame_RAM0_data or ext_frame_RAM1_data or
|
||||
dis_frame_RAM_wr or dis_frame_RAM_wr_addr)
|
||||
case (ext_frame_RAM_sel)
|
||||
1'b0:
|
||||
begin
|
||||
//ext_frame_RAM0 as dis_frame_RAM to be written
|
||||
ext_frame_RAM0_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM0_wr <= dis_frame_RAM_wr;
|
||||
ext_frame_RAM0_addr <= dis_frame_RAM_wr_addr;
|
||||
|
||||
//ext_frame_RAM1 as ref_frame_RAM to be read
|
||||
ext_frame_RAM1_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM1_wr <= 1'b0;
|
||||
ext_frame_RAM1_addr <= ref_frame_RAM_rd_addr;
|
||||
|
||||
ref_frame_RAM_dout <= ext_frame_RAM1_data;
|
||||
end
|
||||
1'b1:
|
||||
begin
|
||||
//ext_frame_RAM0 as ref_frame_RAM to be read
|
||||
ext_frame_RAM0_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM0_wr <= 1'b0;
|
||||
ext_frame_RAM0_addr <= ref_frame_RAM_rd_addr;
|
||||
|
||||
//ext_frame_RAM1 as dis_frame_RAM to be written
|
||||
ext_frame_RAM1_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM1_wr <= dis_frame_RAM_wr;
|
||||
ext_frame_RAM1_addr <= dis_frame_RAM_wr_addr;
|
||||
|
||||
ref_frame_RAM_dout <= ext_frame_RAM0_data;
|
||||
end
|
||||
endcase
|
||||
//assign ext_frame_RAM0_data = (!ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz;
|
||||
//assign ext_frame_RAM1_data = ( ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz;
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,135 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : ext_frame_RAM0_wrapper.v
|
||||
// Generated : April 23,2006
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit)
|
||||
// Sync Read,Sync Write
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1.July 23,2006
|
||||
// Change the ext_frame_RAM0 from async read to sync read.
|
||||
//
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module ext_frame_RAM0_wrapper (clk,reset_n,ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,dis_frame_RAM_din,ext_frame_RAM0_data,
|
||||
pic_num,slice_header_s6);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input ext_frame_RAM0_cs_n;
|
||||
input ext_frame_RAM0_wr;
|
||||
input [13:0] ext_frame_RAM0_addr;
|
||||
input [31:0] dis_frame_RAM_din;
|
||||
input [5:0] pic_num;
|
||||
input slice_header_s6;
|
||||
output [31:0] ext_frame_RAM0_data;
|
||||
|
||||
reg [31:0] ext_frame_RAM0 [0:9503];
|
||||
reg [31:0] ext_frame_RAM0_data;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (!ext_frame_RAM0_cs_n && ext_frame_RAM0_wr)
|
||||
ext_frame_RAM0[ext_frame_RAM0_addr] <= dis_frame_RAM_din;
|
||||
|
||||
//assign ext_frame_RAM0_data = (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr)? ext_frame_RAM0[ext_frame_RAM0_addr]:32'bz;
|
||||
always @ (posedge clk)
|
||||
if (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr)
|
||||
ext_frame_RAM0_data <= ext_frame_RAM0[ext_frame_RAM0_addr];
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
integer tracefile_display;
|
||||
integer tracefile_verify;
|
||||
integer mb_num;
|
||||
integer j;
|
||||
reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3;
|
||||
reg [31:0] Cb_out0,Cb_out1;
|
||||
reg [31:0] Cr_out0,Cr_out1;
|
||||
reg [8:0] pic_num_ext;
|
||||
|
||||
parameter display = 1;
|
||||
parameter verify = 1;
|
||||
|
||||
always @ (negedge reset_n or pic_num)
|
||||
if (reset_n == 1'b0)
|
||||
pic_num_ext <= 0;
|
||||
else
|
||||
pic_num_ext <= pic_num_ext + 1;
|
||||
|
||||
|
||||
always @ (posedge clk)
|
||||
if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b1)
|
||||
begin
|
||||
if (display == 1'b1) //display
|
||||
begin
|
||||
tracefile_display = $fopen("nova_display.log","a");
|
||||
for (j= 0; j < 9504; j= j + 1)
|
||||
begin
|
||||
$fdisplay (tracefile_display,"%h",ext_frame_RAM0[j]);
|
||||
end
|
||||
$fclose(tracefile_display);
|
||||
end
|
||||
if (verify == 1'b1) //verify
|
||||
begin
|
||||
tracefile_verify = $fopen("nova_MB_output.log","a");
|
||||
for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1)
|
||||
begin
|
||||
$fdisplay (tracefile_verify,"-------------------------------------------");
|
||||
$fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num);
|
||||
$fdisplay (tracefile_verify,"-------------------------------------------");
|
||||
$fdisplay (tracefile_verify," luma 16x16 block:");
|
||||
for (j = 0; j < 16; j = j + 1)
|
||||
begin
|
||||
luma_out0 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44];
|
||||
luma_out1 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+1];
|
||||
luma_out2 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+2];
|
||||
luma_out3 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+3];
|
||||
|
||||
$fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H",
|
||||
luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24],
|
||||
luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24],
|
||||
luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24],
|
||||
luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]);
|
||||
|
||||
if (j == 3 || j == 7 || j == 11)
|
||||
$fdisplay (tracefile_verify, "");
|
||||
end
|
||||
$fdisplay (tracefile_verify," Chroma Cb 8x8 block:");
|
||||
for (j = 0; j < 8; j = j + 1)
|
||||
begin
|
||||
Cb_out0 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22];
|
||||
Cb_out1 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1];
|
||||
|
||||
$fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H",
|
||||
Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24],
|
||||
Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]);
|
||||
if (j == 3)
|
||||
$fdisplay (tracefile_verify, "");
|
||||
end
|
||||
$fdisplay (tracefile_verify," Chroma Cr 8x8 block:");
|
||||
for (j = 0; j < 8; j = j + 1)
|
||||
begin
|
||||
Cr_out0 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22];
|
||||
Cr_out1 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1];
|
||||
|
||||
$fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H",
|
||||
Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24],
|
||||
Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]);
|
||||
if (j == 3)
|
||||
$fdisplay (tracefile_verify, "");
|
||||
end
|
||||
end
|
||||
$fclose(tracefile_verify);
|
||||
end
|
||||
end
|
||||
// synopsys translate_on
|
||||
endmodule
|
||||
@@ -0,0 +1,134 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : ext_frame_RAM1_wrapper.v
|
||||
// Generated : April 23,2006
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit)
|
||||
// Sync Read,Sync Write
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1.July 23,2006
|
||||
// Change the ext_frame_RAM1 from async read to sync read.
|
||||
//
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module ext_frame_RAM1_wrapper (clk,reset_n,ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,dis_frame_RAM_din,ext_frame_RAM1_data,
|
||||
pic_num,slice_header_s6);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input ext_frame_RAM1_cs_n;
|
||||
input ext_frame_RAM1_wr;
|
||||
input [13:0] ext_frame_RAM1_addr;
|
||||
input [31:0] dis_frame_RAM_din;
|
||||
input [5:0] pic_num;
|
||||
input slice_header_s6;
|
||||
output [31:0] ext_frame_RAM1_data;
|
||||
|
||||
reg [31:0] ext_frame_RAM1 [0:9503];
|
||||
reg [31:0] ext_frame_RAM1_data;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (!ext_frame_RAM1_cs_n && ext_frame_RAM1_wr)
|
||||
ext_frame_RAM1[ext_frame_RAM1_addr] <= dis_frame_RAM_din;
|
||||
|
||||
//assign ext_frame_RAM1_data = (!ext_frame_RAM1_cs_n && !ext_frame_RAM1_wr)? ext_frame_RAM1[ext_frame_RAM1_addr]:32'bz;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (!ext_frame_RAM1_cs_n && !ext_frame_RAM1_wr)
|
||||
ext_frame_RAM1_data <= ext_frame_RAM1[ext_frame_RAM1_addr];
|
||||
|
||||
// synopsys translate_off
|
||||
integer tracefile_display;
|
||||
integer tracefile_verify;
|
||||
integer mb_num;
|
||||
integer j;
|
||||
reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3;
|
||||
reg [31:0] Cb_out0,Cb_out1;
|
||||
reg [31:0] Cr_out0,Cr_out1;
|
||||
reg [8:0] pic_num_ext;
|
||||
|
||||
parameter display = 1;
|
||||
parameter verify = 1;
|
||||
|
||||
always @ (negedge reset_n or pic_num)
|
||||
if (reset_n == 1'b0)
|
||||
pic_num_ext <= 0;
|
||||
else
|
||||
pic_num_ext <= pic_num_ext + 1;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b0 && pic_num_ext != 0)
|
||||
begin
|
||||
if (display == 1'b1) //display
|
||||
begin
|
||||
tracefile_display = $fopen("nova_display.log","a");
|
||||
for (j= 0; j < 9504; j= j + 1)
|
||||
begin
|
||||
$fdisplay (tracefile_display,"%h",ext_frame_RAM1[j]);
|
||||
end
|
||||
$fclose(tracefile_display);
|
||||
end
|
||||
if (verify == 1'b1) //verify
|
||||
begin
|
||||
tracefile_verify = $fopen("nova_MB_output.log","a");
|
||||
for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1)
|
||||
begin
|
||||
$fdisplay (tracefile_verify,"-------------------------------------------");
|
||||
$fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num);
|
||||
$fdisplay (tracefile_verify,"-------------------------------------------");
|
||||
$fdisplay (tracefile_verify," luma 16x16 block:");
|
||||
for (j = 0; j < 16; j = j + 1)
|
||||
begin
|
||||
luma_out0 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44];
|
||||
luma_out1 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+1];
|
||||
luma_out2 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+2];
|
||||
luma_out3 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+3];
|
||||
|
||||
$fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H",
|
||||
luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24],
|
||||
luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24],
|
||||
luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24],
|
||||
luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]);
|
||||
|
||||
if (j == 3 || j == 7 || j == 11)
|
||||
$fdisplay (tracefile_verify, "");
|
||||
end
|
||||
$fdisplay (tracefile_verify," Chroma Cb 8x8 block:");
|
||||
for (j = 0; j < 8; j = j + 1)
|
||||
begin
|
||||
Cb_out0 = ext_frame_RAM1[6336+(mb_num/11)*176+(mb_num%11)*2+j*22];
|
||||
Cb_out1 = ext_frame_RAM1[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1];
|
||||
|
||||
$fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H",
|
||||
Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24],
|
||||
Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]);
|
||||
if (j == 3)
|
||||
$fdisplay (tracefile_verify, "");
|
||||
end
|
||||
$fdisplay (tracefile_verify," Chroma Cr 8x8 block:");
|
||||
for (j = 0; j < 8; j = j + 1)
|
||||
begin
|
||||
Cr_out0 = ext_frame_RAM1[7920+(mb_num/11)*176+(mb_num%11)*2+j*22];
|
||||
Cr_out1 = ext_frame_RAM1[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1];
|
||||
|
||||
$fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H",
|
||||
Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24],
|
||||
Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]);
|
||||
if (j == 3)
|
||||
$fdisplay (tracefile_verify, "");
|
||||
end
|
||||
end
|
||||
$fclose(tracefile_verify);
|
||||
end
|
||||
end
|
||||
// synopsys translate_on
|
||||
endmodule
|
||||
@@ -0,0 +1,60 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : heading_one_detector.v
|
||||
// Generated : June 6, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Priority based heading one detection
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module heading_one_detector (heading_one_en,BitStream_buffer_output,heading_one_pos);
|
||||
input heading_one_en;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
output [3:0] heading_one_pos;
|
||||
reg [3:0] heading_one_pos;
|
||||
|
||||
always @ (heading_one_en or BitStream_buffer_output)
|
||||
if (heading_one_en == 1'b0)
|
||||
begin
|
||||
if (BitStream_buffer_output[15] == 1'b1 || BitStream_buffer_output[14] == 1'b1)
|
||||
begin
|
||||
if (BitStream_buffer_output[15] == 1'b1) heading_one_pos <= 0;
|
||||
else heading_one_pos <= 4'd1;
|
||||
end
|
||||
else if (BitStream_buffer_output[13] == 1'b1 || BitStream_buffer_output[12] == 1'b1 ||
|
||||
BitStream_buffer_output[11] == 1'b1 || BitStream_buffer_output[10] == 1'b1)
|
||||
begin
|
||||
if (BitStream_buffer_output[13] == 1'b1) heading_one_pos <= 4'd2;
|
||||
else if (BitStream_buffer_output[12] == 1'b1) heading_one_pos <= 4'd3;
|
||||
else if (BitStream_buffer_output[11] == 1'b1) heading_one_pos <= 4'd4;
|
||||
else heading_one_pos <= 4'd5;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (BitStream_buffer_output[9] == 1'b1) heading_one_pos <= 4'd6;
|
||||
else if (BitStream_buffer_output[8] == 1'b1) heading_one_pos <= 4'd7;
|
||||
else if (BitStream_buffer_output[7] == 1'b1) heading_one_pos <= 4'd8;
|
||||
else if (BitStream_buffer_output[6] == 1'b1) heading_one_pos <= 4'd9;
|
||||
else if (BitStream_buffer_output[5] == 1'b1) heading_one_pos <= 4'd10;
|
||||
else if (BitStream_buffer_output[4] == 1'b1) heading_one_pos <= 4'd11;
|
||||
else if (BitStream_buffer_output[3] == 1'b1) heading_one_pos <= 4'd12;
|
||||
else if (BitStream_buffer_output[2] == 1'b1) heading_one_pos <= 4'd13;
|
||||
else if (BitStream_buffer_output[1] == 1'b1) heading_one_pos <= 4'd14;
|
||||
else heading_one_pos <= 4'd15;
|
||||
end
|
||||
end
|
||||
else
|
||||
heading_one_pos <= 0;
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,265 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : hybrid_pipeline_ctrl.v
|
||||
// Generated : Sept 5, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Control 4x4 block level pipeline for reconstruction
|
||||
// Receive the 1cycle end_of_xxx signal(combinational)
|
||||
// Generated the 1cycle trigger_xxx signal
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Revise log
|
||||
// 1.April 11,2006
|
||||
// Modify the 1cycle trigger_xxx signal from registers to combinational logic to save decoding clock cycles
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module hybrid_pipeline_ctrl (clk,reset_n,mb_num_h,mb_num_v,blk4x4_rec_counter,CodedBlockPatternLuma,CodedBlockPatternChroma,
|
||||
mb_type_general,slice_data_state,residual_state,TotalCoeff,Is_skip_run_entry,skip_mv_calc,
|
||||
end_of_one_residual_block,end_of_DCBlk_IQIT,end_of_ACBlk4x4_IQIT,end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,
|
||||
end_of_one_blk4x4_sum,end_of_MB_DF,disable_DF,
|
||||
|
||||
curr_CBPLuma_IsZero,end_of_MB_DEC,trigger_CAVLC,trigger_blk4x4_intra_pred,
|
||||
trigger_blk4x4_inter_pred,trigger_blk4x4_rec_sum);
|
||||
input clk,reset_n;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input [3:0] CodedBlockPatternLuma;
|
||||
input [1:0] CodedBlockPatternChroma;
|
||||
input [3:0] mb_type_general;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] residual_state;
|
||||
input [4:0] TotalCoeff;
|
||||
input Is_skip_run_entry;
|
||||
input skip_mv_calc;
|
||||
input end_of_one_residual_block;
|
||||
input end_of_DCBlk_IQIT;
|
||||
input end_of_ACBlk4x4_IQIT;
|
||||
input end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,end_of_one_blk4x4_sum;
|
||||
input end_of_MB_DF;
|
||||
input disable_DF;
|
||||
|
||||
output curr_CBPLuma_IsZero;
|
||||
output end_of_MB_DEC;
|
||||
output trigger_CAVLC;
|
||||
output trigger_blk4x4_intra_pred,trigger_blk4x4_inter_pred;
|
||||
output trigger_blk4x4_rec_sum;
|
||||
|
||||
//change trigger_blk4x4_intra_pred from combination to reg
|
||||
reg trigger_CAVLC; //combination
|
||||
reg trigger_blk4x4_intra_pred; //reg
|
||||
reg trigger_blk4x4_inter_pred; //reg
|
||||
reg trigger_blk4x4_rec_sum; //combination
|
||||
|
||||
//CBPLuma only make sense for residual_state == LumaLevel_s
|
||||
//CBPLuma is derived to help judge whether res_blk4x4_IsAllZero caused by CodedBlockPattern != 4'b1111
|
||||
reg curr_CBPLuma_IsZero;
|
||||
always @ (blk4x4_rec_counter or CodedBlockPatternLuma)
|
||||
if (blk4x4_rec_counter < 16)
|
||||
case (blk4x4_rec_counter[3:2])
|
||||
2'b00:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[0];
|
||||
2'b01:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[1];
|
||||
2'b10:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[2];
|
||||
2'b11:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[3];
|
||||
endcase
|
||||
else
|
||||
curr_CBPLuma_IsZero <= 0;
|
||||
//---------------------------------------------------------------------------------
|
||||
//signals to trigger:
|
||||
// 1.4x4 blk CAVLC
|
||||
// 2.4x4 Intra Prediction
|
||||
// 3.4x4 Inter Prediction
|
||||
// 4.4x4 reconstruction sum
|
||||
// 5.16x16 deblocking filter
|
||||
// All the trigger_xxx signals are generated by sequential logic
|
||||
//---------------------------------------------------------------------------------
|
||||
|
||||
//1. trigger_CAVLC: when reconstruction is dealing with skip_run or zero residual (construction
|
||||
// only from inter/intra prediction) blocks,CAVLC decoder,as well as whole bitstream parsing FSM,
|
||||
// needs to be stalled and wait until the reconstruction process of previous
|
||||
|
||||
always @ (slice_data_state or residual_state or mb_type_general[3:2] or CodedBlockPatternLuma
|
||||
or CodedBlockPatternChroma or end_of_one_residual_block or end_of_DCBlk_IQIT or end_of_one_blk4x4_sum
|
||||
or blk4x4_rec_counter or TotalCoeff or curr_CBPLuma_IsZero)
|
||||
// Entry
|
||||
if (slice_data_state == `residual && residual_state == `rst_residual)
|
||||
begin
|
||||
if (mb_type_general[3:2] == 2'b10) //Intra16x16:first block must be DC
|
||||
trigger_CAVLC <= 1'b1;
|
||||
else if (CodedBlockPatternLuma[0] == 1'b0) //First 8x8 block has no residuals
|
||||
trigger_CAVLC <= 1'b0;
|
||||
else //normal case
|
||||
trigger_CAVLC <= 1'b1;
|
||||
end
|
||||
// End of one DC
|
||||
else if ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
|
||||
residual_state == `ChromaDCLevel_Cr_s) && ((end_of_one_residual_block && TotalCoeff == 0)|| end_of_DCBlk_IQIT))
|
||||
case (residual_state)
|
||||
`Intra16x16DCLevel_s: //end of luma DC
|
||||
trigger_CAVLC <= (CodedBlockPatternLuma[0] == 1'b0)? 1'b0:1'b1;
|
||||
`ChromaDCLevel_Cb_s: //end of chroma DC Cb,trigger chroma DC Cr now!
|
||||
trigger_CAVLC <= 1'b1;
|
||||
`ChromaDCLevel_Cr_s: //end of chroma DC Cr
|
||||
trigger_CAVLC <= (CodedBlockPatternChroma == 2'b01)? 1'b0:1'b1;
|
||||
default:trigger_CAVLC <= 1'b0;
|
||||
endcase
|
||||
// End of skip or normal
|
||||
else if (end_of_one_blk4x4_sum)
|
||||
begin
|
||||
if (slice_data_state == `skip_run_duration)
|
||||
trigger_CAVLC <= 1'b0;
|
||||
else
|
||||
case (blk4x4_rec_counter)
|
||||
0,1,2,4,5,6,8,9,10,12,13,14:trigger_CAVLC <= (curr_CBPLuma_IsZero)? 1'b0:1'b1;
|
||||
3 :trigger_CAVLC <= (CodedBlockPatternLuma[1])? 1'b1:1'b0;
|
||||
7 :trigger_CAVLC <= (CodedBlockPatternLuma[2])? 1'b1:1'b0;
|
||||
11:trigger_CAVLC <= (CodedBlockPatternLuma[3])? 1'b1:1'b0;
|
||||
15:trigger_CAVLC <= (CodedBlockPatternChroma == 0)? 1'b0:1'b1;
|
||||
23:trigger_CAVLC <= 1'b0;
|
||||
default:trigger_CAVLC <= (CodedBlockPatternChroma == 2)? 1'b1:1'b0;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
trigger_CAVLC <= 1'b0;
|
||||
|
||||
//end_of_MB_rec:end of one MB reconstruction
|
||||
wire end_of_MB_rec;
|
||||
assign end_of_MB_rec = (blk4x4_rec_counter == 5'd23 && end_of_one_blk4x4_sum == 1'b1)? 1'b1:1'b0;
|
||||
|
||||
//MB_needs_DF: identify whether this MB needs to be deblocking filtered
|
||||
reg MB_needs_DF;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
MB_needs_DF <= 1'b0;
|
||||
else if (end_of_MB_DEC == 1'b1 && !disable_DF)
|
||||
MB_needs_DF <= 1'b1;
|
||||
else if (end_of_MB_DEC == 1'b1 && disable_DF)
|
||||
MB_needs_DF <= 1'b0;
|
||||
//MB_rec_DF_align:latch the first arrival of end_of_MB_rec and end_of_MB_DF
|
||||
reg MB_rec_DF_align;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
MB_rec_DF_align <= 1'b0;
|
||||
else if (end_of_MB_DEC)
|
||||
MB_rec_DF_align <= 1'b0;
|
||||
else if (MB_needs_DF && (end_of_MB_rec || end_of_MB_DF == 1'b1))
|
||||
MB_rec_DF_align <= 1'b1;
|
||||
|
||||
|
||||
//end_of_MB_DEC:end of one macroblock decoding (end of both reconstruction and previous MB's deblocking
|
||||
// (if previous MB needs deblocking)),generated by combinational logic
|
||||
reg end_of_MB_DEC;
|
||||
always @ (MB_needs_DF or end_of_MB_rec or end_of_MB_DF or MB_rec_DF_align or mb_num_h or mb_num_v)
|
||||
if (MB_needs_DF == 1'b1)
|
||||
begin
|
||||
if (end_of_MB_rec && end_of_MB_DF) //arrive simultaneously
|
||||
end_of_MB_DEC <= 1'b1;
|
||||
else if (MB_rec_DF_align == 1'b1 && (end_of_MB_rec || end_of_MB_DF))
|
||||
end_of_MB_DEC <= 1'b1;
|
||||
else if (mb_num_h == 0 && mb_num_v == 0 && end_of_MB_rec)//first MB has no correspinding DF process
|
||||
end_of_MB_DEC <= 1'b1;
|
||||
else
|
||||
end_of_MB_DEC <= 1'b0;
|
||||
end
|
||||
else
|
||||
end_of_MB_DEC <= (end_of_MB_rec)? 1'b1:1'b0;
|
||||
|
||||
//2. trigger_blk4x4_intra_pred
|
||||
wire trigger_blk4x4_intra_pred_tmp;
|
||||
assign trigger_blk4x4_intra_pred_tmp = (mb_type_general[3] && ((slice_data_state == `residual &&
|
||||
residual_state == `rst_residual) || (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)))? 1'b1:1'b0;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
trigger_blk4x4_intra_pred <= 1'b0;
|
||||
else
|
||||
trigger_blk4x4_intra_pred <= trigger_blk4x4_intra_pred_tmp;
|
||||
|
||||
//3. trigger_blk4x4_inter_pred
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
trigger_blk4x4_inter_pred <= 1'b0;
|
||||
//For skip_run_duration
|
||||
// 1.trigger inter pred when entering skip_run_duration after mb_skip_run_s state
|
||||
else if (Is_skip_run_entry)
|
||||
trigger_blk4x4_inter_pred <= 1'b1;
|
||||
// 2.trigger inter pred during skip_run_duration
|
||||
else if (slice_data_state == `skip_run_duration)
|
||||
begin
|
||||
if (skip_mv_calc)
|
||||
trigger_blk4x4_inter_pred <= 1'b1;
|
||||
else
|
||||
trigger_blk4x4_inter_pred <= (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)? 1'b1:1'b0;
|
||||
end
|
||||
//For normal case:inside residual_state
|
||||
// 1.entry
|
||||
else if (slice_data_state == `residual && residual_state == `rst_residual && !mb_type_general[3])
|
||||
trigger_blk4x4_inter_pred <= 1'b1;
|
||||
// 2.end of normal
|
||||
else if (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23 && !mb_type_general[3])
|
||||
trigger_blk4x4_inter_pred <= 1'b1;
|
||||
else
|
||||
trigger_blk4x4_inter_pred <= 1'b0;
|
||||
|
||||
//4. trigger reconstruction sum
|
||||
// Need to align the output of residual(IQIT) and predition(inter/intra)
|
||||
wire end_of_one_blk4x4_pred;
|
||||
wire end_of_one_blk4x4_res; //end of one zero or non-zero AC blk4x4 IQIT (NOT DC!)
|
||||
reg blk4x4_res_pred_align;
|
||||
|
||||
assign end_of_one_blk4x4_pred = (end_of_one_blk4x4_inter || end_of_one_blk4x4_intra);
|
||||
assign end_of_one_blk4x4_res = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
|
||||
residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) &&
|
||||
(end_of_one_residual_block && TotalCoeff == 0)) || end_of_ACBlk4x4_IQIT)? 1'b1:1'b0;
|
||||
|
||||
//align the completion of prediction and residual decoding
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_res_pred_align <= 0;
|
||||
else if (trigger_blk4x4_rec_sum == 1'b1)
|
||||
blk4x4_res_pred_align <= 1'b0;
|
||||
else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously,no align
|
||||
blk4x4_res_pred_align <= 1'b0;
|
||||
else if (end_of_one_blk4x4_res || end_of_one_blk4x4_pred)
|
||||
blk4x4_res_pred_align <= 1'b1;
|
||||
|
||||
|
||||
always @ (slice_data_state or residual_state or curr_CBPLuma_IsZero or blk4x4_res_pred_align or
|
||||
end_of_one_blk4x4_pred or end_of_one_blk4x4_res)
|
||||
if (slice_data_state == `skip_run_duration)
|
||||
trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred)? 1'b1:1'b0;
|
||||
// Normal
|
||||
else if (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
|
||||
residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)
|
||||
begin
|
||||
if (curr_CBPLuma_IsZero)
|
||||
trigger_blk4x4_rec_sum <= (blk4x4_res_pred_align)? 1'b1:end_of_one_blk4x4_pred;
|
||||
else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously
|
||||
trigger_blk4x4_rec_sum <= 1'b1;
|
||||
else if ((end_of_one_blk4x4_res || end_of_one_blk4x4_pred) && blk4x4_res_pred_align)
|
||||
trigger_blk4x4_rec_sum <= 1'b1;
|
||||
else
|
||||
trigger_blk4x4_rec_sum <= 1'b0;
|
||||
end
|
||||
// zero blocks
|
||||
else if (residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_0_s
|
||||
|| residual_state == `ChromaACLevel_0_s)
|
||||
trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred || blk4x4_res_pred_align)? 1'b1:1'b0;
|
||||
else
|
||||
trigger_blk4x4_rec_sum <= 1'b0;
|
||||
|
||||
//5.trigger Deblocking Filter
|
||||
//assign trigger_MB_DF = (end_of_MB_DEC == 1'b1 && !disable_DF)? 1'b1:1'b0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,206 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : level_decoding.v
|
||||
// Generated : June 9, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Devive the level_prefix,level_suffix,suffixLength,levelSuffixSize,levelCode
|
||||
// In systemC,levelSuffixSize is decoded @LevelPrefix,in RTL,now changed to @LevelSuffix
|
||||
// level_suffix[7:0],levelCode[7:0],level[8:0]
|
||||
// 1. level_abs_tmp[8:0]:|levelCode+2| or |-levelCode-1| | reg
|
||||
// 2. level_abs [7:0]:level_abs_tmp >> 1 and latched, used for suffixLength calculation | wire
|
||||
// 3. level_tmp [8:0]:2's complement, equals (levelCode+2)>>1 or (-levelCode-1)>>1 | wire
|
||||
// 4. level_0 ~ level_15:According to i_level,level_tmp is assigned to level_[i_level] | reg
|
||||
// level_0 ~ level_15 are 2's complement
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module level_decoding (clk,reset_n,cavlc_decoder_state,heading_one_pos,suffix_length_initialized,i_level,
|
||||
TotalCoeff,TrailingOnes,BitStream_buffer_output,
|
||||
levelSuffixSize,
|
||||
level_0,level_1,level_2, level_3, level_4, level_5, level_6, level_7,
|
||||
level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15);
|
||||
input clk,reset_n;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [3:0] heading_one_pos;
|
||||
input suffix_length_initialized;
|
||||
input [3:0] i_level;
|
||||
input [4:0] TotalCoeff;
|
||||
input [1:0] TrailingOnes;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
output [3:0] levelSuffixSize;
|
||||
output [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7;
|
||||
output [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15;
|
||||
|
||||
reg [3:0] levelSuffixSize;
|
||||
reg [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7;
|
||||
reg [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15;
|
||||
|
||||
reg [3:0] level_prefix;
|
||||
reg [3:0] suffixLength;
|
||||
reg [11:0] level_suffix;
|
||||
reg [8:0] levelCode;
|
||||
reg [8:0] level_tmp;
|
||||
reg [7:0] level_abs;
|
||||
|
||||
wire [8:0] levelCode_tmp;
|
||||
|
||||
//@LevelPrefix,latch the result
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
level_prefix <= 0;
|
||||
else if (cavlc_decoder_state == `LevelPrefix)
|
||||
level_prefix <= heading_one_pos;
|
||||
//@LevelPrefix,latch the result
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
suffixLength <= 0;
|
||||
else if (cavlc_decoder_state == `LevelPrefix)
|
||||
begin
|
||||
if (suffix_length_initialized == 1'b0)
|
||||
suffixLength <= (TotalCoeff > 10 && TrailingOnes < 3)? 4'd1:4'd0;
|
||||
//Revise log:March 26,2006
|
||||
//else if (suffixLength == 0 && ((level_abs > (8'd3 << (suffixLength - 1))) && suffixLength < 6))
|
||||
else if (suffixLength == 0 && level_abs > 8'd3)
|
||||
suffixLength <= 4'd2;
|
||||
else if (suffixLength == 0)
|
||||
suffixLength <= 4'd1;
|
||||
else if ((level_abs > (8'd3 << (suffixLength - 1))) && suffixLength < 6)
|
||||
suffixLength <= suffixLength + 1;
|
||||
end
|
||||
//@LevelSuffix,temporary result
|
||||
always @ (cavlc_decoder_state or level_prefix or suffixLength)
|
||||
if (cavlc_decoder_state == `LevelSuffix)
|
||||
begin
|
||||
if (level_prefix == 14 && suffixLength == 0)
|
||||
levelSuffixSize <= 4;
|
||||
else if (level_prefix == 4'd15)
|
||||
levelSuffixSize <= 4'd12;
|
||||
else
|
||||
levelSuffixSize <= suffixLength;
|
||||
end
|
||||
else
|
||||
levelSuffixSize <= 0;
|
||||
//@LevelSuffix,temporay result
|
||||
always @ (cavlc_decoder_state or levelSuffixSize or BitStream_buffer_output)
|
||||
if (cavlc_decoder_state == `LevelSuffix)
|
||||
begin
|
||||
if (levelSuffixSize == 0)
|
||||
level_suffix <= 0;
|
||||
else
|
||||
case (levelSuffixSize)
|
||||
1 :level_suffix <= {11'b0,BitStream_buffer_output[15]};
|
||||
2 :level_suffix <= {10'b0,BitStream_buffer_output[15:14]};
|
||||
3 :level_suffix <= {9'b0,BitStream_buffer_output[15:13]};
|
||||
4 :level_suffix <= {8'b0,BitStream_buffer_output[15:12]};
|
||||
5 :level_suffix <= {7'b0,BitStream_buffer_output[15:11]};
|
||||
6 :level_suffix <= {6'b0,BitStream_buffer_output[15:10]};
|
||||
7 :level_suffix <= {5'b0,BitStream_buffer_output[15:9]};
|
||||
8 :level_suffix <= {4'b0,BitStream_buffer_output[15:8]};
|
||||
9 :level_suffix <= {3'b0,BitStream_buffer_output[15:7]};
|
||||
10:level_suffix <= {2'b0,BitStream_buffer_output[15:6]};
|
||||
11:level_suffix <= {1'b0,BitStream_buffer_output[15:5]};
|
||||
12:level_suffix <= BitStream_buffer_output[15:4];
|
||||
default:level_suffix <= 0;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
level_suffix <= 0;
|
||||
|
||||
assign levelCode_tmp = (cavlc_decoder_state == `LevelSuffix)? ((level_prefix << suffixLength) + level_suffix):0;
|
||||
|
||||
always @ (cavlc_decoder_state or level_prefix or suffixLength or i_level or TrailingOnes or levelCode_tmp)
|
||||
if (cavlc_decoder_state == `LevelSuffix)
|
||||
begin
|
||||
if (level_prefix == 15 && suffixLength == 0 && i_level == {2'b0,TrailingOnes} && TrailingOnes < 3)
|
||||
levelCode <= levelCode_tmp + 17;
|
||||
else if (level_prefix == 15 && suffixLength == 0)
|
||||
levelCode <= levelCode_tmp + 15;
|
||||
else if (i_level == {2'b0,TrailingOnes} && TrailingOnes < 3)
|
||||
levelCode <= levelCode_tmp + 2;
|
||||
else
|
||||
levelCode <= levelCode_tmp;
|
||||
end
|
||||
else
|
||||
levelCode <= 0;
|
||||
//We need an additional "level_abs" signal here in order to upgrade suffixLength for next codeword,but for
|
||||
//trailingones,no need to do so since abs(+1/-1) will never greater than (3<<(suffixLength-1)).
|
||||
|
||||
//level_abs_tmp:absolute value of level
|
||||
reg [8:0] level_abs_tmp;
|
||||
always @ (cavlc_decoder_state or levelCode)
|
||||
if (cavlc_decoder_state == `LevelSuffix)
|
||||
begin
|
||||
if (levelCode[0] == 1'b0) //even
|
||||
level_abs_tmp <= levelCode + 2;
|
||||
else
|
||||
level_abs_tmp <= levelCode + 1;
|
||||
end
|
||||
else
|
||||
level_abs_tmp <= 0;
|
||||
|
||||
//level_abs:latched absolute value of level,for upgrading of suffixLength
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
level_abs <= 0;
|
||||
else if (cavlc_decoder_state == `LevelSuffix)
|
||||
level_abs <= level_abs_tmp[8:1];
|
||||
|
||||
always @ (cavlc_decoder_state or levelCode or level_abs_tmp)
|
||||
if (cavlc_decoder_state == `LevelSuffix)
|
||||
begin
|
||||
if (levelCode[0] == 1'b0) //even
|
||||
level_tmp <= {1'b0,level_abs_tmp[8:1]};
|
||||
else
|
||||
level_tmp <= {1'b1,~levelCode[8:1]};
|
||||
end
|
||||
else
|
||||
level_tmp <= 0;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
level_0 <= 0; level_1 <= 0; level_2 <= 0; level_3 <= 0;
|
||||
level_4 <= 0; level_5 <= 0; level_6 <= 0; level_7 <= 0;
|
||||
level_8 <= 0; level_9 <= 0; level_10<= 0; level_11<= 0;
|
||||
level_12<= 0; level_13<= 0; level_14<= 0; level_15<= 0;
|
||||
end
|
||||
else if (cavlc_decoder_state == `TrailingOnesSignFlag)
|
||||
begin
|
||||
level_0 <= (BitStream_buffer_output[15] == 0)? 9'b000000001:9'b111111111;
|
||||
if (TrailingOnes > 1)
|
||||
level_1 <= (BitStream_buffer_output[14] == 0)? 9'b000000001:9'b111111111;
|
||||
if (TrailingOnes == 3)
|
||||
level_2 <= (BitStream_buffer_output[13] == 0)? 9'b000000001:9'b111111111;
|
||||
end
|
||||
else if (cavlc_decoder_state == `LevelSuffix)
|
||||
case (i_level)
|
||||
0 :level_0 <= level_tmp;
|
||||
1 :level_1 <= level_tmp;
|
||||
2 :level_2 <= level_tmp;
|
||||
3 :level_3 <= level_tmp;
|
||||
4 :level_4 <= level_tmp;
|
||||
5 :level_5 <= level_tmp;
|
||||
6 :level_6 <= level_tmp;
|
||||
7 :level_7 <= level_tmp;
|
||||
8 :level_8 <= level_tmp;
|
||||
9 :level_9 <= level_tmp;
|
||||
10:level_10<= level_tmp;
|
||||
11:level_11<= level_tmp;
|
||||
12:level_12<= level_tmp;
|
||||
13:level_13<= level_tmp;
|
||||
14:level_14<= level_tmp;
|
||||
15:level_15<= level_tmp;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,761 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : nC_decoding.v
|
||||
// Generated : May 18, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Devive the number of none-zero coeff during nC decoding for TotalCoeff & TrailingOnes LUT
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module nC_decoding (clk,reset_n,gclk_end_of_MB_DEC,
|
||||
cavlc_decoder_state,residual_state,slice_data_state,
|
||||
mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr,CodedBlockPatternLuma,CodedBlockPatternChroma,
|
||||
LumaLevel_mbAddrB_dout,ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout,
|
||||
end_of_one_residual_block,TotalCoeff,
|
||||
|
||||
nC,
|
||||
Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA,
|
||||
LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3,
|
||||
LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n,LumaLevel_mbAddrB_rd_addr,
|
||||
LumaLevel_mbAddrB_wr_addr,LumaLevel_mbAddrB_din,
|
||||
ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n,ChromaLevel_Cb_mbAddrB_rd_addr,
|
||||
ChromaLevel_Cb_mbAddrB_wr_addr,ChromaLevel_Cb_mbAddrB_din,
|
||||
ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n,ChromaLevel_Cr_mbAddrB_rd_addr,
|
||||
ChromaLevel_Cr_mbAddrB_wr_addr,ChromaLevel_Cr_mbAddrB_din);
|
||||
|
||||
input clk,reset_n;
|
||||
input gclk_end_of_MB_DEC;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input [1:0] i8x8,i4x4;
|
||||
input [1:0] i4x4_CbCr;
|
||||
input [3:0] CodedBlockPatternLuma;
|
||||
input [1:0] CodedBlockPatternChroma;
|
||||
input [19:0] LumaLevel_mbAddrB_dout;
|
||||
input [9:0] ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout;
|
||||
input end_of_one_residual_block;
|
||||
input [4:0] TotalCoeff;
|
||||
|
||||
output [4:0] nC;
|
||||
output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA;
|
||||
output [19:0] LumaLevel_mbAddrA;
|
||||
output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
|
||||
output LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n;
|
||||
output [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr;
|
||||
output [19:0]LumaLevel_mbAddrB_din;
|
||||
output ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n;
|
||||
output [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr;
|
||||
output [9:0] ChromaLevel_Cb_mbAddrB_din;
|
||||
output ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n;
|
||||
output [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr;
|
||||
output [9:0] ChromaLevel_Cr_mbAddrB_din;
|
||||
|
||||
reg [4:0] nC;
|
||||
reg LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n;
|
||||
reg [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr;
|
||||
reg [19:0]LumaLevel_mbAddrB_din;
|
||||
reg ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n;
|
||||
reg [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr;
|
||||
reg [9:0] ChromaLevel_Cb_mbAddrB_din;
|
||||
reg ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n;
|
||||
reg [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr;
|
||||
reg [9:0] ChromaLevel_Cr_mbAddrB_din;
|
||||
|
||||
reg nA_availability,nB_availability;
|
||||
reg nA_availability_reg,nB_availability_reg;
|
||||
reg [4:0] nA,nB;
|
||||
reg [19:0] LumaLevel_mbAddrA;
|
||||
reg [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
|
||||
reg [19:0] ChromaLevel_Cb_CurrMb;
|
||||
reg [9:0] ChromaLevel_Cb_mbAddrA;
|
||||
reg [19:0] ChromaLevel_Cr_CurrMb;
|
||||
reg [9:0] ChromaLevel_Cr_mbAddrA;
|
||||
reg [1:0] Luma_8x8_AllZeroCoeff_mbAddrA;
|
||||
reg [0:21] Luma_8x8_AllZeroCoeff_mbAddrB_reg;
|
||||
reg [0:1] Luma_8x8_AllZeroCoeff_mbAddrB;
|
||||
reg Chroma_8x8_AllZeroCoeff_mbAddrA;
|
||||
reg [10:0] Chroma_8x8_AllZeroCoeff_mbAddrB_reg;
|
||||
reg Chroma_8x8_AllZeroCoeff_mbAddrB;
|
||||
|
||||
always @ (mb_num_h or Luma_8x8_AllZeroCoeff_mbAddrB_reg)
|
||||
case (mb_num_h)
|
||||
0 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1];
|
||||
1 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3];
|
||||
2 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5];
|
||||
3 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7];
|
||||
4 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9];
|
||||
5 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11];
|
||||
6 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13];
|
||||
7 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15];
|
||||
8 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17];
|
||||
9 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19];
|
||||
10:Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21];
|
||||
default:Luma_8x8_AllZeroCoeff_mbAddrB <= 0;
|
||||
endcase
|
||||
always @ (mb_num_h or Chroma_8x8_AllZeroCoeff_mbAddrB_reg)
|
||||
case (mb_num_h)
|
||||
0 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0];
|
||||
1 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1];
|
||||
2 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2];
|
||||
3 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3];
|
||||
4 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4];
|
||||
5 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5];
|
||||
6 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6];
|
||||
7 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7];
|
||||
8 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8];
|
||||
9 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9];
|
||||
10:Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10];
|
||||
default:Chroma_8x8_AllZeroCoeff_mbAddrB <= 0;
|
||||
endcase
|
||||
//----------------------------
|
||||
//Update 8x8_AllZero registers
|
||||
//----------------------------
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
Luma_8x8_AllZeroCoeff_mbAddrA <= 0;
|
||||
else if (slice_data_state == `skip_run_duration)
|
||||
Luma_8x8_AllZeroCoeff_mbAddrA <= 0;
|
||||
else //update 8x8_AllZero reg when finished one MB residual parsing
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrA[0] <= (CodedBlockPatternLuma[1] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrA[1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg <= 0;
|
||||
else if (slice_data_state == `skip_run_duration)
|
||||
case (mb_num_h)
|
||||
0 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1] <= 0;
|
||||
1 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3] <= 0;
|
||||
2 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5] <= 0;
|
||||
3 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7] <= 0;
|
||||
4 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9] <= 0;
|
||||
5 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11] <= 0;
|
||||
6 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13] <= 0;
|
||||
7 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15] <= 0;
|
||||
8 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17] <= 0;
|
||||
9 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19] <= 0;
|
||||
10:Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21] <= 0;
|
||||
endcase
|
||||
else //update 8x8_AllZero reg when finished one MB residual parsing
|
||||
case (mb_num_h)
|
||||
0:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [0] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
1:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [2] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [3] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
2:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [4] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [5] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
3:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [6] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [7] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
4:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [8] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [9] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
5:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [10] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [11] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
6:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [12] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [13] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
7:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [14] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [15] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
8:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [16] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [17] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
9:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [18] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [19] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
10:
|
||||
begin
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [20] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB_reg [21] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
|
||||
end
|
||||
endcase
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
Chroma_8x8_AllZeroCoeff_mbAddrA <= 0;
|
||||
else if (slice_data_state == `skip_run_duration)
|
||||
Chroma_8x8_AllZeroCoeff_mbAddrA <= 0;
|
||||
else //update 8x8_AllZero reg when finished one MB residual parsing
|
||||
Chroma_8x8_AllZeroCoeff_mbAddrA <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
Chroma_8x8_AllZeroCoeff_mbAddrB_reg <= 0;
|
||||
else if (slice_data_state == `skip_run_duration)
|
||||
case (mb_num_h)
|
||||
0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0] <= 0;
|
||||
1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1] <= 0;
|
||||
2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2] <= 0;
|
||||
3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3] <= 0;
|
||||
4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4] <= 0;
|
||||
5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5] <= 0;
|
||||
6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6] <= 0;
|
||||
7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7] <= 0;
|
||||
8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8] <= 0;
|
||||
9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9] <= 0;
|
||||
10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= 0;
|
||||
endcase
|
||||
else if (mb_num_v != 8)
|
||||
case (mb_num_h)
|
||||
0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
|
||||
endcase
|
||||
//-------------------
|
||||
//nA_availability
|
||||
//-------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
nA_availability_reg <= 0;
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s)
|
||||
nA_availability_reg <= nA_availability;
|
||||
always @ (reset_n or cavlc_decoder_state or residual_state or mb_num_h or i8x8 or i4x4 or i4x4_CbCr or nA_availability_reg)
|
||||
if (reset_n == 1'b0)
|
||||
nA_availability <= 1'b0;
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s)
|
||||
case (residual_state)
|
||||
//luma
|
||||
`Intra16x16DCLevel_s:nA_availability <= (mb_num_h == 0)? 1'b0:1'b1;
|
||||
`Intra16x16ACLevel_s,`LumaLevel_s:
|
||||
if ((i8x8 == 0 || i8x8 == 2) && (i4x4 == 0 || i4x4 == 2))
|
||||
nA_availability <= (mb_num_h == 0)? 1'b0:1'b1;
|
||||
else
|
||||
nA_availability <= 1'b1;
|
||||
//chroma
|
||||
`ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s:
|
||||
nA_availability <= (mb_num_h == 0 && i4x4_CbCr[0] == 0)? 1'b0:1'b1;
|
||||
default:nA_availability <= 1'b0;
|
||||
endcase
|
||||
else
|
||||
nA_availability <= nA_availability_reg;
|
||||
//-------------------
|
||||
//nB_availability
|
||||
//-------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
nB_availability_reg <= 0;
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s)
|
||||
nB_availability_reg <= nB_availability;
|
||||
always @ (reset_n or cavlc_decoder_state or residual_state or mb_num_v or i8x8 or i4x4 or i4x4_CbCr
|
||||
or nB_availability_reg)
|
||||
if (reset_n == 1'b0)
|
||||
nB_availability <= 1'b0;
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s)
|
||||
case (residual_state)
|
||||
//luma
|
||||
`Intra16x16DCLevel_s:nB_availability <= (mb_num_v == 0)? 1'b0:1'b1;
|
||||
`Intra16x16ACLevel_s,`LumaLevel_s:
|
||||
if ((i8x8 == 0 || i8x8 == 1) && (i4x4 == 0 || i4x4 == 1))
|
||||
nB_availability <= (mb_num_v == 0)? 1'b0:1'b1;
|
||||
else
|
||||
nB_availability <= 1'b1;
|
||||
//chroma
|
||||
`ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s:
|
||||
nB_availability <= (mb_num_v == 0 && i4x4_CbCr[1] == 0)? 1'b0:1'b1;
|
||||
default:nB_availability <= 1'b0;
|
||||
endcase
|
||||
else
|
||||
nB_availability <= nB_availability_reg;
|
||||
//------------
|
||||
//Derive nA
|
||||
//------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
nA <= 0;
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nA_availability == 1)
|
||||
case (residual_state)
|
||||
//luma
|
||||
`Intra16x16DCLevel_s:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[4:0];
|
||||
`Intra16x16ACLevel_s,`LumaLevel_s:
|
||||
case (i8x8)
|
||||
0:
|
||||
case (i4x4)
|
||||
0:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[4:0];
|
||||
1:nA <= LumaLevel_CurrMb0[4:0];
|
||||
2:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[9:5];
|
||||
3:nA <= LumaLevel_CurrMb0[14:10];
|
||||
endcase
|
||||
1:
|
||||
case (i4x4)
|
||||
0:nA <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[9:5];
|
||||
1:nA <= LumaLevel_CurrMb1[4:0];
|
||||
2:nA <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[19:15];
|
||||
3:nA <= LumaLevel_CurrMb1[14:10];
|
||||
endcase
|
||||
2:
|
||||
case (i4x4)
|
||||
0:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[1] == 0)? 0:LumaLevel_mbAddrA[14:10];
|
||||
1:nA <= LumaLevel_CurrMb2[4:0];
|
||||
2:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[1] == 0)? 0:LumaLevel_mbAddrA[19:15];
|
||||
3:nA <= LumaLevel_CurrMb2[14:10];
|
||||
endcase
|
||||
3:
|
||||
case (i4x4)
|
||||
0:nA <= (CodedBlockPatternLuma[2] == 0)? 0:LumaLevel_CurrMb2[9:5];
|
||||
1:nA <= LumaLevel_CurrMb3[4:0];
|
||||
2:nA <= (CodedBlockPatternLuma[2] == 0)? 0:LumaLevel_CurrMb2[19:15];
|
||||
3:nA <= LumaLevel_CurrMb3[14:10];
|
||||
endcase
|
||||
endcase
|
||||
//chroma
|
||||
`ChromaACLevel_Cb_s:
|
||||
case (i4x4_CbCr)
|
||||
2'b00:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cb_mbAddrA[4:0];
|
||||
2'b10:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cb_mbAddrA[9:5];
|
||||
2'b01:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cb_CurrMb[4:0];
|
||||
2'b11:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cb_CurrMb[14:10];
|
||||
endcase
|
||||
`ChromaACLevel_Cr_s:
|
||||
case (i4x4_CbCr)
|
||||
2'b00:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cr_mbAddrA[4:0];
|
||||
2'b10:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cr_mbAddrA[9:5];
|
||||
2'b01:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cr_CurrMb[4:0];
|
||||
2'b11:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cr_CurrMb[14:10];
|
||||
endcase
|
||||
endcase
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nA_availability == 0)
|
||||
nA <= 0;
|
||||
//------------
|
||||
//Derive nB
|
||||
//------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
nB <= 0;
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1)
|
||||
case (residual_state)
|
||||
`Intra16x16DCLevel_s:
|
||||
nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[19:15];
|
||||
`Intra16x16ACLevel_s,`LumaLevel_s:
|
||||
case (i8x8)
|
||||
0:
|
||||
case (i4x4)
|
||||
0:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[19:15];
|
||||
1:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[14:10];
|
||||
2:nB <= LumaLevel_CurrMb0[4:0];
|
||||
3:nB <= LumaLevel_CurrMb0[9:5];
|
||||
endcase
|
||||
1:
|
||||
case (i4x4)
|
||||
0:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)? 0:LumaLevel_mbAddrB_dout[9:5];
|
||||
1:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)? 0:LumaLevel_mbAddrB_dout[4:0];
|
||||
2:nB <= LumaLevel_CurrMb1[4:0];
|
||||
3:nB <= LumaLevel_CurrMb1[9:5];
|
||||
endcase
|
||||
2:
|
||||
case (i4x4)
|
||||
0:nB <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[14:10];
|
||||
1:nB <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[19:15];
|
||||
2:nB <= LumaLevel_CurrMb2[4:0];
|
||||
3:nB <= LumaLevel_CurrMb2[9:5];
|
||||
endcase
|
||||
3:
|
||||
case (i4x4)
|
||||
0:nB <= (CodedBlockPatternLuma[1] == 0)? 0:LumaLevel_CurrMb1[14:10];
|
||||
1:nB <= (CodedBlockPatternLuma[1] == 0)? 0:LumaLevel_CurrMb1[19:15];
|
||||
2:nB <= LumaLevel_CurrMb3[4:0];
|
||||
3:nB <= LumaLevel_CurrMb3[9:5];
|
||||
endcase
|
||||
endcase
|
||||
`ChromaACLevel_Cb_s:
|
||||
case (i4x4_CbCr)
|
||||
0:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cb_mbAddrB_dout[9:5];
|
||||
1:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cb_mbAddrB_dout[4:0];
|
||||
2:nB <= ChromaLevel_Cb_CurrMb[4:0];
|
||||
3:nB <= ChromaLevel_Cb_CurrMb[9:5];
|
||||
endcase
|
||||
`ChromaACLevel_Cr_s:
|
||||
case (i4x4_CbCr)
|
||||
0:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cr_mbAddrB_dout[9:5];
|
||||
1:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cr_mbAddrB_dout[4:0];
|
||||
2:nB <= ChromaLevel_Cr_CurrMb[4:0];
|
||||
3:nB <= ChromaLevel_Cr_CurrMb[9:5];
|
||||
endcase
|
||||
default: nB <= 0;
|
||||
endcase
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 0)
|
||||
nB <= 0;
|
||||
//------------
|
||||
//Derive nC
|
||||
//------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
nC <= 0;
|
||||
else if (cavlc_decoder_state == `nC_decoding_s)
|
||||
begin
|
||||
if (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)
|
||||
nC <= 5'b11111;
|
||||
else if (nA_availability == 1 && nB_availability == 1)
|
||||
nC <= (nA + nB + 1) >> 1;
|
||||
else
|
||||
nC <= nA + nB;
|
||||
end
|
||||
//-----------------------
|
||||
//LumaLevel_CurrMb write
|
||||
//-----------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
LumaLevel_CurrMb0 <= 0; LumaLevel_CurrMb1 <= 0;
|
||||
LumaLevel_CurrMb2 <= 0; LumaLevel_CurrMb3 <= 0;
|
||||
end
|
||||
else if (end_of_one_residual_block == 1 && (residual_state == `Intra16x16ACLevel_s ||
|
||||
residual_state == `LumaLevel_s))
|
||||
case (i8x8)
|
||||
0:
|
||||
case (i4x4)
|
||||
0:LumaLevel_CurrMb0[4:0] <= TotalCoeff;
|
||||
1:LumaLevel_CurrMb0[9:5] <= TotalCoeff;
|
||||
2:LumaLevel_CurrMb0[14:10] <= TotalCoeff;
|
||||
3:LumaLevel_CurrMb0[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
1:
|
||||
case (i4x4)
|
||||
0:LumaLevel_CurrMb1[4:0] <= TotalCoeff;
|
||||
1:LumaLevel_CurrMb1[9:5] <= TotalCoeff;
|
||||
2:LumaLevel_CurrMb1[14:10] <= TotalCoeff;
|
||||
3:LumaLevel_CurrMb1[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
2:
|
||||
case (i4x4)
|
||||
0:LumaLevel_CurrMb2[4:0] <= TotalCoeff;
|
||||
1:LumaLevel_CurrMb2[9:5] <= TotalCoeff;
|
||||
2:LumaLevel_CurrMb2[14:10] <= TotalCoeff;
|
||||
3:LumaLevel_CurrMb2[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
3:
|
||||
case (i4x4)
|
||||
0:LumaLevel_CurrMb3[4:0] <= TotalCoeff;
|
||||
1:LumaLevel_CurrMb3[9:5] <= TotalCoeff;
|
||||
2:LumaLevel_CurrMb3[14:10] <= TotalCoeff;
|
||||
3:LumaLevel_CurrMb3[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
endcase
|
||||
//---------------------------
|
||||
//ChromaLevel_Cb_CurrMb write
|
||||
//---------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
ChromaLevel_Cb_CurrMb <= 0;
|
||||
else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s)
|
||||
case (i4x4_CbCr)
|
||||
0:ChromaLevel_Cb_CurrMb[4:0] <= TotalCoeff;
|
||||
1:ChromaLevel_Cb_CurrMb[9:5] <= TotalCoeff;
|
||||
2:ChromaLevel_Cb_CurrMb[14:10] <= TotalCoeff;
|
||||
3:ChromaLevel_Cb_CurrMb[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
//---------------------------
|
||||
//ChromaLevel_Cr_CurrMb write
|
||||
//---------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
ChromaLevel_Cr_CurrMb <= 0;
|
||||
else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s)
|
||||
case (i4x4_CbCr)
|
||||
0:ChromaLevel_Cr_CurrMb[4:0] <= TotalCoeff;
|
||||
1:ChromaLevel_Cr_CurrMb[9:5] <= TotalCoeff;
|
||||
2:ChromaLevel_Cr_CurrMb[14:10] <= TotalCoeff;
|
||||
3:ChromaLevel_Cr_CurrMb[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
//-----------------------
|
||||
//LumaLevel_mbAddrA write
|
||||
//-----------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
LumaLevel_mbAddrA <= 0;
|
||||
else if (end_of_one_residual_block == 1 && (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && mb_num_h != 10)
|
||||
case (i8x8)
|
||||
1:
|
||||
case (i4x4)
|
||||
1:LumaLevel_mbAddrA[4:0] <= TotalCoeff;
|
||||
3:LumaLevel_mbAddrA[9:5] <= TotalCoeff;
|
||||
endcase
|
||||
3:
|
||||
case (i4x4)
|
||||
1:LumaLevel_mbAddrA[14:10] <= TotalCoeff;
|
||||
3:LumaLevel_mbAddrA[19:15] <= TotalCoeff;
|
||||
endcase
|
||||
endcase
|
||||
//----------------------------
|
||||
//ChromaLevel_Cb_mbAddrA write
|
||||
//----------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
ChromaLevel_Cb_mbAddrA <= 0;
|
||||
else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s && mb_num_h != 10)
|
||||
begin
|
||||
if (i4x4_CbCr == 1)
|
||||
ChromaLevel_Cb_mbAddrA[4:0] <= TotalCoeff;
|
||||
if (i4x4_CbCr == 3)
|
||||
ChromaLevel_Cb_mbAddrA[9:5] <= TotalCoeff;
|
||||
end
|
||||
//----------------------------
|
||||
//ChromaLevel_Cr_mbAddrA write
|
||||
//----------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
ChromaLevel_Cr_mbAddrA <= 0;
|
||||
else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s && mb_num_h != 10)
|
||||
begin
|
||||
if (i4x4_CbCr == 1)
|
||||
ChromaLevel_Cr_mbAddrA[4:0] <= TotalCoeff;
|
||||
if (i4x4_CbCr == 3)
|
||||
ChromaLevel_Cr_mbAddrA[9:5] <= TotalCoeff;
|
||||
end
|
||||
//------------------------------
|
||||
//LumaLevel_mbAddrB read & write
|
||||
//------------------------------
|
||||
always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or
|
||||
Luma_8x8_AllZeroCoeff_mbAddrB or i8x8 or i4x4 or end_of_one_residual_block or
|
||||
mb_num_v or mb_num_h or CodedBlockPatternLuma or LumaLevel_CurrMb2 or LumaLevel_CurrMb3 or TotalCoeff)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
//--read--
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1) //read
|
||||
case (residual_state)
|
||||
`Intra16x16DCLevel_s:
|
||||
if (Luma_8x8_AllZeroCoeff_mbAddrB == 0)
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
`Intra16x16ACLevel_s,`LumaLevel_s:
|
||||
case (i8x8)
|
||||
0:
|
||||
if (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
1:
|
||||
if (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
endcase
|
||||
default:
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
endcase
|
||||
//--write--
|
||||
else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_residual_block == 1 && mb_num_v != 8)
|
||||
case (CodedBlockPatternLuma[3:2])
|
||||
2'b00:
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
2'b10,2'b11:
|
||||
if (i8x8 == 3 && i4x4 == 3)
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h;
|
||||
LumaLevel_mbAddrB_din <= (CodedBlockPatternLuma[3:2] == 2'b10)?
|
||||
{10'b0, LumaLevel_CurrMb3[14:10],TotalCoeff}:
|
||||
{LumaLevel_CurrMb2[14:10],LumaLevel_CurrMb2[19:15],LumaLevel_CurrMb3[14:10],TotalCoeff};
|
||||
end
|
||||
else
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
2'b01:
|
||||
if (i8x8 == 2 && i4x4 == 3)
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h;
|
||||
LumaLevel_mbAddrB_din <= {LumaLevel_CurrMb2[14:10],TotalCoeff,10'b0};
|
||||
end
|
||||
else
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
endcase
|
||||
else
|
||||
begin
|
||||
LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1;
|
||||
LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0;
|
||||
LumaLevel_mbAddrB_din <= 0;
|
||||
end
|
||||
//-----------------------------------
|
||||
//ChromaLevel_Cb_mbAddrB read & write
|
||||
//-----------------------------------
|
||||
always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr or ChromaLevel_Cb_CurrMb
|
||||
or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff or end_of_one_residual_block)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cb_mbAddrB_din <= 0;
|
||||
end
|
||||
//--read--
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 &&
|
||||
residual_state == `ChromaACLevel_Cb_s)
|
||||
begin
|
||||
if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1)
|
||||
begin
|
||||
ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cb_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cb_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cb_mbAddrB_din <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cb_mbAddrB_din <= 0;
|
||||
end
|
||||
end
|
||||
//--write--
|
||||
else if (residual_state == `ChromaACLevel_Cb_s && end_of_one_residual_block == 1 && mb_num_v != 8)
|
||||
begin
|
||||
if (i4x4_CbCr == 3)
|
||||
begin
|
||||
ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 0;
|
||||
ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= mb_num_h;
|
||||
ChromaLevel_Cb_mbAddrB_din <= {ChromaLevel_Cb_CurrMb[14:10],TotalCoeff};
|
||||
end
|
||||
else
|
||||
begin
|
||||
ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cb_mbAddrB_din <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cb_mbAddrB_din <= 0;
|
||||
end
|
||||
//-----------------------------------
|
||||
//ChromaLevel_Cr_mbAddrB read & write
|
||||
//-----------------------------------
|
||||
always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr
|
||||
or ChromaLevel_Cr_CurrMb or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff
|
||||
or end_of_one_residual_block)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cr_mbAddrB_din <= 0;
|
||||
end
|
||||
//--read--
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && residual_state == `ChromaACLevel_Cr_s) //read
|
||||
begin
|
||||
if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1)
|
||||
begin
|
||||
ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cr_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cr_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cr_mbAddrB_din <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cr_mbAddrB_din <= 0;
|
||||
end
|
||||
end
|
||||
//--write--
|
||||
else if (residual_state == `ChromaACLevel_Cr_s && end_of_one_residual_block == 1 && mb_num_v != 8)
|
||||
begin
|
||||
if (i4x4_CbCr == 3)
|
||||
begin
|
||||
ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 0;
|
||||
ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= mb_num_h;
|
||||
ChromaLevel_Cr_mbAddrB_din <= {ChromaLevel_Cr_CurrMb[14:10],TotalCoeff};
|
||||
end
|
||||
else
|
||||
begin
|
||||
ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cr_mbAddrB_din <= 0;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1;
|
||||
ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0;
|
||||
ChromaLevel_Cr_mbAddrB_din <= 0;
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,259 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : nova.v
|
||||
// Generated : Feb 25,2006
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Top module of nova design, including two main blocks: BitStream controller and reconstruction datapath
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module nova (clk,reset_n,BitStream_buffer_input,BitStream_ram_ren,BitStream_ram_addr,
|
||||
pic_num,pin_disable_DF,freq_ctrl0,freq_ctrl1,
|
||||
ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
|
||||
ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data,
|
||||
dis_frame_RAM_din,
|
||||
|
||||
slice_header_s6
|
||||
);
|
||||
input clk,reset_n;
|
||||
input [15:0] BitStream_buffer_input;
|
||||
input pin_disable_DF;
|
||||
input freq_ctrl0;
|
||||
input freq_ctrl1;
|
||||
|
||||
output BitStream_ram_ren;
|
||||
output [16:0] BitStream_ram_addr;
|
||||
output [5:0] pic_num;
|
||||
//---ext_frame_RAM0---
|
||||
output ext_frame_RAM0_cs_n;
|
||||
output ext_frame_RAM0_wr;
|
||||
output [13:0] ext_frame_RAM0_addr;
|
||||
//inout [31:0] ext_frame_RAM0_data;
|
||||
input [31:0] ext_frame_RAM0_data;
|
||||
|
||||
//---ext_frame_RAM1---
|
||||
output ext_frame_RAM1_cs_n;
|
||||
output ext_frame_RAM1_wr;
|
||||
output [13:0] ext_frame_RAM1_addr;
|
||||
//inout [31:0] ext_frame_RAM1_data;
|
||||
input [31:0] ext_frame_RAM1_data;
|
||||
|
||||
output [31:0] dis_frame_RAM_din;
|
||||
output slice_header_s6;
|
||||
|
||||
wire trigger_CAVLC;
|
||||
wire end_of_NonZeroCoeff_CAVLC;
|
||||
wire end_of_DCBlk_IQIT;
|
||||
wire end_of_one_blk4x4_sum;
|
||||
wire end_of_MB_DEC;
|
||||
wire gclk_end_of_MB_DEC;
|
||||
wire end_of_one_residual_block;
|
||||
wire end_of_one_frame;
|
||||
wire Is_skip_run_entry;
|
||||
wire Is_skip_run_end;
|
||||
wire skip_mv_calc;
|
||||
wire [3:0] mb_type_general;
|
||||
wire [3:0] mb_num_h;
|
||||
wire [3:0] mb_num_v;
|
||||
wire NextMB_IsSkip;
|
||||
wire LowerMB_IsSkip;
|
||||
wire [4:0] blk4x4_rec_counter;
|
||||
wire [3:0] slice_data_state;
|
||||
wire [3:0] residual_state;
|
||||
wire [3:0] cavlc_decoder_state;
|
||||
wire [1:0] Intra16x16_predmode;
|
||||
wire [63:0] Intra4x4_predmode_CurrMb;
|
||||
wire [1:0] Intra_chroma_predmode;
|
||||
wire [5:0] QPy;
|
||||
wire [5:0] QPc;
|
||||
wire [1:0] i4x4_CbCr;
|
||||
wire [3:0] slice_alpha_c0_offset_div2;
|
||||
wire [3:0] slice_beta_offset_div2;
|
||||
wire [3:0] CodedBlockPatternLuma;
|
||||
wire [1:0] CodedBlockPatternChroma;
|
||||
wire [4:0] TotalCoeff;
|
||||
wire disable_DF;
|
||||
wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5;
|
||||
wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
|
||||
wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
|
||||
wire mv_is16x16;
|
||||
wire [3:0] mv_below8x8;
|
||||
wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
|
||||
wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
wire curr_DC_IsZero;
|
||||
wire end_of_BS_DEC;
|
||||
|
||||
BitStream_controller BitStream_controller (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.freq_ctrl0(freq_ctrl0),
|
||||
.freq_ctrl1(freq_ctrl1),
|
||||
.BitStream_buffer_input(BitStream_buffer_input),
|
||||
.pin_disable_DF(pin_disable_DF),
|
||||
.trigger_CAVLC(trigger_CAVLC),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.curr_DC_IsZero(curr_DC_IsZero),
|
||||
|
||||
.BitStream_ram_ren(BitStream_ram_ren),
|
||||
.BitStream_ram_addr(BitStream_ram_addr),
|
||||
.pic_num(pic_num),
|
||||
.mb_type_general(mb_type_general),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.NextMB_IsSkip(NextMB_IsSkip),
|
||||
.LowerMB_IsSkip(LowerMB_IsSkip),
|
||||
.slice_data_state(slice_data_state),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
|
||||
.end_of_one_frame(end_of_one_frame),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.QPy(QPy),
|
||||
.QPc(QPc),
|
||||
.i4x4_CbCr(i4x4_CbCr),
|
||||
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
|
||||
.slice_beta_offset_div2(slice_beta_offset_div2),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.Is_skip_run_entry(Is_skip_run_entry),
|
||||
.skip_mv_calc(skip_mv_calc),
|
||||
.disable_DF(disable_DF),
|
||||
.coeffLevel_0(coeffLevel_0),
|
||||
.coeffLevel_1(coeffLevel_1),
|
||||
.coeffLevel_2(coeffLevel_2),
|
||||
.coeffLevel_3(coeffLevel_3),
|
||||
.coeffLevel_4(coeffLevel_4),
|
||||
.coeffLevel_5(coeffLevel_5),
|
||||
.coeffLevel_6(coeffLevel_6),
|
||||
.coeffLevel_7(coeffLevel_7),
|
||||
.coeffLevel_8(coeffLevel_8),
|
||||
.coeffLevel_9(coeffLevel_9),
|
||||
.coeffLevel_10(coeffLevel_10),
|
||||
.coeffLevel_11(coeffLevel_11),
|
||||
.coeffLevel_12(coeffLevel_12),
|
||||
.coeffLevel_13(coeffLevel_13),
|
||||
.coeffLevel_14(coeffLevel_14),
|
||||
.coeffLevel_15(coeffLevel_15),
|
||||
.mv_is16x16(mv_is16x16),
|
||||
.mv_below8x8(mv_below8x8),
|
||||
.mvx_CurrMb0(mvx_CurrMb0),
|
||||
.mvx_CurrMb1(mvx_CurrMb1),
|
||||
.mvx_CurrMb2(mvx_CurrMb2),
|
||||
.mvx_CurrMb3(mvx_CurrMb3),
|
||||
.mvy_CurrMb0(mvy_CurrMb0),
|
||||
.mvy_CurrMb1(mvy_CurrMb1),
|
||||
.mvy_CurrMb2(mvy_CurrMb2),
|
||||
.mvy_CurrMb3(mvy_CurrMb3),
|
||||
.end_of_BS_DEC(end_of_BS_DEC),
|
||||
.bs_V0(bs_V0),
|
||||
.bs_V1(bs_V1),
|
||||
.bs_V2(bs_V2),
|
||||
.bs_V3(bs_V3),
|
||||
.bs_H0(bs_H0),
|
||||
.bs_H1(bs_H1),
|
||||
.bs_H2(bs_H2),
|
||||
.bs_H3(bs_H3),
|
||||
|
||||
.slice_header_s6(slice_header_s6)
|
||||
);
|
||||
reconstruction reconstruction (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_type_general(mb_type_general),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.NextMB_IsSkip(NextMB_IsSkip),
|
||||
.LowerMB_IsSkip(LowerMB_IsSkip),
|
||||
.slice_data_state(slice_data_state),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
|
||||
.end_of_one_frame(end_of_one_frame),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.QPy(QPy),
|
||||
.QPc(QPc),
|
||||
.i4x4_CbCr(i4x4_CbCr),
|
||||
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
|
||||
.slice_beta_offset_div2(slice_beta_offset_div2),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.Is_skip_run_entry(Is_skip_run_entry),
|
||||
.skip_mv_calc(skip_mv_calc),
|
||||
.disable_DF(disable_DF),
|
||||
.coeffLevel_0(coeffLevel_0),
|
||||
.coeffLevel_1(coeffLevel_1),
|
||||
.coeffLevel_2(coeffLevel_2),
|
||||
.coeffLevel_3(coeffLevel_3),
|
||||
.coeffLevel_4(coeffLevel_4),
|
||||
.coeffLevel_5(coeffLevel_5),
|
||||
.coeffLevel_6(coeffLevel_6),
|
||||
.coeffLevel_7(coeffLevel_7),
|
||||
.coeffLevel_8(coeffLevel_8),
|
||||
.coeffLevel_9(coeffLevel_9),
|
||||
.coeffLevel_10(coeffLevel_10),
|
||||
.coeffLevel_11(coeffLevel_11),
|
||||
.coeffLevel_12(coeffLevel_12),
|
||||
.coeffLevel_13(coeffLevel_13),
|
||||
.coeffLevel_14(coeffLevel_14),
|
||||
.coeffLevel_15(coeffLevel_15),
|
||||
.mv_is16x16(mv_is16x16),
|
||||
.mv_below8x8(mv_below8x8),
|
||||
.mvx_CurrMb0(mvx_CurrMb0),
|
||||
.mvx_CurrMb1(mvx_CurrMb1),
|
||||
.mvx_CurrMb2(mvx_CurrMb2),
|
||||
.mvx_CurrMb3(mvx_CurrMb3),
|
||||
.mvy_CurrMb0(mvy_CurrMb0),
|
||||
.mvy_CurrMb1(mvy_CurrMb1),
|
||||
.mvy_CurrMb2(mvy_CurrMb2),
|
||||
.mvy_CurrMb3(mvy_CurrMb3),
|
||||
.end_of_BS_DEC(end_of_BS_DEC),
|
||||
.bs_V0(bs_V0),
|
||||
.bs_V1(bs_V1),
|
||||
.bs_V2(bs_V2),
|
||||
.bs_V3(bs_V3),
|
||||
.bs_H0(bs_H0),
|
||||
.bs_H1(bs_H1),
|
||||
.bs_H2(bs_H2),
|
||||
.bs_H3(bs_H3),
|
||||
|
||||
.trigger_CAVLC(trigger_CAVLC),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.curr_DC_IsZero(curr_DC_IsZero),
|
||||
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
|
||||
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
|
||||
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
|
||||
.ext_frame_RAM0_data(ext_frame_RAM0_data),
|
||||
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
|
||||
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
|
||||
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
|
||||
.ext_frame_RAM1_data(ext_frame_RAM1_data),
|
||||
.dis_frame_RAM_din(dis_frame_RAM_din)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,309 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : nova_defines.v
|
||||
// Generated : April 20,2008
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Global parameters of nova
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
//BitStream_controller parameters
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
//---Beha_BitStream_ram.v---
|
||||
`define Beha_Bitstream_ram_size 131071 //Beha_Bitstream_ram size
|
||||
|
||||
//bitstream_gclk_gen
|
||||
//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame
|
||||
//1)50,000 cycles are not enough for foreman300,8th frame.So increase to 51,000 cycles
|
||||
//2)51,000 cycles are not enough for foreman300,11th frame.So increase to 51,500 cycles
|
||||
//3)51,500 cycles are not enough for foreman300,38th frame.So increase to 52,000 cycles
|
||||
//4)52,000 cycles are not enough for foreman300,66th frame.So increase to 52,500 cycles
|
||||
//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles
|
||||
//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles
|
||||
//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read,
|
||||
//the cycles required to decode each frame increased
|
||||
//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles
|
||||
//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles
|
||||
`define cycles_per_frame0 17'd45000
|
||||
`define cycles_per_frame1 17'd50000 //fast enough for akiyo300
|
||||
`define cycles_per_frame2 17'd57300 //preferred frequency for most critical sequence:foreman300
|
||||
`define cycles_per_frame3 17'd70000
|
||||
|
||||
//---pc_decoding---
|
||||
`define rst_consumed_bits_sel 3'b000
|
||||
`define exp_golomb 3'b001
|
||||
`define fixed_length 3'b011
|
||||
`define dependent_variable 3'b010
|
||||
`define cavlc_consumed 3'b110
|
||||
`define trailing_bits 3'b111
|
||||
`define pcm_alignment 3'b101
|
||||
|
||||
//---syntax_decoding---
|
||||
//mb_type_general
|
||||
`define MB_Inter16x16 4'b0000
|
||||
`define MB_Inter16x8 4'b0001
|
||||
`define MB_Inter8x16 4'b0010
|
||||
`define MB_P_8x8 4'b0011
|
||||
`define MB_P_8x8ref0 4'b0100
|
||||
`define MB_P_skip 4'b0101
|
||||
`define MB_I_PCM 4'b0110
|
||||
`define MB_type_reserved0 4'b0111
|
||||
`define MB_Intra16x16_CBPChroma0 4'b1000
|
||||
`define MB_Intra16x16_CBPChroma1 4'b1001
|
||||
`define MB_Intra16x16_CBPChroma2 4'b1010
|
||||
`define MB_type_reserved1 4'b1011
|
||||
`define MB_Intra4x4 4'b1100
|
||||
`define MB_type_reserved2 4'b1101
|
||||
`define MB_type_reserved3 4'b1110
|
||||
`define MB_type_rst 4'b1111
|
||||
|
||||
//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg
|
||||
`define MB_addrA_addrB_Inter 2'b00
|
||||
`define MB_addrA_addrB_P_skip 2'b01
|
||||
`define MB_addrA_addrB_Intra16x16 2'b10
|
||||
`define MB_addrA_addrB_Intra4x4 2'b11
|
||||
|
||||
//MBTypeGen_mbAddrD
|
||||
`define MB_addrD_Inter_P_skip 1'b0
|
||||
`define MB_addrD_Intra 1'b1
|
||||
|
||||
//Gray-encoded FSM states to reduce power consumption during state switching
|
||||
`define rst_parser 2'b00
|
||||
`define start_code_prefix 2'b01
|
||||
`define nal_unit 2'b11
|
||||
|
||||
`define rst_nal_unit 3'b000
|
||||
`define forbidden_zero_bit_2_nal_unit_type 3'b001
|
||||
`define slice_layer_non_IDR_rbsp 3'b011
|
||||
`define slice_layer_IDR_rbsp 3'b010
|
||||
`define seq_parameter_set_rbsp 3'b110
|
||||
`define pic_parameter_set_rbsp 3'b111
|
||||
`define rbsp_trailing_one_bit 3'b101
|
||||
`define rbsp_trailing_zero_bits 3'b100
|
||||
|
||||
`define rst_slice_layer_wo_partitioning 2'b00
|
||||
`define slice_header 2'b01
|
||||
`define slice_data 2'b11
|
||||
|
||||
`define rst_seq_parameter_set 4'b0000
|
||||
`define fixed_header 4'b0001
|
||||
`define level_idc_s 4'b0011
|
||||
`define seq_parameter_set_id_sps_s 4'b0010
|
||||
`define log2_max_frame_num_minus4_s 4'b0110
|
||||
`define pic_order_cnt_type_s 4'b0111
|
||||
`define log2_max_pic_order_cnt_lsb_minus4_s 4'b0101
|
||||
`define num_ref_frames_s 4'b0100
|
||||
`define gaps_in_frame_num_value_allowed_flag_s 4'b1100
|
||||
`define pic_width_in_mbs_minus1_s 4'b1101
|
||||
`define pic_height_in_map_units_minus1_s 4'b1111
|
||||
`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110
|
||||
`define vui_parameter_present_flag_s 4'b1010
|
||||
|
||||
`define rst_pic_parameter_set 4'b0000
|
||||
`define pic_parameter_set_id_pps_s 4'b0001
|
||||
`define seq_parameter_set_id_pps_s 4'b0011
|
||||
`define entropy_coding_mode_flag_2_pic_order_present_flag 4'b0010
|
||||
`define num_slice_groups_minus1_s 4'b0110
|
||||
`define num_ref_idx_l0_active_minus1_pps_s 4'b0111
|
||||
`define num_ref_idx_l1_active_minus1_pps_s 4'b0101
|
||||
`define weighted_pred_flag_2_weighted_bipred_idc 4'b0100
|
||||
`define pic_init_qp_minus26_s 4'b1100
|
||||
`define pic_init_qs_minus26_s 4'b1101
|
||||
`define chroma_qp_index_offset_s 4'b1111
|
||||
`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110
|
||||
|
||||
`define rst_slice_header 4'b0000
|
||||
`define first_mb_in_slice_s 4'b0001
|
||||
`define slice_type_s 4'b0011
|
||||
`define pic_parameter_set_id_slice_header_s 4'b0010
|
||||
`define frame_num_s 4'b0110
|
||||
`define idr_pic_id_s 4'b0111
|
||||
`define pic_order_cnt_lsb_s 4'b0101
|
||||
`define num_ref_idx_active_override_flag_s 4'b0100
|
||||
`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100
|
||||
`define ref_pic_list_reordering 4'b1101
|
||||
`define dec_ref_pic_marking 4'b1111
|
||||
`define slice_qp_delta_s 4'b1110
|
||||
`define disable_deblocking_filter_idc_s 4'b1010
|
||||
`define slice_alpha_c0_offset_div2_s 4'b1011
|
||||
`define slice_beta_offset_div2_s 4'b1001
|
||||
|
||||
//ref_pic_list_reordering_state
|
||||
`define rst_ref_pic_list_reordering 3'b000
|
||||
`define ref_pic_list_reordering_flag_l0_s 3'b001
|
||||
|
||||
//dec_ref_pic_marking_state
|
||||
`define rst_dec_ref_pic_marking 2'b00
|
||||
`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01
|
||||
`define adaptive_ref_pic_marking_mode_flag_s 2'b11
|
||||
|
||||
`define rst_slice_data 4'b0000
|
||||
`define mb_skip_run_s 4'b0001
|
||||
`define skip_run_duration 4'b0011
|
||||
`define mb_type_s 4'b0010
|
||||
`define pcm_alignment_zero_bit_s 4'b0110
|
||||
`define pcm_byte_s 4'b0111
|
||||
`define sub_mb_pred 4'b0101
|
||||
`define mb_pred 4'b0100
|
||||
`define coded_block_pattern_s 4'b1100
|
||||
`define mb_qp_delta_s 4'b1101
|
||||
`define residual 4'b1111
|
||||
`define mb_num_update 4'b1110
|
||||
|
||||
//mb_pred_state
|
||||
`define rst_mb_pred 3'b000
|
||||
`define prev_intra4x4_pred_mode_flag_s 3'b001
|
||||
`define rem_intra4x4_pred_mode_s 3'b011
|
||||
`define intra_chroma_pred_mode_s 3'b010
|
||||
`define ref_idx_l0_s 3'b110
|
||||
`define mvd_l0_s 3'b111
|
||||
|
||||
//sub_mb_pred_state
|
||||
`define rst_sub_mb_pred 2'b00
|
||||
`define sub_mb_type_s 2'b01
|
||||
`define sub_ref_idx_l0_s 2'b11
|
||||
`define sub_mvd_l0_s 2'b10
|
||||
|
||||
`define rst_residual 4'b0000
|
||||
`define Intra16x16DCLevel_s 4'b0001
|
||||
`define Intra16x16ACLevel_s 4'b0011
|
||||
`define Intra16x16ACLevel_0_s 4'b0010
|
||||
`define LumaLevel_s 4'b0110
|
||||
`define LumaLevel_0_s 4'b0111
|
||||
`define ChromaDCLevel_Cb_s 4'b0101
|
||||
`define ChromaDCLevel_Cr_s 4'b0100
|
||||
`define ChromaACLevel_Cb_s 4'b1100
|
||||
`define ChromaACLevel_Cr_s 4'b1101
|
||||
`define ChromaACLevel_0_s 4'b1110
|
||||
|
||||
`define rst_cavlc_decoder 4'b0000
|
||||
`define nAnB_decoding_s 4'b0001
|
||||
`define nC_decoding_s 4'b0011
|
||||
`define NumCoeffTrailingOnes_LUT 4'b0010
|
||||
`define TrailingOnesSignFlag 4'b0110
|
||||
`define LevelPrefix 4'b0111
|
||||
`define LevelSuffix 4'b0101
|
||||
`define total_zeros_LUT 4'b0100
|
||||
`define run_before_LUT 4'b1100
|
||||
`define RunOfZeros 4'b1101
|
||||
`define LevelRunCombination 4'b1111
|
||||
|
||||
//---LumaLevel_mbAddrB_RF---
|
||||
`define LumaLevel_mbAddrB_RF_data_width 20
|
||||
`define LumaLevel_mbAddrB_RF_data_depth 11
|
||||
//---ChromaLevel_Cb_mbAddrB_RF---
|
||||
`define ChromaLevel_Cb_mbAddrB_RF_data_width 10
|
||||
`define ChromaLevel_Cb_mbAddrB_RF_data_depth 11
|
||||
//---ChromaLevel_Cr_mbAddrB_RF---
|
||||
`define ChromaLevel_Cr_mbAddrB_RF_data_width 10
|
||||
`define ChromaLevel_Cr_mbAddrB_RF_data_depth 11
|
||||
|
||||
//---Intra4x4_PredMode_RF---
|
||||
`define Intra4x4_PredMode_RF_data_width 16
|
||||
`define Intra4x4_PredMode_RF_data_depth 11
|
||||
|
||||
//---mvx_mbAddrB_RF---
|
||||
`define mvx_mbAddrB_RF_data_width 32
|
||||
`define mvx_mbAddrB_RF_data_depth 11
|
||||
//---mvy_mbAddrB_RF---
|
||||
`define mvy_mbAddrB_RF_data_width 32
|
||||
`define mvy_mbAddrB_RF_data_depth 11
|
||||
//---mvx_mbAddrC_RF---
|
||||
`define mvx_mbAddrC_RF_data_width 8
|
||||
`define mvx_mbAddrC_RF_data_depth 10
|
||||
//---mvy_mbAddrC_RF---
|
||||
`define mvy_mbAddrC_RF_data_width 8
|
||||
`define mvy_mbAddrC_RF_data_depth 10
|
||||
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
//Intra prediction parameters
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
//---Intra_mbAddrB_RAM---
|
||||
`define Intra_mbAddrB_RAM_data_width 32
|
||||
`define Intra_mbAddrB_RAM_data_depth 88
|
||||
|
||||
//---Intra_pred_PE,Intra_pred_pipeline,Intra_pred_reg_ctrl---
|
||||
`define Intra4x4_Vertical 4'b0000
|
||||
`define Intra4x4_Horizontal 4'b0001
|
||||
`define Intra4x4_DC 4'b0010
|
||||
`define Intra4x4_Diagonal_Down_Left 4'b0011
|
||||
`define Intra4x4_Diagonal_Down_Right 4'b0100
|
||||
`define Intra4x4_Vertical_Right 4'b0101
|
||||
`define Intra4x4_Horizontal_Down 4'b0110
|
||||
`define Intra4x4_Vertical_Left 4'b0111
|
||||
`define Intra4x4_Horizontal_Up 4'b1000
|
||||
|
||||
`define Intra16x16_Vertical 2'b00
|
||||
`define Intra16x16_Horizontal 2'b01
|
||||
`define Intra16x16_DC 2'b10
|
||||
`define Intra16x16_Plane 2'b11
|
||||
|
||||
`define Intra_chroma_DC 2'b00
|
||||
`define Intra_chroma_Horizontal 2'b01
|
||||
`define Intra_chroma_Vertical 2'b10
|
||||
`define Intra_chroma_Plane 2'b11
|
||||
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
//Inter prediction parameters
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
//---Inter_pred_LPE,Inter_pred_pipeline,Inter_pred_reg_ctrl,Inter_pred_sliding_window---
|
||||
`define pos_Int 4'b0000
|
||||
`define pos_a 4'b0100
|
||||
`define pos_b 4'b1000
|
||||
`define pos_c 4'b1100
|
||||
`define pos_d 4'b0001
|
||||
`define pos_e 4'b0101
|
||||
`define pos_f 4'b1001
|
||||
`define pos_g 4'b1101
|
||||
`define pos_h 4'b0010
|
||||
`define pos_i 4'b0110
|
||||
`define pos_j 4'b1010
|
||||
`define pos_k 4'b1110
|
||||
`define pos_n 4'b0011
|
||||
`define pos_p 4'b0111
|
||||
`define pos_q 4'b1011
|
||||
`define pos_r 4'b1111
|
||||
|
||||
//---Inter_pred_pipeline
|
||||
`define pic_width 8'd176
|
||||
`define pic_height 8'd144
|
||||
`define half_pic_width 7'd88
|
||||
`define half_pic_height 7'd72
|
||||
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
//Deblocking filter parameters
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
//---bs_decoding---
|
||||
`define I8x8 2'b00 //size of inter prediction partitions
|
||||
`define I16x8 2'b01
|
||||
`define I8x16 2'b10
|
||||
`define I16x16 2'b11
|
||||
|
||||
//---DF_mbAddrA_RAM---
|
||||
`define DF_mbAddrA_RAM_data_width 32
|
||||
`define DF_mbAddrA_RAM_data_depth 32
|
||||
|
||||
//---DF_mbAddrB_RAM---
|
||||
`define DF_mbAddrB_RAM_data_width 32
|
||||
`define DF_mbAddrB_RAM_data_depth 352
|
||||
|
||||
//---rec_DF_RAM0---
|
||||
`define rec_DF_RAM0_data_width 32
|
||||
`define rec_DF_RAM0_data_depth 96
|
||||
|
||||
//---rec_DF_RAM1---
|
||||
`define rec_DF_RAM1_data_width 32
|
||||
`define rec_DF_RAM1_data_depth 96
|
||||
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
//Hybrid pipeline control parameters
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,108 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : nova_tb.v
|
||||
// Generated : March 13,2006
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Testbench for nova
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module nova_tb;
|
||||
|
||||
reg clk;
|
||||
reg reset_n;
|
||||
reg pin_disable_DF;
|
||||
reg freq_ctrl0;
|
||||
reg freq_ctrl1;
|
||||
|
||||
wire BitStream_ram_ren;
|
||||
wire [16:0] BitStream_ram_addr;
|
||||
wire [15:0] BitStream_buffer_input;
|
||||
wire [5:0] pic_num;
|
||||
wire [6:0] mb_num;
|
||||
|
||||
wire [13:0] ext_frame_RAM0_addr;
|
||||
wire [31:0] ext_frame_RAM0_data;
|
||||
wire [13:0] ext_frame_RAM1_addr;
|
||||
wire [31:0] ext_frame_RAM1_data;
|
||||
wire [31:0] dis_frame_RAM_din;
|
||||
|
||||
wire [15:0] temp;
|
||||
assign temp = dis_frame_RAM_din[15:0];
|
||||
|
||||
//for debug only
|
||||
wire slice_header_s6;
|
||||
|
||||
Beha_BitStream_ram Beha_BitStream_ram (
|
||||
.clk(clk),
|
||||
.BitStream_ram_ren(BitStream_ram_ren),
|
||||
.BitStream_ram_addr(BitStream_ram_addr),
|
||||
.BitStream_ram_data(BitStream_buffer_input)
|
||||
);
|
||||
ext_frame_RAM0_wrapper ext_frame_RAM0_wrapper (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
|
||||
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
|
||||
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
|
||||
.dis_frame_RAM_din(dis_frame_RAM_din),
|
||||
.ext_frame_RAM0_data(ext_frame_RAM0_data),
|
||||
.pic_num(pic_num),
|
||||
.slice_header_s6(slice_header_s6)
|
||||
);
|
||||
ext_frame_RAM1_wrapper ext_frame_RAM1_wrapper (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
|
||||
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
|
||||
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
|
||||
.dis_frame_RAM_din(dis_frame_RAM_din),
|
||||
.ext_frame_RAM1_data(ext_frame_RAM1_data),
|
||||
.pic_num(pic_num),
|
||||
.slice_header_s6(slice_header_s6)
|
||||
);
|
||||
nova nova (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.freq_ctrl0(freq_ctrl0),
|
||||
.freq_ctrl1(freq_ctrl1),
|
||||
.BitStream_buffer_input(BitStream_buffer_input),
|
||||
.BitStream_ram_ren(BitStream_ram_ren),
|
||||
.BitStream_ram_addr(BitStream_ram_addr),
|
||||
.pic_num(pic_num),
|
||||
.pin_disable_DF(pin_disable_DF),
|
||||
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
|
||||
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
|
||||
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
|
||||
.ext_frame_RAM0_data(ext_frame_RAM0_data),
|
||||
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
|
||||
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
|
||||
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
|
||||
.ext_frame_RAM1_data(ext_frame_RAM1_data),
|
||||
.dis_frame_RAM_din(dis_frame_RAM_din),
|
||||
.slice_header_s6(slice_header_s6)
|
||||
);
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b1;
|
||||
reset_n = 1'b1;
|
||||
pin_disable_DF = 1'b0;
|
||||
freq_ctrl0 = 1'b0;
|
||||
freq_ctrl1 = 1'b1;
|
||||
#1100 reset_n = 1'b0;
|
||||
#1000 reset_n = 1'b1;
|
||||
end
|
||||
|
||||
always
|
||||
#340 clk = ~clk;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,204 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : pc_decoding.v
|
||||
// Generated : June 6, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding program counter for bitstream_buffer
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module pc_decoding (clk,reset_n,parser_state,nal_unit_state,slice_header_state,ref_pic_list_reordering_state,
|
||||
dec_ref_pic_marking_state,slice_data_state,sub_mb_pred_state,mb_pred_state,seq_parameter_set_state,
|
||||
pic_parameter_set_state,exp_golomb_len,dependent_variable_len,cavlc_consumed_bits_len,
|
||||
pc);
|
||||
input clk,reset_n;
|
||||
input [1:0] parser_state;
|
||||
input [2:0] nal_unit_state;
|
||||
input [3:0] slice_header_state;
|
||||
input [2:0] ref_pic_list_reordering_state;
|
||||
input [1:0] dec_ref_pic_marking_state;
|
||||
input [3:0] slice_data_state;
|
||||
input [1:0] sub_mb_pred_state;
|
||||
input [2:0] mb_pred_state;
|
||||
input [3:0] seq_parameter_set_state;
|
||||
input [3:0] pic_parameter_set_state;
|
||||
input [3:0] exp_golomb_len;
|
||||
input [3:0] dependent_variable_len;
|
||||
input [4:0] cavlc_consumed_bits_len;
|
||||
output [6:0] pc;
|
||||
reg [6:0] pc;
|
||||
|
||||
reg [2:0] consumed_bits_sel;
|
||||
reg [4:0] FixedLen;
|
||||
|
||||
always @ (reset_n or parser_state or nal_unit_state or slice_header_state or ref_pic_list_reordering_state or
|
||||
dec_ref_pic_marking_state or slice_data_state or sub_mb_pred_state or mb_pred_state or
|
||||
seq_parameter_set_state or pic_parameter_set_state)
|
||||
if (reset_n == 0)
|
||||
consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
else if (parser_state == `start_code_prefix)
|
||||
consumed_bits_sel <= `fixed_length;
|
||||
else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type)
|
||||
consumed_bits_sel <= `fixed_length;
|
||||
else if (slice_header_state != `rst_slice_header)
|
||||
case (slice_header_state)
|
||||
`first_mb_in_slice_s :consumed_bits_sel <= `exp_golomb;
|
||||
`slice_type_s :consumed_bits_sel <= `exp_golomb;
|
||||
`pic_parameter_set_id_slice_header_s :consumed_bits_sel <= `exp_golomb;
|
||||
`frame_num_s :consumed_bits_sel <= `dependent_variable;
|
||||
`idr_pic_id_s :consumed_bits_sel <= `exp_golomb;
|
||||
`pic_order_cnt_lsb_s :consumed_bits_sel <= `dependent_variable;
|
||||
`num_ref_idx_active_override_flag_s :consumed_bits_sel <= `fixed_length;
|
||||
`num_ref_idx_l0_active_minus1_slice_header_s:consumed_bits_sel <= `exp_golomb;
|
||||
`ref_pic_list_reordering:
|
||||
case (ref_pic_list_reordering_state)
|
||||
`ref_pic_list_reordering_flag_l0_s:consumed_bits_sel <= `fixed_length;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
`dec_ref_pic_marking:
|
||||
case (dec_ref_pic_marking_state)
|
||||
`no_output_of_prior_pics_flag_2_long_term_reference_flag:consumed_bits_sel <= `fixed_length;
|
||||
`adaptive_ref_pic_marking_mode_flag_s :consumed_bits_sel <= `fixed_length;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
`slice_qp_delta_s :consumed_bits_sel <= `exp_golomb;
|
||||
`disable_deblocking_filter_idc_s:consumed_bits_sel <= `exp_golomb;
|
||||
`slice_alpha_c0_offset_div2_s :consumed_bits_sel <= `exp_golomb;
|
||||
`slice_beta_offset_div2_s :consumed_bits_sel <= `exp_golomb;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
else if (slice_data_state != `rst_slice_data)
|
||||
case (slice_data_state)
|
||||
`mb_skip_run_s :consumed_bits_sel <= `exp_golomb;
|
||||
`mb_type_s :consumed_bits_sel <= `exp_golomb;
|
||||
`pcm_alignment_zero_bit_s:consumed_bits_sel <= `exp_golomb;
|
||||
`pcm_byte_s :consumed_bits_sel <= `pcm_alignment;
|
||||
`sub_mb_pred:
|
||||
case (sub_mb_pred_state)
|
||||
`rst_sub_mb_pred:consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
default :consumed_bits_sel <= `exp_golomb;
|
||||
endcase
|
||||
`mb_pred:
|
||||
case (mb_pred_state)
|
||||
`prev_intra4x4_pred_mode_flag_s:consumed_bits_sel <= `fixed_length;
|
||||
`rem_intra4x4_pred_mode_s :consumed_bits_sel <= `fixed_length;
|
||||
`intra_chroma_pred_mode_s :consumed_bits_sel <= `exp_golomb;
|
||||
`ref_idx_l0_s :consumed_bits_sel <= `exp_golomb;
|
||||
`mvd_l0_s :consumed_bits_sel <= `exp_golomb;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
`coded_block_pattern_s:consumed_bits_sel <= `exp_golomb;
|
||||
`mb_qp_delta_s :consumed_bits_sel <= `exp_golomb;
|
||||
`residual :consumed_bits_sel <= `cavlc_consumed;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
else if (seq_parameter_set_state != `rst_seq_parameter_set)
|
||||
case (seq_parameter_set_state)
|
||||
`fixed_header :consumed_bits_sel <= `fixed_length;
|
||||
`level_idc_s :consumed_bits_sel <= `fixed_length;
|
||||
`seq_parameter_set_id_sps_s :consumed_bits_sel <= `exp_golomb;
|
||||
`log2_max_frame_num_minus4_s :consumed_bits_sel <= `exp_golomb;
|
||||
`pic_order_cnt_type_s :consumed_bits_sel <= `exp_golomb;
|
||||
`log2_max_pic_order_cnt_lsb_minus4_s :consumed_bits_sel <= `exp_golomb;
|
||||
`num_ref_frames_s :consumed_bits_sel <= `exp_golomb;
|
||||
`gaps_in_frame_num_value_allowed_flag_s :consumed_bits_sel <= `fixed_length;
|
||||
`pic_width_in_mbs_minus1_s :consumed_bits_sel <= `exp_golomb;
|
||||
`pic_height_in_map_units_minus1_s :consumed_bits_sel <= `exp_golomb;
|
||||
`frame_mbs_only_flag_2_frame_cropping_flag:consumed_bits_sel <= `fixed_length;
|
||||
`vui_parameter_present_flag_s :consumed_bits_sel <= `fixed_length;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
else if (pic_parameter_set_state != `rst_pic_parameter_set)
|
||||
case (pic_parameter_set_state)
|
||||
`pic_parameter_set_id_pps_s :consumed_bits_sel <= `exp_golomb;
|
||||
`seq_parameter_set_id_pps_s :consumed_bits_sel <= `exp_golomb;
|
||||
`entropy_coding_mode_flag_2_pic_order_present_flag :consumed_bits_sel <= `fixed_length;
|
||||
`num_slice_groups_minus1_s :consumed_bits_sel <= `exp_golomb;
|
||||
`num_ref_idx_l0_active_minus1_pps_s :consumed_bits_sel <= `exp_golomb;
|
||||
`num_ref_idx_l1_active_minus1_pps_s :consumed_bits_sel <= `exp_golomb;
|
||||
`weighted_pred_flag_2_weighted_bipred_idc :consumed_bits_sel <= `fixed_length;
|
||||
`pic_init_qp_minus26_s :consumed_bits_sel <= `exp_golomb;
|
||||
`pic_init_qs_minus26_s :consumed_bits_sel <= `exp_golomb;
|
||||
`chroma_qp_index_offset_s :consumed_bits_sel <= `exp_golomb;
|
||||
`deblocking_filter_control_2_redundant_pic_cnt_present_flag:consumed_bits_sel <= `fixed_length;
|
||||
default :consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
endcase
|
||||
else if (nal_unit_state == `rbsp_trailing_one_bit)
|
||||
consumed_bits_sel <= `fixed_length;
|
||||
else if (nal_unit_state == `rbsp_trailing_zero_bits)
|
||||
consumed_bits_sel <= `trailing_bits;
|
||||
else
|
||||
consumed_bits_sel <= `rst_consumed_bits_sel;
|
||||
|
||||
always @ (reset_n or parser_state or nal_unit_state or slice_header_state or ref_pic_list_reordering_state or
|
||||
dec_ref_pic_marking_state or slice_data_state or mb_pred_state or seq_parameter_set_state or pic_parameter_set_state)
|
||||
if (reset_n == 0)
|
||||
FixedLen <= 0;
|
||||
else
|
||||
begin
|
||||
if (parser_state == `start_code_prefix)
|
||||
FixedLen <= 5'd16;
|
||||
else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type)
|
||||
FixedLen <= 8;
|
||||
else if (slice_header_state == `num_ref_idx_active_override_flag_s)
|
||||
FixedLen <= 1;
|
||||
else if (ref_pic_list_reordering_state == `ref_pic_list_reordering_flag_l0_s)
|
||||
FixedLen <= 1;
|
||||
else if (dec_ref_pic_marking_state == `no_output_of_prior_pics_flag_2_long_term_reference_flag)
|
||||
FixedLen <= 2;
|
||||
else if (dec_ref_pic_marking_state == `adaptive_ref_pic_marking_mode_flag_s)
|
||||
FixedLen <= 1;
|
||||
else if (slice_data_state == `pcm_byte_s)
|
||||
FixedLen <= 5'd16;
|
||||
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
||||
FixedLen <= 1;
|
||||
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
||||
FixedLen <= 3;
|
||||
else if (seq_parameter_set_state == `fixed_header)
|
||||
FixedLen <= 5'd16;
|
||||
else if (seq_parameter_set_state == `level_idc_s)
|
||||
FixedLen <= 8;
|
||||
else if (seq_parameter_set_state == `gaps_in_frame_num_value_allowed_flag_s)
|
||||
FixedLen <= 1;
|
||||
else if (seq_parameter_set_state == `frame_mbs_only_flag_2_frame_cropping_flag)
|
||||
FixedLen <= 3;
|
||||
else if (seq_parameter_set_state == `vui_parameter_present_flag_s)
|
||||
FixedLen <= 1;
|
||||
else if (pic_parameter_set_state == `entropy_coding_mode_flag_2_pic_order_present_flag)
|
||||
FixedLen <= 2;
|
||||
else if (pic_parameter_set_state == `weighted_pred_flag_2_weighted_bipred_idc)
|
||||
FixedLen <= 3;
|
||||
else if (pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag)
|
||||
FixedLen <= 3;
|
||||
else if (nal_unit_state == `rbsp_trailing_one_bit)
|
||||
FixedLen <= 1;
|
||||
else
|
||||
FixedLen <= 1;
|
||||
end
|
||||
|
||||
reg [6:0] pc_reg;
|
||||
always @ (consumed_bits_sel or pc_reg or exp_golomb_len or dependent_variable_len or
|
||||
cavlc_consumed_bits_len or FixedLen)
|
||||
case (consumed_bits_sel)
|
||||
`exp_golomb :pc <= pc_reg + exp_golomb_len;
|
||||
`dependent_variable:pc <= pc_reg + dependent_variable_len;
|
||||
`cavlc_consumed :pc <= pc_reg + cavlc_consumed_bits_len;
|
||||
`fixed_length :pc <= pc_reg + FixedLen;
|
||||
`trailing_bits :pc <= (pc_reg[2:0] == 3'b000)? pc_reg:{{pc_reg[6:3] + 1},3'b0};
|
||||
`pcm_alignment :pc <= (pc_reg[2:0] == 3'b000)? pc_reg:{{pc_reg[6:3] + 1},3'b0};
|
||||
default :pc <= pc_reg;
|
||||
endcase
|
||||
always @ (posedge clk)
|
||||
pc_reg <= (reset_n == 0)? 0:pc;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : ram_async_1r_sync_1w.v
|
||||
// Generated : April 25,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Synch Write, Asynch Read RAM, NOT synthesizable
|
||||
// In real silicon, use register file (DFF) instead of RAM
|
||||
// legal range:data_width [ 1 to 128 ]
|
||||
// legal range:data_depth [ 2 to 256 ]
|
||||
// Input data :data_in[data_width-1:0]
|
||||
// Output data:data_out[data_width-1:0]
|
||||
// Read Address :rd_addr[addr_width-1:0]
|
||||
// Write Address:wr_addr[addr_width-1:0]
|
||||
// Write enable (active low): wr_n
|
||||
// Chip select (active low): cs_n
|
||||
// Reset (active low): rst_n
|
||||
// Clock:clk
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
module ram_async_1r_sync_1w (clk, rst_n, cs_n, wr_n, rd_addr, wr_addr, data_in, data_out);
|
||||
|
||||
parameter data_width = 4; //will be overrided during module instantiation
|
||||
parameter data_depth = 8; //will be overrided during module instantiation
|
||||
|
||||
`define addr_width ((data_depth>16)?((data_depth>64)?((data_depth>128)?8:7):((data_depth>32)?6:5)):((data_depth>4)?((data_depth>8)?4:3):((data_depth>2)?2:1)))
|
||||
|
||||
input clk;
|
||||
input rst_n;
|
||||
input cs_n;
|
||||
input wr_n;
|
||||
input [data_width-1:0] data_in;
|
||||
input [`addr_width-1:0] rd_addr;
|
||||
input [`addr_width-1:0] wr_addr;
|
||||
output [data_width-1:0] data_out;
|
||||
|
||||
reg [data_width-1:0] ram [data_depth-1:0];
|
||||
|
||||
//data_width & data_depth check
|
||||
initial
|
||||
begin:parameter_check
|
||||
integer param_error_flag;
|
||||
param_error_flag = 0;
|
||||
|
||||
if ( (data_width < 1) || (data_width > 128) )
|
||||
begin
|
||||
param_error_flag = 1;
|
||||
$display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 128)",data_width );
|
||||
end
|
||||
|
||||
if ( (data_depth < 2) || (data_depth > 256 ) )
|
||||
begin
|
||||
param_error_flag = 1;
|
||||
$display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 256 )",data_depth );
|
||||
end
|
||||
|
||||
if ( param_error_flag == 1)
|
||||
begin
|
||||
$display("%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // end data_width & data_depth check
|
||||
|
||||
//read
|
||||
assign data_out = ((rd_addr ^ rd_addr) !== {`addr_width{1'b0}})? {data_width{1'bx}} : ((rd_addr >= data_depth)? {data_width{1'b0}} : ram[rd_addr] );
|
||||
|
||||
//write
|
||||
always @ (posedge clk)
|
||||
if (!cs_n && !wr_n)
|
||||
ram[wr_addr] <= data_in;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,94 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : ram_sync_1r_sync_1w.v
|
||||
// Generated : April 25,2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Synch Write, Synch Read RAM, NOT synthesizable
|
||||
// In real silicon, use customized RAM instead of DFF
|
||||
// legal range:data_width [ 1 to 256 ]
|
||||
// legal range:data_depth [ 2 to 1024 ]
|
||||
// Input data :data_in[data_width-1:0]
|
||||
// Output data:data_out[data_width-1:0]
|
||||
// Read Address :rd_addr[addr_width-1:0]
|
||||
// Write Address:wr_addr[addr_width-1:0]
|
||||
// Write enable (active low): wr_n
|
||||
// Chip select (active low): cs_n
|
||||
// Reset (active low): rst_n
|
||||
// Clock:clk
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module ram_sync_1r_sync_1w (clk, rst_n, wr_n, rd_n, wr_addr, rd_addr, data_in, data_out);
|
||||
|
||||
parameter data_width = 4; //will be overrided during module instantiation
|
||||
parameter data_depth = 8; //will be overrided during module instantiation
|
||||
|
||||
`define addr_width ((data_depth>32)?((data_depth>256)?((data_depth>512)?10:9):((data_depth>128)?8:((data_depth>64)?7:6))):((data_depth>8) ?((data_depth>16) ?5:4) :((data_depth>4) ?3:((data_depth>2) ?1:0))))
|
||||
|
||||
input clk;
|
||||
input rst_n;
|
||||
input wr_n;
|
||||
input rd_n;
|
||||
input [`addr_width-1:0] wr_addr;
|
||||
input [`addr_width-1:0] rd_addr;
|
||||
input [data_width-1:0] data_in;
|
||||
output [data_width-1:0] data_out;
|
||||
|
||||
reg [data_width-1:0] data_out;
|
||||
reg [data_width-1:0] ram [data_depth-1:0];
|
||||
|
||||
//data_width, data_depth, simultaneously read/write check
|
||||
initial
|
||||
begin:parameter_check
|
||||
integer param_error_flag;
|
||||
param_error_flag = 0;
|
||||
|
||||
if ( (data_width < 1) || (data_width > 256) )
|
||||
begin
|
||||
param_error_flag = 1;
|
||||
$display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 256)",data_width );
|
||||
end
|
||||
|
||||
if ( (data_depth < 2) || (data_depth > 1024 ) )
|
||||
begin
|
||||
param_error_flag = 1;
|
||||
$display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 1024 )",data_depth );
|
||||
end
|
||||
|
||||
/*
|
||||
if ( (cs_n == 1'b0 && wr_n == 1'b0 && rd_n == 1'b0 ) )
|
||||
begin
|
||||
param_error_flag = 1;
|
||||
$display("Error: %m :\n Not allowed! RAM simultaneously read and write occur");
|
||||
end
|
||||
*/
|
||||
if ( param_error_flag == 1)
|
||||
begin
|
||||
$display("%m :\n Simulation aborted due to invalid parameter value(s)");
|
||||
$finish;
|
||||
end
|
||||
|
||||
end // end data_width & data_depth check
|
||||
|
||||
//read
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if (rst_n == 1'b0)
|
||||
data_out <= 0;
|
||||
else if (!rd_n)
|
||||
data_out <= ram[rd_addr];
|
||||
|
||||
//write
|
||||
always @ (posedge clk)
|
||||
if (!wr_n)
|
||||
ram[wr_addr] <= data_in;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,173 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : rec_DF_RAM_ctrl.v
|
||||
// Generated : Nov 3, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Controller for rec_DF_RAM0 & rec_DF_RAM1,single port SRAM
|
||||
// write during reconstruction,read during DF
|
||||
// assume "_wr" & "_rd" are both high active
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module rec_DF_RAM_ctrl (clk,reset_n,disable_DF,end_of_MB_DEC,
|
||||
DF_edge_counter_MR,one_edge_counter_MR,
|
||||
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
||||
blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM0_dout,rec_DF_RAM1_dout,
|
||||
|
||||
rec_DF_RAM_dout,
|
||||
rec_DF_RAM0_wr,rec_DF_RAM0_rd,rec_DF_RAM0_addr,rec_DF_RAM0_din,
|
||||
rec_DF_RAM1_wr,rec_DF_RAM1_rd,rec_DF_RAM1_addr,rec_DF_RAM1_din);
|
||||
input clk,reset_n;
|
||||
input disable_DF;
|
||||
input end_of_MB_DEC;
|
||||
input [5:0] DF_edge_counter_MR;
|
||||
input [1:0] one_edge_counter_MR;
|
||||
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input [4:0] blk4x4_rec_counter_2_raster_order;
|
||||
input [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout;
|
||||
|
||||
output [31:0] rec_DF_RAM_dout;
|
||||
output rec_DF_RAM0_wr;
|
||||
output rec_DF_RAM0_rd;
|
||||
output [6:0]rec_DF_RAM0_addr;
|
||||
output [31:0] rec_DF_RAM0_din;
|
||||
output rec_DF_RAM1_wr;
|
||||
output rec_DF_RAM1_rd;
|
||||
output [6:0]rec_DF_RAM1_addr;
|
||||
output [31:0] rec_DF_RAM1_din;
|
||||
|
||||
reg rec_DF_RAM0_wr;
|
||||
reg rec_DF_RAM0_rd;
|
||||
reg [6:0]rec_DF_RAM0_addr;
|
||||
reg [31:0] rec_DF_RAM0_din;
|
||||
reg rec_DF_RAM1_wr;
|
||||
reg rec_DF_RAM1_rd;
|
||||
reg [6:0]rec_DF_RAM1_addr;
|
||||
reg [31:0] rec_DF_RAM1_din;
|
||||
//-----------------------------------------------------------------
|
||||
//Write:after reconstruction
|
||||
//-----------------------------------------------------------------
|
||||
wire rec_DF_RAM_wr;
|
||||
wire [4:0] rec_DF_RAM_wr_addr_blk4x4;
|
||||
wire [1:0] rec_DF_RAM_wr_addr_offset;
|
||||
wire [6:0] rec_DF_RAM_wr_addr;
|
||||
wire [31:0] rec_DF_RAM_din;
|
||||
|
||||
assign rec_DF_RAM_wr = !disable_DF && (blk4x4_sum_counter[2] != 1'b1);
|
||||
assign rec_DF_RAM_wr_addr_blk4x4 = {5{rec_DF_RAM_wr}} & blk4x4_rec_counter_2_raster_order;
|
||||
assign rec_DF_RAM_wr_addr_offset = {2{rec_DF_RAM_wr}} & blk4x4_sum_counter[1:0];
|
||||
assign rec_DF_RAM_wr_addr = {rec_DF_RAM_wr_addr_blk4x4,2'b0} + rec_DF_RAM_wr_addr_offset;
|
||||
assign rec_DF_RAM_din = (rec_DF_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0;
|
||||
//-----------------------------------------------------------------
|
||||
//Read:during deblocking filter
|
||||
//-----------------------------------------------------------------
|
||||
wire rec_DF_RAM_rd;
|
||||
reg [4:0] rec_DF_RAM_rd_addr_blk4x4;
|
||||
wire [1:0] rec_DF_RAM_rd_addr_offset;
|
||||
wire [6:0] rec_DF_RAM_rd_addr;
|
||||
|
||||
assign rec_DF_RAM_rd = ((DF_edge_counter_MR[5] == 1'b0 && (DF_edge_counter_MR[3:0] == 4'd0 ||
|
||||
DF_edge_counter_MR[3:0] == 4'd1 || DF_edge_counter_MR[3:0] == 4'd2 || DF_edge_counter_MR[3:0] == 4'd3 ||
|
||||
DF_edge_counter_MR[3:0] == 4'd6 || DF_edge_counter_MR[3:0] == 4'd7 || DF_edge_counter_MR[3:0] == 4'd10||
|
||||
DF_edge_counter_MR[3:0] == 4'd11)) || (DF_edge_counter_MR[5] == 1'b1 && DF_edge_counter_MR[2] == 1'b0));
|
||||
|
||||
always @ (rec_DF_RAM_rd or DF_edge_counter_MR)
|
||||
if (rec_DF_RAM_rd)
|
||||
case (DF_edge_counter_MR)
|
||||
6'd0 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd0;
|
||||
6'd1 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd1;
|
||||
6'd2 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd4;
|
||||
6'd3 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd5;
|
||||
6'd6 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd2;
|
||||
6'd7 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd6;
|
||||
6'd10:rec_DF_RAM_rd_addr_blk4x4 <= 5'd3;
|
||||
6'd11:rec_DF_RAM_rd_addr_blk4x4 <= 5'd7;
|
||||
6'd16:rec_DF_RAM_rd_addr_blk4x4 <= 5'd8;
|
||||
6'd17:rec_DF_RAM_rd_addr_blk4x4 <= 5'd9;
|
||||
6'd18:rec_DF_RAM_rd_addr_blk4x4 <= 5'd12;
|
||||
6'd19:rec_DF_RAM_rd_addr_blk4x4 <= 5'd13;
|
||||
6'd22:rec_DF_RAM_rd_addr_blk4x4 <= 5'd10;
|
||||
6'd23:rec_DF_RAM_rd_addr_blk4x4 <= 5'd14;
|
||||
6'd26:rec_DF_RAM_rd_addr_blk4x4 <= 5'd11;
|
||||
6'd27:rec_DF_RAM_rd_addr_blk4x4 <= 5'd15;
|
||||
6'd32:rec_DF_RAM_rd_addr_blk4x4 <= 5'd16;
|
||||
6'd33:rec_DF_RAM_rd_addr_blk4x4 <= 5'd17;
|
||||
6'd34:rec_DF_RAM_rd_addr_blk4x4 <= 5'd18;
|
||||
6'd35:rec_DF_RAM_rd_addr_blk4x4 <= 5'd19;
|
||||
6'd40:rec_DF_RAM_rd_addr_blk4x4 <= 5'd20;
|
||||
6'd41:rec_DF_RAM_rd_addr_blk4x4 <= 5'd21;
|
||||
6'd42:rec_DF_RAM_rd_addr_blk4x4 <= 5'd22;
|
||||
6'd43:rec_DF_RAM_rd_addr_blk4x4 <= 5'd23;
|
||||
default:rec_DF_RAM_rd_addr_blk4x4 <= 0;
|
||||
endcase
|
||||
else
|
||||
rec_DF_RAM_rd_addr_blk4x4 <= 0;
|
||||
|
||||
assign rec_DF_RAM_rd_addr_offset = one_edge_counter_MR;
|
||||
assign rec_DF_RAM_rd_addr = {rec_DF_RAM_rd_addr_blk4x4,2'b0} + rec_DF_RAM_rd_addr_offset;
|
||||
|
||||
//----------------------------------------------------------------------------------
|
||||
//Generate control signals for rec_DF_RAM0 & rec_DF_RAM1
|
||||
//----------------------------------------------------------------------------------
|
||||
reg rec_DF_RAM_sel; //0:rec_DF_RAM0 at reconstruction stage
|
||||
//0:rec_DF_RAM1 at DF stage
|
||||
//1:rec_DF_RAM0 at DF stage
|
||||
//1:rec_DF_RAM1 at reconstruction stage
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
rec_DF_RAM_sel <= 1'b0;
|
||||
else if (end_of_MB_DEC)
|
||||
rec_DF_RAM_sel <= ~ rec_DF_RAM_sel;
|
||||
|
||||
assign rec_DF_RAM_dout = (rec_DF_RAM_sel == 1'b0)? rec_DF_RAM1_dout:rec_DF_RAM0_dout;
|
||||
|
||||
always @ (rec_DF_RAM_sel
|
||||
or rec_DF_RAM_wr or rec_DF_RAM_wr_addr or rec_DF_RAM_din
|
||||
or rec_DF_RAM_rd or rec_DF_RAM_rd_addr)
|
||||
case (rec_DF_RAM_sel)
|
||||
1'b0: //rec_DF_RAM0 at reconstruction stage,rec_DF_RAM1 at DF stage
|
||||
begin
|
||||
rec_DF_RAM0_wr <= rec_DF_RAM_wr;
|
||||
rec_DF_RAM0_rd <= 1'b0;
|
||||
rec_DF_RAM0_addr <= rec_DF_RAM_wr_addr;
|
||||
rec_DF_RAM0_din <= rec_DF_RAM_din;
|
||||
|
||||
rec_DF_RAM1_wr <= 1'b0;
|
||||
rec_DF_RAM1_rd <= rec_DF_RAM_rd;
|
||||
rec_DF_RAM1_addr <= rec_DF_RAM_rd_addr;
|
||||
rec_DF_RAM1_din <= 0;
|
||||
end
|
||||
1'b1: //rec_DF_RAM0 at DF stage,rec_DF_RAM1 at reconstruction stage
|
||||
begin
|
||||
rec_DF_RAM0_wr <= 1'b0;
|
||||
rec_DF_RAM0_rd <= rec_DF_RAM_rd;
|
||||
rec_DF_RAM0_addr <= rec_DF_RAM_rd_addr;
|
||||
rec_DF_RAM0_din <= 0;
|
||||
|
||||
rec_DF_RAM1_wr <= rec_DF_RAM_wr;
|
||||
rec_DF_RAM1_rd <= 1'b0;
|
||||
rec_DF_RAM1_addr <= rec_DF_RAM_wr_addr;
|
||||
rec_DF_RAM1_din <= rec_DF_RAM_din;
|
||||
end
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,427 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : rec_gclk_gen.v
|
||||
// Generated : Jan 3, 2006
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Gated clock generation module for reconstruction
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module rec_gclk_gen(clk,
|
||||
//IQIT
|
||||
end_of_NonZeroCoeff_CAVLC,OneD_counter,TwoD_counter,rescale_counter,
|
||||
rounding_counter,residual_state,cavlc_decoder_state,
|
||||
gclk_1D,gclk_2D,gclk_rescale,gclk_rounding,
|
||||
//Intra pred
|
||||
mb_num_h,mb_num_v,NextMB_IsSkip,
|
||||
mb_type_general,blk4x4_rec_counter,blk4x4_sum_counter,blk4x4_intra_preload_counter,
|
||||
blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
|
||||
Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
|
||||
gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,
|
||||
gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
|
||||
//Inter pred
|
||||
blk4x4_inter_preload_counter,gclk_Inter_ref_rf,
|
||||
//sum
|
||||
Inter_blk4x4_pred_output_valid,gclk_pred_output,gclk_blk4x4_sum,
|
||||
//Deblocking filter
|
||||
end_of_MB_DEC,end_of_BS_DEC,DF_duration,
|
||||
gclk_end_of_MB_DEC,gclk_DF,
|
||||
//memory
|
||||
Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_wr,gclk_Intra_mbAddrB_RAM,
|
||||
rec_DF_RAM0_cs_n,gclk_rec_DF_RAM0,
|
||||
rec_DF_RAM1_cs_n,gclk_rec_DF_RAM1,
|
||||
DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,gclk_DF_mbAddrA_RF,
|
||||
DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,gclk_DF_mbAddrB_RAM
|
||||
);
|
||||
input clk;
|
||||
//IQIT
|
||||
input end_of_NonZeroCoeff_CAVLC;
|
||||
input [2:0] OneD_counter;
|
||||
input [2:0] TwoD_counter;
|
||||
input [2:0] rescale_counter;
|
||||
input [2:0] rounding_counter;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
output gclk_1D;
|
||||
output gclk_2D;
|
||||
output gclk_rescale;
|
||||
output gclk_rounding;
|
||||
//Intra pred
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input NextMB_IsSkip;
|
||||
input [3:0] mb_type_general;
|
||||
input [4:0] blk4x4_rec_counter;
|
||||
input [2:0] blk4x4_sum_counter;
|
||||
input [2:0] blk4x4_intra_preload_counter;
|
||||
input [3:0] blk4x4_intra_precompute_counter;
|
||||
input [2:0] blk4x4_intra_calculate_counter;
|
||||
input [3:0] Intra4x4_predmode;
|
||||
input [1:0] Intra16x16_predmode;
|
||||
input [1:0] Intra_chroma_predmode;
|
||||
output gclk_intra_mbAddrA_luma;
|
||||
output gclk_intra_mbAddrA_Cb;
|
||||
output gclk_intra_mbAddrA_Cr;
|
||||
output gclk_intra_mbAddrB;
|
||||
output gclk_intra_mbAddrC_luma;
|
||||
output gclk_intra_mbAddrD;
|
||||
output gclk_seed;
|
||||
//Inter pred
|
||||
input [5:0] blk4x4_inter_preload_counter;
|
||||
output gclk_Inter_ref_rf;
|
||||
//sum
|
||||
input [1:0] Inter_blk4x4_pred_output_valid;
|
||||
output gclk_pred_output;
|
||||
output gclk_blk4x4_sum;
|
||||
//DF
|
||||
input end_of_MB_DEC;
|
||||
input end_of_BS_DEC;
|
||||
input DF_duration;
|
||||
output gclk_end_of_MB_DEC;
|
||||
output gclk_DF;
|
||||
//memory
|
||||
input Intra_mbAddrB_RAM_rd;
|
||||
input Intra_mbAddrB_RAM_wr;
|
||||
output gclk_Intra_mbAddrB_RAM;
|
||||
input rec_DF_RAM0_cs_n;
|
||||
output gclk_rec_DF_RAM0;
|
||||
input rec_DF_RAM1_cs_n;
|
||||
output gclk_rec_DF_RAM1;
|
||||
input DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr;
|
||||
output gclk_DF_mbAddrA_RF;
|
||||
input DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
|
||||
output gclk_DF_mbAddrB_RAM;
|
||||
|
||||
parameter rst_residual = 4'b0000;
|
||||
parameter Intra16x16DCLevel_s = 4'b0001;
|
||||
parameter Intra16x16ACLevel_s = 4'b0011;
|
||||
parameter Intra16x16ACLevel_0_s = 4'b0010;
|
||||
parameter LumaLevel_s = 4'b0110;
|
||||
parameter LumaLevel_0_s = 4'b0111;
|
||||
parameter ChromaDCLevel_Cb_s = 4'b0101;
|
||||
parameter ChromaDCLevel_Cr_s = 4'b0100;
|
||||
parameter ChromaACLevel_Cb_s = 4'b1100;
|
||||
parameter ChromaACLevel_Cr_s = 4'b1101;
|
||||
|
||||
parameter Intra4x4_Vertical = 4'b0000;
|
||||
parameter Intra4x4_Horizontal = 4'b0001;
|
||||
parameter Intra4x4_DC = 4'b0010;
|
||||
parameter Intra4x4_Diagonal_Down_Left = 4'b0011;
|
||||
parameter Intra4x4_Diagonal_Down_Right = 4'b0100;
|
||||
parameter Intra4x4_Vertical_Right = 4'b0101;
|
||||
parameter Intra4x4_Horizontal_Down = 4'b0110;
|
||||
parameter Intra4x4_Vertical_Left = 4'b0111;
|
||||
parameter Intra4x4_Horizontal_Up = 4'b1000;
|
||||
|
||||
parameter Intra16x16_Plane = 2'b11;
|
||||
parameter Intra_chroma_Plane = 2'b11;
|
||||
|
||||
parameter NumCoeffTrailingOnes_LUT = 4'b0010;
|
||||
//-------------------------------------------------
|
||||
//IQIT
|
||||
//-------------------------------------------------
|
||||
//gclk_end_of_one_residual_block
|
||||
//reg l_end_of_one_residual_block;
|
||||
//wire gclk_end_of_one_residual_block;
|
||||
//always @ (clk or end_of_one_residual_block)
|
||||
// if (!clk) l_end_of_one_residual_block <= end_of_one_residual_block;
|
||||
//assign gclk_end_of_one_residual_block = clk & l_end_of_one_residual_block;
|
||||
|
||||
//gclk_endof1NonZeroCoeffResBlk
|
||||
//reg l_end_of_NonZeroCoeff_CAVLC;
|
||||
//wire gclk_endof1NonZeroCoeffResBlk;
|
||||
//always @ (clk or end_of_NonZeroCoeff_CAVLC)
|
||||
// if (!clk) l_end_of_NonZeroCoeff_CAVLC <= end_of_NonZeroCoeff_CAVLC;
|
||||
//assign gclk_endof1NonZeroCoeffResBlk = clk & l_end_of_NonZeroCoeff_CAVLC;
|
||||
|
||||
//gclk_1D
|
||||
wire OneD_en;
|
||||
reg l_OneD_en;
|
||||
wire gclk_1D;
|
||||
assign OneD_en = (
|
||||
// trap DC case after CAVLC:residual_state is still available now
|
||||
(end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT &&
|
||||
(residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
|
||||
residual_state == `ChromaDCLevel_Cr_s)) ||
|
||||
// trap AC case after rescale:residual_state is still available now
|
||||
((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || residual_state == `ChromaACLevel_Cb_s ||
|
||||
residual_state == `ChromaACLevel_Cr_s) && rescale_counter == 3'b100) ||
|
||||
// trap internal loop
|
||||
OneD_counter != 0);
|
||||
always @ (clk or OneD_en)
|
||||
if (!clk) l_OneD_en <= OneD_en;
|
||||
assign gclk_1D = clk & l_OneD_en;
|
||||
|
||||
//gclk_2D
|
||||
wire TwoD_en;
|
||||
reg l_TwoD_en;
|
||||
wire gclk_2D;
|
||||
assign TwoD_en = ((OneD_counter == 3'b001 && residual_state != `ChromaDCLevel_Cb_s && residual_state != `ChromaDCLevel_Cr_s)
|
||||
|| TwoD_counter != 0);
|
||||
always @ (clk or TwoD_en)
|
||||
if (!clk) l_TwoD_en <= TwoD_en;
|
||||
assign gclk_2D = clk & l_TwoD_en;
|
||||
|
||||
//gclk_rescale
|
||||
wire rescale_en;
|
||||
reg l_rescale_en;
|
||||
wire gclk_rescale;
|
||||
assign rescale_en = (
|
||||
//trap AC after CAVLC except all zero coeffs case
|
||||
(end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && (
|
||||
residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
|
||||
residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)) ||
|
||||
//trap DC case after IDCT,chromaDC:after 1D-IDCT,lumaDC:after 2D-IDCT
|
||||
((residual_state == `Intra16x16DCLevel_s && TwoD_counter == 3'b100) ||
|
||||
((residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) && OneD_counter == 3'b001)) ||
|
||||
//trap internal loop
|
||||
rescale_counter != 0);
|
||||
always @ (clk or rescale_en)
|
||||
if (!clk) l_rescale_en <= rescale_en;
|
||||
and gc_rescale (gclk_rescale,clk,l_rescale_en);
|
||||
|
||||
//gclk_rounding
|
||||
wire rounding_en;
|
||||
reg l_rounding_en;
|
||||
wire gclk_rounding;
|
||||
assign rounding_en = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
|
||||
residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && TwoD_counter == 3'b100)
|
||||
|| rounding_counter !=0)?1'b1:1'b0;
|
||||
always @ (clk or rounding_en)
|
||||
if (!clk) l_rounding_en <= rounding_en;
|
||||
assign gclk_rounding = clk & l_rounding_en;
|
||||
//-------------------------------------------------
|
||||
//Intra pred
|
||||
//-------------------------------------------------
|
||||
//1.gclk_intra_mbAddrA_luma @ Intra_pred_reg_ctrl.v
|
||||
// For intra pred,update after every blk4x4 is summed
|
||||
// For inter pred,update after blk4x4 5,7,13,15 is summed
|
||||
wire intra_mbAddrA_luma_ena;
|
||||
reg l_intra_mbAddrA_luma_ena;
|
||||
wire gclk_intra_mbAddrA_luma;
|
||||
wire Is_LumaRightMostBlk4x4;
|
||||
|
||||
assign Is_LumaRightMostBlk4x4 = (blk4x4_rec_counter == 5 || blk4x4_rec_counter == 7 ||
|
||||
blk4x4_rec_counter == 13 || blk4x4_rec_counter == 15);
|
||||
|
||||
assign intra_mbAddrA_luma_ena = (blk4x4_rec_counter < 16 && blk4x4_sum_counter == 3'd3 && (
|
||||
//Intra4x4:update when every blk4x4 summed
|
||||
(mb_type_general[3:2] == 2'b11 && !(mb_num_h == 10 && Is_LumaRightMostBlk4x4)) ||
|
||||
//Intra16x16 && Inter (including skip MB):update when blk4x4 5/7/13/15 is summed
|
||||
//and NextMB_IsSkip is false
|
||||
(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_LumaRightMostBlk4x4 && !NextMB_IsSkip)));
|
||||
always @ (clk or intra_mbAddrA_luma_ena)
|
||||
if (!clk) l_intra_mbAddrA_luma_ena <= intra_mbAddrA_luma_ena;
|
||||
assign gclk_intra_mbAddrA_luma = l_intra_mbAddrA_luma_ena & clk;
|
||||
|
||||
//2.gclk_intra_mbAddrA_Cb @ Intra_pred_reg_ctrl.v
|
||||
wire intra_mbAddrA_Cb_ena;
|
||||
reg l_intra_mbAddrA_Cb_ena;
|
||||
wire gclk_intra_mbAddrA_Cb;
|
||||
wire Is_CbRightMostBlk4x4;
|
||||
assign Is_CbRightMostBlk4x4 = (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 19);
|
||||
|
||||
assign intra_mbAddrA_Cb_ena = (blk4x4_sum_counter == 3'd3 && (
|
||||
//Intra4x4
|
||||
(mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4) ||
|
||||
//Intra16x16 && Inter (including skip MB)
|
||||
(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4 && !NextMB_IsSkip)));
|
||||
always @ (clk or intra_mbAddrA_Cb_ena)
|
||||
if (!clk) l_intra_mbAddrA_Cb_ena <= intra_mbAddrA_Cb_ena;
|
||||
assign gclk_intra_mbAddrA_Cb = l_intra_mbAddrA_Cb_ena & clk;
|
||||
|
||||
//3.gclk_intra_mbAddrA_Cr @ Intra_pred_reg_ctrl.v
|
||||
wire intra_mbAddrA_Cr_ena;
|
||||
reg l_intra_mbAddrA_Cr_ena;
|
||||
wire gclk_intra_mbAddrA_Cr;
|
||||
wire Is_CrRightMostBlk4x4;
|
||||
assign Is_CrRightMostBlk4x4 = (blk4x4_rec_counter == 21 || blk4x4_rec_counter == 23);
|
||||
assign intra_mbAddrA_Cr_ena = (blk4x4_sum_counter == 3'd3 && (
|
||||
//Intra4x4
|
||||
(mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4) ||
|
||||
//Intra16x16 && Inter (including skip MB)
|
||||
(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4 && !NextMB_IsSkip)));
|
||||
always @ (clk or intra_mbAddrA_Cr_ena)
|
||||
if (!clk) l_intra_mbAddrA_Cr_ena <= intra_mbAddrA_Cr_ena;
|
||||
assign gclk_intra_mbAddrA_Cr = l_intra_mbAddrA_Cr_ena & clk;
|
||||
|
||||
//4.gclk_intra_mbAddrB @ Intra_pred_reg_ctrl.v
|
||||
// Control the write of Intra_mbAddrB_reg0 ~ reg 15
|
||||
wire intra_mbAddrB_ena;
|
||||
reg l_intra_mbAddrB_ena;
|
||||
wire gclk_intra_mbAddrB;
|
||||
assign intra_mbAddrB_ena = (
|
||||
// Intra4x4
|
||||
(mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 &&
|
||||
(blk4x4_intra_preload_counter == 1 || blk4x4_sum_counter[2] != 1'b1)) ||
|
||||
// Intra16x16
|
||||
(mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && blk4x4_intra_preload_counter !=0) ||
|
||||
// Intra chroma
|
||||
(mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && blk4x4_intra_preload_counter !=0));
|
||||
always @ (clk or intra_mbAddrB_ena)
|
||||
if (!clk) l_intra_mbAddrB_ena <= intra_mbAddrB_ena;
|
||||
assign gclk_intra_mbAddrB = l_intra_mbAddrB_ena & clk;
|
||||
|
||||
//5.gclk_intra_mbAddrC_luma @ Intra_pred_reg_ctrl.v
|
||||
//1)For blkIdx=0/1/4/5,Intra_mbAddrC_reg are loaded from Intra_mbAddrB_RAM
|
||||
//2)For blkIdx other than 0/1/4/5,Intra_mbAddrC_reg directly obtained from Intra_mbAddrB_reg
|
||||
wire intra_mbAddrC_luma_ena;
|
||||
reg l_intra_mbAddrC_luma_ena;
|
||||
wire gclk_intra_mbAddrC_luma;
|
||||
assign intra_mbAddrC_luma_ena = (mb_type_general[3:2] == 2'b11 && (Intra4x4_predmode == Intra4x4_Diagonal_Down_Left
|
||||
|| Intra4x4_predmode == Intra4x4_Vertical_Left) && blk4x4_intra_preload_counter == 3'b010);
|
||||
always @ (clk or intra_mbAddrC_luma_ena)
|
||||
if (!clk) l_intra_mbAddrC_luma_ena <= intra_mbAddrC_luma_ena;
|
||||
assign gclk_intra_mbAddrC_luma = l_intra_mbAddrC_luma_ena & clk;
|
||||
|
||||
//6.gclk_intra_mbAddrD @ Intra_pred_reg_ctrl.v
|
||||
//1)For Intra4x4 blkIdx=1/4/5 or Intra16x16 & Chrom plane mode,Intra mbAddrD regs are loaded from
|
||||
// Intra_mbAddrB_RAM.
|
||||
//2)For blkIdx other than 1/4/5,Intra mbAddrD reg are updated during sum
|
||||
wire intra_mbAddrD_ena;
|
||||
reg l_intra_mbAddrD_ena;
|
||||
wire gclk_intra_mbAddrD;
|
||||
assign intra_mbAddrD_ena = (
|
||||
//1.Update when blkIdx = 15,19,23,from Intra_mbAddrB_RAM
|
||||
// In reality,sum_counter = 0/1/2/3 are all OK for update,we choose sum_counter = 0 here
|
||||
(blk4x4_sum_counter == 3'd1 && mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip &&
|
||||
(blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23)) ||
|
||||
(mb_type_general[3:2] == 2'b11 && (
|
||||
//2.For blk4x4 1/4/5 mbAddrD reg update from Intra_mbAddrB_RAM
|
||||
(blk4x4_intra_preload_counter == 3'b010 &&
|
||||
(Intra4x4_predmode == Intra4x4_Diagonal_Down_Right || Intra4x4_predmode == Intra4x4_Vertical_Right
|
||||
|| Intra4x4_predmode == Intra4x4_Horizontal_Down)) ||
|
||||
//3.For other blk4x4 mbAddrD reg update from sum output
|
||||
(blk4x4_sum_counter == 3'd3 && (
|
||||
blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 ||
|
||||
blk4x4_rec_counter == 2 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 6 ||
|
||||
blk4x4_rec_counter == 8 || blk4x4_rec_counter == 9 || blk4x4_rec_counter == 12)))));
|
||||
always @ (clk or intra_mbAddrD_ena)
|
||||
if (!clk) l_intra_mbAddrD_ena <= intra_mbAddrD_ena;
|
||||
assign gclk_intra_mbAddrD = l_intra_mbAddrD_ena & clk;
|
||||
|
||||
//7.gclk_seed @ Intra_pred_reg_ctrl.v
|
||||
wire seed_ena;
|
||||
reg l_seed_ena;
|
||||
wire gclk_seed;
|
||||
//assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ((Intra16x16_predmode == Intra16x16_Plane ||
|
||||
//Intra_chroma_predmode == Intra_chroma_Plane) && blk4x4_intra_calculate_counter == 3));
|
||||
|
||||
assign seed_ena = (blk4x4_intra_precompute_counter == 1 || (
|
||||
(Intra16x16_predmode == Intra16x16_Plane && (
|
||||
((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8) &&
|
||||
blk4x4_intra_calculate_counter == 3'b100) ||
|
||||
((blk4x4_rec_counter == 1 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 9 ||
|
||||
blk4x4_rec_counter == 11) && blk4x4_intra_calculate_counter == 3'b001))) ||
|
||||
(Intra_chroma_predmode == Intra_chroma_Plane && (
|
||||
(blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_calculate_counter == 3'b100))));
|
||||
|
||||
always @ (clk or seed_ena)
|
||||
if (!clk) l_seed_ena <= seed_ena;
|
||||
assign gclk_seed = l_seed_ena & clk;
|
||||
|
||||
//-------------------------------------------------
|
||||
//Inter pred
|
||||
//-------------------------------------------------
|
||||
wire Inter_ref_rf_ena;
|
||||
reg l_Inter_ref_rf_ena;
|
||||
wire gclk_Inter_ref_rf;
|
||||
assign Inter_ref_rf_ena = (blk4x4_inter_preload_counter == 0)? 1'b0:1'b1;
|
||||
always @ (clk or Inter_ref_rf_ena)
|
||||
if (!clk) l_Inter_ref_rf_ena <= Inter_ref_rf_ena;
|
||||
assign gclk_Inter_ref_rf = l_Inter_ref_rf_ena & clk;
|
||||
|
||||
//-------------------------------------------------
|
||||
//sum
|
||||
//-------------------------------------------------
|
||||
//1.gclk_pred_output
|
||||
wire pred_output_ena;
|
||||
reg l_pred_output_ena;
|
||||
wire gclk_pred_output;
|
||||
assign pred_output_ena = (blk4x4_intra_calculate_counter != 0 || Inter_blk4x4_pred_output_valid != 0)? 1'b1:1'b0;
|
||||
always @ (clk or pred_output_ena)
|
||||
if (!clk) l_pred_output_ena <= pred_output_ena;
|
||||
assign gclk_pred_output = l_pred_output_ena & clk;
|
||||
|
||||
//2.gclk_blk4x4_sum
|
||||
wire blk4x4_sum_ena;
|
||||
reg l_blk4x4_sum_ena;
|
||||
wire gclk_blk4x4_sum;
|
||||
assign blk4x4_sum_ena = (blk4x4_sum_counter[2] != 1'b1);
|
||||
always @ (clk or blk4x4_sum_ena)
|
||||
if (!clk) l_blk4x4_sum_ena <= blk4x4_sum_ena;
|
||||
assign gclk_blk4x4_sum = l_blk4x4_sum_ena & clk;
|
||||
|
||||
//-------------------------------------------------
|
||||
//deblocking filter
|
||||
//-------------------------------------------------
|
||||
//1.gclk_end_of_MB_DEC
|
||||
reg l_end_of_MB_DEC;
|
||||
wire gclk_end_of_MB_DEC;
|
||||
always @ (clk or end_of_MB_DEC)
|
||||
if (!clk) l_end_of_MB_DEC <= end_of_MB_DEC;
|
||||
assign gclk_end_of_MB_DEC = l_end_of_MB_DEC & clk;
|
||||
//2.gclk_DF
|
||||
wire DF_ena;
|
||||
reg l_DF_ena;
|
||||
assign DF_ena = DF_duration | end_of_BS_DEC;
|
||||
always @ (clk or DF_ena)
|
||||
if (!clk) l_DF_ena <= DF_ena;
|
||||
assign gclk_DF = l_DF_ena & clk;
|
||||
|
||||
//-------------------------------------------------
|
||||
//memory
|
||||
//-------------------------------------------------
|
||||
//gclk_Intra_mbAddrB_RAM
|
||||
wire Intra_mbAddrB_RAM_ena;
|
||||
reg l_Intra_mbAddrB_RAM_ena;
|
||||
wire gclk_Intra_mbAddrB_RAM;
|
||||
assign Intra_mbAddrB_RAM_ena = Intra_mbAddrB_RAM_rd | Intra_mbAddrB_RAM_wr;
|
||||
always @ (clk or Intra_mbAddrB_RAM_ena)
|
||||
if (!clk) l_Intra_mbAddrB_RAM_ena <= Intra_mbAddrB_RAM_ena;
|
||||
assign gclk_Intra_mbAddrB_RAM = clk & l_Intra_mbAddrB_RAM_ena;
|
||||
|
||||
//gclk_rec_DF_RAM0
|
||||
reg l_rec_DF_RAM0_ena;
|
||||
wire gclk_rec_DF_RAM0;
|
||||
always @ (clk or rec_DF_RAM0_cs_n)
|
||||
if (!clk) l_rec_DF_RAM0_ena <= !rec_DF_RAM0_cs_n;
|
||||
assign gclk_rec_DF_RAM0 = clk & l_rec_DF_RAM0_ena;
|
||||
|
||||
//gclk_rec_DF_RAM1
|
||||
reg l_rec_DF_RAM1_ena;
|
||||
wire gclk_rec_DF_RAM1;
|
||||
always @ (clk or rec_DF_RAM1_cs_n)
|
||||
if (!clk) l_rec_DF_RAM1_ena <= !rec_DF_RAM1_cs_n;
|
||||
assign gclk_rec_DF_RAM1 = clk & l_rec_DF_RAM1_ena;
|
||||
|
||||
//gclk_DF_mbAddrA_RF
|
||||
wire DF_mbAddrA_RF_ena;
|
||||
reg l_DF_mbAddrA_RF_ena;
|
||||
wire gclk_DF_mbAddrA_RF;
|
||||
assign DF_mbAddrA_RF_ena = DF_mbAddrA_RF_rd | DF_mbAddrA_RF_wr;
|
||||
always @ (clk or DF_mbAddrA_RF_ena)
|
||||
if (!clk) l_DF_mbAddrA_RF_ena <= DF_mbAddrA_RF_ena;
|
||||
assign gclk_DF_mbAddrA_RF = clk & l_DF_mbAddrA_RF_ena;
|
||||
|
||||
//gclk_DF_mbAddrB_RAM
|
||||
wire DF_mbAddrB_RAM_ena;
|
||||
reg l_DF_mbAddrB_RAM_ena;
|
||||
wire gclk_DF_mbAddrB_RAM;
|
||||
assign DF_mbAddrB_RAM_ena = DF_mbAddrB_RAM_rd | DF_mbAddrB_RAM_wr;
|
||||
always @ (clk or DF_mbAddrB_RAM_ena)
|
||||
if (!clk) l_DF_mbAddrB_RAM_ena <= DF_mbAddrB_RAM_ena;
|
||||
assign gclk_DF_mbAddrB_RAM = clk & l_DF_mbAddrB_RAM_ena;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,626 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : reconstruction.v
|
||||
// Generated : Jan 3,2006
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// reconstruction top module,including:
|
||||
// rec_gclk_gen
|
||||
// hybrid_pipeline_ctrl
|
||||
// IQIT
|
||||
// Intra_pred_top
|
||||
// sum
|
||||
// DF_top
|
||||
// rec_DF_RAM_ctrl
|
||||
// rec_DF_RAM0
|
||||
// rec_DF_RAM1
|
||||
// ext_RAM_ctrl
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module reconstruction (clk,reset_n,mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip,
|
||||
slice_data_state,residual_state,cavlc_decoder_state,
|
||||
end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame,
|
||||
Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
|
||||
QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
|
||||
CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff,Is_skip_run_entry,
|
||||
skip_mv_calc,disable_DF,
|
||||
|
||||
coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7,
|
||||
coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15,
|
||||
mv_is16x16,mv_below8x8,
|
||||
mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
|
||||
end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
|
||||
|
||||
trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,
|
||||
end_of_MB_DEC,gclk_end_of_MB_DEC,curr_DC_IsZero,
|
||||
ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
|
||||
ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data,
|
||||
dis_frame_RAM_din
|
||||
);
|
||||
input clk;
|
||||
input reset_n;
|
||||
input [3:0] mb_type_general;
|
||||
input [3:0] mb_num_h;
|
||||
input [3:0] mb_num_v;
|
||||
input NextMB_IsSkip;
|
||||
input LowerMB_IsSkip;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input end_of_one_residual_block;
|
||||
input end_of_NonZeroCoeff_CAVLC;
|
||||
input end_of_one_frame;
|
||||
input [1:0] Intra16x16_predmode;
|
||||
input [63:0] Intra4x4_predmode_CurrMb;
|
||||
input [1:0] Intra_chroma_predmode;
|
||||
input [5:0] QPy;
|
||||
input [5:0] QPc;
|
||||
input [1:0] i4x4_CbCr;
|
||||
input [3:0] slice_alpha_c0_offset_div2;
|
||||
input [3:0] slice_beta_offset_div2;
|
||||
input [3:0] CodedBlockPatternLuma;
|
||||
input [1:0] CodedBlockPatternChroma;
|
||||
input [4:0] TotalCoeff;
|
||||
input Is_skip_run_entry;
|
||||
input skip_mv_calc;
|
||||
input disable_DF;
|
||||
input [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5;
|
||||
input [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
|
||||
input [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
|
||||
input mv_is16x16;
|
||||
input [3:0] mv_below8x8;
|
||||
input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
|
||||
input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
|
||||
input end_of_BS_DEC;
|
||||
input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
|
||||
input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
|
||||
input [31:0] ext_frame_RAM0_data;
|
||||
input [31:0] ext_frame_RAM1_data;
|
||||
|
||||
output trigger_CAVLC;
|
||||
output [4:0] blk4x4_rec_counter;
|
||||
output end_of_DCBlk_IQIT;
|
||||
output end_of_one_blk4x4_sum;
|
||||
output end_of_MB_DEC;
|
||||
output gclk_end_of_MB_DEC;
|
||||
output curr_DC_IsZero;
|
||||
|
||||
output ext_frame_RAM0_cs_n;
|
||||
output ext_frame_RAM0_wr;
|
||||
output [13:0] ext_frame_RAM0_addr;
|
||||
|
||||
output ext_frame_RAM1_cs_n;
|
||||
output ext_frame_RAM1_wr;
|
||||
output [13:0] ext_frame_RAM1_addr;
|
||||
|
||||
output [31:0] dis_frame_RAM_din;
|
||||
|
||||
wire gclk_endof1resblk;
|
||||
wire gclk_1D;
|
||||
wire gclk_2D;
|
||||
wire gclk_rescale;
|
||||
wire gclk_rounding;
|
||||
wire gclk_intra_mbAddrA_luma;
|
||||
wire gclk_intra_mbAddrA_Cb;
|
||||
wire gclk_intra_mbAddrA_Cr;
|
||||
wire gclk_intra_mbAddrB;
|
||||
wire gclk_intra_mbAddrC_luma;
|
||||
wire gclk_intra_mbAddrD;
|
||||
wire gclk_seed;
|
||||
wire gclk_Inter_ref_rf;
|
||||
wire gclk_pred_output;
|
||||
wire gclk_blk4x4_sum;
|
||||
wire gclk_DF;
|
||||
wire gclk_end_of_MB_DEC;
|
||||
|
||||
wire curr_CBPLuma_IsZero;
|
||||
wire curr_DC_IsZero;
|
||||
wire end_of_ACBlk4x4_IQIT;
|
||||
wire end_of_one_blk4x4_intra;
|
||||
wire end_of_one_blk4x4_inter;
|
||||
wire end_of_one_blk4x4_sum;
|
||||
wire end_of_MB_DF;
|
||||
wire end_of_MB_DEC;
|
||||
wire trigger_blk4x4_intra_pred;
|
||||
wire trigger_blk4x4_inter_pred;
|
||||
wire trigger_blk4x4_rec_sum;
|
||||
wire [15:0] res_luma_DConly;
|
||||
wire res_chroma_DConly;
|
||||
wire res_AC;
|
||||
wire res_DC;
|
||||
wire res_luma;
|
||||
wire [2:0] OneD_counter;
|
||||
wire [2:0] TwoD_counter;
|
||||
wire [2:0] rescale_counter;
|
||||
wire [2:0] rounding_counter;
|
||||
wire [2:0] blk4x4_intra_preload_counter;
|
||||
wire [3:0] blk4x4_intra_precompute_counter;
|
||||
wire [2:0] blk4x4_intra_calculate_counter;
|
||||
wire [5:0] blk4x4_inter_preload_counter;
|
||||
wire [3:0] blk4x4_inter_calculate_counter;
|
||||
wire [1:0] Inter_chroma2x2_counter;
|
||||
wire [4:0] blk4x4_rec_counter;
|
||||
wire [2:0] blk4x4_sum_counter;
|
||||
wire [4:0] blk4x4_rec_counter_2_raster_order;
|
||||
wire [5:0] DF_edge_counter_MR;
|
||||
wire [1:0] one_edge_counter_MR;
|
||||
wire [1:0] Inter_blk4x4_pred_output_valid;
|
||||
wire mv_below8x8_curr;
|
||||
wire [3:0] pos_FracL;
|
||||
|
||||
wire [3:0] Intra4x4_predmode;
|
||||
wire [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3;
|
||||
wire [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7;
|
||||
wire [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11;
|
||||
wire [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15;
|
||||
wire [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out;
|
||||
wire [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
|
||||
wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
wire [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
|
||||
wire [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
|
||||
wire [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
|
||||
wire [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
|
||||
wire [8:0] curr_DC_scaled;
|
||||
wire [23:0] sum_right_column_reg;
|
||||
|
||||
wire DF_duration;
|
||||
wire gclk_Intra_mbAddrB_RAM;
|
||||
wire Intra_mbAddrB_RAM_rd;
|
||||
wire Intra_mbAddrB_RAM_wr;
|
||||
wire [6:0] Intra_mbAddrB_RAM_rd_addr,Intra_mbAddrB_RAM_wr_addr;
|
||||
wire [31:0] Intra_mbAddrB_RAM_din;
|
||||
wire [31:0] Intra_mbAddrB_RAM_dout;
|
||||
wire gclk_DF_mbAddrA_RF;
|
||||
wire DF_mbAddrA_RF_rd;
|
||||
wire DF_mbAddrA_RF_wr;
|
||||
wire [4:0] DF_mbAddrA_RF_rd_addr;
|
||||
wire [4:0] DF_mbAddrA_RF_wr_addr;
|
||||
wire [31:0] DF_mbAddrA_RF_din;
|
||||
wire [31:0] DF_mbAddrA_RF_dout;
|
||||
wire gclk_DF_mbAddrB_RAM;
|
||||
wire DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
|
||||
wire [8:0] DF_mbAddrB_RAM_addr;
|
||||
wire [31:0] DF_mbAddrB_RAM_din;
|
||||
wire [31:0] DF_mbAddrB_RAM_dout;
|
||||
wire gclk_rec_DF_RAM0,gclk_rec_DF_RAM1;
|
||||
wire [31:0] rec_DF_RAM_dout;
|
||||
wire rec_DF_RAM0_wr,rec_DF_RAM1_wr;
|
||||
wire rec_DF_RAM0_rd,rec_DF_RAM1_rd;
|
||||
wire [6:0] rec_DF_RAM0_addr,rec_DF_RAM1_addr;
|
||||
wire [31:0] rec_DF_RAM0_din,rec_DF_RAM1_din;
|
||||
wire [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout;
|
||||
wire dis_frame_RAM_wr;
|
||||
wire [13:0] dis_frame_RAM_wr_addr;
|
||||
wire [31:0] dis_frame_RAM_din;
|
||||
wire ref_frame_RAM_rd;
|
||||
wire [13:0] ref_frame_RAM_rd_addr;
|
||||
wire [31:0] ref_frame_RAM_dout;
|
||||
|
||||
|
||||
rec_gclk_gen rec_gclk_gen (
|
||||
.clk(clk),
|
||||
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
|
||||
.OneD_counter(OneD_counter),
|
||||
.TwoD_counter(TwoD_counter),
|
||||
.rescale_counter(rescale_counter),
|
||||
.rounding_counter(rounding_counter),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.gclk_1D(gclk_1D),
|
||||
.gclk_2D(gclk_2D),
|
||||
.gclk_rescale(gclk_rescale),
|
||||
.gclk_rounding(gclk_rounding),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.NextMB_IsSkip(NextMB_IsSkip),
|
||||
.mb_type_general(mb_type_general),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
||||
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
||||
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
||||
.Intra4x4_predmode(Intra4x4_predmode),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
|
||||
.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
|
||||
.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
|
||||
.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
|
||||
.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
|
||||
.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
|
||||
.gclk_seed(gclk_seed),
|
||||
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter),
|
||||
.gclk_Inter_ref_rf(gclk_Inter_ref_rf),
|
||||
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
|
||||
.gclk_pred_output(gclk_pred_output),
|
||||
.gclk_blk4x4_sum(gclk_blk4x4_sum),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.end_of_BS_DEC(end_of_BS_DEC),
|
||||
.DF_duration(DF_duration),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.gclk_DF(gclk_DF),
|
||||
.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd),
|
||||
.Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr),
|
||||
.gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM),
|
||||
.rec_DF_RAM0_cs_n(rec_DF_RAM0_cs_n),
|
||||
.gclk_rec_DF_RAM0(gclk_rec_DF_RAM0),
|
||||
.rec_DF_RAM1_cs_n(rec_DF_RAM1_cs_n),
|
||||
.gclk_rec_DF_RAM1(gclk_rec_DF_RAM1),
|
||||
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
|
||||
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
|
||||
.gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF),
|
||||
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
||||
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
||||
.gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM)
|
||||
);
|
||||
hybrid_pipeline_ctrl hybrid_pipeline_ctrl (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.mb_type_general(mb_type_general),
|
||||
.slice_data_state(slice_data_state),
|
||||
.residual_state(residual_state),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.Is_skip_run_entry(Is_skip_run_entry),
|
||||
.skip_mv_calc(skip_mv_calc),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
|
||||
.end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT),
|
||||
.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
|
||||
.end_of_one_blk4x4_inter(end_of_one_blk4x4_inter),
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.end_of_MB_DF(end_of_MB_DF),
|
||||
.disable_DF(disable_DF),
|
||||
|
||||
.curr_CBPLuma_IsZero(curr_CBPLuma_IsZero),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.trigger_CAVLC(trigger_CAVLC),
|
||||
.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
|
||||
.trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred),
|
||||
.trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum)
|
||||
);
|
||||
IQIT IQIT (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.gclk_1D(gclk_1D),
|
||||
.gclk_2D(gclk_2D),
|
||||
.gclk_rescale(gclk_rescale),
|
||||
.gclk_rounding(gclk_rounding),
|
||||
.residual_state(residual_state),
|
||||
.cavlc_decoder_state(cavlc_decoder_state),
|
||||
.end_of_one_residual_block(end_of_one_residual_block),
|
||||
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
|
||||
.QPy(QPy),
|
||||
.QPc(QPc),
|
||||
.i4x4_CbCr(i4x4_CbCr),
|
||||
.coeffLevel_ext_0({{7{coeffLevel_0[8]}},coeffLevel_0}),
|
||||
.coeffLevel_ext_1({{7{coeffLevel_1[8]}},coeffLevel_1}),
|
||||
.coeffLevel_ext_2({{7{coeffLevel_2[8]}},coeffLevel_2}),
|
||||
.coeffLevel_ext_3({{7{coeffLevel_3[8]}},coeffLevel_3}),
|
||||
.coeffLevel_ext_4({{7{coeffLevel_4[8]}},coeffLevel_4}),
|
||||
.coeffLevel_ext_5({{7{coeffLevel_5[8]}},coeffLevel_5}),
|
||||
.coeffLevel_ext_6({{7{coeffLevel_6[8]}},coeffLevel_6}),
|
||||
.coeffLevel_ext_7({{7{coeffLevel_7[8]}},coeffLevel_7}),
|
||||
.coeffLevel_ext_8({{7{coeffLevel_8[8]}},coeffLevel_8}),
|
||||
.coeffLevel_ext_9({{7{coeffLevel_9[8]}},coeffLevel_9}),
|
||||
.coeffLevel_ext_10({{7{coeffLevel_10[8]}},coeffLevel_10}),
|
||||
.coeffLevel_ext_11({{7{coeffLevel_11[8]}},coeffLevel_11}),
|
||||
.coeffLevel_ext_12({{7{coeffLevel_12[8]}},coeffLevel_12}),
|
||||
.coeffLevel_ext_13({{7{coeffLevel_13[8]}},coeffLevel_13}),
|
||||
.coeffLevel_ext_14({{7{coeffLevel_14[8]}},coeffLevel_14}),
|
||||
.coeffLevel_ext_15({{7{coeffLevel_15[8]}},coeffLevel_15}),
|
||||
|
||||
.OneD_counter(OneD_counter),
|
||||
.TwoD_counter(TwoD_counter),
|
||||
.rescale_counter(rescale_counter),
|
||||
.rounding_counter(rounding_counter),
|
||||
.curr_DC_IsZero(curr_DC_IsZero),
|
||||
.curr_DC_scaled(curr_DC_scaled),
|
||||
.rounding_output_0(IQIT_output_0),
|
||||
.rounding_output_1(IQIT_output_1),
|
||||
.rounding_output_2(IQIT_output_2),
|
||||
.rounding_output_3(IQIT_output_3),
|
||||
.rounding_output_4(IQIT_output_4),
|
||||
.rounding_output_5(IQIT_output_5),
|
||||
.rounding_output_6(IQIT_output_6),
|
||||
.rounding_output_7(IQIT_output_7),
|
||||
.rounding_output_8(IQIT_output_8),
|
||||
.rounding_output_9(IQIT_output_9),
|
||||
.rounding_output_10(IQIT_output_10),
|
||||
.rounding_output_11(IQIT_output_11),
|
||||
.rounding_output_12(IQIT_output_12),
|
||||
.rounding_output_13(IQIT_output_13),
|
||||
.rounding_output_14(IQIT_output_14),
|
||||
.rounding_output_15(IQIT_output_15),
|
||||
.end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT),
|
||||
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT)
|
||||
);
|
||||
Intra_pred_top Intra_pred_top (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
|
||||
.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
|
||||
.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
|
||||
.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
|
||||
.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
|
||||
.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
|
||||
.gclk_seed(gclk_seed),
|
||||
.gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.mb_type_general(mb_type_general),
|
||||
.NextMB_IsSkip(NextMB_IsSkip),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.sum_right_column_reg(sum_right_column_reg),
|
||||
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
||||
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
||||
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
||||
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
||||
.blk4x4_pred_output0(blk4x4_pred_output0),
|
||||
.blk4x4_pred_output1(blk4x4_pred_output1),
|
||||
.blk4x4_pred_output2(blk4x4_pred_output2),
|
||||
.blk4x4_pred_output4(blk4x4_pred_output4),
|
||||
.blk4x4_pred_output5(blk4x4_pred_output5),
|
||||
.blk4x4_pred_output6(blk4x4_pred_output6),
|
||||
.blk4x4_pred_output8(blk4x4_pred_output8),
|
||||
.blk4x4_pred_output9(blk4x4_pred_output9),
|
||||
.blk4x4_pred_output10(blk4x4_pred_output10),
|
||||
.blk4x4_pred_output12(blk4x4_pred_output12),
|
||||
.blk4x4_pred_output13(blk4x4_pred_output13),
|
||||
.blk4x4_pred_output14(blk4x4_pred_output14),
|
||||
.Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr),
|
||||
.Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
||||
.Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din),
|
||||
|
||||
.PE0_out(Intra_pred_PE0_out),
|
||||
.PE1_out(Intra_pred_PE1_out),
|
||||
.PE2_out(Intra_pred_PE2_out),
|
||||
.PE3_out(Intra_pred_PE3_out),
|
||||
.Intra4x4_predmode(Intra4x4_predmode),
|
||||
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
||||
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
||||
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
||||
.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
|
||||
.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd)
|
||||
);
|
||||
Inter_pred_top Inter_pred_top (
|
||||
.clk(clk),
|
||||
.gclk_Inter_ref_rf(gclk_Inter_ref_rf),
|
||||
.reset_n(reset_n),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.mb_type_general_bit3(mb_type_general[3]),
|
||||
.mv_is16x16(mv_is16x16),
|
||||
.mv_below8x8(mv_below8x8),
|
||||
.mvx_CurrMb0(mvx_CurrMb0),
|
||||
.mvx_CurrMb1(mvx_CurrMb1),
|
||||
.mvx_CurrMb2(mvx_CurrMb2),
|
||||
.mvx_CurrMb3(mvx_CurrMb3),
|
||||
.mvy_CurrMb0(mvy_CurrMb0),
|
||||
.mvy_CurrMb1(mvy_CurrMb1),
|
||||
.mvy_CurrMb2(mvy_CurrMb2),
|
||||
.mvy_CurrMb3(mvy_CurrMb3),
|
||||
.ref_frame_RAM_dout(ref_frame_RAM_dout),
|
||||
|
||||
.Inter_pred_out0(Inter_pred_out0),
|
||||
.Inter_pred_out1(Inter_pred_out1),
|
||||
.Inter_pred_out2(Inter_pred_out2),
|
||||
.Inter_pred_out3(Inter_pred_out3),
|
||||
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter),
|
||||
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
||||
.Inter_chroma2x2_counter(Inter_chroma2x2_counter),
|
||||
.mv_below8x8_curr(mv_below8x8_curr),
|
||||
.pos_FracL(pos_FracL),
|
||||
.end_of_one_blk4x4_inter(end_of_one_blk4x4_inter),
|
||||
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
|
||||
.ref_frame_RAM_rd(ref_frame_RAM_rd),
|
||||
.ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr)
|
||||
);
|
||||
sum sum (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.slice_data_state(slice_data_state),
|
||||
.residual_state(residual_state),
|
||||
.TotalCoeff(TotalCoeff),
|
||||
.curr_CBPLuma_IsZero(curr_CBPLuma_IsZero),
|
||||
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
||||
.curr_DC_IsZero(curr_DC_IsZero),
|
||||
.curr_DC_scaled(curr_DC_scaled),
|
||||
.gclk_pred_output(gclk_pred_output),
|
||||
.gclk_blk4x4_sum(gclk_blk4x4_sum),
|
||||
.trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum),
|
||||
.IQIT_output_0(IQIT_output_0),
|
||||
.IQIT_output_1(IQIT_output_1),
|
||||
.IQIT_output_2(IQIT_output_2),
|
||||
.IQIT_output_3(IQIT_output_3),
|
||||
.IQIT_output_4(IQIT_output_4),
|
||||
.IQIT_output_5(IQIT_output_5),
|
||||
.IQIT_output_6(IQIT_output_6),
|
||||
.IQIT_output_7(IQIT_output_7),
|
||||
.IQIT_output_8(IQIT_output_8),
|
||||
.IQIT_output_9(IQIT_output_9),
|
||||
.IQIT_output_10(IQIT_output_10),
|
||||
.IQIT_output_11(IQIT_output_11),
|
||||
.IQIT_output_12(IQIT_output_12),
|
||||
.IQIT_output_13(IQIT_output_13),
|
||||
.IQIT_output_14(IQIT_output_14),
|
||||
.IQIT_output_15(IQIT_output_15),
|
||||
.mb_type_general(mb_type_general),
|
||||
.Intra4x4_predmode(Intra4x4_predmode),
|
||||
.Intra16x16_predmode(Intra16x16_predmode),
|
||||
.Intra_chroma_predmode(Intra_chroma_predmode),
|
||||
.Intra_pred_PE0_out(Intra_pred_PE0_out),
|
||||
.Intra_pred_PE1_out(Intra_pred_PE1_out),
|
||||
.Intra_pred_PE2_out(Intra_pred_PE2_out),
|
||||
.Intra_pred_PE3_out(Intra_pred_PE3_out),
|
||||
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
||||
.Inter_pred_out0(Inter_pred_out0),
|
||||
.Inter_pred_out1(Inter_pred_out1),
|
||||
.Inter_pred_out2(Inter_pred_out2),
|
||||
.Inter_pred_out3(Inter_pred_out3),
|
||||
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
||||
.Inter_chroma2x2_counter(Inter_chroma2x2_counter),
|
||||
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
|
||||
.mv_below8x8_curr(mv_below8x8_curr),
|
||||
.pos_FracL(pos_FracL),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.LowerMB_IsSkip(LowerMB_IsSkip),
|
||||
|
||||
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.blk4x4_rec_counter(blk4x4_rec_counter),
|
||||
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
||||
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
||||
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
||||
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
||||
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
||||
.sum_right_column_reg(sum_right_column_reg),
|
||||
.blk4x4_pred_output0(blk4x4_pred_output0),
|
||||
.blk4x4_pred_output1(blk4x4_pred_output1),
|
||||
.blk4x4_pred_output2(blk4x4_pred_output2),
|
||||
.blk4x4_pred_output4(blk4x4_pred_output4),
|
||||
.blk4x4_pred_output5(blk4x4_pred_output5),
|
||||
.blk4x4_pred_output6(blk4x4_pred_output6),
|
||||
.blk4x4_pred_output8(blk4x4_pred_output8),
|
||||
.blk4x4_pred_output9(blk4x4_pred_output9),
|
||||
.blk4x4_pred_output10(blk4x4_pred_output10),
|
||||
.blk4x4_pred_output12(blk4x4_pred_output12),
|
||||
.blk4x4_pred_output13(blk4x4_pred_output13),
|
||||
.blk4x4_pred_output14(blk4x4_pred_output14),
|
||||
.Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr),
|
||||
.Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
||||
.Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din)
|
||||
);
|
||||
DF_top DF_top (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.gclk_DF(gclk_DF),
|
||||
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
||||
.gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF),
|
||||
.gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM),
|
||||
.end_of_BS_DEC(end_of_BS_DEC),
|
||||
.disable_DF(disable_DF),
|
||||
.mb_num_h(mb_num_h),
|
||||
.mb_num_v(mb_num_v),
|
||||
.bs_V0(bs_V0),
|
||||
.bs_V1(bs_V1),
|
||||
.bs_V2(bs_V2),
|
||||
.bs_V3(bs_V3),
|
||||
.bs_H0(bs_H0),
|
||||
.bs_H1(bs_H1),
|
||||
.bs_H2(bs_H2),
|
||||
.bs_H3(bs_H3),
|
||||
.QPy(QPy),
|
||||
.QPc(QPc),
|
||||
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
|
||||
.slice_beta_offset_div2(slice_beta_offset_div2),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
||||
.rec_DF_RAM_dout(rec_DF_RAM_dout),
|
||||
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
||||
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
||||
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
||||
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
||||
|
||||
.DF_duration(DF_duration),
|
||||
.end_of_MB_DF(end_of_MB_DF),
|
||||
.DF_edge_counter_MR(DF_edge_counter_MR),
|
||||
.one_edge_counter_MR(one_edge_counter_MR),
|
||||
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
|
||||
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
|
||||
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
||||
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
||||
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
||||
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
||||
.dis_frame_RAM_din(dis_frame_RAM_din)
|
||||
);
|
||||
rec_DF_RAM_ctrl rec_DF_RAM_ctrl (
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.disable_DF(disable_DF),
|
||||
.end_of_MB_DEC(end_of_MB_DEC),
|
||||
.DF_edge_counter_MR(DF_edge_counter_MR),
|
||||
.one_edge_counter_MR(one_edge_counter_MR),
|
||||
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
||||
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
||||
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
||||
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
||||
.blk4x4_sum_counter(blk4x4_sum_counter),
|
||||
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
||||
.rec_DF_RAM0_dout(rec_DF_RAM0_dout),
|
||||
.rec_DF_RAM1_dout(rec_DF_RAM1_dout),
|
||||
|
||||
.rec_DF_RAM_dout(rec_DF_RAM_dout),
|
||||
.rec_DF_RAM0_wr(rec_DF_RAM0_wr),
|
||||
.rec_DF_RAM0_rd(rec_DF_RAM0_rd),
|
||||
.rec_DF_RAM0_addr(rec_DF_RAM0_addr),
|
||||
.rec_DF_RAM0_din(rec_DF_RAM0_din),
|
||||
.rec_DF_RAM1_wr(rec_DF_RAM1_wr),
|
||||
.rec_DF_RAM1_rd(rec_DF_RAM1_rd),
|
||||
.rec_DF_RAM1_addr(rec_DF_RAM1_addr),
|
||||
.rec_DF_RAM1_din(rec_DF_RAM1_din)
|
||||
);
|
||||
ram_sync_1r_sync_1w #(`rec_DF_RAM0_data_width,`rec_DF_RAM0_data_depth)
|
||||
rec_DF_RAM0 (
|
||||
.clk(gclk_rec_DF_RAM0),
|
||||
.rst_n(reset_n),
|
||||
.wr_n(~rec_DF_RAM0_wr),
|
||||
.rd_n(~rec_DF_RAM0_rd),
|
||||
.wr_addr(rec_DF_RAM0_addr),
|
||||
.rd_addr(rec_DF_RAM0_addr),
|
||||
.data_in(rec_DF_RAM0_din),
|
||||
.data_out(rec_DF_RAM0_dout)
|
||||
);
|
||||
ram_sync_1r_sync_1w #(`rec_DF_RAM1_data_width,`rec_DF_RAM1_data_depth)
|
||||
rec_DF_RAM1 (
|
||||
.clk(gclk_rec_DF_RAM1),
|
||||
.rst_n(reset_n),
|
||||
.wr_n(~rec_DF_RAM1_wr),
|
||||
.rd_n(~rec_DF_RAM1_rd),
|
||||
.wr_addr(rec_DF_RAM1_addr),
|
||||
.rd_addr(rec_DF_RAM1_addr),
|
||||
.data_in(rec_DF_RAM1_din),
|
||||
.data_out(rec_DF_RAM1_dout)
|
||||
);
|
||||
ext_RAM_ctrl ext_RAM_ctrl(
|
||||
.clk(clk),
|
||||
.reset_n(reset_n),
|
||||
.end_of_one_frame(end_of_one_frame),
|
||||
.ref_frame_RAM_rd(ref_frame_RAM_rd),
|
||||
.ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr),
|
||||
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
||||
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
||||
//.dis_frame_RAM_din(dis_frame_RAM_din),
|
||||
.ref_frame_RAM_dout(ref_frame_RAM_dout),
|
||||
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
|
||||
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
|
||||
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
|
||||
.ext_frame_RAM0_data(ext_frame_RAM0_data),
|
||||
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
|
||||
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
|
||||
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
|
||||
.ext_frame_RAM1_data(ext_frame_RAM1_data)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,299 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : run_decoding.v
|
||||
// Generated : June 11, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding the all the remaining syntax for CAVLC
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module run_decoding (clk,reset_n,cavlc_decoder_state,BitStream_buffer_output,total_zeros,
|
||||
level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7,
|
||||
level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15,
|
||||
TotalCoeff,i_run,i_TotalCoeff,coeffNum,IsRunLoop,
|
||||
|
||||
run_of_zeros_len,zerosLeft,run,
|
||||
coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7,
|
||||
coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15);
|
||||
input clk,reset_n;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
input [3:0] total_zeros;
|
||||
input [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7;
|
||||
input [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15;
|
||||
input [4:0] TotalCoeff;
|
||||
input [3:0] i_run;
|
||||
input [3:0] i_TotalCoeff;
|
||||
input [3:0] coeffNum;
|
||||
input IsRunLoop;
|
||||
output [3:0] run_of_zeros_len;
|
||||
output [3:0] zerosLeft;
|
||||
output [3:0] run;
|
||||
output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6;
|
||||
output [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13;
|
||||
output [8:0] coeffLevel_14,coeffLevel_15;
|
||||
|
||||
reg [3:0] run_of_zeros_len;
|
||||
reg [3:0] zerosLeft;
|
||||
reg [3:0] run;
|
||||
reg [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6;
|
||||
reg [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13;
|
||||
reg [8:0] coeffLevel_14,coeffLevel_15;
|
||||
|
||||
reg [3:0] run_before;
|
||||
reg [3:0] zerosLeft_reg;
|
||||
reg [3:0] run_0,run_1,run_2,run_3,run_4,run_5,run_6,run_7;
|
||||
reg [3:0] run_8,run_9,run_10,run_11,run_12,run_13,run_14,run_15;
|
||||
reg [8:0] level_output;
|
||||
|
||||
//decoding Table 9-10
|
||||
always @ (cavlc_decoder_state or zerosLeft or BitStream_buffer_output)
|
||||
if (cavlc_decoder_state == `run_before_LUT)
|
||||
case (zerosLeft)
|
||||
0:run_of_zeros_len <= 0;//special case added for "total_zeros==0"
|
||||
1:run_of_zeros_len <= 1;
|
||||
2:run_of_zeros_len <= (BitStream_buffer_output[15] == 1)? 4'd1:4'd2;
|
||||
3:run_of_zeros_len <= 2;
|
||||
4:run_of_zeros_len <= (BitStream_buffer_output[15:14] == 2'b00)? 4'd3:4'd2;
|
||||
5:run_of_zeros_len <= (BitStream_buffer_output[15] == 1)? 4'd2:4'd3;
|
||||
6:run_of_zeros_len <= (BitStream_buffer_output[15:14] == 2'b11)? 4'd2:4'd3;
|
||||
default:
|
||||
if (BitStream_buffer_output[15] == 1 || BitStream_buffer_output[14] == 1 || BitStream_buffer_output[13] == 1)
|
||||
run_of_zeros_len <= 3;
|
||||
else if (BitStream_buffer_output[15:12] == 1) run_of_zeros_len <= 4;
|
||||
else if (BitStream_buffer_output[15:11] == 1) run_of_zeros_len <= 5;
|
||||
else if (BitStream_buffer_output[15:10] == 1) run_of_zeros_len <= 6;
|
||||
else if (BitStream_buffer_output[15:9] == 1) run_of_zeros_len <= 7;
|
||||
else if (BitStream_buffer_output[15:8] == 1) run_of_zeros_len <= 4'd8;
|
||||
else if (BitStream_buffer_output[15:7] == 1) run_of_zeros_len <= 4'd9;
|
||||
else if (BitStream_buffer_output[15:6] == 1) run_of_zeros_len <= 4'd10;
|
||||
else if (BitStream_buffer_output[15:5] == 1) run_of_zeros_len <= 4'd11;
|
||||
else run_of_zeros_len <= 0;
|
||||
endcase
|
||||
else
|
||||
run_of_zeros_len <= 0;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
run_before <= 0;
|
||||
else if (cavlc_decoder_state == `run_before_LUT)
|
||||
case (zerosLeft)
|
||||
0:run_before <= 0;//special case added for "total_zeros==0"
|
||||
1:run_before <= (BitStream_buffer_output[15] == 0)? 4'd1:4'd0;
|
||||
2:if (BitStream_buffer_output[15] == 1) run_before <= 0;
|
||||
else if (BitStream_buffer_output[15:14] == 2'b01) run_before <= 1;
|
||||
else run_before <= 2;
|
||||
3:case (BitStream_buffer_output[15:14])
|
||||
2'b00:run_before <= 3;
|
||||
2'b01:run_before <= 2;
|
||||
2'b10:run_before <= 1;
|
||||
2'b11:run_before <= 0;
|
||||
endcase
|
||||
4:case (BitStream_buffer_output[15:14])
|
||||
2'b00:run_before <= (BitStream_buffer_output[13] == 1)? 4'd3:4'd4;
|
||||
2'b01:run_before <= 2;
|
||||
2'b10:run_before <= 1;
|
||||
2'b11:run_before <= 0;
|
||||
endcase
|
||||
5:case (BitStream_buffer_output[15:14])
|
||||
2'b00:run_before <= (BitStream_buffer_output[13] == 1)? 4'd4:4'd5;
|
||||
2'b01:run_before <= (BitStream_buffer_output[13] == 1)? 4'd2:4'd3;
|
||||
2'b10:run_before <= 1;
|
||||
2'b11:run_before <= 0;
|
||||
endcase
|
||||
6:casex (BitStream_buffer_output[15:13])
|
||||
3'b11x:run_before <= 0;
|
||||
3'b000:run_before <= 1;
|
||||
3'b001:run_before <= 2;
|
||||
3'b011:run_before <= 3;
|
||||
3'b010:run_before <= 4;
|
||||
3'b101:run_before <= 5;
|
||||
3'b100:run_before <= 6;
|
||||
endcase
|
||||
default:
|
||||
case (BitStream_buffer_output[15:13])
|
||||
3'b000:run_before <= run_of_zeros_len + 3;
|
||||
3'b111:run_before <= 0;
|
||||
3'b110:run_before <= 1;
|
||||
3'b101:run_before <= 2;
|
||||
3'b100:run_before <= 3;
|
||||
3'b011:run_before <= 4;
|
||||
3'b010:run_before <= 5;
|
||||
3'b001:run_before <= 6;
|
||||
endcase
|
||||
endcase
|
||||
|
||||
always @ (cavlc_decoder_state or total_zeros or run_before or zerosLeft_reg or IsRunLoop)
|
||||
if (cavlc_decoder_state == `run_before_LUT)
|
||||
zerosLeft <= (IsRunLoop == 0)? total_zeros:zerosLeft_reg;
|
||||
else if (cavlc_decoder_state == `RunOfZeros)
|
||||
zerosLeft <= zerosLeft_reg - run_before;
|
||||
else
|
||||
zerosLeft <= 0;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
zerosLeft_reg <= 0;
|
||||
else if (cavlc_decoder_state == `run_before_LUT || cavlc_decoder_state == `RunOfZeros)
|
||||
zerosLeft_reg <= zerosLeft;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0;
|
||||
run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0;
|
||||
run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0;
|
||||
run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0;
|
||||
end
|
||||
//reset run0 ~ run15 for each 4x4 CAVLC as early as nAnB_decoding_s stage
|
||||
else if (cavlc_decoder_state == `nAnB_decoding_s)
|
||||
begin
|
||||
run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0;
|
||||
run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0;
|
||||
run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0;
|
||||
run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0;
|
||||
end
|
||||
else if (cavlc_decoder_state == `RunOfZeros)
|
||||
begin
|
||||
if (TotalCoeff == 1)
|
||||
run_0 <= total_zeros;
|
||||
else if (total_zeros == 0)
|
||||
begin
|
||||
run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0;
|
||||
run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0;
|
||||
run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0;
|
||||
run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0;
|
||||
end
|
||||
else if ({1'b0,i_run} == TotalCoeff - 2)
|
||||
case (i_run)
|
||||
0 :begin run_0 <= run_before; run_1 <= zerosLeft; end
|
||||
1 :begin run_1 <= run_before; run_2 <= zerosLeft; end
|
||||
2 :begin run_2 <= run_before; run_3 <= zerosLeft; end
|
||||
3 :begin run_3 <= run_before; run_4 <= zerosLeft; end
|
||||
4 :begin run_4 <= run_before; run_5 <= zerosLeft; end
|
||||
5 :begin run_5 <= run_before; run_6 <= zerosLeft; end
|
||||
6 :begin run_6 <= run_before; run_7 <= zerosLeft; end
|
||||
7 :begin run_7 <= run_before; run_8 <= zerosLeft; end
|
||||
8 :begin run_8 <= run_before; run_9 <= zerosLeft; end
|
||||
9 :begin run_9 <= run_before; run_10<= zerosLeft; end
|
||||
10:begin run_10<= run_before; run_11<= zerosLeft; end
|
||||
11:begin run_11<= run_before; run_12<= zerosLeft; end
|
||||
12:begin run_12<= run_before; run_13<= zerosLeft; end
|
||||
13:begin run_13<= run_before; run_14<= zerosLeft; end
|
||||
endcase
|
||||
else
|
||||
case (i_run)
|
||||
0 :run_0 <= run_before;
|
||||
1 :run_1 <= run_before;
|
||||
2 :run_2 <= run_before;
|
||||
3 :run_3 <= run_before;
|
||||
4 :run_4 <= run_before;
|
||||
5 :run_5 <= run_before;
|
||||
6 :run_6 <= run_before;
|
||||
7 :run_7 <= run_before;
|
||||
8 :run_8 <= run_before;
|
||||
9 :run_9 <= run_before;
|
||||
10:run_10<= run_before;
|
||||
11:run_11<= run_before;
|
||||
12:run_12<= run_before;
|
||||
13:run_13<= run_before;
|
||||
endcase
|
||||
end
|
||||
always @ (cavlc_decoder_state or i_TotalCoeff or run_0 or run_1 or run_2 or run_3 or run_4 or
|
||||
run_5 or run_6 or run_7 or run_8 or run_9 or run_10 or run_11 or run_12 or run_13 or run_14)
|
||||
if (cavlc_decoder_state == `LevelRunCombination)
|
||||
case (i_TotalCoeff) //coeffNum = coeffNum + run[i_TotalCoeff-1] + 1;
|
||||
0 :run <= run_0;
|
||||
1 :run <= run_1;
|
||||
2 :run <= run_2;
|
||||
3 :run <= run_3;
|
||||
4 :run <= run_4;
|
||||
5 :run <= run_5;
|
||||
6 :run <= run_6;
|
||||
7 :run <= run_7;
|
||||
8 :run <= run_8;
|
||||
9 :run <= run_9;
|
||||
10:run <= run_10;
|
||||
11:run <= run_11;
|
||||
12:run <= run_12;
|
||||
13:run <= run_13;
|
||||
14:run <= run_14;
|
||||
default:run <= 0;
|
||||
endcase
|
||||
else
|
||||
run <= 0;
|
||||
|
||||
always @ (i_TotalCoeff or level_0 or level_1 or level_2 or level_3 or level_4 or level_5 or level_6 or
|
||||
level_7 or level_8 or level_9 or level_10 or level_11 or level_12 or level_13 or level_14 or level_15)
|
||||
case (i_TotalCoeff)
|
||||
0 :level_output <= level_0;
|
||||
1 :level_output <= level_1;
|
||||
2 :level_output <= level_2;
|
||||
3 :level_output <= level_3;
|
||||
4 :level_output <= level_4;
|
||||
5 :level_output <= level_5;
|
||||
6 :level_output <= level_6;
|
||||
7 :level_output <= level_7;
|
||||
8 :level_output <= level_8;
|
||||
9 :level_output <= level_9;
|
||||
10:level_output <= level_10;
|
||||
11:level_output <= level_11;
|
||||
12:level_output <= level_12;
|
||||
13:level_output <= level_13;
|
||||
14:level_output <= level_14;
|
||||
15:level_output <= level_15;
|
||||
endcase
|
||||
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
coeffLevel_0 <= 0; coeffLevel_1 <= 0; coeffLevel_2 <= 0; coeffLevel_3 <= 0;
|
||||
coeffLevel_4 <= 0; coeffLevel_5 <= 0; coeffLevel_6 <= 0; coeffLevel_7 <= 0;
|
||||
coeffLevel_8 <= 0; coeffLevel_9 <= 0; coeffLevel_10 <= 0; coeffLevel_11 <= 0;
|
||||
coeffLevel_12 <= 0; coeffLevel_13 <= 0; coeffLevel_14 <= 0; coeffLevel_15 <= 0;
|
||||
end
|
||||
//Revise log: March 24,2006
|
||||
//change reset coeffLevel_0 ~ 14 at total_zeros_LUT stage
|
||||
//else if (cavlc_decoder_state == RunOfZeros && //reset coeffLevel_0 ~ 14 only at last RunOfZeros
|
||||
// (i_run == TotalCoeff - 1 || i_run == TotalCoeff - 2 || zerosLeft == 0))
|
||||
else if (cavlc_decoder_state == `total_zeros_LUT)
|
||||
begin
|
||||
coeffLevel_0 <= 0; coeffLevel_1 <= 0; coeffLevel_2 <= 0; coeffLevel_3 <= 0;
|
||||
coeffLevel_4 <= 0; coeffLevel_5 <= 0; coeffLevel_6 <= 0; coeffLevel_7 <= 0;
|
||||
coeffLevel_8 <= 0; coeffLevel_9 <= 0; coeffLevel_10 <= 0; coeffLevel_11 <= 0;
|
||||
coeffLevel_12 <= 0; coeffLevel_13 <= 0; coeffLevel_14 <= 0; coeffLevel_15 <= 0;
|
||||
end
|
||||
else if (cavlc_decoder_state == `LevelRunCombination)
|
||||
begin
|
||||
case (coeffNum)
|
||||
0 :coeffLevel_0 <= level_output;
|
||||
1 :coeffLevel_1 <= level_output;
|
||||
2 :coeffLevel_2 <= level_output;
|
||||
3 :coeffLevel_3 <= level_output;
|
||||
4 :coeffLevel_4 <= level_output;
|
||||
5 :coeffLevel_5 <= level_output;
|
||||
6 :coeffLevel_6 <= level_output;
|
||||
7 :coeffLevel_7 <= level_output;
|
||||
8 :coeffLevel_8 <= level_output;
|
||||
9 :coeffLevel_9 <= level_output;
|
||||
10:coeffLevel_10<= level_output;
|
||||
11:coeffLevel_11<= level_output;
|
||||
12:coeffLevel_12<= level_output;
|
||||
13:coeffLevel_13<= level_output;
|
||||
14:coeffLevel_14<= level_output;
|
||||
15:coeffLevel_15<= level_output;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,510 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : sum.v
|
||||
// Generated : Oct 29, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Sum module for residual + prediction
|
||||
// Including output transpose and Intra_mbAddrB_RAM write control
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module sum (clk,reset_n,slice_data_state,residual_state,TotalCoeff,curr_CBPLuma_IsZero,CodedBlockPatternChroma,
|
||||
curr_DC_IsZero,curr_DC_scaled,gclk_pred_output,gclk_blk4x4_sum,trigger_blk4x4_rec_sum,
|
||||
IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3,
|
||||
IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7,
|
||||
IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11,
|
||||
IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15,
|
||||
mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
|
||||
Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out,blk4x4_intra_calculate_counter,
|
||||
Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter,
|
||||
Inter_blk4x4_pred_output_valid,mv_below8x8_curr,pos_FracL,mb_num_v,mb_num_h,LowerMB_IsSkip,
|
||||
|
||||
end_of_one_blk4x4_sum,blk4x4_sum_counter,blk4x4_rec_counter,
|
||||
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
||||
sum_right_column_reg,blk4x4_rec_counter_2_raster_order,
|
||||
blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
|
||||
blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
|
||||
blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
|
||||
blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
|
||||
Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din
|
||||
);
|
||||
input clk,reset_n;
|
||||
input [3:0] slice_data_state;
|
||||
input [3:0] residual_state;
|
||||
input [4:0] TotalCoeff;
|
||||
input curr_CBPLuma_IsZero;
|
||||
input [1:0] CodedBlockPatternChroma;
|
||||
input curr_DC_IsZero;
|
||||
input [8:0] curr_DC_scaled;
|
||||
input gclk_pred_output;
|
||||
input gclk_blk4x4_sum;
|
||||
input trigger_blk4x4_rec_sum;
|
||||
//residual from IQIT
|
||||
input [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3;
|
||||
input [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7;
|
||||
input [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11;
|
||||
input [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15;
|
||||
//Intra prediction output
|
||||
input [3:0] mb_type_general;
|
||||
input [3:0] Intra4x4_predmode;
|
||||
input [1:0] Intra16x16_predmode;
|
||||
input [1:0] Intra_chroma_predmode;
|
||||
input [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out;
|
||||
input [2:0] blk4x4_intra_calculate_counter;
|
||||
//Inter prediction output
|
||||
input [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
|
||||
input [1:0] Inter_blk4x4_pred_output_valid;
|
||||
input mv_below8x8_curr;
|
||||
input [3:0] pos_FracL;
|
||||
input [3:0] blk4x4_inter_calculate_counter;
|
||||
input [1:0] Inter_chroma2x2_counter;
|
||||
input [3:0] mb_num_h,mb_num_v;
|
||||
input LowerMB_IsSkip;
|
||||
|
||||
output end_of_one_blk4x4_sum;
|
||||
output [2:0] blk4x4_sum_counter;
|
||||
output [4:0] blk4x4_rec_counter;
|
||||
output [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
||||
output [23:0] sum_right_column_reg;
|
||||
output [4:0] blk4x4_rec_counter_2_raster_order;
|
||||
output [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
|
||||
output [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
|
||||
output [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
|
||||
output [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
|
||||
output Intra_mbAddrB_RAM_wr;
|
||||
output [6:0] Intra_mbAddrB_RAM_wr_addr;
|
||||
output [31:0] Intra_mbAddrB_RAM_din;
|
||||
|
||||
reg [2:0] blk4x4_sum_counter;
|
||||
reg [4:0] blk4x4_rec_counter;
|
||||
reg [4:0] blk4x4_rec_counter_2_raster_order;
|
||||
reg [23:0] sum_right_column_reg;
|
||||
|
||||
reg [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, blk4x4_pred_output3;
|
||||
reg [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, blk4x4_pred_output7;
|
||||
reg [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,blk4x4_pred_output11;
|
||||
reg [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,blk4x4_pred_output15;
|
||||
|
||||
|
||||
always @ (posedge gclk_pred_output or negedge reset_n)
|
||||
if (reset_n == 1'b0)
|
||||
begin blk4x4_pred_output0 <= 0; blk4x4_pred_output1 <= 0; blk4x4_pred_output2 <= 0; blk4x4_pred_output3 <= 0;
|
||||
blk4x4_pred_output4 <= 0; blk4x4_pred_output5 <= 0; blk4x4_pred_output6 <= 0; blk4x4_pred_output7 <= 0;
|
||||
blk4x4_pred_output8 <= 0; blk4x4_pred_output9 <= 0; blk4x4_pred_output10 <= 0; blk4x4_pred_output11 <= 0;
|
||||
blk4x4_pred_output12 <= 0; blk4x4_pred_output13<= 0; blk4x4_pred_output14 <= 0; blk4x4_pred_output15 <= 0; end
|
||||
else if (blk4x4_intra_calculate_counter != 0)
|
||||
begin
|
||||
//Intra4x4DC or chromaDC intra prediction:output valid only at cycle3 by PE0
|
||||
if ((mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 && Intra4x4_predmode == `Intra4x4_DC) ||
|
||||
(mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_DC))
|
||||
begin
|
||||
if (blk4x4_intra_calculate_counter == 3'd3) //Intra4x4DC or chromaDC completes calculation at cycle3 by PE0
|
||||
begin
|
||||
blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output1 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output3 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output4 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output6 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output8 <= Intra_pred_PE0_out; blk4x4_pred_output9 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out;
|
||||
end
|
||||
end
|
||||
//Intra16x16DC intra prediction:output valid only at cycle1 by PE0
|
||||
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && Intra16x16_predmode == `Intra16x16_DC)
|
||||
begin
|
||||
if (blk4x4_rec_counter == 0 && blk4x4_intra_calculate_counter == 3'd1)
|
||||
begin
|
||||
blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output1 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output3 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output4 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output6 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output8 <= Intra_pred_PE0_out; blk4x4_pred_output9 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out;
|
||||
blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out;
|
||||
end
|
||||
end
|
||||
//Besides above DC intra prediction case,other intra prediction modes output valid from cycle4 ~ cycle1
|
||||
else
|
||||
case (blk4x4_intra_calculate_counter)
|
||||
3'd4:begin blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output4 <= Intra_pred_PE1_out;
|
||||
blk4x4_pred_output8 <= Intra_pred_PE2_out; blk4x4_pred_output12 <= Intra_pred_PE3_out; end
|
||||
3'd3:begin blk4x4_pred_output1 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE1_out;
|
||||
blk4x4_pred_output9 <= Intra_pred_PE2_out; blk4x4_pred_output13 <= Intra_pred_PE3_out; end
|
||||
3'd2:begin blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output6 <= Intra_pred_PE1_out;
|
||||
blk4x4_pred_output10 <= Intra_pred_PE2_out; blk4x4_pred_output14 <= Intra_pred_PE3_out; end
|
||||
3'd1:begin blk4x4_pred_output3 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE1_out;
|
||||
blk4x4_pred_output11 <= Intra_pred_PE2_out; blk4x4_pred_output15 <= Intra_pred_PE3_out; end
|
||||
endcase
|
||||
end
|
||||
//Inter luma prediction output store
|
||||
else if (Inter_blk4x4_pred_output_valid == 2'b01)
|
||||
begin
|
||||
if (pos_FracL == `pos_i || pos_FracL == `pos_k)
|
||||
case (blk4x4_inter_calculate_counter)
|
||||
4'd7:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output4 <= Inter_pred_out1;
|
||||
blk4x4_pred_output8 <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3; end
|
||||
4'd5:begin blk4x4_pred_output1 <= Inter_pred_out0; blk4x4_pred_output5 <= Inter_pred_out1;
|
||||
blk4x4_pred_output9 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end
|
||||
4'd3:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output6 <= Inter_pred_out1;
|
||||
blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3; end
|
||||
4'd1:begin blk4x4_pred_output3 <= Inter_pred_out0; blk4x4_pred_output7 <= Inter_pred_out1;
|
||||
blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end
|
||||
endcase
|
||||
else
|
||||
case (blk4x4_inter_calculate_counter)
|
||||
4'd4:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output4 <= Inter_pred_out1;
|
||||
blk4x4_pred_output8 <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3; end
|
||||
4'd3:begin blk4x4_pred_output1 <= Inter_pred_out0; blk4x4_pred_output5 <= Inter_pred_out1;
|
||||
blk4x4_pred_output9 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end
|
||||
4'd2:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output6 <= Inter_pred_out1;
|
||||
blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3; end
|
||||
4'd1:begin blk4x4_pred_output3 <= Inter_pred_out0; blk4x4_pred_output7 <= Inter_pred_out1;
|
||||
blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end
|
||||
endcase
|
||||
end
|
||||
//Inter chroma prediction output store
|
||||
else if (Inter_blk4x4_pred_output_valid == 2'b10)
|
||||
case (mv_below8x8_curr)
|
||||
1'b1:
|
||||
case (Inter_chroma2x2_counter)
|
||||
2'b11:
|
||||
begin
|
||||
blk4x4_pred_output0 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0;
|
||||
blk4x4_pred_output1 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0;
|
||||
blk4x4_pred_output4 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0;
|
||||
blk4x4_pred_output5 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0;
|
||||
end
|
||||
2'b10:
|
||||
begin
|
||||
blk4x4_pred_output2 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0;
|
||||
blk4x4_pred_output3 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0;
|
||||
blk4x4_pred_output6 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0;
|
||||
blk4x4_pred_output7 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0;
|
||||
end
|
||||
2'b01:
|
||||
begin
|
||||
blk4x4_pred_output8 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0;
|
||||
blk4x4_pred_output9 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0;
|
||||
blk4x4_pred_output12 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0;
|
||||
blk4x4_pred_output13 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0;
|
||||
end
|
||||
2'b00:
|
||||
begin
|
||||
blk4x4_pred_output10 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0;
|
||||
blk4x4_pred_output11 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0;
|
||||
blk4x4_pred_output14 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0;
|
||||
blk4x4_pred_output15 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0;
|
||||
end
|
||||
endcase
|
||||
1'b0:
|
||||
case (blk4x4_inter_calculate_counter)
|
||||
4'd4:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output1 <= Inter_pred_out1;
|
||||
blk4x4_pred_output4 <= Inter_pred_out2; blk4x4_pred_output5 <= Inter_pred_out3; end
|
||||
4'd3:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output3 <= Inter_pred_out1;
|
||||
blk4x4_pred_output6 <= Inter_pred_out2; blk4x4_pred_output7 <= Inter_pred_out3; end
|
||||
4'd2:begin blk4x4_pred_output8 <= Inter_pred_out0; blk4x4_pred_output9 <= Inter_pred_out1;
|
||||
blk4x4_pred_output12 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end
|
||||
4'd1:begin blk4x4_pred_output10 <= Inter_pred_out0; blk4x4_pred_output11 <= Inter_pred_out1;
|
||||
blk4x4_pred_output14 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end
|
||||
endcase
|
||||
endcase
|
||||
|
||||
//------------------------------------------------------
|
||||
//blk4x4_sum_counter
|
||||
//------------------------------------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_sum_counter <= 3'd4;
|
||||
else if (trigger_blk4x4_rec_sum == 1'b1)
|
||||
blk4x4_sum_counter <= 3'd0;
|
||||
else if (blk4x4_sum_counter != 3'd4)
|
||||
blk4x4_sum_counter <= blk4x4_sum_counter + 1;
|
||||
|
||||
assign end_of_one_blk4x4_sum = (blk4x4_sum_counter == 3'd3)? 1'b1:1'b0;
|
||||
//------------------------------------------------------
|
||||
//blk4x4_rec_counter
|
||||
//------------------------------------------------------
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
blk4x4_rec_counter <= 0;
|
||||
else if (blk4x4_sum_counter == 3'd3)
|
||||
blk4x4_rec_counter <= (blk4x4_rec_counter == 5'd23)? 5'd0:(blk4x4_rec_counter + 1);
|
||||
//------------------------------------------------------
|
||||
//reconstruction sum
|
||||
//------------------------------------------------------
|
||||
|
||||
//Note:since res_blk4x4_IsAllZero has a higer priority over res_blk4x4_OnlyDC,the conditions
|
||||
//to assign res_blk4x4_OnlyDC is NOT complete (but when take current assigned res_blk4x4_IsAllZero
|
||||
//value into account, res_blk4x4_OnlyDC is correct!)
|
||||
|
||||
//res_blk4x4_IsAllZero:curr_DC_IsZero? curr_CBPLuma_IsZero? TotalCoeff is zero? CBPChroma is zero or one?
|
||||
|
||||
reg res_blk4x4_IsAllZero;
|
||||
reg res_blk4x4_onlyDC;
|
||||
always @ (slice_data_state or residual_state or curr_DC_IsZero or TotalCoeff
|
||||
or curr_DC_IsZero or curr_CBPLuma_IsZero or CodedBlockPatternChroma)
|
||||
if (slice_data_state == `skip_run_duration)
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= 1'b1;
|
||||
res_blk4x4_onlyDC <= 1'b0;
|
||||
end
|
||||
else
|
||||
case (residual_state)
|
||||
`Intra16x16ACLevel_0_s:
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0;
|
||||
res_blk4x4_onlyDC <= (curr_DC_IsZero)? 1'b0:1'b1;
|
||||
end
|
||||
`Intra16x16ACLevel_s,`ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s:
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b1:1'b0;
|
||||
res_blk4x4_onlyDC <= (TotalCoeff == 0)? 1'b1:1'b0;
|
||||
end
|
||||
`LumaLevel_0_s:
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= 1'b1;
|
||||
res_blk4x4_onlyDC <= 1'b0;
|
||||
end
|
||||
`LumaLevel_s:
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= (TotalCoeff == 0 || curr_CBPLuma_IsZero)? 1'b1:1'b0;
|
||||
res_blk4x4_onlyDC <= 1'b0;
|
||||
end
|
||||
`ChromaACLevel_0_s: //CodedBlockPatternChroma == 0 or 1
|
||||
if (CodedBlockPatternChroma == 0) //CodedBlockPatternChroma == 0
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= 1'b1;
|
||||
res_blk4x4_onlyDC <= 1'b0;
|
||||
end
|
||||
else //CodedBlockPatternChroma == 1
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0;
|
||||
res_blk4x4_onlyDC <= (curr_DC_IsZero)? 1'b0:1'b1;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
res_blk4x4_IsAllZero <= 1'b0;
|
||||
res_blk4x4_onlyDC <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
|
||||
reg [8:0] sum_PE0_a,sum_PE1_a,sum_PE2_a,sum_PE3_a;
|
||||
reg [7:0] sum_PE0_b,sum_PE1_b,sum_PE2_b,sum_PE3_b;
|
||||
wire sum_PE_bypass; //only one bypass signal for all sum_PE0 ~ sum_PE3
|
||||
assign sum_PE_bypass = (blk4x4_sum_counter != 3'd4 && !res_blk4x4_IsAllZero)? 1'b0:1'b1;
|
||||
|
||||
sum_PE sum_PE0 (
|
||||
.a(sum_PE0_a),
|
||||
.b(sum_PE0_b),
|
||||
.bypass(sum_PE_bypass),
|
||||
.c(blk4x4_sum_PE0_out)
|
||||
);
|
||||
sum_PE sum_PE1 (
|
||||
.a(sum_PE1_a),
|
||||
.b(sum_PE1_b),
|
||||
.bypass(sum_PE_bypass),
|
||||
.c(blk4x4_sum_PE1_out)
|
||||
);
|
||||
sum_PE sum_PE2 (
|
||||
.a(sum_PE2_a),
|
||||
.b(sum_PE2_b),
|
||||
.bypass(sum_PE_bypass),
|
||||
.c(blk4x4_sum_PE2_out)
|
||||
);
|
||||
sum_PE sum_PE3 (
|
||||
.a(sum_PE3_a),
|
||||
.b(sum_PE3_b),
|
||||
.bypass(sum_PE_bypass),
|
||||
.c(blk4x4_sum_PE3_out)
|
||||
);
|
||||
|
||||
// only for statistical purpose
|
||||
// synopsys translate_off
|
||||
integer number_of_IsAllZero;
|
||||
integer number_of_onlyDC;
|
||||
initial
|
||||
begin
|
||||
number_of_IsAllZero = 0;
|
||||
number_of_onlyDC = 0;
|
||||
end
|
||||
always @ (blk4x4_sum_counter)
|
||||
if (blk4x4_sum_counter == 3'd2)
|
||||
begin
|
||||
if (res_blk4x4_IsAllZero == 1'b1) number_of_IsAllZero <= number_of_IsAllZero + 1;
|
||||
else if (res_blk4x4_onlyDC == 1'b1) number_of_onlyDC <= number_of_onlyDC + 1;
|
||||
end
|
||||
// synopsys translate_on
|
||||
|
||||
always @ (blk4x4_sum_counter or res_blk4x4_IsAllZero or res_blk4x4_onlyDC or curr_DC_scaled or
|
||||
IQIT_output_0 or IQIT_output_1 or IQIT_output_2 or IQIT_output_3 or
|
||||
IQIT_output_4 or IQIT_output_5 or IQIT_output_6 or IQIT_output_7 or
|
||||
IQIT_output_8 or IQIT_output_9 or IQIT_output_10 or IQIT_output_11 or
|
||||
IQIT_output_12 or IQIT_output_13 or IQIT_output_14 or IQIT_output_15)
|
||||
if (res_blk4x4_IsAllZero)
|
||||
begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end
|
||||
else if (res_blk4x4_onlyDC)
|
||||
begin sum_PE0_a <= curr_DC_scaled; sum_PE1_a <= curr_DC_scaled;
|
||||
sum_PE2_a <= curr_DC_scaled; sum_PE3_a <= curr_DC_scaled; end
|
||||
else
|
||||
case (blk4x4_sum_counter)
|
||||
0:begin sum_PE0_a <= IQIT_output_0; sum_PE1_a <= IQIT_output_1;
|
||||
sum_PE2_a <= IQIT_output_2; sum_PE3_a <= IQIT_output_3; end
|
||||
1:begin sum_PE0_a <= IQIT_output_4; sum_PE1_a <= IQIT_output_5;
|
||||
sum_PE2_a <= IQIT_output_6; sum_PE3_a <= IQIT_output_7; end
|
||||
2:begin sum_PE0_a <= IQIT_output_8; sum_PE1_a <= IQIT_output_9;
|
||||
sum_PE2_a <= IQIT_output_10;sum_PE3_a <= IQIT_output_11; end
|
||||
3:begin sum_PE0_a <= IQIT_output_12;sum_PE1_a <= IQIT_output_13;
|
||||
sum_PE2_a <= IQIT_output_14;sum_PE3_a <= IQIT_output_15; end
|
||||
default:begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end
|
||||
endcase
|
||||
always @ (blk4x4_sum_counter or
|
||||
blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 or blk4x4_pred_output3 or
|
||||
blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output6 or blk4x4_pred_output7 or
|
||||
blk4x4_pred_output8 or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output11 or
|
||||
blk4x4_pred_output12 or blk4x4_pred_output13 or blk4x4_pred_output14 or blk4x4_pred_output15)
|
||||
case (blk4x4_sum_counter)
|
||||
0:begin sum_PE0_b <= blk4x4_pred_output0; sum_PE1_b <= blk4x4_pred_output1;
|
||||
sum_PE2_b <= blk4x4_pred_output2; sum_PE3_b <= blk4x4_pred_output3; end
|
||||
1:begin sum_PE0_b <= blk4x4_pred_output4; sum_PE1_b <= blk4x4_pred_output5;
|
||||
sum_PE2_b <= blk4x4_pred_output6; sum_PE3_b <= blk4x4_pred_output7; end
|
||||
2:begin sum_PE0_b <= blk4x4_pred_output8; sum_PE1_b <= blk4x4_pred_output9;
|
||||
sum_PE2_b <= blk4x4_pred_output10;sum_PE3_b <= blk4x4_pred_output11; end
|
||||
3:begin sum_PE0_b <= blk4x4_pred_output12;sum_PE1_b <= blk4x4_pred_output13;
|
||||
sum_PE2_b <= blk4x4_pred_output14;sum_PE3_b <= blk4x4_pred_output15; end
|
||||
default:begin sum_PE0_b <= 0; sum_PE1_b <= 0; sum_PE2_b <= 0; sum_PE3_b <= 0; end
|
||||
endcase
|
||||
//----------------------------------------------------------------------
|
||||
//sum right most column latch for Intra mbAddrA
|
||||
//----------------------------------------------------------------------
|
||||
//sum_right_column_reg:
|
||||
always @ (posedge gclk_blk4x4_sum or negedge reset_n)
|
||||
if (reset_n == 0)
|
||||
sum_right_column_reg <= 0;
|
||||
else
|
||||
case (blk4x4_sum_counter)
|
||||
3'd0:sum_right_column_reg[7:0] <= blk4x4_sum_PE3_out;
|
||||
3'd1:sum_right_column_reg[15:8] <= blk4x4_sum_PE3_out;
|
||||
3'd2:sum_right_column_reg[23:16] <= blk4x4_sum_PE3_out;
|
||||
endcase
|
||||
|
||||
//blk4x4_rec_counter_2_raster_order:
|
||||
//change from double-z order to raster order
|
||||
always @ (blk4x4_rec_counter)
|
||||
case (blk4x4_rec_counter)
|
||||
5'd2 :blk4x4_rec_counter_2_raster_order <= 5'd4;
|
||||
5'd3 :blk4x4_rec_counter_2_raster_order <= 5'd5;
|
||||
5'd4 :blk4x4_rec_counter_2_raster_order <= 5'd2;
|
||||
5'd5 :blk4x4_rec_counter_2_raster_order <= 5'd3;
|
||||
5'd10:blk4x4_rec_counter_2_raster_order <= 5'd12;
|
||||
5'd11:blk4x4_rec_counter_2_raster_order <= 5'd13;
|
||||
5'd12:blk4x4_rec_counter_2_raster_order <= 5'd10;
|
||||
5'd13:blk4x4_rec_counter_2_raster_order <= 5'd11;
|
||||
default:blk4x4_rec_counter_2_raster_order <= blk4x4_rec_counter;
|
||||
endcase
|
||||
//----------------------------------------------------------------------
|
||||
//Intra_mbAddrB_RAM write control
|
||||
//----------------------------------------------------------------------
|
||||
wire Is_blk4x4_rec_bottom;
|
||||
assign Is_blk4x4_rec_bottom = (blk4x4_rec_counter == 5'd10 || blk4x4_rec_counter == 5'd11 ||
|
||||
blk4x4_rec_counter == 5'd14 || blk4x4_rec_counter == 5'd15 || blk4x4_rec_counter == 5'd18 ||
|
||||
blk4x4_rec_counter == 5'd19 || blk4x4_rec_counter == 5'd22 || blk4x4_rec_counter == 5'd23);
|
||||
|
||||
assign Intra_mbAddrB_RAM_wr = (mb_num_v != 4'd8 && blk4x4_sum_counter == 3'd3 && Is_blk4x4_rec_bottom && !LowerMB_IsSkip);
|
||||
assign Intra_mbAddrB_RAM_din = (Intra_mbAddrB_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0;
|
||||
|
||||
// base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr
|
||||
reg [6:0] Intra_mbAddrB_RAM_addr_bp;
|
||||
always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2])
|
||||
if (Intra_mbAddrB_RAM_wr)
|
||||
begin
|
||||
if (blk4x4_rec_counter[4] == 1'b0) Intra_mbAddrB_RAM_addr_bp <= 0;
|
||||
else if (blk4x4_rec_counter[2] == 1'b0) Intra_mbAddrB_RAM_addr_bp <= 7'd44;
|
||||
else Intra_mbAddrB_RAM_addr_bp <= 7'd66;
|
||||
end
|
||||
else Intra_mbAddrB_RAM_addr_bp <= 0;
|
||||
|
||||
// shift pointer,x2 for chroma,x4 for luma
|
||||
wire [5:0] Intra_mbAddrB_RAM_addr_sp;
|
||||
assign Intra_mbAddrB_RAM_addr_sp = (Intra_mbAddrB_RAM_wr && blk4x4_rec_counter[4] == 1'b1)?
|
||||
{1'b0,mb_num_h,1'b0}:{mb_num_h,2'b0};
|
||||
// pointer for relative address of each 4x4 block inside a MB
|
||||
reg [1:0] Intra_mbAddrB_RAM_addr_ip;
|
||||
always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2:0])
|
||||
if (Intra_mbAddrB_RAM_wr)
|
||||
begin
|
||||
if (blk4x4_rec_counter[4] == 1'b0)
|
||||
case (blk4x4_rec_counter[2:0])
|
||||
3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'd0;
|
||||
3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'd1;
|
||||
3'b110:Intra_mbAddrB_RAM_addr_ip <= 2'd2;
|
||||
3'b111:Intra_mbAddrB_RAM_addr_ip <= 2'd3;
|
||||
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
endcase
|
||||
else
|
||||
Intra_mbAddrB_RAM_addr_ip <= {1'b0,blk4x4_rec_counter[0]};
|
||||
end
|
||||
else
|
||||
Intra_mbAddrB_RAM_addr_ip <= 0;
|
||||
|
||||
assign Intra_mbAddrB_RAM_wr_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip;
|
||||
|
||||
/*
|
||||
// synopsys translate_off
|
||||
integer tracefile;
|
||||
initial
|
||||
begin
|
||||
tracefile = $fopen("nova_sum_output.log");
|
||||
end
|
||||
|
||||
wire [6:0] mb_num;
|
||||
assign mb_num = mb_num_v * 11 + mb_num_h;
|
||||
|
||||
wire [1:0] blk4x4_rec_counter_M4;
|
||||
assign blk4x4_rec_counter_M4 = blk4x4_rec_counter[1:0];
|
||||
|
||||
reg [8:0] pic_num;
|
||||
always @ (reset_n or mb_num)
|
||||
if (reset_n == 1'b0)
|
||||
pic_num <= 9'b111111111;
|
||||
else if (mb_num == 0)
|
||||
pic_num <= pic_num + 1;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (blk4x4_sum_counter == 0)
|
||||
begin
|
||||
$fdisplay (tracefile,"------------------------ Pic = %3d, MB = %3d -------------------------",pic_num,mb_num);
|
||||
if (blk4x4_rec_counter < 16)
|
||||
$fdisplay (tracefile," [Luma] blk4x4Idx = %2d",blk4x4_rec_counter);
|
||||
else
|
||||
$fdisplay (tracefile," [Chroma] blk4x4Idx = %2d",blk4x4_rec_counter_M4);
|
||||
$fdisplay (tracefile," Sum output: %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out);
|
||||
end
|
||||
else if (blk4x4_sum_counter != 3'd4)
|
||||
$fdisplay (tracefile," %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out);
|
||||
// synopsys translate_on
|
||||
*/
|
||||
|
||||
endmodule
|
||||
|
||||
module sum_PE (a,b,bypass,c);
|
||||
input [8:0] a; //for residual from IQIT
|
||||
input [7:0] b; //for prediction from intra or inter
|
||||
input bypass;
|
||||
output [7:0] c;
|
||||
|
||||
wire [9:0] sum;
|
||||
|
||||
assign sum = (bypass)? 0:({2'b0,b} + {a[8],a});
|
||||
assign c = (bypass)? b:((sum[9] == 1'b1)? 0:((sum[8] == 1'b1)? 8'd255:sum[7:0]));
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,622 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : syntax_decoding.v
|
||||
// Generated : May 23, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding each sytax inside the bitstream
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module syntax_decoding (clk,reset_n,mb_num_h,mb_num_v,end_of_MB_DEC,pin_disable_DF,
|
||||
parser_state,nal_unit_state,seq_parameter_set_state,pic_parameter_set_state,
|
||||
slice_header_state,slice_data_state,mb_pred_state,sub_mb_pred_state,
|
||||
exp_golomb_decoding_output,BitStream_buffer_output,dependent_variable_decoding_output,mbPartIdx,
|
||||
|
||||
nal_unit_type,start_code_prefix_found,
|
||||
deblocking_filter_control_present_flag,disable_deblocking_filter_idc,disable_DF,
|
||||
slice_alpha_c0_offset_div2,slice_beta_offset_div2,
|
||||
mb_skip_run,NumMbPart,NumSubMbPart,
|
||||
MBTypeGen_mbAddrA,MBTypeGen_mbAddrD,MBTypeGen_mbAddrB_reg,
|
||||
log2_max_frame_num_minus4,log2_max_pic_order_cnt_lsb_minus4,constrained_intra_pred_flag,
|
||||
num_ref_idx_active_override_flag,num_ref_idx_l0_active_minus1,
|
||||
slice_type,mb_type,mb_type_general,sub_mb_type,Intra16x16_predmode,intra_chroma_pred_mode,
|
||||
pic_init_qp_minus26,chroma_qp_index_offset,
|
||||
rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,mvd,mv_below8x8);
|
||||
input clk,reset_n;
|
||||
input [3:0] mb_num_h,mb_num_v;
|
||||
input end_of_MB_DEC;
|
||||
input pin_disable_DF;
|
||||
input [1:0] parser_state;
|
||||
input [2:0] nal_unit_state;
|
||||
input [3:0] seq_parameter_set_state;
|
||||
input [3:0] pic_parameter_set_state;
|
||||
input [3:0] slice_header_state;
|
||||
input [3:0] slice_data_state;
|
||||
input [2:0] mb_pred_state;
|
||||
input [1:0] sub_mb_pred_state;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
input [7:0] exp_golomb_decoding_output;
|
||||
input [9:0] dependent_variable_decoding_output;
|
||||
input [1:0] mbPartIdx;
|
||||
|
||||
output [4:0] nal_unit_type;
|
||||
output start_code_prefix_found;
|
||||
output deblocking_filter_control_present_flag;
|
||||
output [1:0] disable_deblocking_filter_idc;
|
||||
output disable_DF;
|
||||
output [3:0] slice_alpha_c0_offset_div2;
|
||||
output [3:0] slice_beta_offset_div2;
|
||||
output [6:0] mb_skip_run;
|
||||
output [2:0] NumMbPart;
|
||||
output [2:0] NumSubMbPart;
|
||||
output [1:0] MBTypeGen_mbAddrA;
|
||||
output MBTypeGen_mbAddrD;
|
||||
output [21:0] MBTypeGen_mbAddrB_reg;
|
||||
output [3:0] log2_max_frame_num_minus4;
|
||||
output [3:0] log2_max_pic_order_cnt_lsb_minus4;
|
||||
output constrained_intra_pred_flag;
|
||||
output num_ref_idx_active_override_flag;
|
||||
output [2:0] num_ref_idx_l0_active_minus1;
|
||||
output [2:0] slice_type;
|
||||
output [4:0] mb_type;
|
||||
output [3:0] mb_type_general;
|
||||
output [1:0] Intra16x16_predmode;
|
||||
output [1:0] intra_chroma_pred_mode;
|
||||
output [1:0] sub_mb_type;
|
||||
output [5:0] pic_init_qp_minus26;
|
||||
output [4:0] chroma_qp_index_offset;
|
||||
output [2:0] rem_intra4x4_pred_mode;
|
||||
output prev_intra4x4_pred_mode_flag;
|
||||
output [7:0] mvd;
|
||||
output [3:0] mv_below8x8;
|
||||
//--------------------------
|
||||
//start_code_prefix
|
||||
//--------------------------
|
||||
reg start_code_prefix_found;
|
||||
always @ (parser_state or BitStream_buffer_output)
|
||||
if (parser_state == `start_code_prefix)
|
||||
begin
|
||||
if (BitStream_buffer_output == 16'b0000000000000001)
|
||||
start_code_prefix_found <= 1;
|
||||
else
|
||||
start_code_prefix_found <= 0;
|
||||
end
|
||||
else
|
||||
start_code_prefix_found <= 0;
|
||||
//--------------------------
|
||||
//nal_unit
|
||||
//--------------------------
|
||||
reg forbidden_zero_bit;
|
||||
reg [1:0] nal_ref_idc;
|
||||
reg [4:0] nal_unit_type_reg;
|
||||
wire [4:0] nal_unit_type;
|
||||
assign nal_unit_type = (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type)? BitStream_buffer_output[12:8]:nal_unit_type_reg;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
forbidden_zero_bit <= 0;
|
||||
nal_ref_idc <= 0;
|
||||
nal_unit_type_reg <= 0;
|
||||
end
|
||||
else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type)
|
||||
begin
|
||||
forbidden_zero_bit <= BitStream_buffer_output[15];
|
||||
nal_ref_idc <= BitStream_buffer_output[14:13];
|
||||
nal_unit_type_reg <= nal_unit_type;
|
||||
end
|
||||
//--------------------------
|
||||
//seq_parameter_set
|
||||
//--------------------------
|
||||
reg [7:0] profile_idc;
|
||||
reg constraint_set0_flag,constraint_set1_flag,constraint_set2_flag,constraint_set3_flag;
|
||||
reg [3:0] reserved_zero_4bits;
|
||||
reg [7:0] level_idc;
|
||||
reg [4:0] seq_parameter_set_id_sps;
|
||||
reg [3:0] log2_max_frame_num_minus4;
|
||||
reg [1:0] pic_order_cnt_type;
|
||||
reg [3:0] log2_max_pic_order_cnt_lsb_minus4;
|
||||
reg [2:0] num_ref_frames; //however,we only support 1 reference frame currently
|
||||
reg gaps_in_frame_num_value_allowed_flag;
|
||||
reg [3:0] pic_width_in_mbs_minus1;
|
||||
reg [3:0] pic_height_in_map_units_minus1;
|
||||
reg frame_mbs_only_flag;
|
||||
reg direct_8x8_inference_flag;
|
||||
reg frame_cropping_flag;
|
||||
reg vui_parameter_present_flag;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
profile_idc <= 0;
|
||||
constraint_set0_flag <= 0;
|
||||
constraint_set1_flag <= 0;
|
||||
constraint_set2_flag <= 0;
|
||||
constraint_set3_flag <= 0;
|
||||
reserved_zero_4bits <= 0;
|
||||
level_idc <= 0;
|
||||
seq_parameter_set_id_sps <= 0;
|
||||
log2_max_frame_num_minus4 <= 0;
|
||||
pic_order_cnt_type <= 0;
|
||||
log2_max_pic_order_cnt_lsb_minus4 <= 0;
|
||||
num_ref_frames <= 0;
|
||||
gaps_in_frame_num_value_allowed_flag <= 0;
|
||||
pic_width_in_mbs_minus1 <= 0;
|
||||
pic_height_in_map_units_minus1 <= 0;
|
||||
frame_mbs_only_flag <= 0;
|
||||
direct_8x8_inference_flag <= 0;
|
||||
frame_cropping_flag <= 0;
|
||||
vui_parameter_present_flag <= 0;
|
||||
end
|
||||
else
|
||||
case (seq_parameter_set_state)
|
||||
`fixed_header:
|
||||
begin
|
||||
profile_idc <= BitStream_buffer_output[15:8];
|
||||
constraint_set0_flag <= BitStream_buffer_output[7];
|
||||
constraint_set1_flag <= BitStream_buffer_output[6];
|
||||
constraint_set2_flag <= BitStream_buffer_output[5];
|
||||
constraint_set3_flag <= BitStream_buffer_output[4];
|
||||
reserved_zero_4bits <= BitStream_buffer_output[3:0];
|
||||
end
|
||||
`level_idc_s :level_idc <= BitStream_buffer_output[15:8];
|
||||
`seq_parameter_set_id_sps_s :seq_parameter_set_id_sps <= exp_golomb_decoding_output[4:0];
|
||||
`log2_max_frame_num_minus4_s :log2_max_frame_num_minus4 <= exp_golomb_decoding_output[3:0];
|
||||
`pic_order_cnt_type_s :pic_order_cnt_type <= exp_golomb_decoding_output[1:0];
|
||||
`log2_max_pic_order_cnt_lsb_minus4_s :log2_max_pic_order_cnt_lsb_minus4 <= exp_golomb_decoding_output[3:0];
|
||||
`num_ref_frames_s :num_ref_frames <= exp_golomb_decoding_output[0];
|
||||
`gaps_in_frame_num_value_allowed_flag_s:gaps_in_frame_num_value_allowed_flag <= BitStream_buffer_output[15];
|
||||
`pic_width_in_mbs_minus1_s :pic_width_in_mbs_minus1 <= exp_golomb_decoding_output[3:0];
|
||||
`pic_height_in_map_units_minus1_s :pic_height_in_map_units_minus1 <= exp_golomb_decoding_output[3:0];
|
||||
`frame_mbs_only_flag_2_frame_cropping_flag:
|
||||
begin
|
||||
frame_mbs_only_flag <= BitStream_buffer_output[15];
|
||||
direct_8x8_inference_flag <= BitStream_buffer_output[14];
|
||||
frame_cropping_flag <= BitStream_buffer_output[13];
|
||||
end
|
||||
`vui_parameter_present_flag_s:vui_parameter_present_flag <= BitStream_buffer_output[15];
|
||||
endcase
|
||||
//--------------------------
|
||||
//pic_parameter_set
|
||||
//--------------------------
|
||||
reg [7:0] pic_parameter_set_id_pps;
|
||||
reg [4:0] seq_parameter_set_id_pps;
|
||||
reg entropy_coding_mode_flag;
|
||||
reg pic_order_present_flag;
|
||||
reg [2:0] num_slice_groups_minus1;
|
||||
reg [2:0] num_ref_idx_l0_active_minus1;
|
||||
reg [2:0] num_ref_idx_l1_active_minus1;
|
||||
reg weighted_pred_flag;
|
||||
reg [1:0] weighted_bipred_idc;
|
||||
reg [5:0] pic_init_qp_minus26,pic_init_qs_minus26;
|
||||
reg [4:0] chroma_qp_index_offset;
|
||||
reg deblocking_filter_control_present_flag;
|
||||
reg constrained_intra_pred_flag;
|
||||
reg redundant_pic_cnt_present_flag;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
pic_parameter_set_id_pps <= 0;
|
||||
seq_parameter_set_id_pps <= 0;
|
||||
entropy_coding_mode_flag <= 0;
|
||||
pic_order_present_flag <= 0;
|
||||
num_slice_groups_minus1 <= 0;
|
||||
num_ref_idx_l0_active_minus1 <= 0;
|
||||
num_ref_idx_l1_active_minus1 <= 0;
|
||||
weighted_pred_flag <= 0;
|
||||
weighted_bipred_idc <= 0;
|
||||
pic_init_qp_minus26 <= 0;
|
||||
pic_init_qs_minus26 <= 0;
|
||||
chroma_qp_index_offset <= 0;
|
||||
deblocking_filter_control_present_flag <= 0;
|
||||
constrained_intra_pred_flag <= 0;
|
||||
redundant_pic_cnt_present_flag <= 0;
|
||||
end
|
||||
else
|
||||
case (pic_parameter_set_state)
|
||||
`pic_parameter_set_id_pps_s:pic_parameter_set_id_pps <= exp_golomb_decoding_output[7:0];
|
||||
`seq_parameter_set_id_pps_s:seq_parameter_set_id_pps <= exp_golomb_decoding_output[4:0];
|
||||
`entropy_coding_mode_flag_2_pic_order_present_flag:
|
||||
begin
|
||||
entropy_coding_mode_flag <= BitStream_buffer_output[15];
|
||||
pic_order_present_flag <= BitStream_buffer_output[14];
|
||||
end
|
||||
`num_slice_groups_minus1_s :num_slice_groups_minus1 <= exp_golomb_decoding_output[2:0];
|
||||
`num_ref_idx_l0_active_minus1_pps_s:num_ref_idx_l0_active_minus1 <= exp_golomb_decoding_output[2:0];
|
||||
`num_ref_idx_l1_active_minus1_pps_s:num_ref_idx_l1_active_minus1 <= exp_golomb_decoding_output[2:0];
|
||||
`weighted_pred_flag_2_weighted_bipred_idc:
|
||||
begin
|
||||
weighted_pred_flag <= BitStream_buffer_output[15];
|
||||
weighted_bipred_idc <= BitStream_buffer_output[14:13];
|
||||
end
|
||||
`pic_init_qp_minus26_s :pic_init_qp_minus26 <= exp_golomb_decoding_output[5:0];
|
||||
`pic_init_qs_minus26_s :pic_init_qs_minus26 <= exp_golomb_decoding_output[5:0];
|
||||
`chroma_qp_index_offset_s:chroma_qp_index_offset <= exp_golomb_decoding_output[4:0];
|
||||
`deblocking_filter_control_2_redundant_pic_cnt_present_flag:
|
||||
begin
|
||||
deblocking_filter_control_present_flag <= BitStream_buffer_output[15];
|
||||
constrained_intra_pred_flag <= BitStream_buffer_output[14];
|
||||
redundant_pic_cnt_present_flag <= BitStream_buffer_output[13];
|
||||
end
|
||||
endcase
|
||||
//--------------------------
|
||||
//slice_header
|
||||
//--------------------------
|
||||
reg first_mb_in_slice;
|
||||
reg [2:0] slice_type;
|
||||
reg [7:0] pic_parameter_set_id_slice_header;
|
||||
reg [3:0] frame_num;
|
||||
reg idr_pic_id;
|
||||
reg [9:0] pic_order_cnt_lsb;
|
||||
reg num_ref_idx_active_override_flag;
|
||||
reg [1:0] disable_deblocking_filter_idc;
|
||||
reg [3:0] slice_alpha_c0_offset_div2_dec;
|
||||
reg [3:0] slice_beta_offset_div2_dec;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
first_mb_in_slice <= 0;
|
||||
slice_type <= 0;
|
||||
pic_parameter_set_id_slice_header <= 0;
|
||||
frame_num <= 0;
|
||||
idr_pic_id <= 0;
|
||||
pic_order_cnt_lsb <= 0;
|
||||
num_ref_idx_active_override_flag <= 0;
|
||||
disable_deblocking_filter_idc <= 0;
|
||||
slice_alpha_c0_offset_div2_dec <= 0;
|
||||
slice_beta_offset_div2_dec <= 0;
|
||||
end
|
||||
else
|
||||
case (slice_header_state)
|
||||
`first_mb_in_slice_s :first_mb_in_slice <= exp_golomb_decoding_output[0];
|
||||
`slice_type_s :slice_type <= exp_golomb_decoding_output[2:0];
|
||||
`pic_parameter_set_id_slice_header_s:pic_parameter_set_id_slice_header <= exp_golomb_decoding_output;
|
||||
`frame_num_s :frame_num <= dependent_variable_decoding_output[3:0];
|
||||
`idr_pic_id_s :idr_pic_id <= exp_golomb_decoding_output[0];
|
||||
`pic_order_cnt_lsb_s :pic_order_cnt_lsb <= dependent_variable_decoding_output[9:0];
|
||||
`num_ref_idx_active_override_flag_s :num_ref_idx_active_override_flag <= BitStream_buffer_output[15];
|
||||
//num_ref_idx_l0_active_minus1_slice_header_s:
|
||||
//slice_qp_delta_s:slice_qp_delta <= exp_golomb_decoding_output[5:0];
|
||||
`disable_deblocking_filter_idc_s :disable_deblocking_filter_idc <= exp_golomb_decoding_output[1:0];
|
||||
`slice_alpha_c0_offset_div2_s :slice_alpha_c0_offset_div2_dec <= exp_golomb_decoding_output[3:0];
|
||||
`slice_beta_offset_div2_s :slice_beta_offset_div2_dec <= exp_golomb_decoding_output[3:0];
|
||||
//slice_group_change_cycle_s:
|
||||
endcase
|
||||
|
||||
wire [3:0] slice_alpha_c0_offset_div2;
|
||||
wire [3:0] slice_beta_offset_div2;
|
||||
assign slice_alpha_c0_offset_div2 = {4{deblocking_filter_control_present_flag}} & slice_alpha_c0_offset_div2_dec;
|
||||
assign slice_beta_offset_div2 = {4{deblocking_filter_control_present_flag}} & slice_beta_offset_div2_dec;
|
||||
|
||||
reg sw_disable_DF;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
sw_disable_DF <= 0;
|
||||
else if (slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 1)
|
||||
sw_disable_DF <= 1;
|
||||
else
|
||||
sw_disable_DF <= 0;
|
||||
|
||||
assign disable_DF = sw_disable_DF | pin_disable_DF;
|
||||
//--------------------------
|
||||
//slice_data
|
||||
//--------------------------
|
||||
wire [6:0] mb_skip_run;
|
||||
reg [6:0] mb_skip_run_reg;
|
||||
reg [4:0] mb_type;
|
||||
reg [3:0] mb_type_general;
|
||||
reg [3:0] mb_type_general_reg;
|
||||
reg [1:0] Intra16x16_predmode;
|
||||
|
||||
//mb_type_general
|
||||
assign mb_skip_run = (slice_data_state == `mb_skip_run_s)? exp_golomb_decoding_output[6:0]:mb_skip_run_reg;
|
||||
always @ (slice_data_state or slice_type or exp_golomb_decoding_output or mb_type_general_reg)
|
||||
if (slice_data_state == `skip_run_duration)
|
||||
mb_type_general <= `MB_P_skip;
|
||||
else if (slice_data_state == `mb_type_s)
|
||||
begin
|
||||
if (slice_type == 2 || slice_type == 7) //I slice
|
||||
case (exp_golomb_decoding_output)
|
||||
0: mb_type_general <= `MB_Intra4x4;
|
||||
1,2,3,4,13,14,15,16: mb_type_general <= `MB_Intra16x16_CBPChroma0;
|
||||
5,6,7,8,17,18,19,20: mb_type_general <= `MB_Intra16x16_CBPChroma1;
|
||||
9,10,11,12,21,22,23,24: mb_type_general <= `MB_Intra16x16_CBPChroma2;
|
||||
default: mb_type_general <= `MB_Inter16x16;
|
||||
endcase
|
||||
else //P slice
|
||||
case (exp_golomb_decoding_output)
|
||||
0: mb_type_general <= `MB_Inter16x16;
|
||||
1: mb_type_general <= `MB_Inter16x8;
|
||||
2: mb_type_general <= `MB_Inter8x16;
|
||||
3: mb_type_general <= `MB_P_8x8;
|
||||
4: mb_type_general <= `MB_P_8x8ref0;
|
||||
5: mb_type_general <= `MB_Intra4x4;
|
||||
6,7,8,9,18,19,20,21: mb_type_general <= `MB_Intra16x16_CBPChroma0;
|
||||
10,11,12,13,22,23,24,25:mb_type_general <= `MB_Intra16x16_CBPChroma1;
|
||||
14,15,16,17,26,27,28,29:mb_type_general <= `MB_Intra16x16_CBPChroma0;
|
||||
default: mb_type_general <= `MB_Inter16x8;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
mb_type_general <= mb_type_general_reg;
|
||||
|
||||
//Intra16x16_predmode
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
Intra16x16_predmode <= 2'b0;
|
||||
else if (slice_data_state == `mb_type_s)
|
||||
begin
|
||||
if (slice_type == 2 || slice_type == 7) //I slice
|
||||
begin
|
||||
if (exp_golomb_decoding_output != 0)
|
||||
case (exp_golomb_decoding_output[1:0])
|
||||
2'b00:Intra16x16_predmode <= 2'b11;
|
||||
2'b01:Intra16x16_predmode <= 2'b00;
|
||||
2'b10:Intra16x16_predmode <= 2'b01;
|
||||
2'b11:Intra16x16_predmode <= 2'b10;
|
||||
endcase
|
||||
end
|
||||
else if (exp_golomb_decoding_output[4:0] > 5) //P slice
|
||||
case (exp_golomb_decoding_output[1:0])
|
||||
2'b00:Intra16x16_predmode <= 2'b10;
|
||||
2'b01:Intra16x16_predmode <= 2'b11;
|
||||
2'b10:Intra16x16_predmode <= 2'b00;
|
||||
2'b11:Intra16x16_predmode <= 2'b01;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
mb_skip_run_reg <= 0;
|
||||
mb_type <= 0;
|
||||
mb_type_general_reg <= `MB_type_rst;
|
||||
end
|
||||
else
|
||||
case (slice_data_state)
|
||||
`mb_skip_run_s:mb_skip_run_reg <= mb_skip_run;
|
||||
`skip_run_duration:
|
||||
begin
|
||||
mb_type <= 5'd31;
|
||||
mb_type_general_reg <= mb_type_general;
|
||||
end
|
||||
`mb_type_s:
|
||||
begin
|
||||
mb_type <= exp_golomb_decoding_output[4:0];
|
||||
mb_type_general_reg <= mb_type_general;
|
||||
end
|
||||
//pcm_byte_s: --> Currently no deal with it
|
||||
//coded_block_pattern_s: --> See CodedBlockPattern_decoding.v
|
||||
//mb_qp_delta_s:mb_qp_delta <= exp_golomb_decoding_output;
|
||||
endcase
|
||||
//Update MBTypeGen information
|
||||
reg [1:0] MBTypeGen_mbAddrA;
|
||||
reg MBTypeGen_mbAddrD_tmp;
|
||||
reg MBTypeGen_mbAddrD;
|
||||
reg [21:0] MBTypeGen_mbAddrB_reg;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
MBTypeGen_mbAddrA <= 0;
|
||||
MBTypeGen_mbAddrD_tmp <= 0;
|
||||
MBTypeGen_mbAddrB_reg <= 0;
|
||||
end
|
||||
else if (slice_data_state == `skip_run_duration && end_of_MB_DEC)//for P_skip
|
||||
begin
|
||||
if (mb_num_h != 10)
|
||||
MBTypeGen_mbAddrA <= `MB_addrA_addrB_P_skip;
|
||||
if (mb_num_h == 9)
|
||||
MBTypeGen_mbAddrD_tmp <= 1'b0;
|
||||
if (mb_num_v != 8)
|
||||
case (mb_num_h)
|
||||
0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_P_skip;1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_P_skip;
|
||||
2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_P_skip;3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_P_skip;
|
||||
4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_P_skip;5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_P_skip;
|
||||
6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_P_skip;7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_P_skip;
|
||||
8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_P_skip;9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_P_skip;
|
||||
10:MBTypeGen_mbAddrB_reg[21:20] <= `MB_addrA_addrB_P_skip;
|
||||
endcase
|
||||
end
|
||||
else if (slice_data_state == `mb_num_update)
|
||||
begin
|
||||
if (mb_num_h != 10)
|
||||
begin
|
||||
if (mb_type_general[3] == 1'b0)
|
||||
MBTypeGen_mbAddrA <= `MB_addrA_addrB_Inter;
|
||||
else if (mb_type_general[3:2] == 2'b10)
|
||||
MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra16x16;
|
||||
else if (mb_type_general == `MB_Intra4x4)
|
||||
MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra4x4;
|
||||
end
|
||||
if (mb_num_h == 9)
|
||||
MBTypeGen_mbAddrD_tmp <= mb_type_general[3];
|
||||
if (mb_num_v != 8)
|
||||
begin
|
||||
if (mb_type_general[3] == 1'b0)
|
||||
case (mb_num_h)
|
||||
0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Inter; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Inter;
|
||||
2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Inter; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Inter;
|
||||
4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Inter; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Inter;
|
||||
6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Inter; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Inter;
|
||||
8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Inter; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Inter;
|
||||
10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Inter;
|
||||
endcase
|
||||
else if (mb_type_general[3:2] == 2'b10)
|
||||
case (mb_num_h)
|
||||
0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Intra16x16; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Intra16x16;
|
||||
2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Intra16x16; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Intra16x16;
|
||||
4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Intra16x16; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra16x16;
|
||||
6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra16x16; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra16x16;
|
||||
8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra16x16; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra16x16;
|
||||
10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra16x16;
|
||||
endcase
|
||||
else if (mb_type_general == `MB_Intra4x4)
|
||||
case (mb_num_h)
|
||||
0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Intra4x4; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Intra4x4;
|
||||
2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Intra4x4; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Intra4x4;
|
||||
4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Intra4x4; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra4x4;
|
||||
6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra4x4; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra4x4;
|
||||
8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra4x4; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra4x4;
|
||||
10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra4x4;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
MBTypeGen_mbAddrD <= 0;
|
||||
else if (mb_num_h == 0)
|
||||
MBTypeGen_mbAddrD <= MBTypeGen_mbAddrD_tmp;
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
//mb_pred & sub_mb_pred
|
||||
// --> Also refer to Intra4x4_PredMode_decoding.v & Inter_mv_decoding.v
|
||||
//----------------------------------------------------------------------
|
||||
wire prev_intra4x4_pred_mode_flag;
|
||||
reg prev_intra4x4_pred_mode_flag_reg;
|
||||
wire [2:0] rem_intra4x4_pred_mode;
|
||||
reg [2:0] rem_intra4x4_pred_mode_reg;
|
||||
reg [1:0] intra_chroma_pred_mode;
|
||||
wire [7:0] mvd;
|
||||
reg [7:0] mvd_reg;
|
||||
reg [7:0] sub_mb_type_reg;
|
||||
assign prev_intra4x4_pred_mode_flag = (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)? BitStream_buffer_output[15]:prev_intra4x4_pred_mode_flag_reg;
|
||||
assign rem_intra4x4_pred_mode = (mb_pred_state == `rem_intra4x4_pred_mode_s)? BitStream_buffer_output[15:13]:rem_intra4x4_pred_mode_reg;
|
||||
assign mvd = ((mb_pred_state == `mvd_l0_s) || (sub_mb_pred_state == `sub_mvd_l0_s))? exp_golomb_decoding_output[7:0]:mvd_reg;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
begin
|
||||
prev_intra4x4_pred_mode_flag_reg <= 0;
|
||||
rem_intra4x4_pred_mode_reg <= 0;
|
||||
intra_chroma_pred_mode <= 0;
|
||||
mvd_reg <= 0;
|
||||
sub_mb_type_reg <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case (mb_pred_state)
|
||||
`prev_intra4x4_pred_mode_flag_s:prev_intra4x4_pred_mode_flag_reg <= prev_intra4x4_pred_mode_flag;
|
||||
`rem_intra4x4_pred_mode_s :rem_intra4x4_pred_mode_reg <= rem_intra4x4_pred_mode;
|
||||
`intra_chroma_pred_mode_s :intra_chroma_pred_mode <= exp_golomb_decoding_output[1:0];
|
||||
//ref_idx_l0_s: --> only 1 reference frame,so never jump into this state
|
||||
`mvd_l0_s: mvd_reg <= mvd;
|
||||
endcase
|
||||
case (sub_mb_pred_state)
|
||||
`sub_mb_type_s:
|
||||
case (mbPartIdx)
|
||||
0:sub_mb_type_reg[1:0] <= exp_golomb_decoding_output[1:0];
|
||||
1:sub_mb_type_reg[3:2] <= exp_golomb_decoding_output[1:0];
|
||||
2:sub_mb_type_reg[5:4] <= exp_golomb_decoding_output[1:0];
|
||||
3:sub_mb_type_reg[7:6] <= exp_golomb_decoding_output[1:0];
|
||||
endcase
|
||||
//sub_ref_idx_l0_s: --> only 1 reference frame,so never jump into this state
|
||||
`sub_mvd_l0_s: mvd_reg <= mvd;
|
||||
endcase
|
||||
end
|
||||
reg [2:0] NumMbPart;
|
||||
reg [2:0] NumSubMbPart;
|
||||
reg [1:0] sub_mb_type;
|
||||
always @ (sub_mb_pred_state or sub_mb_type_reg or mbPartIdx)
|
||||
if (sub_mb_pred_state == `sub_mvd_l0_s)
|
||||
case (mbPartIdx)
|
||||
0:sub_mb_type <= sub_mb_type_reg[1:0];
|
||||
1:sub_mb_type <= sub_mb_type_reg[3:2];
|
||||
2:sub_mb_type <= sub_mb_type_reg[5:4];
|
||||
3:sub_mb_type <= sub_mb_type_reg[7:6];
|
||||
endcase
|
||||
else
|
||||
sub_mb_type <= 0;
|
||||
always @ (mb_pred_state or mb_type_general or sub_mb_pred_state)
|
||||
if (mb_pred_state == `mvd_l0_s)
|
||||
case (mb_type_general)
|
||||
0:NumMbPart <= 3'd1;
|
||||
default:NumMbPart <= 3'd2;
|
||||
endcase
|
||||
else if (sub_mb_pred_state == `sub_mvd_l0_s)
|
||||
NumMbPart <= 3'd4;
|
||||
else
|
||||
NumMbPart <= 3'd0;
|
||||
always @ (sub_mb_pred_state or mbPartIdx or sub_mb_type_reg)
|
||||
if (sub_mb_pred_state == `sub_mvd_l0_s)
|
||||
case (mbPartIdx)
|
||||
0:
|
||||
case (sub_mb_type_reg[1:0])
|
||||
2'b00 :NumSubMbPart <= 3'd1;
|
||||
2'b01,2'b10:NumSubMbPart <= 3'd2;
|
||||
2'b11 :NumSubMbPart <= 3'd4;
|
||||
endcase
|
||||
1:
|
||||
case (sub_mb_type_reg[3:2])
|
||||
2'b00 :NumSubMbPart <= 3'd1;
|
||||
2'b01,2'b10:NumSubMbPart <= 3'd2;
|
||||
2'b11 :NumSubMbPart <= 3'd4;
|
||||
endcase
|
||||
2:
|
||||
case (sub_mb_type_reg[5:4])
|
||||
2'b00 :NumSubMbPart <= 3'd1;
|
||||
2'b01,2'b10:NumSubMbPart <= 3'd2;
|
||||
2'b11 :NumSubMbPart <= 3'd4;
|
||||
endcase
|
||||
3:
|
||||
case (sub_mb_type_reg[7:6])
|
||||
2'b00 :NumSubMbPart <= 3'd1;
|
||||
2'b01,2'b10:NumSubMbPart <= 3'd2;
|
||||
2'b11 :NumSubMbPart <= 3'd4;
|
||||
endcase
|
||||
endcase
|
||||
else
|
||||
NumSubMbPart <= 0;
|
||||
|
||||
//mv_below8x8
|
||||
reg [3:0] mv_below8x8;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 1'b0)
|
||||
mv_below8x8 <= 4'b0;
|
||||
else if (sub_mb_pred_state == `sub_mb_type_s)
|
||||
case (mbPartIdx)
|
||||
0:mv_below8x8[0] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1;
|
||||
1:mv_below8x8[1] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1;
|
||||
2:mv_below8x8[2] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1;
|
||||
3:mv_below8x8[3] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1;
|
||||
endcase
|
||||
else if (slice_data_state == `mb_pred || slice_data_state == `skip_run_duration)
|
||||
mv_below8x8 <= 4'b0;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : timescale.v
|
||||
// Generated : April 20, 2008
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Time scale for the entire design
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ns/1ns
|
||||
@@ -0,0 +1,400 @@
|
||||
//--------------------------------------------------------------------------------------------------
|
||||
// Design : nova
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// File : total_zeros_decoding.v
|
||||
// Generated : June 9, 2005
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
// Description
|
||||
// Decoding total_zeros from Table9-7,Table9-8,Table9-9 of H.264/AVC standard 2003
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
`include "nova_defines.v"
|
||||
|
||||
module total_zeros_decoding (clk,reset_n,residual_state,cavlc_decoder_state,TotalCoeff_3to0,heading_one_pos,
|
||||
BitStream_buffer_output,maxNumCoeff,total_zeros,total_zeros_len);
|
||||
input clk,reset_n;
|
||||
input [3:0] residual_state;
|
||||
input [3:0] cavlc_decoder_state;
|
||||
input [3:0] TotalCoeff_3to0;
|
||||
input [3:0] heading_one_pos;
|
||||
input [15:0] BitStream_buffer_output;
|
||||
output [4:0] maxNumCoeff;
|
||||
output [3:0] total_zeros;
|
||||
output [3:0] total_zeros_len;
|
||||
reg [4:0] maxNumCoeff;
|
||||
reg [3:0] total_zeros;
|
||||
reg [3:0] total_zeros_len;
|
||||
|
||||
reg [3:0] total_zeros_reg;
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
maxNumCoeff <= 0;
|
||||
else
|
||||
case (residual_state)
|
||||
`Intra16x16DCLevel_s:maxNumCoeff <= 5'd16;
|
||||
`Intra16x16ACLevel_s:maxNumCoeff <= 15;
|
||||
`LumaLevel_s :maxNumCoeff <= 5'd16;
|
||||
`ChromaDCLevel_Cb_s :maxNumCoeff <= 4;
|
||||
`ChromaDCLevel_Cr_s :maxNumCoeff <= 4;
|
||||
`ChromaACLevel_Cb_s :maxNumCoeff <= 15;
|
||||
`ChromaACLevel_Cr_s :maxNumCoeff <= 15;
|
||||
endcase
|
||||
|
||||
//total_zeros_len
|
||||
always @ (cavlc_decoder_state or maxNumCoeff or TotalCoeff_3to0 or heading_one_pos or BitStream_buffer_output)
|
||||
if (cavlc_decoder_state == `total_zeros_LUT)
|
||||
begin
|
||||
if (maxNumCoeff == 4)
|
||||
case (TotalCoeff_3to0)
|
||||
1:if (heading_one_pos == 0) total_zeros_len <= 1;
|
||||
else if (heading_one_pos == 1) total_zeros_len <= 2;
|
||||
else total_zeros_len <= 3;
|
||||
2:if (heading_one_pos == 0) total_zeros_len <= 1;
|
||||
else total_zeros_len <= 2;
|
||||
3: total_zeros_len <= 1;
|
||||
default: total_zeros_len <= 0;
|
||||
endcase
|
||||
else
|
||||
case (TotalCoeff_3to0)
|
||||
1:if (heading_one_pos == 0) total_zeros_len <= 1;
|
||||
else if (heading_one_pos == 8) total_zeros_len <= 4'd9;
|
||||
else total_zeros_len <= heading_one_pos + 2;
|
||||
2:if (heading_one_pos == 0) total_zeros_len <= 4'd3;
|
||||
else if (heading_one_pos == 1)
|
||||
total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 2) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 5;
|
||||
else if (heading_one_pos == 4) total_zeros_len <= 6;
|
||||
else total_zeros_len <= 6;
|
||||
3:if (heading_one_pos == 0) total_zeros_len <= 4'd3;
|
||||
else if (heading_one_pos == 1)
|
||||
total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 2) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 5;
|
||||
else if (heading_one_pos == 4) total_zeros_len <= 5;
|
||||
else total_zeros_len <= 4'd6;
|
||||
4:if (heading_one_pos == 0) total_zeros_len <= 3;
|
||||
else if (heading_one_pos == 1)
|
||||
total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 2) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 5;
|
||||
else total_zeros_len <= 5;
|
||||
5:if (heading_one_pos == 0) total_zeros_len <= 4'd3;
|
||||
else if (heading_one_pos == 1)
|
||||
total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 2) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 4;
|
||||
else total_zeros_len <= 5;
|
||||
6:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos ==2)
|
||||
total_zeros_len <= 3;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 4) total_zeros_len <= 5;
|
||||
else total_zeros_len <= 6;
|
||||
7:if (heading_one_pos == 0 && BitStream_buffer_output[14] == 1)
|
||||
total_zeros_len <= 2;
|
||||
else if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2)
|
||||
total_zeros_len <= 3;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 4) total_zeros_len <= 5;
|
||||
else total_zeros_len <= 6;
|
||||
8:if (heading_one_pos == 0) total_zeros_len <= 2;
|
||||
else if (heading_one_pos == 1 || heading_one_pos == 2)
|
||||
total_zeros_len <= 3;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 4) total_zeros_len <= 5;
|
||||
else total_zeros_len <= 6;
|
||||
9:if (heading_one_pos == 0 || heading_one_pos == 1)
|
||||
total_zeros_len <= 2;
|
||||
else if (heading_one_pos == 2) total_zeros_len <= 3;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 4;
|
||||
else if (heading_one_pos == 4) total_zeros_len <= 5;
|
||||
else total_zeros_len <= 6;
|
||||
10:if (heading_one_pos == 0 || heading_one_pos == 1)
|
||||
total_zeros_len <= 2;
|
||||
else if (heading_one_pos == 2) total_zeros_len <= 3;
|
||||
else if (heading_one_pos == 3) total_zeros_len <= 4;
|
||||
else total_zeros_len <= 5;
|
||||
11:if (heading_one_pos == 0) total_zeros_len <= 1;
|
||||
else if (heading_one_pos == 1 || heading_one_pos == 2)
|
||||
total_zeros_len <= 3;
|
||||
else total_zeros_len <= 4;
|
||||
12:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2 || heading_one_pos == 3)
|
||||
total_zeros_len <= heading_one_pos + 1;
|
||||
else total_zeros_len <= 4;
|
||||
13:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2)
|
||||
total_zeros_len <= heading_one_pos + 1;
|
||||
else total_zeros_len <= 3;
|
||||
14:if (heading_one_pos == 0) total_zeros_len <= 1;
|
||||
else total_zeros_len <= 2;
|
||||
15:total_zeros_len <= 1;
|
||||
default:total_zeros_len <= 0;
|
||||
endcase
|
||||
end
|
||||
else
|
||||
total_zeros_len <= 0;
|
||||
|
||||
//total_zeros
|
||||
wire total_zeros_t0,total_zeros_t1;
|
||||
assign total_zeros_t0 = (cavlc_decoder_state == `total_zeros_LUT && maxNumCoeff != 4); //Table 9-7,9-8
|
||||
assign total_zeros_t1 = (cavlc_decoder_state == `total_zeros_LUT && maxNumCoeff == 4); //Table 9-9
|
||||
always @ (total_zeros_t0 or total_zeros_t1 or TotalCoeff_3to0 or heading_one_pos
|
||||
or BitStream_buffer_output or total_zeros_reg)
|
||||
if (total_zeros_t0)
|
||||
case (TotalCoeff_3to0)
|
||||
1:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= 4'd0;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= (BitStream_buffer_output[13])? 4'd1:4'd2;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= (BitStream_buffer_output[12])? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= (BitStream_buffer_output[11])? 4'd5:4'd6;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= (BitStream_buffer_output[10])? 4'd7:4'd8;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= (BitStream_buffer_output[9])? 4'd9:4'd10;
|
||||
else if (heading_one_pos == 4'd6)
|
||||
total_zeros <= (BitStream_buffer_output[8])? 4'd11:4'd12;
|
||||
else if (heading_one_pos == 4'd7)
|
||||
total_zeros <= (BitStream_buffer_output[7])? 4'd13:4'd14;
|
||||
else
|
||||
total_zeros <= 4'd15;
|
||||
2:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= {2'b0,~BitStream_buffer_output[14:13]};
|
||||
else if (heading_one_pos == 4'd1)
|
||||
case (BitStream_buffer_output[13:12])
|
||||
2'b01:total_zeros <= 4'd5;
|
||||
2'b00:total_zeros <= 4'd6;
|
||||
default:total_zeros <= 4'd4;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= (BitStream_buffer_output[12])? 4'd7:4'd8;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= (BitStream_buffer_output[11])? 4'd9:4'd10;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= (BitStream_buffer_output[10])? 4'd11:4'd12;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= 4'd13;
|
||||
else
|
||||
total_zeros <= 4'd14;
|
||||
3:
|
||||
if (heading_one_pos == 4'd0)
|
||||
case (BitStream_buffer_output[14:13])
|
||||
2'b00:total_zeros <= 4'd6;
|
||||
2'b01:total_zeros <= 4'd3;
|
||||
2'b10:total_zeros <= 4'd2;
|
||||
2'b11:total_zeros <= 4'd1;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd1)
|
||||
case (BitStream_buffer_output[13:12])
|
||||
2'b00:total_zeros <= 4'd4;
|
||||
2'b01:total_zeros <= 4'd0;
|
||||
default:total_zeros <= 4'd7;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= (BitStream_buffer_output[12])? 4'd5:4'd8;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= (BitStream_buffer_output[11])? 4'd9:4'd10;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd12;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= 4'd11;
|
||||
else
|
||||
total_zeros <= 4'd13;
|
||||
4:
|
||||
if (heading_one_pos == 4'd0)
|
||||
case (BitStream_buffer_output[14:13])
|
||||
2'b00:total_zeros <= 4'd6;
|
||||
2'b01:total_zeros <= 4'd5;
|
||||
2'b10:total_zeros <= 4'd4;
|
||||
2'b11:total_zeros <= 4'd1;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd1)
|
||||
case (BitStream_buffer_output[13:12])
|
||||
2'b00:total_zeros <= 4'd3;
|
||||
2'b01:total_zeros <= 4'd2;
|
||||
default:total_zeros <= 4'd8;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= (BitStream_buffer_output[12])? 4'd7:4'd9;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= (BitStream_buffer_output[11])? 4'd0:4'd10;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd11;
|
||||
else
|
||||
total_zeros <= 4'd12;
|
||||
5:
|
||||
if (heading_one_pos == 4'd0)
|
||||
case (BitStream_buffer_output[14:13])
|
||||
2'b00:total_zeros <= 4'd6;
|
||||
2'b01:total_zeros <= 4'd5;
|
||||
2'b10:total_zeros <= 4'd4;
|
||||
2'b11:total_zeros <= 4'd3;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd1)
|
||||
case (BitStream_buffer_output[13:12])
|
||||
2'b00:total_zeros <= 4'd1;
|
||||
2'b01:total_zeros <= 4'd0;
|
||||
default:total_zeros <= 4'd7;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= (BitStream_buffer_output[12])? 4'd2:4'd8;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd10;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd9;
|
||||
else
|
||||
total_zeros <= 4'd11;
|
||||
6:
|
||||
if (heading_one_pos == 4'd0)
|
||||
case (BitStream_buffer_output[14:13])
|
||||
2'b00:total_zeros <= 4'd5;
|
||||
2'b01:total_zeros <= 4'd4;
|
||||
2'b10:total_zeros <= 4'd3;
|
||||
2'b11:total_zeros <= 4'd2;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= (BitStream_buffer_output[13])? 4'd6:4'd7;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd9;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd8;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd1;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= 4'd0;
|
||||
else
|
||||
total_zeros <= 4'd10;
|
||||
7:
|
||||
if (heading_one_pos == 4'd0)
|
||||
case (BitStream_buffer_output[14:13])
|
||||
2'b00:total_zeros <= 4'd3;
|
||||
2'b01:total_zeros <= 4'd2;
|
||||
default:total_zeros <= 4'd5;
|
||||
endcase
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= (BitStream_buffer_output[13])? 4'd4:4'd6;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd8;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd7;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd1;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= 4'd0;
|
||||
else
|
||||
total_zeros <= 4'd9;
|
||||
8:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= (BitStream_buffer_output[14])? 4'd4:4'd5;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= (BitStream_buffer_output[13])? 4'd3:4'd6;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd7;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd1;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= 4'd0;
|
||||
else
|
||||
total_zeros <= 4'd8;
|
||||
9:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= (BitStream_buffer_output[14])? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= 4'd6;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd5;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd7;
|
||||
else if (heading_one_pos == 4'd5)
|
||||
total_zeros <= 4'd0;
|
||||
else
|
||||
total_zeros <= 4'd1;
|
||||
10:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= (BitStream_buffer_output[14])? 4'd3:4'd4;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= 4'd5;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd6;
|
||||
else if (heading_one_pos == 4'd4)
|
||||
total_zeros <= 4'd0;
|
||||
else
|
||||
total_zeros <= 4'd1;
|
||||
11:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= 4'd4;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= (BitStream_buffer_output[13])? 4'd5:4'd3;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd1;
|
||||
else
|
||||
total_zeros <= 4'd0;
|
||||
12:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= 4'd3;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd4;
|
||||
else if (heading_one_pos == 4'd3)
|
||||
total_zeros <= 4'd1;
|
||||
else
|
||||
total_zeros <= 4'd0;
|
||||
13:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= 4'd3;
|
||||
else if (heading_one_pos == 4'd2)
|
||||
total_zeros <= 4'd1;
|
||||
else
|
||||
total_zeros <= 4'd0;
|
||||
14:
|
||||
if (heading_one_pos == 4'd0)
|
||||
total_zeros <= 4'd2;
|
||||
else if (heading_one_pos == 4'd1)
|
||||
total_zeros <= 4'd1;
|
||||
else
|
||||
total_zeros <= 4'd0;
|
||||
default:total_zeros <= (heading_one_pos == 4'd0)? 4'd1:4'd0;
|
||||
endcase
|
||||
else if (total_zeros_t1)
|
||||
case (TotalCoeff_3to0)
|
||||
1:if (heading_one_pos == 4'd0) total_zeros <= 4'd0;
|
||||
else if (heading_one_pos == 4'd1) total_zeros <= 4'd1;
|
||||
else if (heading_one_pos == 4'd2) total_zeros <= 4'd2;
|
||||
else total_zeros <= 4'd3;
|
||||
2:if (heading_one_pos == 4'd0) total_zeros <= 4'd0;
|
||||
else if (heading_one_pos == 4'd1) total_zeros <= 4'd1;
|
||||
else total_zeros <= 4'd2;
|
||||
3:total_zeros <= {3'b0,~BitStream_buffer_output[15]};
|
||||
default:total_zeros <= 0;
|
||||
endcase
|
||||
else
|
||||
total_zeros <= total_zeros_reg;
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset_n == 0)
|
||||
total_zeros_reg <= 0;
|
||||
else if (cavlc_decoder_state == `total_zeros_LUT)
|
||||
total_zeros_reg <= total_zeros;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
#! /usr/bin/perl
|
||||
|
||||
# Author(s) : Ke Xu
|
||||
# Email : eexuke@yahoo.com
|
||||
# Description: Convert binary .264 file to text format
|
||||
# Usage : bin2hex.pl xxx.264
|
||||
# Copyright (C) 2008 Ke Xu
|
||||
|
||||
open STDOUT, ">akiyo300_1ref.txt" || die "Can't open output file:$!\n";
|
||||
if (open(BINFILE,"<".$ARGV[0]))
|
||||
{
|
||||
binmode(BINFILE);
|
||||
$s = '';
|
||||
$i = 0;
|
||||
while (!eof(BINFILE))
|
||||
{
|
||||
if ($i >= 2)
|
||||
{
|
||||
printf "%s\n",$s;
|
||||
$s = '';
|
||||
$i = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
$i++;
|
||||
$s .= sprintf("%02X",ord(getc(BINFILE)));
|
||||
}
|
||||
}
|
||||
###if last line of BINFILE is less than 16 byte
|
||||
if ($i < 2)
|
||||
{
|
||||
printf "%s",$s;
|
||||
}
|
||||
close (BINFILE);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,27 @@
|
||||
// Author(s) : Ke Xu
|
||||
// Email : eexuke@yahoo.com
|
||||
// Description: Convert text file to binary (.yuv) file
|
||||
// Copyright (C) 2008 Ke Xu
|
||||
|
||||
#include <stdio.h>
|
||||
int main ()
|
||||
{
|
||||
int buffer;
|
||||
int i;
|
||||
FILE * inFile;
|
||||
FILE * outFile;
|
||||
inFile = fopen ("C:/xxx/xxx/nova_display.log","r");
|
||||
outFile = fopen ("C:/xxx/xxx/nova300.yuv", "w+b");
|
||||
|
||||
//1 frame:9504 x 32bit
|
||||
//300 frame:9504 x 300 x 32 bit = 2851200 x 32bit
|
||||
for (i = 0; i < 2851200; i++)
|
||||
{
|
||||
fscanf (inFile,"%x",&buffer);
|
||||
fwrite (&buffer,4,1,outFile);
|
||||
}
|
||||
fclose (inFile);
|
||||
fclose (outFile);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,5 @@
|
||||
bin2hex.pl :convert binary .264 into text format.
|
||||
|
||||
hex2bin.cpp:convert text format to binary .264.
|
||||
|
||||
bitstream folder:encoded bitstream .264 should be converted first by bin2hex.pl while .txt can be directly read into verilog.
|
||||
Reference in New Issue
Block a user