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+
+The USB 2.0 Function Project Page is:
+http://www.opencores.org/cores/usb/
+
+To find out more about me (Rudolf Usselmann), please visit:
+http://www.asics.ws
+
+Directory Structure
+-------------------
+[core_root]
+ |
+ +-doc                        Documentation
+ |
+ +-bench--+                   Test Bench
+ |        +- verilog          Verilog Sources
+ |        +-vhdl              VHDL Sources
+ |
+ +-rtl----+                   Core RTL Sources
+ |        +-verilog           Verilog Sources
+ |        +-vhdl              VHDL Sources
+ |
+ +-sim----+
+ |        +-rtl_sim---+       Functional verification Directory
+ |        |           +-bin   Makefiles/Run Scripts
+ |        |           +-run   Working Directory
+ |        |
+ |        +-gate_sim--+       Functional & Timing Gate Level
+ |                    |       Verification Directory
+ |                    +-bin   Makefiles/Run Scripts
+ |                    +-run   Working Directory
+ |
+ +-lint--+                    Lint Directory Tree
+ |       +-bin                Makefiles/Run Scripts
+ |       +-run                Working Directory
+ |       +-log                Linter log & result files
+ |
+ +-syn---+                    Synthesis Directory Tree
+ |       +-bin                Synthesis Scripts
+ |       +-run                Working Directory
+ |       +-log                Synthesis log files
+ |       +-out                Synthesis Output
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+This file describes the current status of the checked in HDL code.
+Please submit all bugs/comments/suggestions regarding the USB core
+to: usb@opencores.org
+
+Need Help
+---------
+I'm looking for help in verifying the core. If you think you can help,
+please send an email to the list or to me directly.
+
+
+STATUS
+======
+
+Update (8/2/2001)
+-----------------
+- Changed Directory Structure
+
+Initial Release (31/3/2001)
+---------------------------
+- This is the second officially available release of the core
+- It is still under active development
+- Please do not modify the sources !
+- Things that are not implemented yet, or are known not to work yet:
+  - There is no logic in the core to "help" suspending it. I'm not
+    quite sure yet what to do in this area. (Suggestions welcomed !)
+  - There has been very little testing done on the core
+
+Initial Release (28/2/2001)
+---------------------------
+- This is the very first officially available release of the core
+- It is still under active development
+- Please do not modify the sources !
+- Things that are not implemented yet, or are known not to work yet:
+  - UTMI line/link control interface is not implemented yet. This includes:
+    - Detection of attach/detach
+    - Speed negotiation (Full/High Speed)
+    - USB reset
+    - USB suspend
+  - There is no logic in the core to "help" suspending it. I'm not
+    quite sure yet what to do in this area. (Suggestions welcomed !)
+  - There is no easy way to configure the core (number of endpoints,
+    buffer size)
+  - There has been absolutely no testing done on the core
+