Initial commit
This commit is contained in:
muellerlu
@@ -0,0 +1,78 @@
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export PRJ_ROOT = ../../..
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# directroy containig syrinx application programs
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SWDIR = $(PRJ_ROOT)/sw/risc-v
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DVDIR = $(PRJ_ROOT)/hw/dv
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# toplevel syrinx file list
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RTL_FLIST = $(PRJ_ROOT)/hw/file_lists/rtl_flist.f
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TB_FLIST = $(PRJ_ROOT)/hw/file_lists/tb_flist.f
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# if we have multiple file list, we combine them here
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FLIST = -f $(RTL_FLIST) -f $(TB_FLIST)
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# Default number of simulation cycles
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NCYCLES ?= 500
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# Standard boot loader and dummy application to be used if nothing else is specified
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PROG ?= $(SWDIR)/hello_world/helloWorld.hex
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# top module name
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TOPMODULE = cpu_harness
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# NUmber of GCC parallel threads
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COMPILE_THREADS = 32
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# Verilator CPU usage, should be adapated to simulation host
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SIM_THREADS = 4
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TRACE_THREADS = 1
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EXTRA_ARGS += --trace-fst --trace-structs --trace-max-array 2048 --trace-threads $(TRACE_THREADS) --threads $(SIM_THREADS)
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EXTRA_ARGS += --clk clk --no-timing
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# EXTRA_ARGS += -O2
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# Used by some code constructs
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VDEFS = +define+SIMULATION
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all: ./obj_dir/V$(TOPMODULE)
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wave: wavedump.fst
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@echo
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@echo "*** Starting waveform viewer..."
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$(WAVE_VIEWER) wavedump.fst -s $(DVDIR)/wave_configs/verilator_wave.surf.ron
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run:
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@echo
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@echo "*** Running simulation..."
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@./obj_dir/V$(TOPMODULE) $(NCYCLES) $(PROG)
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./obj_dir/V$(TOPMODULE): .stamp.verilate
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@echo
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@echo "*** Building simulator..."
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make -C obj_dir -f V$(TOPMODULE).mk V$(TOPMODULE) -j $(COMPILE_THREADS)
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.stamp.verilate: src/tb_$(TOPMODULE).cpp
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@echo "*** Generating C++ model..."
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$(VERILATOR) --trace $(EXTRA_ARGS) $(VDEFS) -cc $(FLIST) --top-module $(TOPMODULE) --exe src/tb_$(TOPMODULE).cpp
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@touch .stamp.verilate
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lint:$(VERILOG_SOURCES)
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$(VERILATOR) --lint-only $(INCLUDES) $(VERILOG_SOURCES) --top-module $(TOPMODULE)
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paths:
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@echo $(PRJ_ROOT)/$(APB)
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clean:
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rm -rf .stamp.*;
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rm -rf ./obj_dir
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rm -rf wavedump.fst*
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rm -rf *.dasm
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@@ -0,0 +1,148 @@
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// *********************************************************************************************
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// Description : Verilator simulation harness
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Aug.2025 by Marcus Bednara
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// Last Modified : 15.Oct.2025 by Hussein Elzomor [commit d0452cd]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 H.Elzomor Renamed file and module from soc_harness to cpu_harness
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// 15.Oct.2025 H.Elzomor Added getMem function, setMem task and printMem task
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// *********************************************************************************************
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timeunit 1ps;
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timeprecision 1ps;
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module cpu_harness;
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// local signals
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logic clk,
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rst;
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logic [7:0] led;
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logic [6:0] btn;
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// toplevel instance (DUT)
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cpu u_cpu (
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.led (led),
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.btn ({btn[6:1], rst}),
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.clk_25mhz (clk)
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); // u_cpu
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`ifdef VERILATOR
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// Declare all functions with DPI-C interface to make them accessible from the C++ testbench
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export "DPI-C" task setClk;
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export "DPI-C" task enable;
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export "DPI-C" task loadRAM;
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// export "DPI-C" task dumpSRAM;
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export "DPI-C" task setInitial;
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export "DPI-C" function getLed;
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export "DPI-C" task setBtn;
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export "DPI-C" task setReset;
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export "DPI-C" function getMem;
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export "DPI-C" task setMem;
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export "DPI-C" task printMem;
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export "DPI-C" function getReg;
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export "DPI-C" task printReg;
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// Clocking is controlled from C++ testbench
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task setClk (input logic val);
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clk = val;
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endtask: setClk
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`else
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// If not using verilator, generate clock here
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const realtime clk_PERIOD = 1.0ns;
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initial begin: clock_driver
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clk = '1;
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forever begin
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#(clk_PERIOD/2.0);
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clk <= ~clk;
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end
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end: clock_driver
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task wait_clk_cycles(int unsigned n);
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repeat(n) @(posedge clk);
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endtask
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`endif
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// Remaining tasks are identical for Verilator and other simulators
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task loadRAM (input string fileName);
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$display ("Initializing SRAM memory from %s", fileName);
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$readmemh(fileName, u_cpu.theMem.RAM);
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endtask: loadRAM
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/* Some helper stuff */
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task enable(int val);
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// nothing to do, we have no fetch enable in this design
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endtask: enable
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task setInitial();
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btn = 7'b0;
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rst = 'b0;
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endtask: setInitial
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function int getLed;
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getLed = {24'b0, led};
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endfunction: getLed
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task setBtn(int val);
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btn[6:1] = val[5:0];
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endtask: setBtn
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task setReset (input int val);
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rst = (val==1);
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endtask: setReset
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function int getMem(int location);
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getMem = u_cpu.theMem.RAM[location];
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endfunction: getMem
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task setMem(int location, int value);
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u_cpu.theMem.RAM[location] = value;
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endtask: setMem
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task printMem (int location, string prog);
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case (prog)
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"fibonacci" :$display("Value at RAM[%0d]: 0x%h : %0d", location, getMem(location), getMem(location));
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"helloWorld" :$display("Value at RAM[%0d]: 0x%h : %s" , location, getMem(location), getMem(location));
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default :$display("Value at RAM[%0d]: 0x%h : %0d", location, getMem(location), getMem(location));
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endcase
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endtask: printMem
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function int getReg(int location);
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getReg = u_cpu.theRegisters.registers[location];
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endfunction: getReg
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task printReg (int location, string prog);
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case (prog)
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"primeNumber" :$display("Time =%5dns \t : Register [%0d] updated - Finding the prime factors of %0d", $time, location, getReg(location));
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"primeFactors":$display("Time =%5dns \t : Register [%0d] updated - %0d is a prime factor", $time, location, getReg(location));
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default :$display("Time =%5dns \t : Value at Reg[%0d]: 0x%h", $time, location, getReg(location));
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endcase
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endtask: printReg
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endmodule: cpu_harness
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@@ -0,0 +1,173 @@
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// *********************************************************************************************
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// Description : Verilator simulation harness
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 15.Oct.2025 by Hussein Elzomor
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// Last Modified : 15.Oct.2025 by Hussein Elzomor
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// *********************************************************************************************
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timeunit 1ps;
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timeprecision 1ps;
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module decoder_harness;
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// local Parameters
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localparam MEM_SIZE = 37;
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localparam REG_FILE_SIZE = 32;
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// local signals
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logic clk;
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int counter;
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logic[31:0] mem [MEM_SIZE-1:0];
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logic[31:0] regFile [REG_FILE_SIZE-1:0];
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// PC
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logic[31:0] CurrentPC;
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logic[31:0] JumpOrBranchPC;
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logic JumpOrBranch;
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logic[31:0] NextPC;
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// Memory
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logic[31:0] DAddr;
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logic[31:0] WData;
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logic[31:0] RData;
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logic[31:0] Instruction;
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logic WrMem;
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logic[1:0] DWidth;
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// Register File;
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logic[4:0] Rs1;
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logic[4:0] Rs2;
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logic[4:0] Rd;
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logic[31:0] RRs1;
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logic[31:0] RRs2;
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logic[31:0] WRd;
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logic WrReg;
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// Protection
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logic Illegal;
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// toplevel instance (DUT)
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decoder u_decoder (
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// PC
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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// Memory
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.DAddr(DAddr),
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.WData(WData),
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.RData(RData),
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.Instruction(Instruction),
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.WrMem(WrMem),
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.DWidth(DWidth),
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// Register File
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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// Protection
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.Illegal(Illegal)
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); // u_decoder
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// Special Verilator specific tasks
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`ifdef VERILATOR
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// Declare all functions with DPI-C interface to make them accessible from the C++ testbench
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// Setters
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export "DPI-C" task setClk;
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export "DPI-C" task enable;
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export "DPI-C" task loadRAM;
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export "DPI-C" task setInitial;
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export "DPI-C" task printInfo;
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// Clocking is controlled from C++ testbench
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task setClk (input logic val);
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clk = val;
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endtask: setClk
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`else
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// If not using verilator, generate clock here
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const realtime clk_PERIOD = 1.0ns;
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initial begin: clock_driver
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clk = '1;
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forever begin
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#(clk_PERIOD/2.0);
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clk <= ~clk;
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end
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end: clock_driver
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task wait_clk_cycles(int unsigned n);
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repeat(n) @(posedge clk);
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endtask
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`endif
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// Load a new instruction every cycle
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always_ff @(posedge clk) begin: increment_instruction_and_print_info
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if (counter < MEM_SIZE) begin
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if (counter > 0) printInfo();
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Instruction = mem[counter++];
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end
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end
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// Return the value of the RegFile
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always_comb begin: reg_file_assignment
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RRs1 = regFile[Rs1];
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RRs2 = regFile[Rs2];
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end
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// Remaining tasks are identical for Verilator and other simulators
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task enable(int val);
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// nothing to do, we have no fetch enable in this design
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endtask: enable
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// Load data into memory
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task loadRAM (input string fileName);
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$display ("Initializing SRAM memory from %s", fileName);
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$readmemh(fileName, mem);
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endtask: loadRAM
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// Set initial values
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task setInitial();
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Instruction = mem[0];
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counter = 0;
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CurrentPC = 32'hdeadbeef;
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RData = 32'hbeefdead;
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for(int i=0; i<REG_FILE_SIZE; i++) begin
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regFile[i] = i;
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end
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endtask: setInitial
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// Print decoder signals
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task printInfo();
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$displayh("(cycle %0d) Decoder (I/O) \tDecoder (Internal Signals) \tALU" , counter );
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$displayh(" -------------------------- \t--------------------------------------------- \t---------------------" , );
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$displayh(" CurrentPC : 0x%h OpCode : 0b%b aluOp : 0b%b" , CurrentPC , u_decoder.theOp , u_decoder.aluOp );
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$displayh(" JumpOrBranchPC: 0x%h theFunct3: 0b%b aluNegAr : 0b%b", JumpOrBranchPC, u_decoder.theFunct3, u_decoder.aluNegAr );
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$displayh(" JumpOrBranch : 0b%b \ttheFunct7: 0b%b aluBypass: 0b%b", JumpOrBranch , u_decoder.theFunct7, u_decoder.aluBypass);
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$displayh(" DAddr : 0x%h i_imm : 0b%b op1 : 0x%h" , DAddr , u_decoder.i_imm , u_decoder.op1 );
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$displayh(" WData : 0x%h s_imm : 0b%b op2 : 0x%h" , WData , u_decoder.s_imm , u_decoder.op2 );
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$displayh(" RData : 0x%h b_imm : 0b%b result : 0x%h" , RData , u_decoder.b_imm , u_decoder.result );
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$displayh(" Instruction : 0x%h u_imm : 0b%b eqFlag : 0b%b" , Instruction , u_decoder.u_imm , u_decoder.eqFlag );
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$displayh(" WrMem : 0b%b \tj_imm : 0b%b" , WrMem , u_decoder.j_imm );
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$displayh(" DWidth : 0b%b" , DWidth );
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$displayh(" Rs1 : %0d " , Rs1 );
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$displayh(" Rs2 : %0d " , Rs2 );
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$displayh(" Rd : 0x%h" , Rd );
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$displayh(" RRs1 : %0d " , RRs1 );
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$displayh(" RRs2 : %0d " , RRs2 );
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$displayh(" WRd : 0x%h" , WRd );
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$displayh(" WrReg : 0b%b" , WrReg );
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$displayh(" Illegal : 0b%b" , Illegal );
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$displayh("");
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endtask: printInfo
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endmodule: decoder_harness
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@@ -0,0 +1,328 @@
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// *********************************************************************************************
|
||||
// Description : Verilator tb
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 12.Aug.2025 by Marcus Bednara
|
||||
// Last Modified : 15.Oct.2025 by Hussein Elzomor [commit d0452cd]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// 15.Oct.2025 H.Elzomor Renamed modules from *soc* to *cpu*
|
||||
// 15.Oct.2025 H.Elzomor Added evalText function
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
|
||||
using namespace std;
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||||
|
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#include <stdlib.h>
|
||||
#include <iostream>
|
||||
#include <verilated.h>
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#include <verilated_fst_c.h>
|
||||
#include "Vcpu_harness.h"
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#include "Vcpu_harness__Dpi.h"
|
||||
|
||||
// only required for accessing model internal memory ressources via the rootp pointer.
|
||||
// Bad style, better use systemverilog harness with tasks and functions to do that.
|
||||
// #include "Vcpu_harness___024root.h"
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// #include "svdpi.h"
|
||||
|
||||
|
||||
#define SOC_CLK_PERIOD 40
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||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Simulation environment class for the cpu model.
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/// Contains a set of high level methods for controlling the model from test environment.
|
||||
class cpu
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{
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||||
private:
|
||||
|
||||
Vcpu_harness *dut;
|
||||
VerilatedFstC *mTrace;
|
||||
vluint64_t T;
|
||||
|
||||
uint32_t cpuClkState;
|
||||
|
||||
bool running;
|
||||
|
||||
string program;
|
||||
|
||||
public:
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Constructor
|
||||
cpu (int argc, char** argv)
|
||||
{
|
||||
// setup verilator stuff
|
||||
T = 0;
|
||||
dut = new Vcpu_harness();
|
||||
Verilated::commandArgs(argc, argv);
|
||||
Verilated::traceEverOn(true);
|
||||
mTrace = new VerilatedFstC;
|
||||
dut->trace(mTrace, 5);
|
||||
mTrace->open("wavedump.fst");
|
||||
|
||||
cout << "Registered DPI-C functions:\n";
|
||||
Verilated::scopesDump();
|
||||
const svScope scope = svGetScopeFromName("TOP.cpu_harness");
|
||||
assert(scope); // Check for nullptr if scope not found
|
||||
svSetScope(scope);
|
||||
|
||||
running = false;
|
||||
|
||||
// initialize all input signals
|
||||
initSignals();
|
||||
|
||||
} // swirl()
|
||||
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief simulation tick, advances the simulation time and calls the eval() function of the model on every active clock edge
|
||||
void tick ()
|
||||
{
|
||||
int do_eval;
|
||||
|
||||
if (T%SOC_CLK_PERIOD==0) {
|
||||
dut->setClk(cpuClkState);
|
||||
cpuClkState = 1-cpuClkState;
|
||||
do_eval = 1;
|
||||
}
|
||||
|
||||
|
||||
// Other clock domains must be generated the same way
|
||||
|
||||
// if (T%OTHER_CLK_PERIOD==0) {
|
||||
// dut->setOtherClk(otherClkState);
|
||||
// otherClkState = 1-otherClkState;
|
||||
// do_eval = 1;
|
||||
// }
|
||||
|
||||
if (do_eval) {
|
||||
dut->eval();
|
||||
// evaluate the LED status in each clock cycle if the CPU is running (i.e., after reset)
|
||||
if (running && program == "unknown") evalLed();
|
||||
// evaluate the Fibonacci Series location in stack (starting at 2027) and print value if it has changed
|
||||
if (running && program == "fibonacci") evalFibonacci();
|
||||
// evaluate the 'hello world!' location in the DataMem in each clock cycle if the CPU is running (i.e., after reset)
|
||||
if (running && program == "helloWorld") evalHelloWorld();
|
||||
// evaluate the Prime Factors location in RegFile (x17) and print value if it has changed
|
||||
if (running && program == "primeFactors") evalPrimeFactors();
|
||||
mTrace->dump(T);
|
||||
do_eval = 0;
|
||||
}
|
||||
|
||||
T++;
|
||||
|
||||
} // tick()
|
||||
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Initialize all input signals of the hardware model to a defined value
|
||||
void initSignals()
|
||||
{
|
||||
dut->setInitial();
|
||||
} // initSignals()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Wait for a number of active edges of clk signal
|
||||
/// @param numEdges number of rising edges
|
||||
/// @param active active 1=rising 0=falling edge
|
||||
void waitClocks (int numEdges=1, int activeEdge=1)
|
||||
{
|
||||
int clk_d;
|
||||
|
||||
for (int j=0; j<numEdges; ++j) {
|
||||
while (1) {
|
||||
clk_d = cpuClkState;
|
||||
tick();
|
||||
if (clk_d==1-activeEdge && cpuClkState==activeEdge) break;
|
||||
}
|
||||
} // for
|
||||
} // waitClocks()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Toggle the reset signal active (low)
|
||||
/// @param numEdges number of clock cyles keeping the reset active
|
||||
void reset (int numEdges=1)
|
||||
{
|
||||
dut->setReset(0); // reset is active low
|
||||
waitClocks (numEdges);
|
||||
dut->setReset(1);
|
||||
} // reset();
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief load the cpu memory from vmem formatted file
|
||||
void loadRAM (char* vmemFile)
|
||||
{
|
||||
dut->loadRAM(vmemFile);
|
||||
} // loadRAM()
|
||||
|
||||
/// @brief check the LED status and print value if it has change
|
||||
void evalLed ()
|
||||
{
|
||||
static uint8_t oldLedStatus=0xff;
|
||||
uint8_t currentLedStatus;
|
||||
currentLedStatus=dut->getLed();
|
||||
if (currentLedStatus!=oldLedStatus) {
|
||||
cout << "T=" << T << ": LED=" << std::bitset<8>(currentLedStatus) << endl;
|
||||
oldLedStatus = currentLedStatus;
|
||||
}
|
||||
} // evalLed()
|
||||
|
||||
/// @brief check Fibonacci Series location in stack (starting at 2027) and print value if it has changed
|
||||
void evalFibonacci()
|
||||
{
|
||||
int memStartLoc = 2027;
|
||||
const int memLengthInBytes = 40;
|
||||
const int memLengthInWords = ceil(memLengthInBytes / 4.0);
|
||||
static uint32_t oldValue[memLengthInWords];
|
||||
uint32_t vlaue[memLengthInWords];
|
||||
bool update = 0;
|
||||
for (int i = 0; i < memLengthInWords; i++)
|
||||
{
|
||||
vlaue[i] = dut->getMem(memStartLoc + i);
|
||||
if (oldValue[i] != vlaue[i])
|
||||
update = 1;
|
||||
}
|
||||
if (update)
|
||||
{
|
||||
cout << endl
|
||||
<< "T=" << T << ": \t Hex \t Dec" << endl;
|
||||
for (int i = 0; i < memLengthInWords; i++)
|
||||
{
|
||||
dut->printMem(memStartLoc + i, "fibonacci");
|
||||
oldValue[i] = vlaue[i];
|
||||
}
|
||||
cout << endl;
|
||||
}
|
||||
} // evalFibonacci()
|
||||
|
||||
/// @brief check 'hello world' location in DataMem (starting at 1024) and print value if it has changed
|
||||
void evalHelloWorld()
|
||||
{
|
||||
int memStartLoc = 1024;
|
||||
const int memLengthInBytes = 13;
|
||||
const int memLengthInWords = ceil(memLengthInBytes / 4.0);
|
||||
static uint32_t oldValue[memLengthInWords];
|
||||
uint32_t vlaue[memLengthInWords];
|
||||
bool update = 0;
|
||||
for (int i = 0; i < memLengthInWords; i++)
|
||||
{
|
||||
vlaue[i] = dut->getMem(memStartLoc + i);
|
||||
if (oldValue[i] != vlaue[i])
|
||||
update = 1;
|
||||
}
|
||||
if (update)
|
||||
{
|
||||
cout << endl
|
||||
<< "T=" << T << ": \t Hex \t ASCII" << endl;
|
||||
for (int i = 0; i < memLengthInWords; i++)
|
||||
{
|
||||
dut->printMem(memStartLoc + i, "helloWorld");
|
||||
oldValue[i] = vlaue[i];
|
||||
}
|
||||
cout << endl;
|
||||
}
|
||||
} // evalHelloWorld()
|
||||
|
||||
/// @brief check Prime Factors location in RegFile (x17) and print value if it has changed
|
||||
void evalPrimeFactors()
|
||||
{
|
||||
// Number to be factorised
|
||||
int regLoc_Number = 16;
|
||||
static uint32_t oldValue_Number;
|
||||
uint32_t value_Number;
|
||||
value_Number = dut->getReg(regLoc_Number);
|
||||
if (oldValue_Number != value_Number & value_Number > 1) dut->printReg(regLoc_Number, "primeNumber");
|
||||
oldValue_Number = value_Number;
|
||||
|
||||
// Prime Factors
|
||||
int regLoc_PrimeFactor = 17;
|
||||
static uint32_t oldValue_PrimeFactor;
|
||||
uint32_t value_PrimeFactor;
|
||||
value_PrimeFactor = dut->getReg(regLoc_PrimeFactor);
|
||||
if (oldValue_PrimeFactor != value_PrimeFactor & value_PrimeFactor > 1) dut->printReg(regLoc_PrimeFactor, "primeFactors");
|
||||
oldValue_PrimeFactor = value_PrimeFactor;
|
||||
|
||||
} // evalPrimeFactors()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief start the DUT
|
||||
void start()
|
||||
{
|
||||
running = true;
|
||||
dut->enable(1);
|
||||
} // start()
|
||||
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief close the trace file and delete the Verilator object
|
||||
void stop()
|
||||
{
|
||||
dut->enable(0);
|
||||
mTrace->close();
|
||||
delete dut;
|
||||
} // stop()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Set the program name
|
||||
void setProgram(string prog)
|
||||
{
|
||||
if (prog.find("fibonacci") != string::npos) program = "fibonacci";
|
||||
else if (prog.find("helloWorld") != string::npos) program = "helloWorld";
|
||||
else if (prog.find("primeFactors") != string::npos) program = "primeFactors";
|
||||
else program = "unknown";
|
||||
|
||||
cout << "program set to " << program << endl;
|
||||
} // setProgram()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Get the program name
|
||||
string getProgram()
|
||||
{
|
||||
return program;
|
||||
} // getProgram()
|
||||
|
||||
}; // class cpu
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int main (int argc, char** argv)
|
||||
{
|
||||
uint32_t nCycles;
|
||||
char* program_path = new char[strlen(argv[2])]();
|
||||
|
||||
// Get number of simulation cycles
|
||||
nCycles = atoi(argv[1]);
|
||||
|
||||
// Get the program
|
||||
program_path = argv[2];
|
||||
string program_path_str = program_path;
|
||||
|
||||
cout << "\nCreating model...\n";
|
||||
cpu *m = new cpu(argc, argv);
|
||||
m->loadRAM(program_path);
|
||||
m->setProgram(program_path_str);
|
||||
|
||||
cout << "\nStarting model...\n";
|
||||
|
||||
cout << "\nResetting...\n";
|
||||
m->reset(10);
|
||||
|
||||
cout << "Starting CPU...\n" << std::flush;
|
||||
m->start();
|
||||
|
||||
cout << "Running for " << nCycles << " clock cycles...\n\n" << std::flush;
|
||||
cout << "Printing evaluation for " << m->getProgram() << " program!\n" << std::flush;
|
||||
m->waitClocks(nCycles);
|
||||
|
||||
cout << "\nDone, closing simulation.\n\n\n" << std::flush;
|
||||
m->stop();
|
||||
delete m;
|
||||
|
||||
exit(EXIT_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,185 @@
|
||||
// *********************************************************************************************
|
||||
// Description : Verilator tb
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 15.Oct.2025 by Hussein Elzomor
|
||||
// Last Modified : 15.Oct.2025 by Hussein Elzomor
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
|
||||
using namespace std;
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <iostream>
|
||||
#include <verilated.h>
|
||||
#include <verilated_fst_c.h>
|
||||
#include "Vdecoder_harness.h"
|
||||
#include "Vdecoder_harness__Dpi.h"
|
||||
|
||||
// only required for accessing model internal memory ressources via the rootp pointer.
|
||||
// Bad style, better use systemverilog harness with tasks and functions to do that.
|
||||
// #include "Vdecoder_harness___024root.h"
|
||||
// #include "svdpi.h"
|
||||
|
||||
|
||||
#define DECODER_CLK_PERIOD 40
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Simulation environment class for the decoder model.
|
||||
/// Contains a set of high level methods for controlling the model from test environment.
|
||||
class decoder
|
||||
{
|
||||
private:
|
||||
|
||||
Vdecoder_harness *dut;
|
||||
VerilatedFstC *mTrace;
|
||||
vluint64_t T;
|
||||
|
||||
uint32_t decoderClkState;
|
||||
bool running;
|
||||
|
||||
public:
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Constructor
|
||||
decoder (int argc, char** argv)
|
||||
{
|
||||
// setup verilator stuff
|
||||
T = 0;
|
||||
dut = new Vdecoder_harness();
|
||||
Verilated::commandArgs(argc, argv);
|
||||
Verilated::traceEverOn(true);
|
||||
mTrace = new VerilatedFstC;
|
||||
dut->trace(mTrace, 5);
|
||||
mTrace->open("wavedump.fst");
|
||||
|
||||
cout << "Registered DPI-C functions:\n";
|
||||
Verilated::scopesDump();
|
||||
const svScope scope = svGetScopeFromName("TOP.decoder_harness");
|
||||
assert(scope); // Check for nullptr if scope not found
|
||||
svSetScope(scope);
|
||||
|
||||
running = false;
|
||||
|
||||
// initialize all input signals
|
||||
initSignals();
|
||||
|
||||
} // swirl()
|
||||
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief simulation tick, advances the simulation time and calls the eval() function of the model on every active clock edge
|
||||
void tick ()
|
||||
{
|
||||
int do_eval;
|
||||
|
||||
if (T%DECODER_CLK_PERIOD==0) {
|
||||
dut->setClk(decoderClkState);
|
||||
decoderClkState = 1-decoderClkState;
|
||||
do_eval = 1;
|
||||
}
|
||||
|
||||
if (do_eval) {
|
||||
dut->eval();
|
||||
mTrace->dump(T);
|
||||
do_eval = 0;
|
||||
}
|
||||
|
||||
T++;
|
||||
|
||||
} // tick()
|
||||
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Initialize all input signals of the hardware model to a defined value
|
||||
void initSignals()
|
||||
{
|
||||
dut->setInitial();
|
||||
} // initSignals()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief Wait for a number of active edges of clk signal
|
||||
/// @param numEdges number of rising edges
|
||||
/// @param active active 1=rising 0=falling edge
|
||||
void waitClocks (int numEdges=1, int activeEdge=1)
|
||||
{
|
||||
int clk_d;
|
||||
|
||||
for (int j=0; j<numEdges; ++j) {
|
||||
while (1) {
|
||||
clk_d = decoderClkState;
|
||||
tick();
|
||||
if (clk_d==1-activeEdge && decoderClkState==activeEdge) break;
|
||||
}
|
||||
} // for
|
||||
} // waitClocks()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief load the decoder memory from vmem formatted file
|
||||
void loadRAM(char *vmemFile)
|
||||
{
|
||||
dut->loadRAM(vmemFile);
|
||||
} // loadRAM()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief start the DUT
|
||||
void start()
|
||||
{
|
||||
running = true;
|
||||
dut->enable(1);
|
||||
} // start()
|
||||
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief close the trace file and delete the Verilator object
|
||||
void stop()
|
||||
{
|
||||
dut->enable(0);
|
||||
mTrace->close();
|
||||
delete dut;
|
||||
} // stop()
|
||||
|
||||
//--------------------------------------------------------------
|
||||
/// @brief print signal info
|
||||
void printInfo()
|
||||
{
|
||||
dut->printInfo();
|
||||
}
|
||||
}; // class decoder
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int main (int argc, char** argv)
|
||||
{
|
||||
uint32_t nCycles;
|
||||
int r;
|
||||
|
||||
// Get number of simulation cycles
|
||||
nCycles = atoi(argv[1]);
|
||||
|
||||
cout << "\nCreating model...\n";
|
||||
decoder *m = new decoder(argc, argv);
|
||||
m->loadRAM(argv[2]);
|
||||
|
||||
cout << "Starting DECODER simulation...\n" << std::flush;
|
||||
m->start();
|
||||
|
||||
cout << "Running for " << nCycles << " clock cycles...\n" << std::flush;
|
||||
m->waitClocks(nCycles);
|
||||
|
||||
m->printInfo();
|
||||
|
||||
cout << "\nDone, closing simulation.\n\n\n" << std::flush;
|
||||
m->stop();
|
||||
delete m;
|
||||
|
||||
exit(EXIT_SUCCESS);
|
||||
}
|
||||
Reference in New Issue
Block a user