77 lines
3.5 KiB
Tcl
77 lines
3.5 KiB
Tcl
# =============================================================================
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# Constraints File: cpu.sdc
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# Project: BCDC Microtec Academy - RISC-V CPU
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# Top Module: cpu
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# =============================================================================
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# -----------------------------------------------------------------------------
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# 1. Primary Clock - 25 MHz input clock
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# -----------------------------------------------------------------------------
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create_clock -name clk_25mhz \
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-period 40.000 \
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-waveform {0 20} \
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[get_ports clk_25mhz]
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# -----------------------------------------------------------------------------
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# 2. Generated Clock - 12.5 MHz (divided by 2 inside always_ff)
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# -----------------------------------------------------------------------------
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#create_generated_clock -name clk_12p5 \
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# -source [get_ports clk_25mhz] \
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# -divide_by 2 \
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# [get_pins thePC/clk]
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# -----------------------------------------------------------------------------
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# 3. Clock Uncertainty & Transition
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# -----------------------------------------------------------------------------
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set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz]
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set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz]
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set_clock_transition 0.1 [get_clocks clk_25mhz]
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# -----------------------------------------------------------------------------
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# 4. Input Delays (btn pins - relative to clk_25mhz)
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# -----------------------------------------------------------------------------
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set_input_delay -clock clk_25mhz -max 2.0 [get_ports {btn[*]}]
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set_input_delay -clock clk_25mhz -min 0.5 [get_ports {btn[*]}]
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# -----------------------------------------------------------------------------
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# 5. Output Delays (led pins)
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# -----------------------------------------------------------------------------
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set_output_delay -clock clk_25mhz -max 2.0 [get_ports {led[*]}]
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set_output_delay -clock clk_25mhz -min 0.5 [get_ports {led[*]}]
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# -----------------------------------------------------------------------------
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# 6. False Paths
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# -----------------------------------------------------------------------------
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# Reset is async and driven from a button - no timing analysis needed
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set_false_path -from [get_ports {btn[0]}]
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# LED outputs driven from combinational/slow logic - relax if needed
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# set_false_path -to [get_ports {led[*]}]
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# -----------------------------------------------------------------------------
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# 7. Clock Domain Crossing
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# -----------------------------------------------------------------------------
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# clk12p5 is derived from clk_25mhz via FF division - set as async crossing
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# to prevent hold violations across the two domains
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#set_clock_groups -asynchronous \
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-group [get_clocks clk_25mhz] \
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-group [get_clocks clk_12p5]
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# -----------------------------------------------------------------------------
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# 8. Drive Strength & Load (adjust to your target technology)
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# -----------------------------------------------------------------------------
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#set_driving_cell -lib_cell <YOUR_INPUT_BUF> [get_ports {btn[*]}]
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set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[*]}]
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set_load 0.05 [get_ports {led[*]}]
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# -----------------------------------------------------------------------------
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# 9. Max Fanout & Transition
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# -----------------------------------------------------------------------------
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set_max_fanout 20 [current_design]
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set_max_transition 0.5 [current_design]
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