15 lines
237 B
Systemverilog
15 lines
237 B
Systemverilog
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`include "../spi_interface.v"
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`include "../fsm/Fsm.sv"
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module Top(
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input wire clk
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);
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// Bus (Interface)
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// SPI Interface
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// FSM
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// Parallelport
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// FRAM-Controller
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// Timer
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// Ampelsteuerung
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endmodule
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