I hate git

Top/Top.sv

 `include "../spi_interface.v"
 `include "../fsm/Fsm.sv"
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->>>>>>> b8d8341 (Initalized top level design)
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 `include "../Bus_if/Bus_if.sv"
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->>>>>>> c93bdaf (Added bus_if and fsm to top level design)
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 `include "../timer_port/timer_top.sv"
->>>>>>> 026899b (Added parallelport, timer and ampelsteuerung)
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-`include "../Bus_if/Bus_if.sv"
-`include "../timer_port/timer_top.sv"
->>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
 
 module Top(
     input wire clk,
     // Bus (Interface)
     Bus_if bus(.clk(clk));
     // SPI Interface
-    
     // FSM
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->>>>>>> b8d8341 (Initalized top level design)
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->>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
     Fsm fsm(
         .clk(clk),
         .inAlarmAmpel(bus.AlarmAmpel),
         .outSendData(bus.SendData),
         .outTimerEN(bus.TimerEN)
     );
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->>>>>>> c93bdaf (Added bus_if and fsm to top level design)
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->>>>>>> 026899b930835597e8ea85d65177e75bdc2b1a06
     // Parallelport
     parallelport parallelport1 (
         .inClk(clk),
         .alarm(bus.AlarmAmpel)
     );
 
-    assign AlarmAmpel = bus.AlarmAmpel;
-    
+    assign AlarmAmpel = bus.AlarmAmpel;  
 endmodule