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Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design
top_level_design
1 changed files with 8 additions and 0 deletions
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Top/Top.sv
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| `include "../spi_interface.v" | `include "../spi_interface.v" | ||||
| `include "../fsm/Fsm.sv" | `include "../fsm/Fsm.sv" | ||||
| <<<<<<< HEAD | |||||
| `include "../Bus_if/Bus_if.sv" | `include "../Bus_if/Bus_if.sv" | ||||
| ======= | |||||
| >>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 | |||||
| module Top( | module Top( | ||||
| input wire clk | input wire clk | ||||
| ); | ); | ||||
| // Bus (Interface) | // Bus (Interface) | ||||
| <<<<<<< HEAD | |||||
| Bus_if bus(.clk(clk)); | Bus_if bus(.clk(clk)); | ||||
| // SPI Interface | // SPI Interface | ||||
| // FSM | // FSM | ||||
| .outSendData(bus.SendData), | .outSendData(bus.SendData), | ||||
| .outTimerEN(bus.TimerEN) | .outTimerEN(bus.TimerEN) | ||||
| ); | ); | ||||
| ======= | |||||
| // SPI Interface | |||||
| // FSM | |||||
| >>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 | |||||
| // Parallelport | // Parallelport | ||||
| // FRAM-Controller | // FRAM-Controller | ||||
| // Timer | // Timer |
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