kuntzschcl/ESY1_Projekt_2022
kuntzschcl/ESY1_Projekt_2022
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge branch 'top_level_design' of https://git.efi.th-nuernberg.de/gitea/kuntzschcl/ESY1_Projekt_2022 into top_level_design

Browse Source
This commit is contained in:
sessleral71711 2022-06-14 11:51:22 +02:00
commit 4b0451fc63
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Top/Top.sv
View File

@ -1,11 +1,15 @@
`include "../spi_interface.v" `include "../spi_interface.v"
`include "../fsm/Fsm.sv" `include "../fsm/Fsm.sv"
<<<<<<< HEAD
`include "../Bus_if/Bus_if.sv" `include "../Bus_if/Bus_if.sv"
=======
>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
module Top( module Top(
input wire clk input wire clk
); );
// Bus (Interface) // Bus (Interface)
<<<<<<< HEAD
Bus_if bus(.clk(clk)); Bus_if bus(.clk(clk));
// SPI Interface // SPI Interface
// FSM // FSM
@ -18,6 +22,10 @@ module Top(
.outSendData(bus.SendData), .outSendData(bus.SendData),
.outTimerEN(bus.TimerEN) .outTimerEN(bus.TimerEN)
); );
=======
// SPI Interface
// FSM
>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
// Parallelport // Parallelport
// FRAM-Controller // FRAM-Controller
// Timer // Timer