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Initalized top level design

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sessleral71711 2022-06-14 10:35:05 +02:00
parent 53868c67fd
commit 6a72019f25
1 changed files with 8 additions and 0 deletions
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8
Top/Top.sv
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@ -1,11 +1,15 @@
`include "../spi_interface.v" `include "../spi_interface.v"
`include "../fsm/Fsm.sv" `include "../fsm/Fsm.sv"
<<<<<<< HEAD
`include "../Bus_if/Bus_if.sv" `include "../Bus_if/Bus_if.sv"
=======
>>>>>>> b8d8341 (Initalized top level design)
module Top( module Top(
input wire clk input wire clk
); );
// Bus (Interface) // Bus (Interface)
<<<<<<< HEAD
Bus_if bus(.clk(clk)); Bus_if bus(.clk(clk));
// SPI Interface // SPI Interface
// FSM // FSM
@ -18,6 +22,10 @@ module Top(
.outSendData(bus.SendData), .outSendData(bus.SendData),
.outTimerEN(bus.TimerEN) .outTimerEN(bus.TimerEN)
); );
=======
// SPI Interface
// FSM
>>>>>>> b8d8341 (Initalized top level design)
// Parallelport // Parallelport
// FRAM-Controller // FRAM-Controller
// Timer // Timer