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FSM mit 2 States erstellt und getestet

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This commit is contained in:
sessleral71711 2022-06-02 09:26:16 +02:00
parent 48610eeb8c
commit 71b0458554
2 changed files with 74 additions and 74 deletions
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93
fsm/Fsm.sv
View File

@ -1,63 +1,52 @@
module Fsm module Fsm
( (
input wire clk, input wire clk,
input wire tim_ready, input wire inAlarmAmpel,
input wire alarm, input wire inDataValid,
output logic adc_en, input wire inTasteAktiv,
output logic tim_en, output logic outAlarm_R,
output logic fram_c_en, output logic outSendData,
output logic led_c_en output logic outTimerEN
); );
real S0 = 0; real IDLE = 0;
real S1 = 1; real ALARM = 1;
real S2 = 2;
real S3 = 3; logic state;
real S4 = 4;
real S5 = 5;
real S6 = 6;
logic[2:0] state;
initial begin initial begin
#0 state <= 0; #0 state <= IDLE;
#0 adc_en <= 0; #0 outAlarm_R <= 0;
#0 tim_en <= 0; #0 outSendData <= 0;
#0 fram_c_en <= 0; #0 outTimerEN <= 0;
#0 led_c_en <= 0;
end end
always @(posedge clk) begin always @(posedge clk) begin
case(state) case(state)
S0: begin IDLE: begin
adc_en <= 1'b1; if(inDataValid) begin
tim_en <= 1'b1; outSendData <= 1;
state <= S1; end
end else begin
S1: begin outSendData <= 0;
adc_en <= 1'b0; end
tim_en <= 1'b0; if(inAlarmAmpel) begin
if(tim_ready) begin outAlarm_R <= 1;
fram_c_en <= 1'b1; state <= ALARM;
led_c_en <= 1'b1; end
state <= S2; end
end ALARM: begin
else begin if(inDataValid) begin
// do nothing outSendData <= 1;
end end
end else begin
S2: begin outSendData <= 0;
fram_c_en <= 0'b0; end
led_c_en <= 0'b0; if(inTasteAktiv) begin
if(alarm) begin outAlarm_R <= 0;
// taster state <= IDLE;
end end
else begin end
if(tim_ready) begin
end
state <= S0;
end
end
default: ; default: ;
endcase endcase
end end
endmodule endmodule

55
fsm/tb_Fsm.sv
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@ -3,39 +3,50 @@
module tb_Fsm; module tb_Fsm;
wire clk; wire clk;
logic tim_ready; logic inAlarmAmpel;
logic alarm; logic inDataValid;
wire adc_en; logic inTasteAktiv;
wire tim_en; wire outAlarm_R;
wire fram_c_en; wire outSendData;
wire led_c_en; wire outTimerEN;
Clk_generator clk_gen(.clk(clk)); Clk_generator clk_gen(.clk(clk));
Fsm myfsm Fsm myfsm
( (
.clk(clk), .clk(clk),
.tim_ready(tim_ready), .inAlarmAmpel(inAlarmAmpel),
.alarm(alarm), .inDataValid(inDataValid),
.adc_en(adc_en), .inTasteAktiv(inTasteAktiv),
.tim_en(tim_en), .outAlarm_R(outAlarm_R),
.fram_c_en(fram_c_en), .outSendData(outSendData),
.led_c_en(led_c_en) .outTimerEN(outTimerEN)
); );
always @(posedge clk) begin
#1 tim_ready <= ~tim_ready;
end
initial begin initial begin
$dumpfile("tb_Fsm.vcd"); $dumpfile("tb_Fsm.vcd");
$dumpvars(0, tb_Fsm); $dumpvars(0, tb_Fsm);
#50 $finish; #50 $finish;
end end
initial begin initial begin
#0 tim_ready = 1'b0; #0 inAlarmAmpel = 1'b0;
#0 alarm = 1'b0; #0 inDataValid = 1'b0;
#0 inTasteAktiv = 1'b0;
end
initial begin
#4 inAlarmAmpel = 1'b1;
#5 inAlarmAmpel = 1'b0;
#8 inDataValid = 1'b1;
#9 inDataValid = 1'b0;
#10 inTasteAktiv = 1'b1;
#11 inTasteAktiv = 1'b0;
end end
endmodule
endmodule