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Added bus_if and fsm to top level design

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sessleral71711 2022-06-14 11:53:20 +02:00
parent 1be3ce1cea
commit c93bdaf629
1 changed files with 11 additions and 7 deletions
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18
Top/Top.sv
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@ -1,19 +1,23 @@
`include "../spi_interface.v" `include "../spi_interface.v"
`include "../fsm/Fsm.sv" `include "../fsm/Fsm.sv"
<<<<<<< HEAD `include "../Bus_if/Bus_if.sv"
=======
>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15
module Top( module Top(
input wire clk input wire clk
); );
// Bus (Interface) // Bus (Interface)
<<<<<<< HEAD Bus_if bus(.clk(clk));
=======
// SPI Interface // SPI Interface
// FSM // FSM
>>>>>>> b8d834144be80086a32a76f1769deccce6eaee15 Fsm fsm(
.clk(clk),
.inAlarmAmpel(bus.AlarmAmpel),
.inDataValid(bus.DataValid),
.inTasteAktiv(bus.TasteAktiv),
.outAlarm_R(bus.Alarm_R),
.outSendData(bus.SendData),
.outTimerEN(bus.TimerEN)
);
// Parallelport // Parallelport
// FRAM-Controller // FRAM-Controller
// Timer // Timer