kuntzschcl/ESY1_Projekt_2022
kuntzschcl/ESY1_Projekt_2022
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Compare commits

base: kuntzschcl:main
Branches Tags
kuntzschcl:main
kuntzschcl:top_level_design
..
compare: kuntzschcl:top_level_design
Branches Tags
kuntzschcl:main
kuntzschcl:top_level_design

No commits in common. "main" and "top_level_design" have entirely different histories.
main ... top_level_

4 changed files with 19 additions and 191 deletions
Show Stats Expand all files Collapse all files

18
Top/Top.sv
View File

@ -1,7 +1,7 @@
`include "../spi_interface.v"
`include "../fsm/Fsm.sv" `include "../fsm/Fsm.sv"
`include "../Bus_if/Bus_if.sv" `include "../Bus_if/Bus_if.sv"
`include "../timer_port/timer_top.sv" `include "../timer_port/timer_top.sv"
`include "../spi_interface_radiant/spi_interface.sv"
module Top( module Top(
input wire clk, input wire clk,
@ -9,14 +9,11 @@ module Top(
input wire endOfConv, input wire endOfConv,
output wire LEDg, output wire LEDg,
output wire LEDr, output wire LEDr,
output wire AlarmAmpel, output wire AlarmAmpel
output wire Alarm_R
); );
// Bus (Interface) // Bus (Interface)
Bus_if bus(.clk(clk)); Bus_if bus(.clk(clk));
// SPI Interface // SPI Interface
spi_interface_ports spi_bus(.clk(clk));
// FSM // FSM
Fsm fsm( Fsm fsm(
.clk(clk), .clk(clk),
@ -56,14 +53,5 @@ module Top(
.alarm(bus.AlarmAmpel) .alarm(bus.AlarmAmpel)
); );
assign AlarmAmpel = bus.AlarmAmpel; assign AlarmAmpel = bus.AlarmAmpel;
assign Alarm_R = bus.Alarm_R;
assign bus.sbclk = spi_bus.sb_clk_i;
assign bus.sbstb = spi_bus.sb_stb_i;
assign bus.sbrw = spi_bus.sb_wr_i;
assign bus.sbadr = spi_bus.sb_adr_i;
assign bus.sbdat_r = spi_bus.sb_dat_i;
assign bus.sbdat_w = spi_bus.sb_dat_o;
assign bus.sback = spi_bus.sb_ack_o;
endmodule endmodule

128
Top/random_tl.sv
View File

@ -1,128 +0,0 @@
// Project: ESY-Praktikum-Testbench
// File: random_tl.sv
// Title: Random Testbench Toplevel
// Description: Creates a Testbench that tests the Toplevel-Design with random based verifikation
//
//
// --------------------------------------------------------------------
//
//------------------------------------------------------------
// Notes:
//
//
//------------------------------------------------------------
// Development History:
//
// __DATE__ _BY_ _REV_ _DESCRIPTION___________________________
// 14/06/22 JU/TL 1.0 Initial testbench design
//
//------------------------------------------------------------
// Dependencies:
// Toplevel-Design
//
//
//------------------------------------------------------------
//------------------------------------------------------------
//
//
// Testbench
//
//------------------------------------------------------------
class Taster_rnd;
rand bit [1:0] data;
constraint Rst_rnd
{
data dist {0:=70,1 :=30};
}
endclass
class Data_ADC_rnd;
rand bit [7:0] data;
endclass
`timescale 1ns/1ps
module tb;
// inputs and outputs
reg taster;
reg [7:0]data_ADC;
reg clk12M;
wire RED;
wire GRN;
wire alarm;
wire alarm_r;
wire SI;
wire SO;
wire SCK;
wire nCS;
reg endOfConvRnd;
//random
Taster_rnd taster_rnd = new();
Data_ADC_rnd data_ADC_rnd = new();
// connect module
SPI_FRAM_Module fram_storage(
.SI(SI),
.SO(SO),
.SCK(SCK),
.nCS(nCS),.opcode(),.addr());
Top top(.clk(clk12M),.rst(taster),.endOfConv(endOfConvRnd),.LEDg(GRN),.LEDr(RED),.AlarmAmpel(alarm),.Alarm_R(alarm_r));
initial
begin
clk12M=1'b0;
end
always
#41.666666 clk12M=~clk12M; //clock generation
//random test
initial begin
endOfConvRnd = 1;
repeat (2) begin
#100000000
#100000000
#100000000
#100000000
#100000000
#100000000
#100000000
#100000000
#100000000
#100000000
data_ADC_rnd.randomize();
taster_rnd.randomize();
taster = taster_rnd.data;
data_ADC = data_ADC_rnd.data;
// assertions
// assert color green
assert property(@(posedge clk12M) disable iff (alarm | alarm_r) ((data_ADC < 100) |=> ##4 (!RED && GRN)));
//assert color yellow
assert property(@(posedge clk12M) disable iff (alarm | alarm_r) (((data_ADC >= 100) && (data_ADC <= 168))|=> ##4 (RED && GRN)));
//assert color red + alarm
assert property(@(posedge clk12M) disable iff (alarm_r) (data_ADC > 168) |=> ##4 (RED && !GRN && alarm));
//assert alarm reset working
assert property(@(posedge clk12M) (alarm_r |=> ##4 (!RED && !GRN && !alarm)));
$monitor("time=%t, data_ADC=%d, RED=%d, GRN=%d, taster=%d",$time,data_ADC, RED, GRN, taster);
end
$stop;
end
endmodule

12
spi_interface_radiant/spi_interface.sv → spi_interface_radiant/spi_interface.v
View File

@ -30,12 +30,16 @@ interface spi_interface_ports (input clk);
logic spi1_sck_io; // Clock for SPI-Slave logic spi1_sck_io; // Clock for SPI-Slave
// MODPORT form BUS perspective (internal) // MODPORT form BUS perspective (internal)
// modport input and output from BUS (internal) // modport output from BUS (internal)
modport BUS (output sb_clk_i, sb_stb_i, sb_wr_i, sb_adr_i, sb_dat_i, spi1_miso_io, input sb_dat_o, sb_ack_o, spi1_mosi_io, spi1_mcs_n_o, spi1_sck_io); modport BUS (output sb_clk_i, sb_stb_i, sb_wr_i, sb_adr_i[7:0], sb_dat_i[7:0], spi1_miso_io);
// modport input to BUS (internal)
modport BUS (input sb_dat_o[7:0], sb_ack_o, spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
// MODPORT from SPI perspective (external) // MODPORT from SPI perspective (external)
// modport input and output from SPI (external) // modport output from SPI (external)
modport SPI (output spi1_miso_io, input spi1_mosi_io, spi1_mcs_n_o, spi1_sck_io); modport SPI (output spi1_miso_io);
// modport input to SPI (external)
modport SPI (input spi1_mosi_io, spi1_mcs_n_o[3:0], spi_sck_io);
endinterface endinterface

52
timer_port/timer_top.sv
View File

@ -1,97 +1,61 @@
/*Timer soll signalisieren, wenn 10 Sekunden vorbei sind. //clock divider
Zusätzlich soll der Taster abgefragt werden. Wenn der Taster für 1 Sekunde aktiv ist, soll es signalisiert werden.
inClk: Eingang für Clock 12MHz
inTaste: Eingang Taster
inEN: Enable Pin, wenn HIGH dann stoppt Timer
outReadTemp: signalisiert, dass 10 Sekunden vorbei sind
outTasteAktiv: signalisiert, dass der Taster betätigt wurde
*/
module timer(input inClk, inTaste, inEN, output reg outReadTemp, outTasteAktiv); module timer(input inClk, inTaste, inEN, output reg outReadTemp, outTasteAktiv);
//Wird genutzt um den Eingangstakt zu teilen. int divide1 = 30000000;
int divide1 = 30000000; int divide2 = 60000;
int divide2 = 60000;
//Interne Zwischenspeicher;
logic state = 0; logic state = 0;
logic [31:0] count1 = 32'b0; logic [31:0] count1 = 32'b0;
logic [31:0] count2 = 32'b0; logic [31:0] count2 = 32'b0;
//Initialisierung
initial begin initial begin
outReadTemp = 0; outReadTemp = 0;
outTasteAktiv = 0; outTasteAktiv = 0;
end end
always @(posedge inClk or posedge inEN) begin always @(posedge inClk or posedge inEN) begin
//Bei positiver Flanke und inEN auf HIGH wird Timer gestoppt
if(inEN) begin if(inEN) begin
count1 <= 0; count1 <= 0;
count2 <= 0; count2 <= 0;
outReadTemp <= 0; outReadTemp <= 0;
end end
//sonst wird counter1 inkrementiert
else begin else begin
count1 <= count1 +1; count1 <= count1 +1;
if(count1>=((2**32)-1)) if(count1>=((2**32)-1))
count1 <= 32'b0; count1 <= 32'b0;
//wenn counter1 durch divide1 teilbar ist, so wird outReadTemp getoggelt --> es erfolgt ca. alle 5 Sekunden ein toggeln
//outReadTemp ist für 5 Sekunden HIGH und 5 Sekunden LOW
if(count1 % divide1 == 0) if(count1 % divide1 == 0)
outReadTemp <= ~outReadTemp; outReadTemp <= ~outReadTemp;
//Bei positiver Flanke wird Taster abgefragt
//Solange Taster HIGH ist wird counter2 erhöht
if(inTaste) begin if(inTaste) begin
count2 <= count2 +1; count2 <= count2 +1;
//Sobald counter2 den Wert 6 000 000 übersteigt, wird outTasteAktiv auf HIGH gesetzt --> Taster wurde 1 Sekunde betätigt
if(count2 >= 6000000) if(count2 >= 6000000)
outTasteAktiv = 1; outTasteAktiv = 1;
end end
//Wenn Taster losgelassen wird, dann wird Ausgang und counter2 zurück gesetzt.
else begin else begin
outTasteAktiv <= 0; outTasteAktiv <= 0;
count2 <= 0; count2 <= 0;
end end
end end
end end
endmodule // clk_divider endmodule // clk_divider
/*Parallelport, soll die Daten des ADC alle 10 Sekunden auslesen und auf den Bus legen.
inClk: Eingang für Clock 12MHz
inTimerMeas: Eingang des 10 Sekunden Takt des Timers
inEndOdConv: Eingang vom ADC; Signalisiert valide Daten im ADC
[7:0] inData: Eingang der Daten (parallel)
outDataValid: Signalisiert, dass Daten auf Bus vaild sind
[7:0] outData: Ausgang der Daten (parallel)
*/
module parallelport(input inClk, inTimerMeas, inEndOfConv, [7:0] inData, output reg outDataValid, [7:0] outData); module parallelport(input inClk, inTimerMeas, inEndOfConv, [7:0] inData, output reg outDataValid, [7:0] outData);
//Zwischenspeicher der Daten
logic [7:0] storage = 8'b0; logic [7:0] storage = 8'b0;
//Initalisierung
initial begin initial begin
outDataValid <= 0; outDataValid <= 0;
outData <= 8'b0; outData <= 8'b0;
end end
always @(posedge inClk) begin always @(posedge inClk) begin
//Wenn inEndOfConv HIGH ist, dann werden die Daten in den Zwischenspeicher gelegt
if(inEndOfConv) if(inEndOfConv)
storage <= inData; storage <= inData;
//Wenn inTimerMeas HIGH ist, dann werden die Daten aus dem Zwischenspeicher in das Ausgangsregister gelegt
//Außerdem wird outDataValid auf HIGH gesetzt, was dem Bus signalisiert, dass die Daten gelesen werden können
if(inTimerMeas == 1 && outDataValid == 0) begin if(inTimerMeas == 1 && outDataValid == 0) begin
outData = storage; outData = storage;
outDataValid <= 1; outDataValid <= 1;
end end
//Wenn inTimerMeas LOW ist, dann wird outDataValid auf LOW gesetzt
else if(inTimerMeas == 0) else if(inTimerMeas == 0)
outDataValid <= 0; outDataValid <= 0;
end end