380 lines
13 KiB
Plaintext
380 lines
13 KiB
Plaintext
# // Questa Sim-64
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# // Version 2019.4 linux_x86_64 Oct 15 2019
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# //
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# // Copyright 1991-2019 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // QuestaSim and its associated documentation contain trade
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# // secrets and commercial or financial information that are the property of
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# // Mentor Graphics Corporation and are privileged, confidential,
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# // and exempt from disclosure under the Freedom of Information Act,
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# // 5 U.S.C. Section 552. Furthermore, this information
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
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#
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# create workspace
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vlib-34) Library already exists at "work".
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# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
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# vmap work ./work
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# Modifying modelsim.ini
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#
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# Compile sv-Designfiles
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
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# -- Compiling interface led_if
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# -- Compiling interface dip_if
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# -- Compiling interface fram_if
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# -- Compiling interface clock_if
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#
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# Top level modules:
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# --none--
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
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# -- Compiling module stimuli
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#
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# Top level modules:
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# stimuli
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
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# -- Compiling module top
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# -- Compiling interface bus
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# -- Compiling module parallelport
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# -- Compiling module steuerung
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#
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# Top level modules:
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# top
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
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# -- Compiling module top_tb
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#
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# Top level modules:
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# top_tb
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
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# -- Compiling module timer
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#
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# Top level modules:
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# timer
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
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# -- Compiling module SPI_Master
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#
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# Top level modules:
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# SPI_Master
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
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# -- Compiling module SPI_Master_With_Single_CS
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#
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# Top level modules:
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# SPI_Master_With_Single_CS
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
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# -- Compiling module FRAM
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#
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# Top level modules:
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# FRAM
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
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# -- Compiling module spi
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#
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# Top level modules:
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# spi
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# Run Simulation
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# vsim -cvg63 -voptargs=""+acc"" top_tb
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# Start time: 14:45:51 on Jun 15,2023
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# ** Note: (vsim-3812) Design is being optimized...
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# ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
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# Loading sv_std.std
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# Loading work.top_tb(fast)
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# Loading work.led_if(fast)
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# Loading work.dip_if(fast)
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# Loading work.fram_if(fast)
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# Loading work.clock_if(fast)
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# Loading work.top(fast)
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# Loading work.bus(fast)
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# Loading work.timer(fast)
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# Loading work.steuerung(fast)
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# Loading work.spi(fast)
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# Loading work.FRAM(fast)
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# Loading work.SPI_Master_With_Single_CS(fast)
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# Loading work.SPI_Master(fast)
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# Loading work.parallelport(fast)
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# Loading work.stimuli(fast)
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do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
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#
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# create workspace
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vlib-34) Library already exists at "work".
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# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
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# vmap work ./work
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# Modifying modelsim.ini
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#
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# Compile sv-Designfiles
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
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# -- Compiling interface led_if
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# -- Compiling interface dip_if
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# -- Compiling interface fram_if
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# -- Compiling interface clock_if
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#
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# Top level modules:
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# --none--
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
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# -- Compiling module stimuli
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#
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# Top level modules:
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# stimuli
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
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# -- Compiling module top
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# -- Compiling interface bus
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# -- Compiling module parallelport
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# -- Compiling module steuerung
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#
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# Top level modules:
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# top
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
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# -- Compiling module top_tb
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#
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# Top level modules:
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# top_tb
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
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# -- Compiling module timer
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#
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# Top level modules:
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# timer
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
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# -- Compiling module SPI_Master
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#
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# Top level modules:
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# SPI_Master
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
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# -- Compiling module SPI_Master_With_Single_CS
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#
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# Top level modules:
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# SPI_Master_With_Single_CS
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
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# -- Compiling module FRAM
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#
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# Top level modules:
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# FRAM
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
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# -- Compiling module spi
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#
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# Top level modules:
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# spi
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# Run Simulation
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# End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
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# Errors: 3, Warnings: 2
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# vsim -cvg63 -voptargs=""+acc"" top_tb
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# Start time: 14:48:18 on Jun 15,2023
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# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
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# Loading sv_std.std
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# Loading work.top_tb(fast)
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# Loading work.led_if(fast)
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# Loading work.dip_if(fast)
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# Loading work.fram_if(fast)
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# Loading work.clock_if(fast)
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# Loading work.top(fast)
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# Loading work.bus(fast)
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# Loading work.timer(fast)
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# Loading work.steuerung(fast)
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# Loading work.spi(fast)
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# Loading work.FRAM(fast)
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# Loading work.SPI_Master_With_Single_CS(fast)
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# Loading work.SPI_Master(fast)
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# Loading work.parallelport(fast)
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# Loading work.stimuli(fast)
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add wave -position insertpoint \
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sim:/top_tb/t1/fpga_bus/spi_read
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do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
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#
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# create workspace
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vlib-34) Library already exists at "work".
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# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
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# vmap work ./work
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# Modifying modelsim.ini
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#
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# Compile sv-Designfiles
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
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# -- Compiling interface led_if
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# -- Compiling interface dip_if
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# -- Compiling interface fram_if
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# -- Compiling interface clock_if
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#
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# Top level modules:
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# --none--
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
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# -- Compiling module stimuli
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#
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# Top level modules:
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# stimuli
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
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# -- Compiling module top
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# -- Compiling interface bus
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# -- Compiling module parallelport
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# -- Compiling module steuerung
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#
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# Top level modules:
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# top
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
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# -- Compiling module top_tb
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#
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# Top level modules:
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# top_tb
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
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# -- Compiling module timer
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#
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# Top level modules:
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# timer
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
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# -- Compiling module SPI_Master
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#
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# Top level modules:
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# SPI_Master
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
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# -- Compiling module SPI_Master_With_Single_CS
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#
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# Top level modules:
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# SPI_Master_With_Single_CS
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
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# -- Compiling module FRAM
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#
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# Top level modules:
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# FRAM
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
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# -- Compiling module spi
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#
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# Top level modules:
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# spi
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# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# Run Simulation
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# End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
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# Errors: 1, Warnings: 2
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# vsim -cvg63 -voptargs=""+acc"" top_tb
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# Start time: 14:51:07 on Jun 15,2023
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# ** Note: (vsim-8009) Loading existing optimized design _opt1
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# Loading sv_std.std
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# Loading work.top_tb(fast)
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# Loading work.led_if(fast)
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# Loading work.dip_if(fast)
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# Loading work.fram_if(fast)
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# Loading work.clock_if(fast)
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# Loading work.top(fast)
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# Loading work.bus(fast)
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# Loading work.timer(fast)
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# Loading work.steuerung(fast)
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# Loading work.spi(fast)
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# Loading work.FRAM(fast)
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# Loading work.SPI_Master_With_Single_CS(fast)
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# Loading work.SPI_Master(fast)
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# Loading work.parallelport(fast)
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# Loading work.stimuli(fast)
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# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
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# Errors: 3, Warnings: 0
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