spi aenderungen
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transcript
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14
transcript
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@ -0,0 +1,14 @@
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# // Questa Sim-64
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# // Version 2019.4 linux_x86_64 Oct 15 2019
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# //
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# // Copyright 1991-2019 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // QuestaSim and its associated documentation contain trade
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# // secrets and commercial or financial information that are the property of
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# // Mentor Graphics Corporation and are privileged, confidential,
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# // and exempt from disclosure under the Freedom of Information Act,
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# // 5 U.S.C. Section 552. Furthermore, this information
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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@ -53,13 +53,13 @@ module spi(bus.spi_port b, fram_if.fram_port_top i);
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if(FRAM_go == 1)
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clk_cntr <= clk_cntr + 1;
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if(clk_cntr > 50 && FRAM_RW == 1'h1) begin
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if(clk_cntr > 250 && FRAM_RW == 1'h1) begin
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b.spi_read <= FRAM_DATA_OUT[1:0];
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FRAM_go <= 1'h0;
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FRAM_RW <= 1'h0;
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clk_cntr <= 0;
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end
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else if(clk_cntr > 50 && FRAM_RW == 1'h0) begin
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else if(clk_cntr > 250 && FRAM_RW == 1'h0) begin
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FRAM_go <= 1'h0;
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clk_cntr <= 0;
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end
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@ -5,12 +5,13 @@ add wave -noupdate -radix binary /top_tb/t1/fpga_bus/dip
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add wave -noupdate -radix binary /top_tb/stim_clock_if/clk
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add wave -noupdate -radix binary /top_tb/t1/fpga_bus/clk
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add wave -noupdate -radix binary /top_tb/t1/fpga_bus/timer
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add wave -noupdate -radix binary /top_tb/t1/s/FRAM_Adr
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add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_Adr
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add wave -noupdate -radix binary /top_tb/t1/s/clk_cntr
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add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_IN
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add wave -noupdate -radix binary /top_tb/t1/s/FRAM_DATA_OUT
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add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_IN
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add wave -noupdate -radix hexadecimal /top_tb/t1/s/FRAM_DATA_OUT
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add wave -noupdate -radix binary /top_tb/t1/f/mosi
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add wave -noupdate -radix binary /top_tb/t1/f/sclk
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add wave -noupdate -radix binary /top_tb/t1/fpga_bus/spi_read
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {0 ns} 0}
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quietly wave cursor active 0
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@ -12,16 +12,18 @@
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
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do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
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#
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# create workspace
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vlib-34) Library already exists at "work".
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# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
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# vmap work ./work
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# Modifying modelsim.ini
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#
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# Compile sv-Designfiles
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
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# -- Compiling interface led_if
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# -- Compiling interface dip_if
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@ -30,19 +32,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Top level modules:
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# --none--
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
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# -- Compiling module stimuli
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#
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# Top level modules:
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# stimuli
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
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# -- Compiling module top
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# -- Compiling interface bus
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@ -51,66 +53,66 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Top level modules:
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# top
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:50 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
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# -- Compiling module top_tb
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#
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# Top level modules:
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# top_tb
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:50 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
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# -- Compiling module timer
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#
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# Top level modules:
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# timer
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
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# -- Compiling module SPI_Master
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#
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# Top level modules:
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# SPI_Master
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
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# -- Compiling module SPI_Master_With_Single_CS
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#
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# Top level modules:
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# SPI_Master_With_Single_CS
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
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# -- Compiling module FRAM
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#
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# Top level modules:
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# FRAM
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:51 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
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# -- Compiling module spi
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#
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# Top level modules:
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# spi
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# End time: 14:04:53 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:45:51 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# Run Simulation
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# vsim -cvg63 -voptargs=""+acc"" top_tb
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# Start time: 14:04:53 on Jun 15,2023
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# Start time: 14:45:51 on Jun 15,2023
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# ** Note: (vsim-3812) Design is being optimized...
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# ** Note: (vopt-143) Recognized 1 FSM in module "SPI_Master_With_Single_CS(fast)".
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# Loading sv_std.std
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@ -129,10 +131,11 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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# Loading work.SPI_Master(fast)
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# Loading work.parallelport(fast)
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# Loading work.stimuli(fast)
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do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
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do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
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#
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# create workspace
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vlib-34) Library already exists at "work".
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# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
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# vmap work ./work
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@ -140,7 +143,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Compile sv-Designfiles
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
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# -- Compiling interface led_if
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# -- Compiling interface dip_if
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@ -149,19 +152,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Top level modules:
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# --none--
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
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# -- Compiling module stimuli
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#
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# Top level modules:
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# stimuli
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
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# -- Compiling module top
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# -- Compiling interface bus
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@ -170,68 +173,68 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Top level modules:
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# top
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
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# -- Compiling module top_tb
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#
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# Top level modules:
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# top_tb
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
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# -- Compiling module timer
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#
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# Top level modules:
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# timer
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
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# -- Compiling module SPI_Master
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#
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# Top level modules:
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# SPI_Master
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
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# -- Compiling module SPI_Master_With_Single_CS
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#
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# Top level modules:
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# SPI_Master_With_Single_CS
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
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# -- Compiling module FRAM
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#
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# Top level modules:
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# FRAM
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:11:54 on Jun 15,2023
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# Start time: 14:48:17 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
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# -- Compiling module spi
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#
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# Top level modules:
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# spi
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# End time: 14:11:54 on Jun 15,2023, Elapsed time: 0:00:00
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# End time: 14:48:17 on Jun 15,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# Run Simulation
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# End time: 14:11:55 on Jun 15,2023, Elapsed time: 0:07:02
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# Errors: 12, Warnings: 1
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# End time: 14:48:18 on Jun 15,2023, Elapsed time: 0:02:27
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# Errors: 3, Warnings: 2
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# vsim -cvg63 -voptargs=""+acc"" top_tb
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# Start time: 14:11:55 on Jun 15,2023
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# Start time: 14:48:18 on Jun 15,2023
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# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
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# Loading sv_std.std
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# Loading work.top_tb(fast)
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@ -249,14 +252,13 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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# Loading work.SPI_Master(fast)
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# Loading work.parallelport(fast)
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# Loading work.stimuli(fast)
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# Can't move the Now cursor.
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# Can't move the Now cursor.
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add wave -position insertpoint \
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sim:/top_tb/t1/f/mosi
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do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
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sim:/top_tb/t1/fpga_bus/spi_read
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do /users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt/compilescripts/simulation/compile.tcl
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#
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# create workspace
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt1". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
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# ** Warning: (vlib-34) Library already exists at "work".
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# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
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# vmap work ./work
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@ -264,7 +266,7 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Compile sv-Designfiles
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# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
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# Start time: 14:19:00 on Jun 15,2023
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# Start time: 14:51:02 on Jun 15,2023
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# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
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# -- Compiling interface led_if
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# -- Compiling interface dip_if
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@ -273,19 +275,19 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
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#
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# Top level modules:
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# --none--
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||||
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:00 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
|
||||
# -- Compiling module stimuli
|
||||
#
|
||||
# Top level modules:
|
||||
# stimuli
|
||||
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:00 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
|
||||
# -- Compiling module top
|
||||
# -- Compiling interface bus
|
||||
@ -294,189 +296,69 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
|
||||
#
|
||||
# Top level modules:
|
||||
# top
|
||||
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:00 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
|
||||
# -- Compiling module top_tb
|
||||
#
|
||||
# Top level modules:
|
||||
# top_tb
|
||||
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:00 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
|
||||
# -- Compiling module timer
|
||||
#
|
||||
# Top level modules:
|
||||
# timer
|
||||
# End time: 14:19:00 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:01 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
|
||||
# -- Compiling module SPI_Master
|
||||
#
|
||||
# Top level modules:
|
||||
# SPI_Master
|
||||
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:01 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
|
||||
# -- Compiling module SPI_Master_With_Single_CS
|
||||
#
|
||||
# Top level modules:
|
||||
# SPI_Master_With_Single_CS
|
||||
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:01 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
|
||||
# -- Compiling module FRAM
|
||||
#
|
||||
# Top level modules:
|
||||
# FRAM
|
||||
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:19:01 on Jun 15,2023
|
||||
# Start time: 14:51:02 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
|
||||
# -- Compiling module spi
|
||||
#
|
||||
# Top level modules:
|
||||
# spi
|
||||
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# End time: 14:51:02 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
#
|
||||
# Run Simulation
|
||||
# End time: 14:19:01 on Jun 15,2023, Elapsed time: 0:07:06
|
||||
# Errors: 12, Warnings: 1
|
||||
# End time: 14:51:07 on Jun 15,2023, Elapsed time: 0:02:49
|
||||
# Errors: 1, Warnings: 2
|
||||
# vsim -cvg63 -voptargs=""+acc"" top_tb
|
||||
# Start time: 14:19:01 on Jun 15,2023
|
||||
# ** Note: (vsim-8009) Loading existing optimized design _opt
|
||||
# Loading sv_std.std
|
||||
# Loading work.top_tb(fast)
|
||||
# Loading work.led_if(fast)
|
||||
# Loading work.dip_if(fast)
|
||||
# Loading work.fram_if(fast)
|
||||
# Loading work.clock_if(fast)
|
||||
# Loading work.top(fast)
|
||||
# Loading work.bus(fast)
|
||||
# Loading work.timer(fast)
|
||||
# Loading work.steuerung(fast)
|
||||
# Loading work.spi(fast)
|
||||
# Loading work.FRAM(fast)
|
||||
# Loading work.SPI_Master_With_Single_CS(fast)
|
||||
# Loading work.SPI_Master(fast)
|
||||
# Loading work.parallelport(fast)
|
||||
# Loading work.stimuli(fast)
|
||||
do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescripts/simulation/compile.tcl
|
||||
#
|
||||
# create workspace
|
||||
# ** Warning: (vdel-134) Unable to remove locked optimized design "_opt". Locker is muelleral82290@efiapps1.efi.fh-nuernberg.de.
|
||||
# ** Warning: (vlib-34) Library already exists at "work".
|
||||
# QuestaSim-64 vmap 2019.4 Lib Mapping Utility 2019.10 Oct 15 2019
|
||||
# vmap work ./work
|
||||
# Modifying modelsim.ini
|
||||
#
|
||||
# Compile sv-Designfiles
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/interface.sv
|
||||
# -- Compiling interface led_if
|
||||
# -- Compiling interface dip_if
|
||||
# -- Compiling interface fram_if
|
||||
# -- Compiling interface clock_if
|
||||
#
|
||||
# Top level modules:
|
||||
# --none--
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/stimuli.sv
|
||||
# -- Compiling module stimuli
|
||||
#
|
||||
# Top level modules:
|
||||
# stimuli
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_level.sv
|
||||
# -- Compiling module top
|
||||
# -- Compiling interface bus
|
||||
# -- Compiling module parallelport
|
||||
# -- Compiling module steuerung
|
||||
#
|
||||
# Top level modules:
|
||||
# top
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/top_tb.sv
|
||||
# -- Compiling module top_tb
|
||||
#
|
||||
# Top level modules:
|
||||
# top_tb
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/timer.sv
|
||||
# -- Compiling module timer
|
||||
#
|
||||
# Top level modules:
|
||||
# timer
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master_Control.sv
|
||||
# -- Compiling module SPI_Master
|
||||
#
|
||||
# Top level modules:
|
||||
# SPI_Master
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/SPI_Master.sv
|
||||
# -- Compiling module SPI_Master_With_Single_CS
|
||||
#
|
||||
# Top level modules:
|
||||
# SPI_Master_With_Single_CS
|
||||
# End time: 14:22:07 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:07 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/FRAM_Controller.sv
|
||||
# -- Compiling module FRAM
|
||||
#
|
||||
# Top level modules:
|
||||
# FRAM
|
||||
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:01
|
||||
# Errors: 0, Warnings: 0
|
||||
# QuestaSim-64 vlog 2019.4 Compiler 2019.10 Oct 15 2019
|
||||
# Start time: 14:22:08 on Jun 15,2023
|
||||
# vlog -reportprogress 300 -work work ./hdl_src/sv/fram.sv
|
||||
# -- Compiling module spi
|
||||
#
|
||||
# Top level modules:
|
||||
# spi
|
||||
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 0
|
||||
#
|
||||
# Run Simulation
|
||||
# End time: 14:22:08 on Jun 15,2023, Elapsed time: 0:03:07
|
||||
# Errors: 5, Warnings: 1
|
||||
# vsim -cvg63 -voptargs=""+acc"" top_tb
|
||||
# Start time: 14:22:08 on Jun 15,2023
|
||||
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
|
||||
# Start time: 14:51:07 on Jun 15,2023
|
||||
# ** Note: (vsim-8009) Loading existing optimized design _opt1
|
||||
# Loading sv_std.std
|
||||
# Loading work.top_tb(fast)
|
||||
# Loading work.led_if(fast)
|
||||
@ -493,3 +375,5 @@ do /users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt/compilescript
|
||||
# Loading work.SPI_Master(fast)
|
||||
# Loading work.parallelport(fast)
|
||||
# Loading work.stimuli(fast)
|
||||
# End time: 14:52:23 on Jun 15,2023, Elapsed time: 0:01:16
|
||||
# Errors: 3, Warnings: 0
|
||||
|
||||
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib.qdb
Normal file
BIN
uebung_projekt/work/@_opt1/_lib.qdb
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib1_0.qdb
Normal file
BIN
uebung_projekt/work/@_opt1/_lib1_0.qdb
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib1_0.qpg
Normal file
BIN
uebung_projekt/work/@_opt1/_lib1_0.qpg
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib1_0.qtl
Normal file
BIN
uebung_projekt/work/@_opt1/_lib1_0.qtl
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib2_0.qdb
Normal file
BIN
uebung_projekt/work/@_opt1/_lib2_0.qdb
Normal file
Binary file not shown.
0
uebung_projekt/work/@_opt1/_lib2_0.qpg
Normal file
0
uebung_projekt/work/@_opt1/_lib2_0.qpg
Normal file
BIN
uebung_projekt/work/@_opt1/_lib2_0.qtl
Normal file
BIN
uebung_projekt/work/@_opt1/_lib2_0.qtl
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib3_0.qdb
Normal file
BIN
uebung_projekt/work/@_opt1/_lib3_0.qdb
Normal file
Binary file not shown.
0
uebung_projekt/work/@_opt1/_lib3_0.qpg
Normal file
0
uebung_projekt/work/@_opt1/_lib3_0.qpg
Normal file
BIN
uebung_projekt/work/@_opt1/_lib3_0.qtl
Normal file
BIN
uebung_projekt/work/@_opt1/_lib3_0.qtl
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib4_0.qdb
Normal file
BIN
uebung_projekt/work/@_opt1/_lib4_0.qdb
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib4_0.qpg
Normal file
BIN
uebung_projekt/work/@_opt1/_lib4_0.qpg
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib4_0.qtl
Normal file
BIN
uebung_projekt/work/@_opt1/_lib4_0.qtl
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib5_0.qdb
Normal file
BIN
uebung_projekt/work/@_opt1/_lib5_0.qdb
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib5_0.qpg
Normal file
BIN
uebung_projekt/work/@_opt1/_lib5_0.qpg
Normal file
Binary file not shown.
BIN
uebung_projekt/work/@_opt1/_lib5_0.qtl
Normal file
BIN
uebung_projekt/work/@_opt1/_lib5_0.qtl
Normal file
Binary file not shown.
@ -10,389 +10,400 @@ z2
|
||||
cModel Technology
|
||||
Z0 d/users/ads1/muelleral82290/linux/Dokumente/esy_B/uebung_projekt
|
||||
T_opt
|
||||
Z1 !s110 1686831728
|
||||
!s110 1686831728
|
||||
V2L38BN@acDd:OB=HL_FC32
|
||||
04 6 4 work top_tb fast 0
|
||||
Z1 04 6 4 work top_tb fast 0
|
||||
=1-005056b42dc6-648b0270-7d119-559d
|
||||
o-quiet -auto_acc_if_foreign -work work +acc
|
||||
Z2 tCvgOpt 0
|
||||
Z2 o-quiet -auto_acc_if_foreign -work work +acc
|
||||
Z3 tCvgOpt 0
|
||||
n@_opt
|
||||
OL;O;2019.4;69
|
||||
Z4 OL;O;2019.4;69
|
||||
R0
|
||||
T_opt1
|
||||
!s110 1686833298
|
||||
V4N01Y?dc<]WhdSf73Ue?91
|
||||
R1
|
||||
=1-005056b42dc6-648b0892-563db-611e
|
||||
R2
|
||||
R3
|
||||
n@_opt1
|
||||
R4
|
||||
R0
|
||||
Ybus
|
||||
Z3 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92
|
||||
Z4 !s110 1686831727
|
||||
Z5 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92
|
||||
Z6 !s110 1686833462
|
||||
!i10b 1
|
||||
!s100 T;581z6K]3OXG=KOJdK4G2
|
||||
!s11b Dj[TOJX9onk[mCamXbz9c3
|
||||
I<3_5F:_4Ri@f;?1:3BJf=2
|
||||
Z5 VDg1SIo80bB@j0V0VzS_@n1
|
||||
Z7 VDg1SIo80bB@j0V0VzS_@n1
|
||||
S1
|
||||
R0
|
||||
Z6 w1686830281
|
||||
Z7 8./hdl_src/sv/top_level.sv
|
||||
Z8 F./hdl_src/sv/top_level.sv
|
||||
Z8 d/users/ads1/muelleral82290/linux/Dokumente/ESY1_Projekt_2023/uebung_projekt
|
||||
Z9 w1686832439
|
||||
Z10 8./hdl_src/sv/top_level.sv
|
||||
Z11 F./hdl_src/sv/top_level.sv
|
||||
!i122 -1
|
||||
L0 15
|
||||
Z9 OL;L;2019.4;69
|
||||
Z12 OL;L;2019.4;69
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z10 !s108 1686831727.000000
|
||||
Z11 !s107 ./hdl_src/sv/top_level.sv|
|
||||
Z12 !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_level.sv|
|
||||
Z13 !s108 1686833462.000000
|
||||
Z14 !s107 ./hdl_src/sv/top_level.sv|
|
||||
Z15 !s90 -reportprogress|300|-work|work|./hdl_src/sv/top_level.sv|
|
||||
!i113 0
|
||||
Z13 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
|
||||
R2
|
||||
Z16 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
|
||||
R3
|
||||
Yclock_if
|
||||
R3
|
||||
R4
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 iND9Vz2l5W=c=U<U<OKbg0
|
||||
!s100 heLOC37I>@m@mlh@>YnK82
|
||||
!s11b oJPC4U0:1B^QG:cZC>8A:1
|
||||
IOQJeZ`mU<Z1m4K_[FIhfS2
|
||||
R5
|
||||
IzF198zIQF2djPZ;867:>83
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
Z14 w1686314964
|
||||
Z15 8./hdl_src/sv/interface.sv
|
||||
Z16 F./hdl_src/sv/interface.sv
|
||||
R8
|
||||
Z17 w1686832912
|
||||
Z18 8./hdl_src/sv/interface.sv
|
||||
Z19 F./hdl_src/sv/interface.sv
|
||||
!i122 -1
|
||||
L0 60
|
||||
R9
|
||||
L0 61
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
Z17 !s107 ./hdl_src/sv/interface.sv|
|
||||
Z18 !s90 -reportprogress|300|-work|work|./hdl_src/sv/interface.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
Ydip_if
|
||||
R3
|
||||
R4
|
||||
!i10b 1
|
||||
!s100 lPioFG@0T7j3gKFQYYe8W0
|
||||
!s11b @Hfo8VJnf;PXXPSgXE44V1
|
||||
I@=49][3E;]nafb=5@ka:a0
|
||||
R5
|
||||
S1
|
||||
R0
|
||||
R14
|
||||
R15
|
||||
Z20 !s107 ./hdl_src/sv/interface.sv|
|
||||
Z21 !s90 -reportprogress|300|-work|work|./hdl_src/sv/interface.sv|
|
||||
!i113 0
|
||||
R16
|
||||
!i122 -1
|
||||
L0 33
|
||||
R9
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R3
|
||||
Ydip_if
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 <PVf]bVPeKdaLDk`m:i?Y0
|
||||
!s11b @Hfo8VJnf;PXXPSgXE44V1
|
||||
I@P@no8JU[7ajE4d1Y<M;E2
|
||||
R7
|
||||
S1
|
||||
R8
|
||||
R17
|
||||
R18
|
||||
!i113 0
|
||||
R19
|
||||
!i122 -1
|
||||
Z22 L0 34
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R13
|
||||
R2
|
||||
vFRAM
|
||||
R20
|
||||
R21
|
||||
!i113 0
|
||||
R16
|
||||
R3
|
||||
R1
|
||||
vFRAM
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 6GgRzC`3J8EKCo2KAh]SA3
|
||||
!s11b 48o?`kIzT=WRNj@`=ICgH0
|
||||
Id_KQzKR^jG]NNATEeL[F]1
|
||||
R5
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686826733
|
||||
R8
|
||||
R9
|
||||
8./hdl_src/sv/FRAM_Controller.sv
|
||||
F./hdl_src/sv/FRAM_Controller.sv
|
||||
!i122 -1
|
||||
L0 1
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
!s107 ./hdl_src/sv/FRAM_Controller.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/FRAM_Controller.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
R16
|
||||
R3
|
||||
n@f@r@a@m
|
||||
Yfram_if
|
||||
R3
|
||||
R4
|
||||
!i10b 1
|
||||
!s100 FG9WSXZ0h`ZNCKFUfVEI;0
|
||||
!s11b TH@FFRQ[NJF5WXda=V[<H1
|
||||
IM[7bzae]_QlkaTl;QldDo3
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 ;Pz<e0OVOd241SzfjUmAh0
|
||||
!s11b TH@FFRQ[NJF5WXda=V[<H1
|
||||
Il7_QcI82L^C5SjV==1o`V1
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
R14
|
||||
R15
|
||||
R16
|
||||
R8
|
||||
R17
|
||||
R18
|
||||
R19
|
||||
!i122 -1
|
||||
L0 47
|
||||
R9
|
||||
L0 48
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
R20
|
||||
R21
|
||||
!i113 0
|
||||
R16
|
||||
R3
|
||||
Yled_if
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 AW>Ho3QlAW4UmzOWF^R8D3
|
||||
!s11b JgIFT<E122eWGg7n1X`z=3
|
||||
IlJ8kZ^KF?8@@UY4nOo0OX2
|
||||
R7
|
||||
S1
|
||||
R8
|
||||
R17
|
||||
R18
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
Yled_if
|
||||
R3
|
||||
R4
|
||||
!i10b 1
|
||||
!s100 NHE2==?Gh0C?o>9[W_4_O1
|
||||
!s11b djVBMKk[@Wh5FXIDGlUF[2
|
||||
I`agi[9j3c9e5gcFWSVSH51
|
||||
R5
|
||||
S1
|
||||
R0
|
||||
R14
|
||||
R15
|
||||
R16
|
||||
R19
|
||||
!i122 -1
|
||||
L0 21
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R17
|
||||
R18
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vparallelport
|
||||
R20
|
||||
R21
|
||||
!i113 0
|
||||
R16
|
||||
R3
|
||||
R4
|
||||
vparallelport
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 Oh9lLSH=`_Q:=@41ZzlcY2
|
||||
!s11b k21ML[34E18n]@g]EG:g02
|
||||
I;1_EJNiVm[nDB?57=nXOD3
|
||||
R5
|
||||
S1
|
||||
R0
|
||||
R6
|
||||
R7
|
||||
S1
|
||||
R8
|
||||
R9
|
||||
R10
|
||||
R11
|
||||
!i122 -1
|
||||
L0 30
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R11
|
||||
R12
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vspi
|
||||
R14
|
||||
R15
|
||||
!i113 0
|
||||
R16
|
||||
R3
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 FWg;A^hM6Xk;TFJMgza]m2
|
||||
!s11b NBC7eT]a7]iC:n6DXhW[e0
|
||||
Ilbh>SdZV4bSDzE22EQIiC3
|
||||
vspi
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 GPbXMO8=ajXa5d]lGaVmH2
|
||||
!s11b <niOgj]Bz2TKD=0Y:F^jW2
|
||||
IJ^b4_ZQUY=Ddi7N>AgHIb1
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686830667
|
||||
R8
|
||||
w1686833271
|
||||
8./hdl_src/sv/fram.sv
|
||||
F./hdl_src/sv/fram.sv
|
||||
!i122 -1
|
||||
L0 4
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
!s108 1686831728.000000
|
||||
R13
|
||||
!s107 ./hdl_src/sv/fram.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/fram.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vSPI_Master
|
||||
R16
|
||||
R3
|
||||
R4
|
||||
vSPI_Master
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 LNaIK]EJb:HMhCL_bcUOT2
|
||||
!s11b RZ[UYHW;Fa4LhmckzB[<X2
|
||||
IFYo`G3DmU9[M^WeGMdfi73
|
||||
R5
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686826806
|
||||
R8
|
||||
R9
|
||||
8./hdl_src/sv/SPI_Master_Control.sv
|
||||
F./hdl_src/sv/SPI_Master_Control.sv
|
||||
!i122 -1
|
||||
Z19 L0 34
|
||||
R9
|
||||
R22
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
!s107 ./hdl_src/sv/SPI_Master_Control.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master_Control.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
R16
|
||||
R3
|
||||
n@s@p@i_@master
|
||||
vSPI_Master_With_Single_CS
|
||||
R3
|
||||
R4
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 15??SlXF;4=1UHZHFcb4D2
|
||||
!s11b iXFhD1[A]RQ:BgzgT;=fY3
|
||||
ID5Z=T=j@LdzO_?_@1UFZC3
|
||||
R5
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686826875
|
||||
R8
|
||||
R9
|
||||
8./hdl_src/sv/SPI_Master.sv
|
||||
F./hdl_src/sv/SPI_Master.sv
|
||||
!i122 -1
|
||||
Z20 L0 38
|
||||
R9
|
||||
Z23 L0 38
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
!s107 ./hdl_src/sv/SPI_Master.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/SPI_Master.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
R16
|
||||
R3
|
||||
n@s@p@i_@master_@with_@single_@c@s
|
||||
vsteuerung
|
||||
R3
|
||||
R4
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 >DGbebG_Mk0W]hI8XCQ?k0
|
||||
!s11b WKleG=JcKL4FgO@TP[IO[1
|
||||
IE`WCa5G2QlghM9EX[<1dS3
|
||||
R5
|
||||
S1
|
||||
R0
|
||||
R6
|
||||
R7
|
||||
S1
|
||||
R8
|
||||
!i122 -1
|
||||
R20
|
||||
R9
|
||||
R10
|
||||
R11
|
||||
!i122 -1
|
||||
R23
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R11
|
||||
R12
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vstimuli
|
||||
R14
|
||||
R15
|
||||
!i113 0
|
||||
R16
|
||||
R3
|
||||
R4
|
||||
vstimuli
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 ?c<R_8azXOe4?MR6PN9lb1
|
||||
!s11b f7UOC6iFO:78SRcz4Ojgc1
|
||||
IFCieJ4l88EVc2aVF84efc1
|
||||
R5
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686831722
|
||||
R8
|
||||
R9
|
||||
8./hdl_src/sv/stimuli.sv
|
||||
F./hdl_src/sv/stimuli.sv
|
||||
!i122 -1
|
||||
L0 37
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
!s107 ./hdl_src/sv/stimuli.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/stimuli.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vtimer
|
||||
R16
|
||||
R3
|
||||
R4
|
||||
vtimer
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 ^LgdMGMo^z_E<7OKUmDz:0
|
||||
!s11b [5XV:J9W^QFe>5GG;9B8k3
|
||||
IEenLI0W00diXD61Ele2;U0
|
||||
R5
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686831703
|
||||
R8
|
||||
R9
|
||||
8./hdl_src/sv/timer.sv
|
||||
F./hdl_src/sv/timer.sv
|
||||
!i122 -1
|
||||
L0 19
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
!s107 ./hdl_src/sv/timer.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/timer.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vtop
|
||||
R16
|
||||
R3
|
||||
R4
|
||||
vtop
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 6?3aiGY1NTOnA[jU;ZnEa3
|
||||
!s11b =zPVnM;Zm1L1Ig2finB;E2
|
||||
I^g60QFGiK:2<OB;dYJIk23
|
||||
R5
|
||||
S1
|
||||
R0
|
||||
R6
|
||||
R7
|
||||
S1
|
||||
R8
|
||||
R9
|
||||
R10
|
||||
R11
|
||||
!i122 -1
|
||||
L0 2
|
||||
R9
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R11
|
||||
R12
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
vtop_tb
|
||||
R14
|
||||
R15
|
||||
!i113 0
|
||||
R16
|
||||
R3
|
||||
R4
|
||||
vtop_tb
|
||||
R5
|
||||
R6
|
||||
!i10b 1
|
||||
!s100 MLz@z6Rj=WV;42>b=KZhX2
|
||||
!s11b jcE]a:O3cJ<=CdGZ:MgQ62
|
||||
IbRb[2DAWSb2IUOHB[hFz:2
|
||||
R5
|
||||
R7
|
||||
S1
|
||||
R0
|
||||
w1686315659
|
||||
R8
|
||||
R9
|
||||
8./hdl_src/sv/top_tb.sv
|
||||
F./hdl_src/sv/top_tb.sv
|
||||
!i122 -1
|
||||
R19
|
||||
R9
|
||||
R22
|
||||
R12
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R10
|
||||
R13
|
||||
!s107 ./hdl_src/sv/top_tb.sv|
|
||||
!s90 -reportprogress|300|-work|work|./hdl_src/sv/top_tb.sv|
|
||||
!i113 0
|
||||
R13
|
||||
R2
|
||||
R16
|
||||
R3
|
||||
|
||||
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Loading…
x
Reference in New Issue
Block a user