Initial commit
This commit is contained in:
muellerlu
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Executable
+60
@@ -0,0 +1,60 @@
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module MemGen_32_11 #(
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parameter data_width = 32,
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parameter addr_width = 11,
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parameter mem_depth = 2048
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)(
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input chip_en,
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input clock,
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input [addr_width-1:0]addr,
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output reg [data_width-1:0]rd_data,
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input rd_en,
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input wr_en,
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input [data_width-1:0]wr_data
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);
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// Bank selection: 1 bit selects one of 2 banks
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reg [1:0] mem_sel ;
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wire [31:0] mem_data_out [1:0];
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// Address decoder and output multiplexer
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always @(*)
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begin
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if ( chip_en == 1'b1 )
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case (addr[10])
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1'b0 : begin mem_sel = 2'b01; rd_data = mem_data_out[0]; end
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1'b1 : begin mem_sel = 2'b10; rd_data = mem_data_out[1]; end
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endcase
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else
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begin
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mem_sel = 2'b00;
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rd_data = 32'h00000000;
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end
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end
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genvar i;
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// Instantiate 2 banks, each with 2 halves (low + high 16 bits)
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generate
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for (i = 0; i < 2; i = i + 1) begin
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MemGen_16_10 U_lo (
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.chip_en(mem_sel[i]),
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.clock(clock),
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.addr(addr[9:0]),
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.rd_en(rd_en),
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.rd_data(mem_data_out[i][15:0]),
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.wr_en(wr_en),
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.wr_data(wr_data[15:0])
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);
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MemGen_16_10 U_hi (
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.chip_en(mem_sel[i]),
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.clock(clock),
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.addr(addr[9:0]),
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.rd_en(rd_en),
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.rd_data(mem_data_out[i][31:16]),
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.wr_en(wr_en),
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.wr_data(wr_data[31:16])
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);
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end
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endgenerate
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endmodule
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@@ -0,0 +1,52 @@
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// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 Bomin Kim Refactored ALU logic from decoder into this file
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// *********************************************************************************************
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module alu (
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input logic[2:0] aluOp,
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input logic aluNegAr,
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input logic aluBypass,
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input logic[31:0] op1,
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input logic[31:0] op2,
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output logic[31:0] result,
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output logic eqFlag
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);
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// Local parameters; list of aluOp
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localparam logic[2:0] f3add = 3'b000;
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localparam logic[2:0] f3sl = 3'b001;
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localparam logic[2:0] f3slt = 3'b010;
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localparam logic[2:0] f3sltU = 3'b011;
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localparam logic[2:0] f3xor = 3'b100;
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localparam logic[2:0] f3sr = 3'b101;
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localparam logic[2:0] f3or = 3'b110;
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localparam logic[2:0] f3and = 3'b111;
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// ALU logic
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always_comb begin : ALU
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eqFlag = op1 == op2;
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if (aluBypass) result = op1;
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else case(aluOp)
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f3add: result = aluNegAr ? op1 - op2 : op1 + op2;
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f3sl: result = op1 << op2[4:0];
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f3slt: result = {31'b0, $signed(op1) < $signed(op2)};
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f3sltU: result = {31'b0, $unsigned(op1) < $unsigned(op2)};
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f3xor: result = op1 ^ op2;
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f3sr: result = aluNegAr ? $signed(op1) >>> op2[4:0] : $signed(op1) >> op2[4:0];
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f3or: result = op1 | op2;
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f3and: result = op1 & op2;
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endcase
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end
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endmodule
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@@ -0,0 +1,135 @@
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// *********************************************************************************************
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// Project Version : v1.0
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// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
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// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 H.Elzomor Renamed file and module from soc to cpu
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// 15.Oct.2025 H.Elzomor Added an initial condition for clk_12p5
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// *********************************************************************************************
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module cpu (
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output logic[7:0] led,
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input logic[6:0] btn,
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input logic clk_25mhz
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//input logic scan_en
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);
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// Local Signals
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// Clock & Reset
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logic clk;
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// logic clk12p5;
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logic reset;
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// PC
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logic[31:0] CurrentPC;
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logic[31:0] JumpOrBranchPC;
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logic JumpOrBranch;
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logic[31:0] NextPC;
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// Memory
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logic[31:0] DAddr;
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logic[31:0] WData;
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logic[31:0] RData;
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logic[31:0] Instruction;
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logic WrMem;
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logic[1:0] DWidth;
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// Register File;
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logic[4:0] Rs1;
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logic[4:0] Rs2;
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logic[4:0] Rd;
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logic[31:0] RRs1;
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logic[31:0] RRs2;
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logic[31:0] WRd;
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logic WrReg;
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// Protection
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logic Illegal;
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// Logic
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assign clk = clk_25mhz;
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// Clock (12.5MHz)
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//assign clk = scan_en ? clk_25mhz : clk12p5;
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//assign clk = clk12p5;
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// always_ff @(posedge clk_25mhz) begin
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// if (reset)
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// clk12p5 <= 1'b0;
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// else if (!scan_en)
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// clk12p5 <= ~clk12p5;
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// end
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// Reset
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assign reset = ~btn[0];
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// LED
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assign led[0] = Illegal;
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assign led[1] = WrMem;
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assign led[7:2] = NextPC[7:2];
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// Module Instantiation
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// Decoder
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decoder theDecoder (
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// PC
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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// Memory
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.DAddr(DAddr),
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.WData(WData),
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.RData(RData),
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.Instruction(Instruction),
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.WrMem(WrMem),
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.DWidth(DWidth),
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// Register File
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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// Protection
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.Illegal(Illegal)
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);
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// Register File
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reg_file theRegisters (
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.Rs1(Rs1),
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.Rs2(Rs2),
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.Rd(Rd),
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.RRs1(RRs1),
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.RRs2(RRs2),
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.WRd(WRd),
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.WrReg(WrReg),
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.reset(reset),
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.clk(clk)
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);
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// PC
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pc thePC (
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.CurrentPC(CurrentPC),
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.JumpOrBranchPC(JumpOrBranchPC),
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.JumpOrBranch(JumpOrBranch),
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.NextPC(NextPC),
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.reset(reset),
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.clk(clk)
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);
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// Main Memory
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main_mem #(
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) theMem (
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.DAddr(DAddr),
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.IAddr(NextPC),
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.DWData(WData),
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.DRData(RData),
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.IRData(Instruction),
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.DWE(WrMem),
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.DWidth(DWidth),
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.reset(reset),
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.clk(clk)
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);
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endmodule
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@@ -0,0 +1,231 @@
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// *********************************************************************************************
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// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
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// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
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// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
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// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d]
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// -----
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// HISTORY : Date By Comments
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// ----------- --------- -------------------------------------------------
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// 15.Oct.2025 H.Elzomor Moved PC and ALU logic to their respective files
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// 15.Oct.2025 H.Elzomor Absorbed the branching logic into the decoder logic
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// *********************************************************************************************
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module decoder (
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// PC
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input logic[31:0] CurrentPC,
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output logic[31:0] JumpOrBranchPC,
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output logic JumpOrBranch,
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// Memory
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output logic[31:0] DAddr,
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output logic[31:0] WData,
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input logic[31:0] RData,
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input logic[31:0] Instruction,
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output logic WrMem,
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output logic[1:0] DWidth,
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// Register File
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output logic[4:0] Rs1,
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output logic[4:0] Rs2,
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output logic[4:0] Rd,
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input logic[31:0] RRs1,
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input logic[31:0] RRs2,
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output logic[31:0] WRd,
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output logic WrReg,
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// Protection
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output logic Illegal
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);
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// Local Parameters
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// OpCode: set a local parameter for each operation
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localparam logic[6:0] opLd = 7'b0000011;
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localparam logic[6:0] opAluImm = 7'b0010011;
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localparam logic[6:0] opUpPC = 7'b0010111;
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localparam logic[6:0] opSt = 7'b0100011;
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localparam logic[6:0] opAlu = 7'b0110011;
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localparam logic[6:0] opUpImm = 7'b0110111;
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localparam logic[6:0] opBranch = 7'b1100011;
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localparam logic[6:0] opJALR = 7'b1100111;
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localparam logic[6:0] opJAL = 7'b1101111;
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// Func7: set a local parameter for each function 7
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localparam logic[6:0] f7neg = 7'b0100000;
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// Func3: set a local parameter for each function 3
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// Load/Store
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localparam logic[2:0] f3byte = 3'b000;
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localparam logic[2:0] f3half = 3'b001;
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localparam logic[2:0] f3word = 3'b010;
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localparam logic[2:0] f3byteU = 3'b100;
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localparam logic[2:0] f3halfU = 3'b101;
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// ALU
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localparam logic[2:0] f3add = 3'b000;
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localparam logic[2:0] f3sl = 3'b001;
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localparam logic[2:0] f3slt = 3'b010;
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localparam logic[2:0] f3sltU = 3'b011;
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localparam logic[2:0] f3xor = 3'b100;
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localparam logic[2:0] f3sr = 3'b101;
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localparam logic[2:0] f3or = 3'b110;
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localparam logic[2:0] f3and = 3'b111;
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// Branch
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localparam logic[2:0] f3beq = 3'b000;
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localparam logic[2:0] f3bne = 3'b001;
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localparam logic[2:0] f3blt = 3'b100;
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localparam logic[2:0] f3bge = 3'b101;
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localparam logic[2:0] f3bltU = 3'b110;
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localparam logic[2:0] f3bgeU = 3'b111;
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// Local Signals
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// Instruction breakdown (excluding I/O)
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logic[6:0] theOp;
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logic[2:0] theFunct3;
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logic[6:0] theFunct7;
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logic[31:0] i_imm;
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logic[31:0] s_imm;
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logic[31:0] b_imm;
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logic[31:0] u_imm;
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logic[31:0] j_imm;
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// ALU
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logic[2:0] aluOp;
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logic aluNegAr;
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logic aluBypass;
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logic[31:0] op1;
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logic[31:0] op2;
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logic[31:0] result;
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logic eqFlag;
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// Instruction breakdown: assign values
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// OpCode and functions 3/7
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assign theOp = Instruction[6:0];
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assign theFunct3 = Instruction[14:12];
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assign theFunct7 = Instruction[31:25];
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// Registers
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assign Rs1 = Instruction[19:15];
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assign Rs2 = Instruction[24:20];
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assign Rd = Instruction[11:7];
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// Immediates
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always_comb begin : Immediate_Generator
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i_imm = {{21{Instruction[31]}}, Instruction[30:20]};
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s_imm = {{21{Instruction[31]}}, Instruction[30:25], Instruction[11:7]};
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b_imm = {{20{Instruction[31]}}, Instruction[7], Instruction[30:25], Instruction[11:8], 1'b0};
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u_imm = {Instruction[31:12], 12'b0};
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j_imm = {{12{Instruction[31]}}, Instruction[19:12], Instruction[20], Instruction[30:21], 1'b0};
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end
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// Decoder Logic
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always_comb begin : Main_Decoder
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// Factored port/signal values
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JumpOrBranch = '0;
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JumpOrBranchPC = '0;
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DAddr = '0;
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WData = RRs2;
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WrMem = '0;
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DWidth = f3word[1:0];
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WrReg = '1;
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Illegal = '0;
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aluOp = theFunct3;
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aluNegAr = '0;
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aluBypass = '0;
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op1 = RRs1;
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op2 = RRs2;
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// OpCode Cases
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case(theOp)
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opLd: begin
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DAddr = RRs1 + i_imm;
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DWidth = theFunct3[1:0];
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aluBypass = '1;
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op1 = RData;
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case(theFunct3)
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f3byte: op1[31:8] = {24{RData[7]}};
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f3byteU: op1[31:8] = {24{1'b0}};
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f3half: op1[31:16] = {16{RData[15]}};
|
||||
f3halfU: op1[31:16] = {16{1'b0}};
|
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f3word: ;
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default: begin
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||||
Illegal = '1;
|
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WrReg = '0;
|
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JumpOrBranch = '1;
|
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JumpOrBranchPC = CurrentPC;
|
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end
|
||||
endcase
|
||||
end
|
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opAluImm: begin
|
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op2 = i_imm;
|
||||
aluOp = theFunct3;
|
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aluNegAr = (theFunct7 == f7neg) & (theFunct3 == f3sr);
|
||||
end
|
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opUpPC: begin
|
||||
op1 = u_imm;
|
||||
op2 = CurrentPC;
|
||||
aluOp = f3add;
|
||||
end
|
||||
opSt: begin
|
||||
WrReg = '0;
|
||||
WrMem = '1;
|
||||
DAddr = RRs1 + s_imm;
|
||||
DWidth = theFunct3[1:0];
|
||||
end
|
||||
opAlu: begin
|
||||
aluOp = theFunct3;
|
||||
aluNegAr = (theFunct7 == f7neg) & ((theFunct3 == f3add) | (theFunct3 == f3sr));
|
||||
end
|
||||
opUpImm: begin
|
||||
op1 = u_imm;
|
||||
aluBypass = '1;
|
||||
end
|
||||
opBranch: begin
|
||||
WrReg = '0;
|
||||
JumpOrBranchPC = CurrentPC + b_imm;
|
||||
aluOp = f3slt;
|
||||
case(theFunct3)
|
||||
f3beq : begin JumpOrBranch = ( eqFlag)? '1 : '0; end
|
||||
f3bne : begin JumpOrBranch = (~eqFlag)? '1 : '0; end
|
||||
f3blt : begin JumpOrBranch = ( result[0])? '1 : '0; end
|
||||
f3bge : begin JumpOrBranch = (~result[0])? '1 : '0; end
|
||||
f3bltU: begin aluOp = f3sltU; JumpOrBranch = ( result[0])? '1 : '0; end
|
||||
f3bgeU: begin aluOp = f3sltU; JumpOrBranch = (~result[0])? '1 : '0; end
|
||||
default: begin
|
||||
Illegal = '1;
|
||||
JumpOrBranch = '1;
|
||||
JumpOrBranchPC = CurrentPC;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
opJALR: begin
|
||||
JumpOrBranch = '1;
|
||||
JumpOrBranchPC = (RRs1 + i_imm) & 32'hFFFFFFFE;
|
||||
op1 = CurrentPC;
|
||||
op2 = 4;
|
||||
aluOp = f3add;
|
||||
end
|
||||
opJAL: begin
|
||||
JumpOrBranch = '1;
|
||||
JumpOrBranchPC = CurrentPC + j_imm;
|
||||
op1 = CurrentPC;
|
||||
op2 = 4;
|
||||
aluOp = f3add;
|
||||
end
|
||||
default: begin
|
||||
Illegal = '1;
|
||||
WrReg = '0;
|
||||
JumpOrBranch = '1;
|
||||
JumpOrBranchPC = CurrentPC;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// ALU module instantiation
|
||||
alu theALU (
|
||||
.aluOp(aluOp),
|
||||
.aluNegAr(aluNegAr),
|
||||
.aluBypass(aluBypass),
|
||||
.op1(op1),
|
||||
.op2(op2),
|
||||
.result(result),
|
||||
.eqFlag(eqFlag)
|
||||
);
|
||||
assign WRd = result;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,120 @@
|
||||
// *********************************************************************************************
|
||||
// main_mem.sv - Macro-based implementation using MemGen_32_11
|
||||
// *********************************************************************************************
|
||||
// Replaces the behavioral flip-flop RAM with an SRAM macro wrapper.
|
||||
//
|
||||
// Key differences from the original:
|
||||
// - Uses MemGen_32_11 (2048 words x 32 bits, single-port SRAM macro)
|
||||
// - Time-multiplexed using the 25 MHz clock for two accesses per CPU cycle:
|
||||
// clk12p5=0 -> instruction fetch (IAddr)
|
||||
// clk12p5=1 -> data access (DAddr read/write)
|
||||
// - Word-only writes; SB/SH instructions will be dropped (TODO: add RMW later)
|
||||
// - MEM_INIT_FILE parameter kept for interface compatibility (not functional)
|
||||
// *********************************************************************************************
|
||||
|
||||
module main_mem #(
|
||||
parameter int ABits = 13
|
||||
//parameter string MEM_INIT_FILE = ""
|
||||
)(
|
||||
input logic clk, // 12.5 MHz CPU clock (= clk12p5)
|
||||
// input logic clk_25mhz, // NEW: 25 MHz memory clock
|
||||
input logic reset,
|
||||
input logic[31:0] DAddr,
|
||||
input logic[31:0] IAddr,
|
||||
input logic[31:0] DWData,
|
||||
output logic[31:0] DRData,
|
||||
output logic[31:0] IRData,
|
||||
input logic DWE,
|
||||
input logic[1:0] DWidth
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Localparam
|
||||
//---------------------------------------------------------------------------
|
||||
localparam logic[1:0] _byte = 2'b00;
|
||||
localparam logic[1:0] _half = 2'b01;
|
||||
localparam logic[1:0] _word = 2'b10;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Time-multiplexing logic
|
||||
//
|
||||
// The CPU runs on clk12p5 (half of clk_25mhz).
|
||||
// We use clk_25mhz to drive the memory; within one CPU cycle:
|
||||
// - During clk12p5 LOW: present instruction address
|
||||
// - During clk12p5 HIGH: present data address
|
||||
//
|
||||
// The macro latches the address on the rising edge of its own clock (clk_25mhz),
|
||||
// so we select which address to send based on the current phase.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
logic [10:0] mem_addr; // 11-bit word address for MemGen_32_11
|
||||
logic [31:0] mem_wr_data;
|
||||
logic mem_wr_en;
|
||||
logic mem_rd_en;
|
||||
logic [31:0] mem_rd_data;
|
||||
|
||||
// Phase: 0 = instruction fetch, 1 = data access
|
||||
// Since clk12p5 rises on clk_25mhz rising edge, clk12p5 itself tells us the phase
|
||||
wire phase_is_data = clk; // clk = clk12p5
|
||||
|
||||
always_comb begin
|
||||
if (phase_is_data) begin
|
||||
// Data phase
|
||||
mem_addr = DAddr[12:2];
|
||||
mem_wr_data = DWData;
|
||||
mem_wr_en = DWE && !reset && (DWidth == _word);
|
||||
mem_rd_en = !DWE;
|
||||
end else begin
|
||||
// Instruction phase
|
||||
mem_addr = IAddr[12:2];
|
||||
mem_wr_data = 32'h0;
|
||||
mem_wr_en = 1'b0;
|
||||
mem_rd_en = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Single memory macro - time-multiplexed
|
||||
//---------------------------------------------------------------------------
|
||||
MemGen_32_11 u_mem (
|
||||
.chip_en (1'b1),
|
||||
.clock (clk_25mhz), // 2x CPU clock - enables dual access per CPU cycle
|
||||
.addr (mem_addr),
|
||||
.rd_en (mem_rd_en),
|
||||
.rd_data (mem_rd_data),
|
||||
.wr_en (mem_wr_en),
|
||||
.wr_data (mem_wr_dat)
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Output capture
|
||||
//
|
||||
// On each CPU cycle, we capture:
|
||||
// - IRData: the instruction read during instruction phase
|
||||
// - DRData: the data read during data phase
|
||||
//
|
||||
// The macro delivers rd_data one clk_25mhz cycle after the address.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// Capture IRData at the end of the instruction phase (when data phase starts)
|
||||
always_ff @(posedge clk_25mhz) begin
|
||||
if (reset) begin
|
||||
IRData <= 32'h0;
|
||||
end else if (!phase_is_data) begin
|
||||
// We just presented the data address; the read of the previous
|
||||
// instruction address is now available on mem_rd_data
|
||||
// (Note: timing requires verification against macro characteristics)
|
||||
IRData <= mem_rd_data;
|
||||
end
|
||||
end
|
||||
|
||||
// Capture DRData at the end of the data phase (when instruction phase starts)
|
||||
always_ff @(posedge clk_25mhz) begin
|
||||
if (reset) begin
|
||||
DRData <= 32'h0;
|
||||
end else if (phase_is_data) begin
|
||||
DRData <= mem_rd_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,142 @@
|
||||
// *********************************************************************************************
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
|
||||
// Last Modified : 23.Oct.2025 by Aliakbar Merchant [commit 2f8f03d]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- ---------- -------------------------------------------------
|
||||
// 22.Oct.2025 A.Merchant Added reset handling condition for Instr. read logic
|
||||
// 22.Oct.2025 A.Merchant Added reset handling condition for data write logic
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
module main_mem #(
|
||||
parameter int ABits = 13 // Number of address bits
|
||||
//parameter string MEM_INIT_FILE = "" // Optional memory initializations file
|
||||
) (
|
||||
input logic clk, // Clock
|
||||
input logic reset, // Active high sync reset
|
||||
input logic[31:0] DAddr, // Data Address
|
||||
input logic[31:0] IAddr, // Instruction Address
|
||||
input logic[31:0] DWData, // Data to write
|
||||
output logic[31:0] DRData, // Data read
|
||||
output logic[31:0] IRData, // Instruction read
|
||||
input logic DWE, // Data write enable, 1=Write
|
||||
input logic [1:0] DWidth // Access width (byte, half word, word)
|
||||
);
|
||||
|
||||
// Local Parameter
|
||||
localparam logic[1:0] _byte = 2'b00; // byte: 8 bits
|
||||
localparam logic[1:0] _half = 2'b01; // half: 16 bits
|
||||
localparam logic[1:0] _word = 2'b10; // word: 32 bits
|
||||
|
||||
// Local Signals
|
||||
//logic[31:0] RAM[2**(ABits-2)-1:0]; // Memory array 8KB(8192): ignores lowest 2 bits as 32bit-word
|
||||
logic [31:0] irTmp;
|
||||
logic[31:0] drTmp; // Temporary register to hold the data read from RAM.
|
||||
logic [10:0] mem_addr; // 11-bit word address for MemGen_32_11
|
||||
logic [31:0] mem_wdata; // 32-bit data bus for MemGen_32_11
|
||||
logic [31:0] mem_rdata; // 32-bit data bus for MemGen_32_11
|
||||
|
||||
|
||||
MemGen_32_11 RAM (
|
||||
.chip_en (1'b1),
|
||||
.clock (clk),
|
||||
.addr (mem_addr),
|
||||
.rd_en (!DWE),
|
||||
.rd_data (mem_rdata),
|
||||
.wr_en (DWE),
|
||||
.wr_data (mem_wdata)
|
||||
);
|
||||
|
||||
// memory initilizations
|
||||
// initial begin
|
||||
|
||||
//if (MEM_INIT_FILE != "") begin
|
||||
// $readmemh(MEM_INIT_FILE, RAM);
|
||||
// end
|
||||
// end
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
//--------------------------- DATA WRITE LOGIC ---------------------------//
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
|
||||
always_ff @(negedge clk) begin
|
||||
if (reset) begin
|
||||
mem_addr <= 0;
|
||||
end else begin
|
||||
if (DWE) begin
|
||||
mem_addr <= DAddr[(ABits-1):2];
|
||||
// RAM[DAddr[(ABits-1):2]] <= DWData;
|
||||
case (DWidth)
|
||||
_word:
|
||||
mem_wdata <= DWData;
|
||||
_half:
|
||||
case (DAddr[1])
|
||||
1'b0: mem_wdata [31:16] <= DWData[15:0];
|
||||
1'b1: mem_wdata [15: 0] <= DWData[15:0];
|
||||
endcase
|
||||
_byte:
|
||||
case (DAddr[1:0])
|
||||
2'b00: mem_wdata [31:24] <= DWData[7:0];
|
||||
2'b01: mem_wdata [23:16] <= DWData[7:0];
|
||||
2'b10: mem_wdata [15: 8] <= DWData[7:0];
|
||||
2'b11: mem_wdata [ 7: 0] <= DWData[7:0];
|
||||
endcase
|
||||
default: ;
|
||||
endcase
|
||||
end else begin
|
||||
mem_addr <= IAddr[(ABits-1):2];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
//--------------------------- DATA READ LOGIC ----------------------------//
|
||||
//---------------------------------------------------------------------------//
|
||||
always_ff @(negedge clk) begin
|
||||
drTmp <= mem_rdata;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
case (DWidth)
|
||||
_word:
|
||||
DRData = drTmp;
|
||||
_half:
|
||||
case (DAddr[1])
|
||||
1'b0: DRData = {16'b0, drTmp[31:16]};
|
||||
1'b1: DRData = {16'b0, drTmp[15: 0]};
|
||||
endcase
|
||||
_byte:
|
||||
case (DAddr[1:0])
|
||||
2'b00: DRData = {24'b0, drTmp[31:24]};
|
||||
2'b01: DRData = {24'b0, drTmp[23:16]};
|
||||
2'b10: DRData = {24'b0, drTmp[15: 8]};
|
||||
2'b11: DRData = {24'b0, drTmp[ 7: 0]};
|
||||
endcase
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
//----------------------- INSTRUCTION READ LOGIC -------------------------//
|
||||
//---------------------------------------------------------------------------//
|
||||
//
|
||||
//fetch intrcution from memory into IRData
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) begin
|
||||
IRData <= mem_rdata;
|
||||
end
|
||||
else begin
|
||||
IRData <= mem_rdata;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,15 @@
|
||||
#--------------------------------------------------------------------
|
||||
# date : Thu May 28 12:01:37 CEST 2026
|
||||
# ppid/pid : 2439771/2439781
|
||||
# hostname : efiapps0.ads1.fh-nuernberg.de
|
||||
# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64
|
||||
# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1
|
||||
# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl
|
||||
# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.00
|
||||
# tmpdir : /tmp/oasys.2439771/
|
||||
#--------------------------------------------------------------------
|
||||
# Starting Interactive Session
|
||||
exit
|
||||
#--------------------------------------------------------------------
|
||||
# End Session at Thu May 28 13:20:20 CEST 2026
|
||||
#--------------------------------------------------------------------
|
||||
@@ -0,0 +1,23 @@
|
||||
#--------------------------------------------------------------------
|
||||
# date : Thu May 28 13:29:15 CEST 2026
|
||||
# ppid/pid : 2451524/2451534
|
||||
# hostname : efiapps0.ads1.fh-nuernberg.de
|
||||
# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64
|
||||
# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1
|
||||
# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl
|
||||
# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.01
|
||||
# tmpdir : /tmp/oasys.2451524/
|
||||
#--------------------------------------------------------------------
|
||||
# Starting Interactive Session
|
||||
ls
|
||||
cd ..
|
||||
ls
|
||||
cd ..
|
||||
cd ..
|
||||
ls
|
||||
source scripts_risc_v/1_read_design.tcl
|
||||
source scripts_risc_v/2_synthesize_optimize.tcl
|
||||
exit
|
||||
#--------------------------------------------------------------------
|
||||
# End Session at Thu May 28 13:42:47 CEST 2026
|
||||
#--------------------------------------------------------------------
|
||||
@@ -0,0 +1,317 @@
|
||||
|
||||
@/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.02:1093
|
||||
libc: 2.28-stable
|
||||
|
||||
Timestamp: 1779968572.056193725
|
||||
---
|
||||
PID=2457562 0.129170598 0.075018 0.054153 program start
|
||||
Complete list of environment variables at program start
|
||||
_ /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/oasysGui
|
||||
BASH_FUNC_which%% {() { ( alias;
|
||||
eval ${which_declare} ) | /usr/bin/which --tty-only --read-alias --read-functions --show-tilde --show-dot $@
|
||||
}}
|
||||
CALIBRE_HOME /applications/SiemensEDA/siemenseda2023/calibre/aok_cal_2023.4_39.23
|
||||
CDS_DDIEXPORT /applications/Cadence/cadence2022/DDIEXPORT2233
|
||||
CDS_GENUS /applications/Cadence/cadence2022/DDIEXPORT2233/GENUS*
|
||||
CDS_INNOVUS /applications/Cadence/cadence2022/DDIEXPORT2233/INNOVUS*
|
||||
CDS_JLS /applications/Cadence/cadence2022/DDIEXPORT2233/JLS*
|
||||
CDS_LIC_FILE 1816@141.75.245.12
|
||||
CDS_SSV /applications/Cadence/cadence2022/SSV2213
|
||||
COLORTERM truecolor
|
||||
DBUS_SESSION_BUS_ADDRESS unix:path=/run/user/1083946113/bus,guid=02a4782d1dbcb9e9f51311946a16bc26
|
||||
DBUS_STARTER_ADDRESS unix:path=/run/user/1083946113/bus,guid=02a4782d1dbcb9e9f51311946a16bc26
|
||||
DBUS_STARTER_BUS_TYPE session
|
||||
DESKTOP_SESSION gnome-classic
|
||||
DISPLAY :10
|
||||
ENV_VER 1
|
||||
FORMALITY /applications/Synopsys/synopsys2022/fm/U-2022.12-SP4
|
||||
GNOME_DESKTOP_SESSION_ID this-is-deprecated
|
||||
GNOME_SHELL_SESSION_MODE classic
|
||||
GNOME_TERMINAL_SCREEN /org/gnome/Terminal/screen/46eff583_4eec_45e6_973b_99403434080c
|
||||
GNOME_TERMINAL_SERVICE :1.207
|
||||
HISTCONTROL ignoredups
|
||||
HISTSIZE 1000
|
||||
HOME /users/ads1/charapallivenkatsaja/linux
|
||||
HOSTNAME efiapps0.ads1.fh-nuernberg.de
|
||||
INVOCATION_ID ad18f9577c3a4ac89ac41411f6a6e0c9
|
||||
JOURNAL_STREAM 9:20654617
|
||||
KRB5CCNAME /var/opt/thinlinc/sessions/charapallivenkatsaja/10/krb5cc
|
||||
LANG en_US.UTF-8
|
||||
LANGUAGE en_US
|
||||
LATTICE /applications/Lattice
|
||||
LC_NUMERIC en_US.UTF-8
|
||||
LD_LIBRARY_PATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/Linux-x86_64-O:/opt/thinlinc/lib64:/opt/thinlinc/lib
|
||||
LESSOPEN {||/usr/bin/lesspipe.sh %s}
|
||||
LM_LICENSE_FILE 1818@141.75.245.12:1812@141.75.245.10:1810@141.75.245.10
|
||||
LOGNAME charapallivenkatsaja
|
||||
LS_COLORS {rs=0:di=38;5;33:ln=38;5;51:mh=00:pi=40;38;5;11:so=38;5;13:do=38;5;5:bd=48;5;232;38;5;11:cd=48;5;232;38;5;3:or=48;5;232;38;5;9:mi=01;05;37;41:su=48;5;196;38;5;15:sg=48;5;11;38;5;16:ca=48;5;196;38;5;226:tw=48;5;10;38;5;16:ow=48;5;10;38;5;21:st=48;5;21;38;5;15:ex=38;5;40:*.tar=38;5;9:*.tgz=38;5;9:*.arc=38;5;9:*.arj=38;5;9:*.taz=38;5;9:*.lha=38;5;9:*.lz4=38;5;9:*.lzh=38;5;9:*.lzma=38;5;9:*.tlz=38;5;9:*.txz=38;5;9:*.tzo=38;5;9:*.t7z=38;5;9:*.zip=38;5;9:*.z=38;5;9:*.dz=38;5;9:*.gz=38;5;9:*.lrz=38;5;9:*.lz=38;5;9:*.lzo=38;5;9:*.xz=38;5;9:*.zst=38;5;9:*.tzst=38;5;9:*.bz2=38;5;9:*.bz=38;5;9:*.tbz=38;5;9:*.tbz2=38;5;9:*.tz=38;5;9:*.deb=38;5;9:*.rpm=38;5;9:*.jar=38;5;9:*.war=38;5;9:*.ear=38;5;9:*.sar=38;5;9:*.rar=38;5;9:*.alz=38;5;9:*.ace=38;5;9:*.zoo=38;5;9:*.cpio=38;5;9:*.7z=38;5;9:*.rz=38;5;9:*.cab=38;5;9:*.wim=38;5;9:*.swm=38;5;9:*.dwm=38;5;9:*.esd=38;5;9:*.jpg=38;5;13:*.jpeg=38;5;13:*.mjpg=38;5;13:*.mjpeg=38;5;13:*.gif=38;5;13:*.bmp=38;5;13:*.pbm=38;5;13:*.pgm=38;5;13:*.ppm=38;5;13:*.tga=38;5;13:*.xbm=38;5;13:*.xpm=38;5;13:*.tif=38;5;13:*.tiff=38;5;13:*.png=38;5;13:*.svg=38;5;13:*.svgz=38;5;13:*.mng=38;5;13:*.pcx=38;5;13:*.mov=38;5;13:*.mpg=38;5;13:*.mpeg=38;5;13:*.m2v=38;5;13:*.mkv=38;5;13:*.webm=38;5;13:*.ogm=38;5;13:*.mp4=38;5;13:*.m4v=38;5;13:*.mp4v=38;5;13:*.vob=38;5;13:*.qt=38;5;13:*.nuv=38;5;13:*.wmv=38;5;13:*.asf=38;5;13:*.rm=38;5;13:*.rmvb=38;5;13:*.flc=38;5;13:*.avi=38;5;13:*.fli=38;5;13:*.flv=38;5;13:*.gl=38;5;13:*.dl=38;5;13:*.xcf=38;5;13:*.xwd=38;5;13:*.yuv=38;5;13:*.cgm=38;5;13:*.emf=38;5;13:*.ogv=38;5;13:*.ogx=38;5;13:*.aac=38;5;45:*.au=38;5;45:*.flac=38;5;45:*.m4a=38;5;45:*.mid=38;5;45:*.midi=38;5;45:*.mka=38;5;45:*.mp3=38;5;45:*.mpc=38;5;45:*.ogg=38;5;45:*.ra=38;5;45:*.wav=38;5;45:*.oga=38;5;45:*.opus=38;5;45:*.spx=38;5;45:*.xspf=38;5;45:}
|
||||
MAIL /var/spool/mail/charapallivenkatsaja
|
||||
MANAGERPID 2391729
|
||||
MANPATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/doc/man:
|
||||
MGC_AMS_HOME /applications/SiemensEDA/siemenseda2023/amsv
|
||||
MGC_HOME /applications/SiemensEDA/siemenseda2023
|
||||
MGLS_HOME /applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64/mgls
|
||||
MGLS_LICENSE_FILE 1810@141.75.245.10
|
||||
MODELTECH /applications/SiemensEDA/siemenseda2023/questasim
|
||||
MTI_VCO_MODE 64
|
||||
NIOS2_ROOTDIR /applications/intelFPGA/22.1/nios2eds
|
||||
OASYSLD_LICENSE_FILE /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/license.lic
|
||||
PATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/share/formalpro:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/share/onespin:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/share/slec:/applications/th_tools/scripts:/applications/intelFPGA/22.1/quartus/bin:/applications/intelFPGA/22.1/quartus/qsys/bin:/applications/intelFPGA/22.1/nios2eds:/applications/Lattice/radiant/2023.1/bin/lin64:/applications/Synopsys/synopsys2022/syn/U-2022.12-SP4/amd64/syn/bin:/applications/Synopsys/synopsys2022/scl/2022.12/linux64/bin:/applications/Synopsys/synopsys2022/fm/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/txs/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/lc/V-2023.12/bin:/applications/th_tools/scripts:/applications/intelFPGA/22.1/quartus/bin:/applications/intelFPGA/22.1/quartus/qsys/bin:/applications/intelFPGA/22.1/nios2eds:/applications/Lattice/radiant/2023.1/bin/lin64:/applications/Synopsys/synopsys2022/syn/U-2022.12-SP4/amd64/syn/bin:/applications/Synopsys/synopsys2022/scl/2022.12/linux64/bin:/applications/Synopsys/synopsys2022/fm/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/txs/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/lc/V-2023.12/bin:/users/ads1/charapallivenkatsaja/linux/.local/bin:/users/ads1/charapallivenkatsaja/linux/bin:/bin:/usr/bin:/opt/thinlinc/bin:/usr/local/bin:/usr/bin/X11:/sbin:/usr/sbin:/usr/local/sbin:/applications/Cadence/cadence2022/DDIEXPORT2233/bin:/applications/Cadence/cadence2022/SSV2213/bin:/applications/SiemensEDA/siemenseda2023/questasim/bin:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64:/applications/SiemensEDA/siemenseda2023/questasim/vco:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64/mgls/bin:/applications/SiemensEDA/siemenseda2023/amsv/bin:/applications/SiemensEDA/siemenseda2023/amsv/modeltech/bin:/applications/SiemensEDA/siemenseda2023/calibre/aok_cal_2023.4_39.23/bin:/applications/SiemensEDA/siemenseda2023/tessent/bin:/applications/SiemensEDA/siemenseda2023/oasys/bin:/applications/SiemensEDA/siemenseda2023/precision/bin:/applications/Cadence/cadence2022/DDIEXPORT2233/bin:/applications/Cadence/cadence2022/SSV2213/bin:/applications/SiemensEDA/siemenseda2023/questasim/bin:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64:/applications/SiemensEDA/siemenseda2023/questasim/vco:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64/mgls/bin:/applications/SiemensEDA/siemenseda2023/amsv/bin:/applications/SiemensEDA/siemenseda2023/amsv/modeltech/bin:/applications/SiemensEDA/siemenseda2023/calibre/aok_cal_2023.4_39.23/bin:/applications/SiemensEDA/siemenseda2023/tessent/bin:/applications/SiemensEDA/siemenseda2023/oasys/bin:/applications/SiemensEDA/siemenseda2023/precision/bin
|
||||
PCSCTUN_COOKIE /var/opt/thinlinc/sessions/charapallivenkatsaja/10/pcsctun-cookie
|
||||
PCSCTUN_SERVER 127.0.0.1:5006
|
||||
PULSE_COOKIE /var/opt/thinlinc/sessions/charapallivenkatsaja/10/pulse-cookie
|
||||
PULSE_RUNTIME_PATH /var/opt/thinlinc/sessions/charapallivenkatsaja/10/pulse
|
||||
PULSE_SERVER {/var/opt/thinlinc/sessions/charapallivenkatsaja/10/pulse/native 127.0.0.1:5005}
|
||||
PWD /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl
|
||||
QSYS_ROOTDIR /applications/intelFPGA/22.1/quartus/qsys/bin
|
||||
QT_IM_MODULE ibus
|
||||
QUARTUS /applications/intelFPGA
|
||||
QUARTUS_ROOTDIR /applications/intelFPGA/22.1/quartus
|
||||
RT_CMD {/applications/SiemensEDA/siemenseda2023/oasys/bin/oasys }
|
||||
RT_HOME /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1
|
||||
RT_LIBPATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib
|
||||
RT_MANPATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/doc/man
|
||||
RT_PID 2457552
|
||||
RT_SIGSTKSZ 16
|
||||
RT_TCL_PATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl
|
||||
RT_TMP /tmp/oasys.2457552
|
||||
RT_WRAPPER_SCRIPT /applications/SiemensEDA/siemenseda2023/oasys/bin/oasys
|
||||
SCRIPTS /applications/th_tools/scripts
|
||||
SESSION_MANAGER local/unix:@/tmp/.ICE-unix/2434259,unix/unix:/tmp/.ICE-unix/2434259
|
||||
SHELL /bin/bash
|
||||
SHLVL 4
|
||||
SNPSLMD_LICENSE_FILE 1806@141.75.245.10
|
||||
SSH_ASKPASS /usr/libexec/openssh/gnome-ssh-askpass
|
||||
SSH_AUTH_SOCK /run/user/1083946113/keyring/ssh
|
||||
SYNOPSYS /applications/Synopsys/synopsys2022/syn/U-2022.12-SP4
|
||||
SYNOPSYS_TMAX /applications/Synopsys/synopsys2022/txs/U-2022.12-SP4
|
||||
TCL_LIBRARY /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library
|
||||
TERM xterm-256color
|
||||
TLPREFIX /opt/thinlinc
|
||||
TLPROFILE gnome-classic
|
||||
TLSESSIONDATA /var/opt/thinlinc/sessions/charapallivenkatsaja/10
|
||||
TOWN Springfield
|
||||
USER charapallivenkatsaja
|
||||
USERNAME charapallivenkatsaja
|
||||
VTE_VERSION 5204
|
||||
which_declare {declare -f}
|
||||
XAUTHORITY /var/opt/thinlinc/sessions/charapallivenkatsaja/10/Xauthority
|
||||
XDG_CURRENT_DESKTOP GNOME-Classic:GNOME
|
||||
XDG_DATA_DIRS /users/ads1/charapallivenkatsaja/linux/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share
|
||||
XDG_MENU_PREFIX gnome-
|
||||
XDG_RUNTIME_DIR /run/user/1083946113
|
||||
XDG_SESSION_CLASS user
|
||||
XDG_SESSION_DESKTOP gnome-classic
|
||||
XDG_SESSION_ID 6060
|
||||
XDG_SESSION_TYPE x11
|
||||
XMODIFIERS @im=ibus
|
||||
---
|
||||
|
||||
Timestamp: 1779968572.059144838
|
||||
---
|
||||
Soft resource limits:
|
||||
|
||||
Executing: /bin/bash -f -c {ulimit -a -S}
|
||||
core file size (blocks, -c) 0
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 191837
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 1024
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) 81920
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 191837
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
---
|
||||
|
||||
Timestamp: 1779968572.060768504
|
||||
---
|
||||
Hard resource limits:
|
||||
|
||||
Executing: /bin/bash -f -c {ulimit -a -H}
|
||||
core file size (blocks, -c) unlimited
|
||||
data seg size (kbytes, -d) unlimited
|
||||
scheduling priority (-e) 0
|
||||
file size (blocks, -f) unlimited
|
||||
pending signals (-i) 191837
|
||||
max locked memory (kbytes, -l) 64
|
||||
max memory size (kbytes, -m) unlimited
|
||||
open files (-n) 262144
|
||||
pipe size (512 bytes, -p) 8
|
||||
POSIX message queues (bytes, -q) 819200
|
||||
real-time priority (-r) 0
|
||||
stack size (kbytes, -s) unlimited
|
||||
cpu time (seconds, -t) unlimited
|
||||
max user processes (-u) 191837
|
||||
virtual memory (kbytes, -v) unlimited
|
||||
file locks (-x) unlimited
|
||||
---
|
||||
|
||||
Timestamp: 1779968572.061645115
|
||||
---
|
||||
CPU Information
|
||||
|
||||
processor : 0
|
||||
vendor_id : AuthenticAMD
|
||||
cpu family : 25
|
||||
model : 1
|
||||
model name : AMD EPYC 73F3 16-Core Processor
|
||||
stepping : 1
|
||||
microcode : 0xa0011d3
|
||||
cpu MHz : 3499.999
|
||||
cache size : 512 KB
|
||||
physical id : 0
|
||||
siblings : 1
|
||||
core id : 0
|
||||
cpu cores : 1
|
||||
apicid : 0
|
||||
initial apicid : 0
|
||||
fpu : yes
|
||||
fpu_exception : yes
|
||||
cpuid level : 16
|
||||
wp : yes
|
||||
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl tsc_reliable nonstop_tsc cpuid extd_apicid pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw topoext invpcid_single ibpb vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves clzero wbnoinvd arat umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor fsrm
|
||||
bugs : fxsave_leak sysret_ss_attrs null_seg spectre_v1 spectre_v2 spec_store_bypass srso
|
||||
bogomips : 6999.99
|
||||
TLB size : 2560 4K pages
|
||||
clflush size : 64
|
||||
cache_alignment : 64
|
||||
address sizes : 45 bits physical, 48 bits virtual
|
||||
power management:
|
||||
|
||||
|
||||
processor : 1
|
||||
physical id : 2
|
||||
apicid : 2
|
||||
initial apicid : 2
|
||||
|
||||
processor : 2
|
||||
physical id : 4
|
||||
apicid : 4
|
||||
initial apicid : 4
|
||||
|
||||
processor : 3
|
||||
physical id : 6
|
||||
apicid : 6
|
||||
initial apicid : 6
|
||||
|
||||
processor : 4
|
||||
physical id : 8
|
||||
apicid : 8
|
||||
initial apicid : 8
|
||||
|
||||
processor : 5
|
||||
physical id : 10
|
||||
apicid : 10
|
||||
initial apicid : 10
|
||||
|
||||
processor : 6
|
||||
physical id : 12
|
||||
apicid : 12
|
||||
initial apicid : 12
|
||||
|
||||
processor : 7
|
||||
physical id : 14
|
||||
apicid : 14
|
||||
initial apicid : 14
|
||||
|
||||
processor : 8
|
||||
physical id : 16
|
||||
apicid : 16
|
||||
initial apicid : 16
|
||||
|
||||
processor : 9
|
||||
physical id : 18
|
||||
apicid : 18
|
||||
initial apicid : 18
|
||||
|
||||
processor : 10
|
||||
physical id : 20
|
||||
apicid : 20
|
||||
initial apicid : 20
|
||||
|
||||
processor : 11
|
||||
physical id : 22
|
||||
apicid : 22
|
||||
initial apicid : 22
|
||||
|
||||
This host has 12 processors, with most parameters identical to the first one, except as noted above.
|
||||
|
||||
---
|
||||
|
||||
Timestamp: 1779968572.161364465
|
||||
---
|
||||
Miscellaneous system info for process PID=2457562
|
||||
Recorded at Thu May 28 13:42:52 CEST 2026
|
||||
|
||||
Executing: uptime
|
||||
13:42:52 up 20 days, 1:11, 5 users, load average: 1.99, 2.79, 2.57
|
||||
|
||||
Executing: uname -a
|
||||
Linux efiapps0.ads1.fh-nuernberg.de 4.18.0-553.123.1.el8_10.x86_64 #1 SMP Mon May 4 13:45:48 EDT 2026 x86_64 x86_64 x86_64 GNU/Linux
|
||||
|
||||
Executing: free
|
||||
total used free shared buff/cache available
|
||||
Mem: 49166924 12854332 9280556 826488 27032036 34721076
|
||||
Swap: 25165820 8312 25157508
|
||||
|
||||
Executing: ps u 2457562
|
||||
USER PID %CPU %MEM VSZ RSS TTY STAT START TIME COMMAND
|
||||
charapa+ 2457562 13.0 0.1 438180 69168 pts/2 S+ 13:42 0:00 /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/oasysGui --
|
||||
|
||||
Executing: cat /etc/redhat-release
|
||||
Red Hat Enterprise Linux release 8.9 (Ootpa)
|
||||
|
||||
Executing: ldd /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/oasysGui
|
||||
linux-vdso.so.1 (0x00007fff5a525000)
|
||||
libQt5PrintSupport.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5PrintSupport.so.5 (0x00007f7623103000)
|
||||
libQt5Widgets.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5Widgets.so.5 (0x00007f76226ab000)
|
||||
libQt5Gui.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5Gui.so.5 (0x00007f7621d0f000)
|
||||
libQt5Core.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5Core.so.5 (0x00007f7621178000)
|
||||
libmemsh-102.so => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libmemsh-102.so (0x00007f76235b0000)
|
||||
libncurses.so.5 => /lib64/libncurses.so.5 (0x00007f7620f51000)
|
||||
libpthread.so.0 => /lib64/libpthread.so.0 (0x00007f7620d31000)
|
||||
libdl.so.2 => /lib64/libdl.so.2 (0x00007f7620b2d000)
|
||||
librt.so.1 => /lib64/librt.so.1 (0x00007f7620925000)
|
||||
libX11.so.6 => /lib64/libX11.so.6 (0x00007f76205e1000)
|
||||
libz.so.1 => /lib64/libz.so.1 (0x00007f76203c9000)
|
||||
libm.so.6 => /lib64/libm.so.6 (0x00007f7620047000)
|
||||
libc.so.6 => /lib64/libc.so.6 (0x00007f761fc71000)
|
||||
libgthread-2.0.so.0 => /lib64/libgthread-2.0.so.0 (0x00007f761fa6f000)
|
||||
libglib-2.0.so.0 => /lib64/libglib-2.0.so.0 (0x00007f761f755000)
|
||||
/lib64/ld-linux-x86-64.so.2 (0x00007f76233a4000)
|
||||
libtinfo.so.5 => /lib64/libtinfo.so.5 (0x00007f761f52a000)
|
||||
libxcb.so.1 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libxcb.so.1 (0x00007f761f2f5000)
|
||||
libgnutls.so.30 => /lib64/libgnutls.so.30 (0x00007f761ef04000)
|
||||
libpcre.so.1 => /lib64/libpcre.so.1 (0x00007f761ec93000)
|
||||
libXau.so.6 => /lib64/libXau.so.6 (0x00007f761ea8f000)
|
||||
libXdmcp.so.6 => /lib64/libXdmcp.so.6 (0x00007f761e889000)
|
||||
libp11-kit.so.0 => /lib64/libp11-kit.so.0 (0x00007f761e55f000)
|
||||
libidn2.so.0 => /lib64/libidn2.so.0 (0x00007f761e341000)
|
||||
libunistring.so.2 => /lib64/libunistring.so.2 (0x00007f761dfc0000)
|
||||
libtasn1.so.6 => /lib64/libtasn1.so.6 (0x00007f761ddad000)
|
||||
libnettle.so.6 => /lib64/libnettle.so.6 (0x00007f761db73000)
|
||||
libhogweed.so.4 => /lib64/libhogweed.so.4 (0x00007f761d943000)
|
||||
libgmp.so.10 => /lib64/libgmp.so.10 (0x00007f761d6ab000)
|
||||
libffi.so.6 => /lib64/libffi.so.6 (0x00007f761d4a2000)
|
||||
|
||||
Examining disk space in the following directories:
|
||||
Current directory: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl
|
||||
Oasys' temp directory: /tmp/oasys.2457552/ (normalized path: /tmp/oasys.2457552)
|
||||
RT_TMP directory: /tmp/oasys.2457552
|
||||
|
||||
Executing: df /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl /tmp/oasys.2457552 /tmp/oasys.2457552
|
||||
Filesystem 1K-blocks Used Available Use% Mounted on
|
||||
/dev/sdc1 10485760 2530136 7955624 25% /users
|
||||
/dev/sda3 25582384 9713924 15868460 38% /
|
||||
/dev/sda3 25582384 9713924 15868460 38% /
|
||||
|
||||
|
||||
---
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
*******************************************************************
|
||||
* Oasys-RTL™ - release 2022.2.R1 *
|
||||
* *
|
||||
* This material contains trade secrets or otherwise confidential *
|
||||
* information owned by Siemens Industry Software Inc. or its *
|
||||
* affiliates (collectively, "SISW"), or its licensors. Access to *
|
||||
* and use of this information is strictly limited as set forth *
|
||||
* in the Customer’s applicable agreements with SISW. *
|
||||
* *
|
||||
* Unpublished work. © 2023 Siemens *
|
||||
* *
|
||||
* Program : ../bin/Linux-x86_64-O/oasysGui *
|
||||
* Version : 22.2-p002 *
|
||||
* Date : Mon Jan 16 21:36:23 PST 2023 *
|
||||
* Build : releases/22.2-54756.0-CentOS_6.5-O *
|
||||
*******************************************************************
|
||||
config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft
|
||||
loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap
|
||||
checked out license: psyncore
|
||||
|
||||
date : Thu May 28 12:01:37 CEST 2026
|
||||
ppid/pid : 2439771/2439781
|
||||
hostname : efiapps0.ads1.fh-nuernberg.de
|
||||
arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64
|
||||
install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1
|
||||
currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl
|
||||
logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.00
|
||||
tmpdir : /tmp/oasys.2439771/
|
||||
> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl
|
||||
File diff suppressed because one or more lines are too long
@@ -0,0 +1,16 @@
|
||||
*******************************************************************
|
||||
* Oasys-RTL™ - release 2022.2.R1 *
|
||||
* *
|
||||
* This material contains trade secrets or otherwise confidential *
|
||||
* information owned by Siemens Industry Software Inc. or its *
|
||||
* affiliates (collectively, "SISW"), or its licensors. Access to *
|
||||
* and use of this information is strictly limited as set forth *
|
||||
* in the Customer’s applicable agreements with SISW. *
|
||||
* *
|
||||
* Unpublished work. © 2023 Siemens *
|
||||
* *
|
||||
* Program : ../bin/Linux-x86_64-O/oasysGui *
|
||||
* Version : 22.2-p002 *
|
||||
* Date : Mon Jan 16 21:36:23 PST 2023 *
|
||||
* Build : releases/22.2-54756.0-CentOS_6.5-O *
|
||||
*******************************************************************
|
||||
@@ -0,0 +1,37 @@
|
||||
// *********************************************************************************************
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
|
||||
// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// 15.Oct.2025 Bomin Kim Moved NextPC logic from decoder into PC
|
||||
// 15.Oct.2025 Bomin Kim Removed reset condition from combinational logic
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
module pc (
|
||||
output logic[31:0] CurrentPC,
|
||||
input logic[31:0] JumpOrBranchPC,
|
||||
input logic JumpOrBranch,
|
||||
output logic[31:0] NextPC,
|
||||
input logic reset,
|
||||
input logic clk
|
||||
);
|
||||
|
||||
// NextPC logic; next-state function
|
||||
always_comb begin : Next_PC
|
||||
if (JumpOrBranch) NextPC = JumpOrBranchPC;
|
||||
else NextPC = CurrentPC + 4;
|
||||
end
|
||||
|
||||
// CurrentPC logic; state register
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) CurrentPC <= '0;
|
||||
else CurrentPC <= NextPC;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,44 @@
|
||||
// *********************************************************************************************
|
||||
// Project Version : v1.0
|
||||
// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog
|
||||
// -----
|
||||
// Copyright (c) : 2025 Fraunhofer IIS, Department IDS
|
||||
// Created : 12.Jun.2025 by Lund University [commit 5b1e415]
|
||||
// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d]
|
||||
// -----
|
||||
// HISTORY : Date By Comments
|
||||
// ----------- --------- -------------------------------------------------
|
||||
// 15.Oct.2025 Bomin Kim Added reset handling condition
|
||||
// *********************************************************************************************
|
||||
|
||||
|
||||
module reg_file (
|
||||
input logic[4:0] Rs1,
|
||||
input logic[4:0] Rs2,
|
||||
input logic[4:0] Rd,
|
||||
output logic[31:0] RRs1,
|
||||
output logic[31:0] RRs2,
|
||||
input logic[31:0] WRd,
|
||||
input logic WrReg,
|
||||
input logic reset,
|
||||
input logic clk
|
||||
);
|
||||
|
||||
// Define the registers array
|
||||
logic[31:0] registers[31:1];
|
||||
|
||||
// Register file reading
|
||||
assign RRs1 = Rs1 == 0 ? '0 : registers[Rs1];
|
||||
assign RRs2 = Rs2 == 0 ? '0 : registers[Rs2];
|
||||
|
||||
// Register file writing
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset) begin
|
||||
for (int i=1; i<32; i++)
|
||||
registers[i] <= '0;
|
||||
end else begin
|
||||
if (WrReg & Rd != 0) registers[Rd] <= WRd;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user