10 lines
224 B
Makefile
10 lines
224 B
Makefile
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artifacts += data.py __pycache__
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CHECK_RESULTS = true
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include ../vhdl.mk
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plot: CHECK_RESULTS = false
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plot: sim
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@echo Plotting resulting signal vs. expected signal ...
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@../../scripts/plot.py ${expected_data} 2> /dev/null
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