FPGA Software bearbeitet

2024-01-09 08:28:30 +01:00
parent 0d1b73e3e0
commit 45ef215901
223 changed files with 10970 additions and 12 deletions
@@ -9,9 +9,9 @@ verilog_srcs = \
    ../../../hardware/system/Twiddle1024_32B.v \

 vhdl_srcs = \
+    ../test_utility.vhd \
    ../../../hardware/system/reg32.vhd \
    ../../../hardware/system/avalon_slave.vhd \
-    ../../hardware/test_data_channel.vhd \
    ../../../hardware/system/avalon_slave_transitions.vhd \
    ../../../hardware/system/task.vhd \
    ../../../hardware/system/hardware_task_control.vhd \
@@ -21,9 +21,9 @@ vhdl_srcs = \
    ../../../hardware/system/fft_magnitude_calc.vhd \
    ../../../hardware/signal_processing/fft.vhd \
    ../../../hardware/system/task_fft.vhd \
-    ../test_utility.vhd \
    ../test_avalon_slave.vhd \
    ../test_hardware_task.vhd \
+    ../../hardware/test_data_channel.vhd \
    ../../data/add_rand.vhd \
    ../../data/sine.vhd \
    ../../data/fft.vhd \