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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/4-bit-counter-SV-UVM/sim/.gitignore

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add SV example
3 years ago
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  1. modelsim.*

  2. transcript* 

  3. vlog.* 

  4. work/

  5. counter_cov* 

  6. fcover* 

  7. covhtml* 

  8. vcover* 

  9. *.log

  10. *.wlf