2021-06-09 11:04:53 +02:00
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###############################################################################
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# Copyright (c) 2013 Potential Ventures Ltd
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# Copyright (c) 2013 SolarFlare Communications Inc
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# * Neither the name of Potential Ventures Ltd,
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# SolarFlare Communications Inc nor the
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# names of its contributors may be used to endorse or promote products
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# derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
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# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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###############################################################################
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TOPLEVEL_LANG ?= verilog
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PWD=$(shell pwd)
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ifeq ($(TOPLEVEL_LANG),verilog)
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2021-06-09 11:15:13 +02:00
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VERILOG_SOURCES = $(PWD)/../hdl/counter.v
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2021-06-09 11:04:53 +02:00
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else ifeq ($(TOPLEVEL_LANG),vhdl)
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VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl
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else
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$(error "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
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endif
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TOPLEVEL := counter
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MODULE := test_counter
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include $(shell cocotb-config --makefiles)/Makefile.sim
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clean::
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rm -rf dump.vcd results.xml
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