47 lines
655 B
Coq
47 lines
655 B
Coq
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// File: counter_4bit.v
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// Generated by MyHDL 0.11
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// Date: Mon Jun 7 19:39:23 2021
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`timescale 1ns/10ps
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module counter_4bit (
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clk,
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rst,
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data,
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updown,
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load,
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data_out
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);
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input clk;
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input rst;
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input [3:0] data;
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input updown;
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input load;
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output [3:0] data_out;
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reg [3:0] data_out;
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always @(posedge clk) begin: COUNTER_4BIT_CYCLE
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if (rst) begin
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data_out <= 0;
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end
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else if (load) begin
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data_out <= data;
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end
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else begin
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if (updown) begin
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data_out <= (data_out + 1);
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end
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else begin
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data_out <= (data_out - 1);
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end
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end
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end
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endmodule
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