47 lines
655 B
Verilog
47 lines
655 B
Verilog
// File: counter_4bit.v
|
|
// Generated by MyHDL 0.11
|
|
// Date: Mon Jun 7 19:39:23 2021
|
|
|
|
|
|
`timescale 1ns/10ps
|
|
|
|
module counter_4bit (
|
|
clk,
|
|
rst,
|
|
data,
|
|
updown,
|
|
load,
|
|
data_out
|
|
);
|
|
|
|
|
|
input clk;
|
|
input rst;
|
|
input [3:0] data;
|
|
input updown;
|
|
input load;
|
|
output [3:0] data_out;
|
|
reg [3:0] data_out;
|
|
|
|
|
|
|
|
|
|
always @(posedge clk) begin: COUNTER_4BIT_CYCLE
|
|
if (rst) begin
|
|
data_out <= 0;
|
|
end
|
|
else if (load) begin
|
|
data_out <= data;
|
|
end
|
|
else begin
|
|
if (updown) begin
|
|
data_out <= (data_out + 1);
|
|
end
|
|
else begin
|
|
data_out <= (data_out - 1);
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|