Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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test_counter.py 2.4KB

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  1. import cocotb
  2. from cocotb.clock import Clock
  3. from cocotb.triggers import Timer, RisingEdge, FallingEdge
  4. import random
  5. @cocotb.test()
  6. async def test_counter_reset(dut):
  7. clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
  8. cocotb.fork(clock.start()) # Start the clock
  9. await RisingEdge(dut.clk)
  10. await RisingEdge(dut.clk)
  11. dut.rst <= 1
  12. await RisingEdge(dut.clk)
  13. await FallingEdge(dut.clk)
  14. cnt = dut.data_out.value.integer # assert counter ouput is 0
  15. assert cnt == 0
  16. await RisingEdge(dut.clk)
  17. await RisingEdge(dut.clk)
  18. @cocotb.test()
  19. async def test_counter_load(dut):
  20. clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
  21. cocotb.fork(clock.start()) # Start the clock
  22. dut.rst <= 0
  23. dut.load <= 1
  24. soll = random.randint(0,15)
  25. dut.data <= soll
  26. await RisingEdge(dut.clk)
  27. await FallingEdge(dut.clk)
  28. assert dut.data_out.value.integer == soll, f"counter value is incorrect: {dut.data_out.value.integer} != {soll}"
  29. @cocotb.test()
  30. async def test_counter_inc(dut):
  31. """Test for count up"""
  32. dut.rst <= 0
  33. dut.load <= 0
  34. dut.updown <= 1
  35. dut.data <= random.randint(0,15)
  36. clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
  37. cocotb.fork(clock.start()) # Start the clock
  38. dut.rst <= 1
  39. await RisingEdge(dut.clk)
  40. await FallingEdge(dut.clk)
  41. dut.rst <= 0
  42. soll = 0
  43. for _ in range(10):
  44. assert dut.data_out.value.integer == soll, f"counter value is incorrect: {dut.data_out.value.integer} != {soll}"
  45. await RisingEdge(dut.clk)
  46. soll += 1
  47. await FallingEdge(dut.clk)
  48. @cocotb.test()
  49. async def test_counter_dec(dut):
  50. """Test for count down"""
  51. dut.rst <= 0
  52. dut.load <= 0
  53. dut.updown <= 0
  54. dut.data <= 14
  55. soll = 14
  56. clock = Clock(dut.clk, 10, units="us") # Create a 10us period clock on port clk
  57. cocotb.fork(clock.start()) # Start the clock
  58. dut.rst <= 1
  59. await RisingEdge(dut.clk)
  60. await FallingEdge(dut.clk)
  61. dut.rst <= 0
  62. dut.load <= 1
  63. await RisingEdge(dut.clk)
  64. await FallingEdge(dut.clk)
  65. dut.load <= 0
  66. for _ in range(10):
  67. assert dut.data_out.value.integer == soll, f"counter value is incorrect: {dut.data_out.value.integer} != {soll}"
  68. await RisingEdge(dut.clk)
  69. soll -= 1
  70. await FallingEdge(dut.clk)