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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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Simon Schmidt 28af588549 added LCD seminararbeit 3 years ago
.vscode changed gitignore 3 years ago
4-bit-counter-SV-UVM add SV example 3 years ago
4-bit-counter-cocotb correct makefile error 3 years ago
4-bit-counter-myhdl changed gitignore 3 years ago
7Segment_Lattice_ice40_UltraPlus added subfolder 3 years ago
LCD_EPD_Simulation_VerilogA added LCD seminararbeit 3 years ago
digitaler-filter-cocotb added and changed gitignores 3 years ago
i2c_slave_opencores added i2c example from VL 3 years ago
LICENSE Initial commit 3 years ago
README.md initial commit 3 years ago

README.md

ESY1B Verifikation mit SystemVerilog und Python

Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema “Verifikation mit SystemVerilog und Python”