schmidtsi76327/ESY1A_B_Seminararbeiten
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schmidtsi76327 28af588549 added LCD seminararbeit
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LCD_EPD_Simulation_VerilogA
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README.md
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README.md

ESY1B Verifikation mit SystemVerilog und Python

Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"

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Description
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
Readme
2 MiB
Languages
Verilog 81.9%
Makefile 6.5%
Python 6.3%
Tcl 3.8%
SystemVerilog 0.8%
Other 0.7%