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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/LCD_EPD_Simulation_VerilogA/epaper/4_1_model/create_plots.tcl

create_plots.tcl 950B
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  1. ############################################################

  2. ## EZwave - Saved Window File

  3. ## Tuesday, June 15, 2021 at 1:05:13 AM CEST

  4. ##

  5. ## Note: This is an auto-generated file.

  6. ##

  7. ## In case of modification, Do not remove this comment

  8. ############################################################

  9. 

  10. onerror {resume}

  11. 

  12. # ===== Open required Database =====

  13. dataset open /users/ads1/schmidtsi76327/linux/esy1a/LCD_EPD_Simulation_VerilogA/epaper/4_1_model/demo.wdb demo

  14. 

  15. # ===== Open the window =====

  16. wave addwindow -x 0  -y 0 -width 767  -height 581 -divider 0.85

  17. 

  18. # ===== Create row #1 =====

  19. add wave  -show TRAN.v -color -16711936 -separator : -terminals  :demo:v_gate

  20. 

  21. 

  22. # ===== Create row #2 =====

  23. add wave  -show TRAN.v -color -256 -separator : -terminals  :demo:v_source

  24. 

  25. 

  26. # ===== Create row #3 =====

  27. add wave  -show TRAN.v -color -16744193 -separator : -terminals  :demo:pixel1:v_cell

  28. 

  29. 

  30. # ====== Create the cursors, markers and measurements =====