schmidtsi76327
/
ESY1A_B_Seminararbeiten
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
11 Commits
1 Branch
Tree: 28af588549
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '28af588549'
${ noResults }
ESY1A_B_Seminararbeiten/LCD_EPD_Simulation_VerilogA/epaper/4_2_rdot_pixel/Makefile

Makefile 388B
Raw Blame History

1234567891011121314151617181920212223 
  1. VA_FILE = demo.va

  2. TOP_LEVEL_MODULE = tb_rdot

  3. 

  4. CMD_FILE = demo.cmd

  5. DO_FILE = run.do

  6. OUT_FILE = demo.wdb

  7. 

  8. 

  9. 

  10. sim:

  11. 	valog $(VA_FILE) 

  12. 	vasim -c -cmd $(CMD_FILE) -do $(DO_FILE) $(TOP_LEVEL_MODULE) 

  13. 

  14. ezwave:

  15. 	ezwave -now -loc 10 10 -width 2400 -height 1200 -tcl create_plots.tcl

  16. 

  17. clean:

  18. 	rm DefaultVlogALib -rf

  19. 	rm *.chi *.log *.id *.reuse *.wdb -rf

  20. 	rm simcommand transcript* dok_code* -rf

  21. 

  22.