Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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demo.va 1.3KB

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  1. // Simulation EPaper Cell
  2. `include "disciplines.vams"
  3. `include "constants.vams"
  4. `include "otft.va"
  5. module myfet(d, g, s);
  6. inout electrical d, g, s;
  7. parameter real kp = 1m;
  8. parameter real vt = 1;
  9. real vgst;
  10. real cur;
  11. analog begin
  12. vgst = V(g,s)-vt;
  13. cur = 0.0;
  14. if (vgst > 0)
  15. if (vgst > V(d,s))
  16. cur = (vgst-0.5*V(d,s))*V(d,s);
  17. else
  18. cur = 0.5*pow(vgst, 2);
  19. I(d,s) <+ kp*cur;
  20. end
  21. endmodule
  22. module rdot_pixel(vs, gate, gnd);
  23. electrical vs, gate, gnd;
  24. electrical con;
  25. myfet FET1(con, gate, gnd);
  26. resistor #(.r(2075)) Rppy(vs, con);
  27. capacitor #(.c(500u)) Cppy(vs, con);
  28. endmodule
  29. module tb_rdot;
  30. electrical src_gate, src_vs, gnd;
  31. ground gnd;
  32. parameter real on_V = 10.0;
  33. parameter real off_V = 0;
  34. parameter real on_T = 2; // 2s on after 1s delay
  35. parameter real off_T = 0;
  36. parameter real startDelay = 1;
  37. // Puls-Quelle
  38. /*prameters expected for 'pulse' are '[dc] [mag [phase]] val0 val1 [td [rise [fall [width [period]]]]] */
  39. vpulse #(.val0(off_V), .val1(on_V), .td(startDelay), .rise(1n), .fall(1n), .width(on_T)) PL(src_gate, gnd);
  40. vdc #(.dc(1.0)) VDC1 (src_vs, gnd);
  41. // Pixel
  42. rdot_pixel pixel1(src_vs, src_gate, gnd);
  43. endmodule