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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/LCD_EPD_Simulation_VerilogA/lcd/reflection_vs_input_voltage.../create_plots.tcl

create_plots.tcl 774B
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  1. ############################################################

  2. ## EZwave - Saved Window File

  3. ## Tuesday, June 15, 2021 at 1:00:12 AM CEST

  4. ##

  5. ## Note: This is an auto-generated file.

  6. ##

  7. ## In case of modification, Do not remove this comment

  8. ############################################################

  9. 

  10. onerror {resume}

  11. 

  12. # ===== Open required Database =====

  13. dataset open /users/ads1/schmidtsi76327/linux/esy1a/LCD_EPD_Simulation_VerilogA/lcd/reflection_vs_input_voltage_lcd_cap/demo.wdb demo

  14. 

  15. # ====== Create the expressions =====

  16. 

  17. 

  18. 

  19. # ===== Open the window =====

  20. wave addwindow -x 0  -y 0 -width 767  -height 558 -divider 0.85

  21. 

  22. # ===== Create row #1 =====

  23. add wave  -versus V(:demo:lcc:(a,b)) VAR(:demo:lcc:trans)

  24. 

  25. 

  26. # ====== Create the cursors, markers and measurements =====