Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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create_plots.tcl 1.0KB

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  1. ############################################################
  2. ## EZwave - Saved Window File
  3. ## Tuesday, June 15, 2021 at 12:44:25 AM CEST
  4. ##
  5. ## Note: This is an auto-generated file.
  6. ##
  7. ## In case of modification, Do not remove this comment
  8. ############################################################
  9. onerror {resume}
  10. # ===== Open required Database =====
  11. dataset open /users/ads1/schmidtsi76327/linux/esy1a/LCD_EPD_Simulation_VerilogA/lcd/transient_response_lcd_cap/demo.wdb demo
  12. # ===== Open the window =====
  13. wave addwindow -x 0 -y 0 -width 1490 -height 1075 -divider 0.82
  14. # ===== Create row #1 =====
  15. add wave -overlay -show TRAN.v -color -16711936 -separator : -terminals :demo:lcc:(a,b) -show TRAN.var -color -256 -separator : -signals :demo:lcc:vcontrol
  16. # ===== Create row #2 =====
  17. add wave -show TRAN.var -color -16744193 -separator : -signals :demo:lcc:cap
  18. # ===== Create row #3 =====
  19. add wave -show TRAN.v -color -32768 -separator : -terminals :demo:gate
  20. # ====== Create the cursors, markers and measurements =====