Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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pwm.v 485B

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  1. //pwm module, outputs a pulse width according to the value written
  2. //max width 255 cycles
  3. module pwm(input clk, input en, input [7:0] value_input, output out);
  4. reg [7:0] counter;
  5. reg [7:0] value; //max 255
  6. assign out = (counter < value);
  7. initial begin
  8. counter = 0;
  9. value = 255;
  10. end
  11. always @(posedge clk)
  12. begin
  13. counter <= counter + 1;
  14. if(en == 1'b1)
  15. value <= value_input;
  16. else
  17. value <= 0;
  18. end
  19. endmodule