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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/7Segment_Lattice_ice40_Ultr...
Simon Schmidt 6a96af7ad2 added subfolder 3 years ago
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bcd_to_7seg.v added subfolder 3 years ago
clocks.v added subfolder 3 years ago
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README.md

7-Segment-Display to show Counter Value

The goal of this example is to display a counter output on a 7-segment connected to the fpga.

For used IOs check out io.pcf.

To Upload use Makefile, Project IceStorm is needed for this to work.

I uploaded with RPI4, look at make rpi_prog