Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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top.v 2.1KB

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  1. `include "digit_driver.v"
  2. `include "pwm.v"
  3. `include "clocks.v"
  4. `include "counter.v"
  5. // A verilog module transforms a 4-bit number into a displayable 7-bit value.
  6. // This number is incremented every ~0.25sec.
  7. module top( input clk,
  8. output LED_R, output LED_G, output LED_B,
  9. output seg_b, output seg_a, output seg_f,
  10. output seg_g, output seg_d, output seg_e,
  11. output seg_c, output seg_p, input [3:0] SW,
  12. output dig_1, output dig_2, output dig_3, output dig_4, output dig_5
  13. );
  14. wire clk_pwm;
  15. wire clk_7seg;
  16. wire clk_counter;
  17. clocks #(.PRE_PWM(28'd12), .PRE_7SEG(28'd12000), .PRE_COUNTER(28'd12000)) clocks_inst
  18. (
  19. .clk(clk),
  20. .clk_pwm(clk_pwm),
  21. .clk_7seg(clk_7seg),
  22. .clk_counter(clk_counter)
  23. );
  24. wire rst;
  25. wire updown;
  26. wire load;
  27. reg [19:0] data = 20'h1337;
  28. wire [19:0] data_out;
  29. assign rst = SW[0];
  30. assign updown = SW[1];
  31. assign load = SW[2];
  32. counter TIM1 (
  33. .clk(clk_counter),
  34. .rst(rst),
  35. .data(data),
  36. .updown(updown),
  37. .load(load),
  38. .data_out(data_out)
  39. );
  40. wire pwm_en_write;
  41. assign pwm_en_write = SW[3];
  42. wire [7:0] pwm_brightness;
  43. reg [7:0] led_brightness;
  44. assign pwm_brightness = led_brightness;
  45. wire pwm_out;
  46. pwm pwm_inst(.clk(clk_pwm), .en(pwm_en_write), .value_input(pwm_brightness), .out(pwm_out));
  47. // active low, color white
  48. assign LED_R = ~pwm_out;
  49. assign LED_G = ~pwm_out;
  50. assign LED_B = ~pwm_out;
  51. wire [19:0] number;
  52. assign number = data_out;
  53. assign dot = rst;
  54. wire [7:0] segs;
  55. assign seg_a = segs[0];
  56. assign seg_b = segs[1];
  57. assign seg_c = segs[2];
  58. assign seg_d = segs[3];
  59. assign seg_e = segs[4];
  60. assign seg_f = segs[5];
  61. assign seg_g = segs[6];
  62. assign seg_p = segs[7];
  63. wire [4:0] digs;
  64. assign dig_1 = digs[0];
  65. assign dig_2 = digs[1];
  66. assign dig_3 = digs[2];
  67. assign dig_4 = digs[3];
  68. assign dig_5 = digs[4];
  69. digit_driver dig_inst(.clk(clk_7seg), .number(number), .dot(dot), .segs(segs), .digs(digs));
  70. initial begin
  71. led_brightness = 10;
  72. end
  73. endmodule