Loesung des Praktikums Systementwurf - Bjarne Hoesch - Bernhard Schoeffel
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sine.vhd 4.2KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. library work;
  5. use work.reg32.all;
  6. use work.float.all;
  7. use work.task.all;
  8. entity sine is
  9. port (
  10. clk : in std_logic;
  11. reset : in std_logic;
  12. task_start : in std_logic;
  13. task_state : out work.task.State;
  14. step_size : in work.reg32.word;
  15. phase : in work.reg32.word;
  16. amplitude : in work.reg32.word;
  17. signal_write : out std_logic;
  18. signal_writedata : out std_logic_vector( 31 downto 0 )
  19. );
  20. end entity sine;
  21. architecture rtl of sine is
  22. signal current_task_state : work.task.State;
  23. signal next_task_state : work.task.State;
  24. signal index : integer range 0 to work.task.STREAM_LEN;
  25. type CalcState is (
  26. CALC_IDLE,
  27. CALC_ANGLE,
  28. CALC_START,
  29. CALC_BUSY,
  30. CALC_WRITE,
  31. CALC_DONE
  32. );
  33. signal Calc_State : CalcState;
  34. signal data_valid_ipcore : std_logic;
  35. signal busy_ipcore : std_logic;
  36. signal result_valid_ipcore : std_logic;
  37. signal angle_ipcore : signed(31 downto 0);
  38. signal step_size_adapted : std_logic_vector( 31 downto 0 );
  39. signal sine_amplitude : signed(31 downto 0);
  40. signal sine_ipcore : signed(31 downto 0);
  41. begin
  42. u_float_sine: entity work.float_sine
  43. generic map(
  44. ITERATIONS => 8
  45. )
  46. port map(
  47. clk => clk,
  48. reset => reset,
  49. data_valid => data_valid_ipcore,
  50. busy => busy_ipcore,
  51. result_valid => result_valid_ipcore,
  52. -- " TODO Check if this is allowed (direkt access to maped signal)"
  53. angle => angle_ipcore,
  54. sine => sine_ipcore
  55. );
  56. task_state_transitions : process ( current_task_state, task_start, index ) is
  57. begin
  58. next_task_state <= current_task_state;
  59. case current_task_state is
  60. when work.task.TASK_IDLE =>
  61. if ( task_start = '1' ) then
  62. next_task_state <= work.task.TASK_RUNNING;
  63. end if;
  64. when work.task.TASK_RUNNING =>
  65. if ( index = work.task.STREAM_LEN ) then
  66. next_task_state <= work.task.TASK_DONE;
  67. end if;
  68. when work.task.TASK_DONE =>
  69. if ( task_start = '1' ) then
  70. next_task_state <= work.task.TASK_RUNNING;
  71. end if;
  72. end case;
  73. end process task_state_transitions;
  74. sync : process ( clk, reset ) is
  75. begin
  76. if ( reset = '1' ) then
  77. current_task_state <= work.task.TASK_IDLE;
  78. Calc_State <= CALC_IDLE;
  79. index <= 0;
  80. signal_write <= '0';
  81. elsif ( rising_edge( clk ) ) then
  82. current_task_state <= next_task_state;
  83. case next_task_state is
  84. when work.task.TASK_IDLE =>
  85. index <= 0;
  86. signal_write <= '0';
  87. Calc_State <= CALC_IDLE;
  88. when work.task.TASK_RUNNING =>
  89. case Calc_State is
  90. when CALC_IDLE =>
  91. angle_ipcore <= SIGNED(phase);
  92. Calc_State <= CALC_START;
  93. when CALC_ANGLE =>
  94. angle_ipcore <= (angle_ipcore + (SIGNED(step_size_adapted)));
  95. Calc_State <= CALC_START;
  96. when CALC_START =>
  97. data_valid_ipcore <= '1';
  98. if(busy_ipcore = '1') then
  99. Calc_State <= CALC_BUSY;
  100. end if;
  101. when CALC_BUSY =>
  102. data_valid_ipcore <= '0';
  103. if(result_valid_ipcore = '1') then
  104. Calc_State <= CALC_WRITE;
  105. end if;
  106. when CALC_WRITE =>
  107. -- sine_amplitude <= sine_ipcore(30 downto 23) + (signed(amplitude))(30 downto 23) - "127";
  108. sine_amplitude <= sine_ipcore(31 downto 31) & (sine_ipcore(30 downto 23) + (signed(amplitude(30 downto 23)) - 127)) & sine_ipcore(22 downto 0);
  109. -- sine_amplitude <= STD_LOGIC_VECTOR(sine_ipcore(30 downto 23)) + STD_LOGIC_VECTOR(amplitude(30 downto 23)) - "127";
  110. signal_write <= '1';
  111. Calc_State <= CALC_DONE;
  112. when CALC_DONE =>
  113. signal_write <= '0';
  114. index <= index + 1;
  115. Calc_State <= CALC_ANGLE;
  116. end case;
  117. when work.task.TASK_DONE =>
  118. index <= 0;
  119. signal_write <= '0';
  120. end case;
  121. end if;
  122. end process sync;
  123. signal_writedata <= STD_LOGIC_VECTOR(sine_amplitude);
  124. --step_size_adapted <= (step_size(31-5 downto 0) & "00000");
  125. step_size_adapted <= (step_size );
  126. task_state <= current_task_state;
  127. -- #TODO phase_ipcore <= (SIGNED(phase));
  128. end architecture rtl;