BlinkProjekt
This commit is contained in:
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################################################################################
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# DONOT REMOVE THIS FILE
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# Unified simulation database file for selected simulation model for IP
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#
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# File: ssm.db (Wed Mar 16 19:55:41 2022)
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#
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# This file is generated by the unified simulation automation and contains the
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# selected simulation model information for the IP/BD instances.
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||||
# DONOT REMOVE THIS FILE
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||||
################################################################################
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||||
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||||
<document>
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||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
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||||
The structure and the elements are likely to change over the next few releases.
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||||
This means code written to parse this file will need to be revisited each subsequent release.-->
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
<!-- Product Version: Vivado v2021.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
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||||
|
||||
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|
||||
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||||
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|
||||
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|
||||
<!-- -->
|
||||
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|
||||
|
||||
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|
||||
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||||
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||||
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||||
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||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
<Parent Id="synth_1"/>
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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<Run Id="impl_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
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var ISELogFile = "runme.log";
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var ISELogFileStr = null;
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var ISELogEcho = true;
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var ISEOldVersionWSH = false;
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|
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|
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|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
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||||
// ISE FUNCTIONS
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function ISEInit() {
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||||
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// 1. RUN DIR setup
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var ISEScrFP = WScript.ScriptFullName;
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var ISEScrN = WScript.ScriptName;
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ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7z010clg400-1" LaunchTime="1648199473">
|
||||
<File Type="OPT-HWDEF" Name="pwm_test.hwdef"/>
|
||||
<File Type="ROUTE-BUS-SKEW" Name="pwm_test_bus_skew_routed.rpt"/>
|
||||
<File Type="PA-DCP" Name="pwm_test.dcp"/>
|
||||
<File Type="ROUTE-PWR" Name="pwm_test_power_routed.rpt"/>
|
||||
<File Type="PA-TCL" Name="pwm_test.tcl"/>
|
||||
<File Type="BITSTR-MMI" Name="pwm_test.mmi"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="pwm_test_methodology_drc_opted.rpt"/>
|
||||
<File Type="INIT-TIMING" Name="pwm_test_timing_summary_init.rpt"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="pwm_test_power_summary_routed.pb"/>
|
||||
<File Type="REPORTS-TCL" Name="pwm_test_reports.tcl"/>
|
||||
<File Type="OPT-TIMING" Name="pwm_test_timing_summary_opted.rpt"/>
|
||||
<File Type="OPT-DCP" Name="pwm_test_opt.dcp"/>
|
||||
<File Type="OPT-DRC" Name="pwm_test_drc_opted.rpt"/>
|
||||
<File Type="PWROPT-DCP" Name="pwm_test_pwropt.dcp"/>
|
||||
<File Type="PWROPT-DRC" Name="pwm_test_drc_pwropted.rpt"/>
|
||||
<File Type="PWROPT-TIMING" Name="pwm_test_timing_summary_pwropted.rpt"/>
|
||||
<File Type="PLACE-DCP" Name="pwm_test_placed.dcp"/>
|
||||
<File Type="PLACE-IO" Name="pwm_test_io_placed.rpt"/>
|
||||
<File Type="PLACE-CLK" Name="pwm_test_clock_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL" Name="pwm_test_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="pwm_test_utilization_placed.pb"/>
|
||||
<File Type="PLACE-CTRL" Name="pwm_test_control_sets_placed.rpt"/>
|
||||
<File Type="PLACE-SIMILARITY" Name="pwm_test_incremental_reuse_placed.rpt"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="pwm_test_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="BG-BIN" Name="pwm_test.bin"/>
|
||||
<File Type="PLACE-TIMING" Name="pwm_test_timing_summary_placed.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="pwm_test_postplace_pwropt.dcp"/>
|
||||
<File Type="BITSTR-MSK" Name="pwm_test.msk"/>
|
||||
<File Type="POSTPLACE-PWROPT-TIMING" Name="pwm_test_timing_summary_postplace_pwropted.rpt"/>
|
||||
<File Type="PHYSOPT-DCP" Name="pwm_test_physopt.dcp"/>
|
||||
<File Type="PHYSOPT-DRC" Name="pwm_test_drc_physopted.rpt"/>
|
||||
<File Type="BITSTR-RBT" Name="pwm_test.rbt"/>
|
||||
<File Type="PHYSOPT-TIMING" Name="pwm_test_timing_summary_physopted.rpt"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="pwm_test_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="pwm_test_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="pwm_test_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DRC" Name="pwm_test_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="pwm_test_drc_routed.pb"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="pwm_test_drc_routed.rpx"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="pwm_test_methodology_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="pwm_test_methodology_drc_routed.rpx"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="pwm_test_methodology_drc_routed.pb"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="pwm_test_power_routed.rpx"/>
|
||||
<File Type="ROUTE-STATUS" Name="pwm_test_route_status.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="pwm_test_route_status.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="pwm_test_timing_summary_routed.rpt"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="pwm_test_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="pwm_test_timing_summary_routed.rpx"/>
|
||||
<File Type="ROUTE-SIMILARITY" Name="pwm_test_incremental_reuse_routed.rpt"/>
|
||||
<File Type="ROUTE-CLK" Name="pwm_test_clock_utilization_routed.rpt"/>
|
||||
<File Type="ROUTE-BUS-SKEW-PB" Name="pwm_test_bus_skew_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW-RPX" Name="pwm_test_bus_skew_routed.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="pwm_test_postroute_physopt.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="pwm_test_postroute_physopt_bb.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="pwm_test_timing_summary_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="pwm_test_timing_summary_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="pwm_test_timing_summary_postroute_physopted.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="pwm_test_bus_skew_postroute_physopted.rpt"/>
|
||||
<File Type="BG-BIT" Name="pwm_test.bit"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="pwm_test_bus_skew_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="pwm_test_bus_skew_postroute_physopted.rpx"/>
|
||||
<File Type="BITSTR-NKY" Name="pwm_test.nky"/>
|
||||
<File Type="BITSTR-BMM" Name="pwm_test_bd.bmm"/>
|
||||
<File Type="PDI-FILE" Name="pwm_test.pdi"/>
|
||||
<File Type="RCFI_FILE" Name="pwm_test.rcfi"/>
|
||||
<File Type="CFI_FILE" Name="pwm_test.cfi"/>
|
||||
<File Type="RNPI_FILE" Name="pwm_test.rnpi"/>
|
||||
<File Type="NPI_FILE" Name="pwm_test.npi"/>
|
||||
<File Type="RBD_FILE" Name="pwm_test.rbd"/>
|
||||
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
|
||||
<File Type="BITSTR-LTX" Name="pwm_test.ltx"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="pwm_test.sysdef"/>
|
||||
<File Type="BG-BGN" Name="pwm_test.bgn"/>
|
||||
<File Type="BG-DRC" Name="pwm_test.drc"/>
|
||||
<File Type="RDI-RDI" Name="pwm_test.vdi"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/pwm_test.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="pwm_test"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PPRDIR/../Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<File Path="$PSRCDIR/utils_1/imports/synth_1/pwm_test.dcp">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedInSteps" Val="synth_1"/>
|
||||
<Attr Name="AutoDcp" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,67 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3434:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726f75746573:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6c6576656c:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d696e5f6c6576656c:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d63656c6c73:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d626f756e64696e675f626f786573:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66696c65:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617070656e64:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72657475726e5f737472696e67:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6d706c6578697479:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66756c6c5f6c6f676963616c5f70696e:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73756767657374696f6e:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d716f725f73756d6d617279:5b7370656369666965645d:00:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657874726163745f6d657472696373:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70706c6f635f64697374616e6365:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e67657374696f6e:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d74696d696e67:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6f665f74696d696e675f7061746873:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657874656e64:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7061746873:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365747570:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d686f6c64:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c6f6769635f6c6576656c5f646973747269627574696f6e:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c6f6769635f6c6576656c5f646973745f7061746873:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d656e645f706f696e745f636c6f636b73:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6c6f6769635f6c6576656c73:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726f757465645f76735f657374696d61746564:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f686561646572:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72657475726e5f74696d696e675f7061746873:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d68696572617263686963616c5f6465707468:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7175696574:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572626f7365:64656661756c74:5b6e6f745f7370656369666965645d:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73686f775f616c6c5f636f6e67657374696f6e5f77696e646f7773:64656661756c74:66616c7365:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d696e5f636f6e67657374696f6e5f6c6576656c:64656661756c74:35:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c7573616765:72756e74696d65:302e3030382073656373:00:00
|
||||
7265706f72745f64657369676e5f616e616c79736973:7265706f72745f64657369676e5f616e616c797369735c75736167655f636f756e74:716f725f73756d6d617279:31:00:00
|
||||
eof:1226783488
|
||||
Binary file not shown.
@@ -0,0 +1,311 @@
|
||||
#
|
||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
namespace eval ::optrace {
|
||||
variable script "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.tcl"
|
||||
variable category "vivado_impl"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
|
||||
}
|
||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
|
||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
|
||||
set host $::env(HOSTNAME)
|
||||
} elseif { [info exist ::env(HOST)] } {
|
||||
set host $::env(HOST)
|
||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
|
||||
set host $::env(COMPUTERNAME)
|
||||
}
|
||||
}
|
||||
set ch [open $beginFile w]
|
||||
puts $ch "<?xml version=\"1.0\"?>"
|
||||
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
|
||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
|
||||
puts $ch " </Process>"
|
||||
puts $ch "</ProcessHandle>"
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc end_step { step } {
|
||||
set endFile ".$step.end.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
OPTRACE "impl_1" END { }
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "impl_1" START { ROLLUP_1 }
|
||||
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
set rc [catch {
|
||||
create_msg_db init_design.pb
|
||||
set_param chipscope.maxJobs 3
|
||||
reset_param project.defaultXPMLibraries
|
||||
open_checkpoint C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
|
||||
set_property webtalk.parent_dir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr [current_project]
|
||||
set_property ip_output_repo C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "init_design_reports" START { REPORT }
|
||||
OPTRACE "init_design_reports" END { }
|
||||
OPTRACE "init_design_write_hwdef" START { }
|
||||
OPTRACE "init_design_write_hwdef" END { }
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed init_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step init_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Init Design" END { }
|
||||
OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
|
||||
start_step opt_design
|
||||
set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
OPTRACE "read constraints: opt_design" START { }
|
||||
OPTRACE "read constraints: opt_design" END { }
|
||||
OPTRACE "opt_design" START { }
|
||||
opt_design
|
||||
OPTRACE "opt_design" END { }
|
||||
OPTRACE "read constraints: opt_design_post" START { }
|
||||
OPTRACE "read constraints: opt_design_post" END { }
|
||||
OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force pwm_test_opt.dcp
|
||||
OPTRACE "Opt Design: write_checkpoint" END { }
|
||||
OPTRACE "opt_design reports" START { REPORT }
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx"
|
||||
OPTRACE "opt_design reports" END { }
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Opt Design" END { }
|
||||
OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
|
||||
start_step place_design
|
||||
set ACTIVE_STEP place_design
|
||||
set rc [catch {
|
||||
create_msg_db place_design.pb
|
||||
OPTRACE "read constraints: place_design" START { }
|
||||
OPTRACE "read constraints: place_design" END { }
|
||||
if { [llength [get_debug_cores -quiet] ] > 0 } {
|
||||
OPTRACE "implement_debug_core" START { }
|
||||
implement_debug_core
|
||||
OPTRACE "implement_debug_core" END { }
|
||||
}
|
||||
OPTRACE "place_design" START { }
|
||||
place_design
|
||||
OPTRACE "place_design" END { }
|
||||
OPTRACE "read constraints: place_design_post" START { }
|
||||
OPTRACE "read constraints: place_design_post" END { }
|
||||
OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force pwm_test_placed.dcp
|
||||
OPTRACE "Place Design: write_checkpoint" END { }
|
||||
OPTRACE "place_design reports" START { REPORT }
|
||||
create_report "impl_1_place_report_io_0" "report_io -file pwm_test_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file pwm_test_control_sets_placed.rpt"
|
||||
OPTRACE "place_design reports" END { }
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed place_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step place_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Place Design" END { }
|
||||
OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
|
||||
start_step phys_opt_design
|
||||
set ACTIVE_STEP phys_opt_design
|
||||
set rc [catch {
|
||||
create_msg_db phys_opt_design.pb
|
||||
OPTRACE "read constraints: phys_opt_design" START { }
|
||||
OPTRACE "read constraints: phys_opt_design" END { }
|
||||
OPTRACE "phys_opt_design" START { }
|
||||
phys_opt_design
|
||||
OPTRACE "phys_opt_design" END { }
|
||||
OPTRACE "read constraints: phys_opt_design_post" START { }
|
||||
OPTRACE "read constraints: phys_opt_design_post" END { }
|
||||
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force pwm_test_physopt.dcp
|
||||
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
|
||||
OPTRACE "phys_opt_design report" START { REPORT }
|
||||
OPTRACE "phys_opt_design report" END { }
|
||||
close_msg_db -file phys_opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed phys_opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step phys_opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Physical Opt Design" END { }
|
||||
OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
|
||||
start_step route_design
|
||||
set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
OPTRACE "read constraints: route_design" START { }
|
||||
OPTRACE "read constraints: route_design" END { }
|
||||
OPTRACE "route_design" START { }
|
||||
route_design
|
||||
OPTRACE "route_design" END { }
|
||||
OPTRACE "read constraints: route_design_post" START { }
|
||||
OPTRACE "read constraints: route_design_post" END { }
|
||||
OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force pwm_test_routed.dcp
|
||||
OPTRACE "Route Design: write_checkpoint" END { }
|
||||
OPTRACE "route_design reports" START { REPORT }
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file pwm_test_route_status.rpt -pb pwm_test_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file pwm_test_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file pwm_test_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx"
|
||||
OPTRACE "route_design reports" END { }
|
||||
OPTRACE "route_design misc" START { }
|
||||
close_msg_db -file route_design.pb
|
||||
OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
|
||||
OPTRACE "route_design write_checkpoint" END { }
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
write_checkpoint -force pwm_test_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "route_design misc" END { }
|
||||
OPTRACE "Phase: Route Design" END { }
|
||||
OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
|
||||
OPTRACE "write_bitstream setup" START { }
|
||||
start_step write_bitstream
|
||||
set ACTIVE_STEP write_bitstream
|
||||
set rc [catch {
|
||||
create_msg_db write_bitstream.pb
|
||||
OPTRACE "read constraints: write_bitstream" START { }
|
||||
OPTRACE "read constraints: write_bitstream" END { }
|
||||
catch { write_mem_info -force -no_partial_mmi pwm_test.mmi }
|
||||
OPTRACE "write_bitstream setup" END { }
|
||||
OPTRACE "write_bitstream" START { }
|
||||
write_bitstream -force pwm_test.bit
|
||||
OPTRACE "write_bitstream" END { }
|
||||
OPTRACE "write_bitstream misc" START { }
|
||||
OPTRACE "read constraints: write_bitstream_post" START { }
|
||||
OPTRACE "read constraints: write_bitstream_post" END { }
|
||||
catch {write_debug_probes -quiet -force pwm_test}
|
||||
catch {file copy -force pwm_test.ltx debug_nets.ltx}
|
||||
close_msg_db -file write_bitstream.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed write_bitstream
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step write_bitstream
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "write_bitstream misc" END { }
|
||||
OPTRACE "Phase: Write Bitstream" END { }
|
||||
OPTRACE "impl_1" END { }
|
||||
@@ -0,0 +1,556 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2021.2 (64-bit)
|
||||
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
# Start of session at: Fri Mar 25 10:11:21 2022
|
||||
# Process ID: 10536
|
||||
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1
|
||||
# Command line: vivado.exe -log pwm_test.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
|
||||
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.vdi
|
||||
# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1\vivado.jou
|
||||
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
|
||||
#-----------------------------------------------------------
|
||||
source pwm_test.tcl -notrace
|
||||
Command: open_checkpoint C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
|
||||
|
||||
Starting open_checkpoint Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1262.352 ; gain = 1.801
|
||||
CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
|
||||
CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1266.320 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2021.2
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
||||
INFO: [Timing 38-479] Binary timing data restore complete.
|
||||
INFO: [Project 1-856] Restoring constraints from binary archive.
|
||||
INFO: [Project 1-853] Binary constraint restore complete.
|
||||
Reading XDEF placement.
|
||||
Reading placer database...
|
||||
Reading XDEF routing.
|
||||
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
|
||||
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
|
||||
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1357.309 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
|
||||
open_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1357.309 ; gain = 104.965
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1365.902 ; gain = 8.594
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: 1c056137f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1441.777 ; gain = 75.875
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1c056137f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1c056137f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
||||
Phase 5 Shift Register Optimization | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 0 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
28 Infos, 0 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1726.871 ; gain = 369.562
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
|
||||
Command: report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 13ba8a4a3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bc17a400
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.164 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.170 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Update Timing before SLR Path Opt
|
||||
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2.3 Post-Processing in Floorplanning
|
||||
Phase 2.3 Post-Processing in Floorplanning | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.179 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2.4 Global Placement Core
|
||||
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
|
||||
Phase 2.4 Global Placement Core | Checksum: 12ed945d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 12ed945d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.661 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 12ed945d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.664 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.677 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.720 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.725 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.727 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion
|
||||
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
||||
____________________________________________________
|
||||
| | Global Congestion | Short Congestion |
|
||||
| Direction | Region Size | Region Size |
|
||||
|___________|___________________|___________________|
|
||||
| North| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| South| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| East| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| West| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 4.3 Placer Reporting | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.750 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: deb5d7c7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
47 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file pwm_test_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file pwm_test_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Command: phys_opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
55 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
phys_opt_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_physopt.dcp' has been generated.
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Checksum: PlaceDB: 584981bf ConstDB: 0 ShapeSum: 866c5608 RouteDB: 0
|
||||
Post Restoration Checksum: NetGraph: 32e9d585 NumContArr: cff0ca0e Constraints: 0 Timing: 0
|
||||
Phase 1 Build RT Design | Checksum: 102da9f93
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1799.160 ; gain = 26.402
|
||||
|
||||
Phase 2 Router Initialization
|
||||
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: 102da9f93
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: 102da9f93
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0 %
|
||||
Global Horizontal Routing Utilization = 0 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 48
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 48
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 2 Router Initialization | Checksum: a88dbed9
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 3 Initial Routing
|
||||
|
||||
Phase 3.1 Global Routing
|
||||
Phase 3.1 Global Routing | Checksum: a88dbed9
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
Phase 3 Initial Routing | Checksum: 105c3e9d5
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 4.1 Global Iteration 0 | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
Phase 4 Rip-up And Reroute | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
Phase 5 Delay and Skew Optimization | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
Phase 6.1 Hold Fix Iter | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
Phase 6 Post Hold Fix | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0115428 %
|
||||
Global Horizontal Routing Utilization = 0.0284926 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
|
||||
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
------------------------------
|
||||
Direction: North
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: South
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: East
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: West
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 8d29afef
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
65 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 44.613
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1820.504 ; gain = 9.816
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
|
||||
Command: report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
|
||||
Command: report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
|
||||
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
77 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file pwm_test_route_status.rpt -pb pwm_test_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file pwm_test_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file pwm_test_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
Command: write_bitstream -force pwm_test.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./pwm_test.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
12 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 2293.621 ; gain = 439.371
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:12:18 2022...
|
||||
Binary file not shown.
@@ -0,0 +1,15 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:12:09 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx
|
||||
| Design : pwm_test
|
||||
| Device : 7z010-clg400
|
||||
| Speed File : -1 PRODUCTION 1.12 2019-11-22
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Bus Skew Report
|
||||
|
||||
No bus skew constraints
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,142 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:12:09 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_clock_utilization -file pwm_test_clock_utilization_routed.rpt
|
||||
| Design : pwm_test
|
||||
| Device : 7z010-clg400
|
||||
| Speed File : -1 PRODUCTION 1.12 2019-11-22
|
||||
| Design State : Routed
|
||||
--------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 48 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 8 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 4 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 8 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 2 | 0 | 0 | 0 |
|
||||
| PLL | 0 | 2 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 32 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
|
||||
| src0 | g0 | IBUF/O | IOB_X0Y74 | IOB_X0Y74 | X1Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF |
|
||||
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
| X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
|
||||
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 32 | 1100 | 32 | 350 | 0 | 40 | 0 | 20 | 0 | 20 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y1 | 0 | 1 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
|
||||
| g0 | BUFG/O | n/a | | | | 32 | 0 | 0 | 0 | clk_IBUF_BUFG |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+----+-----+-----------------------+
|
||||
| | X0 | X1 | HORIZONTAL PROG DELAY |
|
||||
+----+----+-----+-----------------------+
|
||||
| Y1 | 0 | 32 | 0 |
|
||||
| Y0 | 0 | 0 | - |
|
||||
+----+----+-----+-----------------------+
|
||||
|
||||
|
||||
7. Clock Region Cell Placement per Global Clock: Region X1Y1
|
||||
------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
|
||||
| g0 | n/a | BUFG/O | None | 32 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+---------------+
|
||||
* Clock Loads column represents the clock pin loads (pin count)
|
||||
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of BUFG Primitives
|
||||
set_property LOC BUFGCTRL_X0Y16 [get_cells clk_IBUF_BUFG_inst]
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
set_property LOC IOB_X0Y74 [get_ports clk]
|
||||
|
||||
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_clk_IBUF_BUFG}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
|
||||
#endgroup
|
||||
@@ -0,0 +1,80 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:11:52 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_control_sets -verbose -file pwm_test_control_sets_placed.rpt
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010
|
||||
-------------------------------------------------------------------------------------
|
||||
|
||||
Control Set Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. Histogram
|
||||
3. Flip-Flop Distribution
|
||||
4. Detailed Control Set Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Total control sets | 2 |
|
||||
| Minimum number of control sets | 2 |
|
||||
| Addition due to synthesis replication | 0 |
|
||||
| Addition due to physical synthesis replication | 0 |
|
||||
| Unused register locations in slices containing registers | 7 |
|
||||
+----------------------------------------------------------+-------+
|
||||
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
|
||||
** Run report_qor_suggestions for automated merging and remapping suggestions
|
||||
|
||||
|
||||
2. Histogram
|
||||
------------
|
||||
|
||||
+--------------------+-------+
|
||||
| Fanout | Count |
|
||||
+--------------------+-------+
|
||||
| Total control sets | 2 |
|
||||
| >= 0 to < 4 | 1 |
|
||||
| >= 4 to < 6 | 0 |
|
||||
| >= 6 to < 8 | 0 |
|
||||
| >= 8 to < 10 | 0 |
|
||||
| >= 10 to < 12 | 0 |
|
||||
| >= 12 to < 14 | 0 |
|
||||
| >= 14 to < 16 | 0 |
|
||||
| >= 16 | 1 |
|
||||
+--------------------+-------+
|
||||
* Control sets can be remapped at either synth_design or opt_design
|
||||
|
||||
|
||||
3. Flip-Flop Distribution
|
||||
-------------------------
|
||||
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 0 | 0 |
|
||||
| No | No | Yes | 32 | 8 |
|
||||
| No | Yes | No | 1 | 1 |
|
||||
| Yes | No | No | 0 | 0 |
|
||||
| Yes | No | Yes | 0 | 0 |
|
||||
| Yes | Yes | No | 0 | 0 |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
|
||||
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+------------------+---------------+------------------+------------------+----------------+--------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
|
||||
+------------------+---------------+------------------+------------------+----------------+--------------+
|
||||
| led_reg_i_1_n_0 | | led_reg_i_2_n_0 | 1 | 1 | 1.00 |
|
||||
| clk_IBUF_BUFG | | led_reg_i_2_n_0 | 8 | 32 | 4.00 |
|
||||
+------------------+---------------+------------------+------------------+----------------+--------------+
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,41 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:11:50 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010clg400-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: checkpoint_pwm_test
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+--------+----------+--------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+--------+----------+--------------------+------------+
|
||||
| ZPS7-1 | Warning | PS7 block required | 1 |
|
||||
+--------+----------+--------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
ZPS7-1#1 Warning
|
||||
PS7 block required
|
||||
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,41 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:12:07 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010clg400-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: checkpoint_pwm_test
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+--------+----------+--------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+--------+----------+--------------------+------------+
|
||||
| ZPS7-1 | Warning | PS7 block required | 1 |
|
||||
+--------+----------+--------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
ZPS7-1#1 Warning
|
||||
PS7 block required
|
||||
The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,442 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:11:52 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_io -file pwm_test_io_placed.rpt
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010
|
||||
| Speed File : -1
|
||||
| Package : clg400
|
||||
| Package Version : FINAL 2012-10-23
|
||||
| Package Pin Delay Version : VERS. 2.0 2012-10-23
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 2 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| A4 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A5 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A6 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A7 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A9 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A10 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A11 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| A14 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A15 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A16 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A17 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A19 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| A20 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B4 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B5 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| B7 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B8 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B9 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B10 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B12 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B14 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B15 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B16 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| B17 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B18 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| B19 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B20 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C1 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C3 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C5 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C6 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C7 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C8 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C11 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C12 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C13 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C15 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C16 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C17 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C18 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| C19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| C20 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| D3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| D8 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D9 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| D13 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D15 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D16 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D18 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D19 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D20 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E3 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| E6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | | | |
|
||||
| E8 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E9 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E11 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E12 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E14 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E15 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| E16 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| E17 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E19 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F1 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F5 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| F9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| F10 | | | RSVDGND | GND | | | | | | | | | | | | | | | |
|
||||
| F11 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| F12 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F14 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F15 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| F16 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| F19 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F20 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| G2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| G3 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| G4 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| G5 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| G6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| G7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| G8 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | |
|
||||
| G9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| G14 | led | High Range | IO_0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| G15 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G17 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G18 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G19 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G20 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| H2 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| H3 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| H4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| H5 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| H6 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H14 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| H15 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H16 | clk | High Range | IO_L13P_T2_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
|
||||
| H17 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H18 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H20 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J1 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| J4 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| J5 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| J6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| J7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J9 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| J10 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| J11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J14 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J15 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J16 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J17 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| J18 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J20 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K1 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| K2 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| K3 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| K4 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| K9 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| K10 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K14 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K16 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K17 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K18 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K19 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| L1 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| L2 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| L3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| L4 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| L5 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| L6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| L7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L9 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| L10 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L14 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L15 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L16 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L17 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L19 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| L20 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M2 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| M3 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| M4 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| M5 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| M6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M8 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| M9 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| M10 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M14 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M15 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
|
||||
| M17 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M19 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| M20 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| N1 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| N2 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| N3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| N4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| N6 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | |
|
||||
| N7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N15 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| N16 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| N17 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N18 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| N19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
|
||||
| N20 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| P2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| P3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| P4 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| P5 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| P6 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P14 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P15 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P19 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| P20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| R2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| R3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| R4 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| R5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| R6 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | |
|
||||
| R7 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| R10 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R14 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
|
||||
| R16 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R19 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| T2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T4 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| T5 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| T6 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | |
|
||||
| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T8 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| T9 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| T10 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T14 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T15 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T16 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T17 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T18 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
|
||||
| T19 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T20 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| U2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| U3 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| U4 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| U5 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U7 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U8 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U9 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| U11 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| U12 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U13 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U14 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U15 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U17 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U20 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V1 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| V2 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| V3 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| V4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| V5 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V6 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V7 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V8 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| V12 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V13 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
|
||||
| V15 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V16 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V17 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V18 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V20 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| W4 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| W5 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| W6 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W7 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| W8 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W9 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W10 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W13 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W14 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W15 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W16 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
|
||||
| W18 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W20 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y1 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| Y2 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| Y3 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| Y4 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y6 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y7 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y8 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y9 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y10 | | Dedicated | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| Y11 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y12 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y13 | | | NC | Not Connected | | | | | | | | | | | | | | | |
|
||||
| Y14 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y16 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y17 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y18 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y19 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
|
||||
+------------+-------------+------------+-------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,201 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:12:08 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010clg400-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: checkpoint_pwm_test
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 33
|
||||
+-----------+------------------+-----------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+------------------+-----------------------------+------------+
|
||||
| TIMING-17 | Critical Warning | Non-clocked sequential cell | 32 |
|
||||
| TIMING-20 | Warning | Non-clocked latch | 1 |
|
||||
+-----------+------------------+-----------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
TIMING-17#1 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[0]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#2 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[10]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#3 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[11]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#4 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[12]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#5 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[13]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#6 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[14]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#7 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[15]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#8 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[16]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#9 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[17]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#10 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[18]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#11 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[19]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#12 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[1]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#13 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[20]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#14 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[21]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#15 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[22]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#16 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[23]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#17 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[24]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#18 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[25]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#19 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[26]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#20 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[27]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#21 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[28]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#22 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[29]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#23 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[2]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#24 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[30]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#25 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[31]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#26 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[3]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#27 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[4]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#28 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[5]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#29 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[6]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#30 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[7]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#31 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[8]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-17#32 Critical Warning
|
||||
Non-clocked sequential cell
|
||||
The clock pin count_reg[9]/C is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#1 Warning
|
||||
Non-clocked latch
|
||||
The latch led_reg cannot be properly analyzed as its control pin led_reg/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,151 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:12:09 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010clg400-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.485 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.391 |
|
||||
| Device Static (W) | 0.094 |
|
||||
| Effective TJA (C/W) | 11.5 |
|
||||
| Max Ambient (C) | 79.4 |
|
||||
| Junction Temperature (C) | 30.6 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
| Slice Logic | 0.201 | 105 | --- | --- |
|
||||
| LUT as Logic | 0.157 | 33 | 17600 | 0.19 |
|
||||
| CARRY4 | 0.025 | 16 | 4400 | 0.36 |
|
||||
| Register | 0.013 | 33 | 35200 | 0.09 |
|
||||
| BUFG | 0.006 | 1 | 32 | 3.13 |
|
||||
| Others | 0.000 | 3 | --- | --- |
|
||||
| Signals | 0.186 | 50 | --- | --- |
|
||||
| I/O | 0.004 | 2 | 100 | 2.00 |
|
||||
| Static Power | 0.094 | | | |
|
||||
| Total | 0.485 | | | |
|
||||
+----------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.395 | 0.391 | 0.004 | NA | Unspecified | NA |
|
||||
| Vccaux | 1.800 | 0.006 | 0.000 | 0.006 | NA | Unspecified | NA |
|
||||
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccpint | 1.000 | 0.019 | 0.000 | 0.019 | NA | Unspecified | NA |
|
||||
| Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | NA | Unspecified | NA |
|
||||
| Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | NA | Unspecified | NA |
|
||||
| Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 11.5 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | none |
|
||||
| ThetaSA (C/W) | 0.0 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 8to11 (8 to 11 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------+--------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------+--------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+----------+-----------+
|
||||
| Name | Power (W) |
|
||||
+----------+-----------+
|
||||
| pwm_test | 0.391 |
|
||||
+----------+-----------+
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,11 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 138 :
|
||||
# of nets not needing routing.......... : 86 :
|
||||
# of internally routed nets........ : 86 :
|
||||
# of routable nets..................... : 52 :
|
||||
# of fully routed nets............. : 52 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,2 @@
|
||||
|
||||
2012.4’)Timing analysis from Implemented netlist.
|
||||
@@ -0,0 +1,808 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:12:09 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation
|
||||
| Design : pwm_test
|
||||
| Device : 7z010-clg400
|
||||
| Speed File : -1 PRODUCTION 1.12 2019-11-22
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Timing Summary Report
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Timer Settings
|
||||
| --------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Enable Multi Corner Analysis : Yes
|
||||
Enable Pessimism Removal : Yes
|
||||
Pessimism Removal Resolution : Nearest Common Node
|
||||
Enable Input Delay Default Clock : No
|
||||
Enable Preset / Clear Arcs : No
|
||||
Disable Flight Delays : No
|
||||
Ignore I/O Paths : No
|
||||
Timing Early Launch at Borrowing Latches : No
|
||||
Borrow Time for Max Delay Exceptions : Yes
|
||||
Merge Timing Exceptions : Yes
|
||||
|
||||
Corner Analyze Analyze
|
||||
Name Max Paths Min Paths
|
||||
------ --------- ---------
|
||||
Slow Yes Yes
|
||||
Fast Yes Yes
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Report Methodology
|
||||
| ------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Rule Severity Description Violations
|
||||
--------- ---------------- --------------------------- ----------
|
||||
TIMING-17 Critical Warning Non-clocked sequential cell 32
|
||||
TIMING-20 Warning Non-clocked latch 1
|
||||
|
||||
Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
|
||||
|
||||
|
||||
|
||||
check_timing report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. checking no_clock (64)
|
||||
2. checking constant_clock (0)
|
||||
3. checking pulse_width_clock (0)
|
||||
4. checking unconstrained_internal_endpoints (66)
|
||||
5. checking no_input_delay (0)
|
||||
6. checking no_output_delay (1)
|
||||
7. checking multiple_clock (0)
|
||||
8. checking generated_clocks (0)
|
||||
9. checking loops (0)
|
||||
10. checking partial_input_delay (0)
|
||||
11. checking partial_output_delay (0)
|
||||
12. checking latch_loops (0)
|
||||
|
||||
1. checking no_clock (64)
|
||||
-------------------------
|
||||
There are 32 register/latch pins with no clock driven by root clock pin: clk (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[0]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[10]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[11]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[12]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[13]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[14]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[15]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[16]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[17]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[18]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[19]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[1]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[20]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[21]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[22]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[23]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[24]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[25]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[26]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[27]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[28]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[29]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[2]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[30]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[31]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[3]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[4]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[5]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[6]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[7]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[8]/Q (HIGH)
|
||||
|
||||
There is 1 register/latch pin with no clock driven by root clock pin: count_reg[9]/Q (HIGH)
|
||||
|
||||
|
||||
2. checking constant_clock (0)
|
||||
------------------------------
|
||||
There are 0 register/latch pins with constant_clock.
|
||||
|
||||
|
||||
3. checking pulse_width_clock (0)
|
||||
---------------------------------
|
||||
There are 0 register/latch pins which need pulse_width check
|
||||
|
||||
|
||||
4. checking unconstrained_internal_endpoints (66)
|
||||
-------------------------------------------------
|
||||
There are 66 pins that are not constrained for maximum delay. (HIGH)
|
||||
|
||||
There are 0 pins that are not constrained for maximum delay due to constant clock.
|
||||
|
||||
|
||||
5. checking no_input_delay (0)
|
||||
------------------------------
|
||||
There are 0 input ports with no input delay specified.
|
||||
|
||||
There are 0 input ports with no input delay but user has a false path constraint.
|
||||
|
||||
|
||||
6. checking no_output_delay (1)
|
||||
-------------------------------
|
||||
There is 1 port with no output delay specified. (HIGH)
|
||||
|
||||
There are 0 ports with no output delay but user has a false path constraint
|
||||
|
||||
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
|
||||
|
||||
|
||||
7. checking multiple_clock (0)
|
||||
------------------------------
|
||||
There are 0 register/latch pins with multiple clocks.
|
||||
|
||||
|
||||
8. checking generated_clocks (0)
|
||||
--------------------------------
|
||||
There are 0 generated clocks that are not connected to a clock source.
|
||||
|
||||
|
||||
9. checking loops (0)
|
||||
---------------------
|
||||
There are 0 combinational loops in the design.
|
||||
|
||||
|
||||
10. checking partial_input_delay (0)
|
||||
------------------------------------
|
||||
There are 0 input ports with partial input delay specified.
|
||||
|
||||
|
||||
11. checking partial_output_delay (0)
|
||||
-------------------------------------
|
||||
There are 0 ports with partial output delay specified.
|
||||
|
||||
|
||||
12. checking latch_loops (0)
|
||||
----------------------------
|
||||
There are 0 combinational latch loops in the design through latch input
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Design Timing Summary
|
||||
| ---------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
||||
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
||||
inf 0.000 0 67 inf 0.000 0 67 NA NA NA NA
|
||||
|
||||
|
||||
There are no user specified timing constraints.
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Clock Summary
|
||||
| -------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Intra Clock Table
|
||||
| -----------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
|
||||
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Inter Clock Table
|
||||
| -----------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
||||
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Other Path Groups Table
|
||||
| -----------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
|
||||
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| User Ignored Path Table
|
||||
| -----------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Path Group From Clock To Clock
|
||||
---------- ---------- --------
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Unconstrained Path Table
|
||||
| ------------------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
Path Group From Clock To Clock
|
||||
---------- ---------- --------
|
||||
(none)
|
||||
|
||||
|
||||
------------------------------------------------------------------------------------------------
|
||||
| Timing Details
|
||||
| --------------
|
||||
------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------------
|
||||
Path Group: (none)
|
||||
From Clock:
|
||||
To Clock:
|
||||
|
||||
Max Delay 67 Endpoints
|
||||
Min Delay 67 Endpoints
|
||||
--------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Max Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: led
|
||||
(output port)
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 9.232ns (logic 5.810ns (62.942%) route 3.421ns (37.058%))
|
||||
Logic Levels: 8 (CARRY4=4 FDCE=1 LDCE=1 LUT2=1 OBUF=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 r led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 0.688 3.042 led_reg_i_2_n_0
|
||||
SLICE_X41Y92 LDCE (SetClr_ldce_CLR_Q) 0.791 3.833 f led_reg/Q
|
||||
net (fo=1, routed) 1.913 5.746 led_OBUF
|
||||
G14 OBUF (Prop_obuf_I_O) 3.485 9.232 f led_OBUF_inst/O
|
||||
net (fo=0) 0.000 9.232 led
|
||||
G14 f led (OUT)
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[24]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 4.152ns (logic 1.534ns (36.946%) route 2.618ns (63.054%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.798 4.152 led_reg_i_2_n_0
|
||||
SLICE_X42Y94 FDCE f count_reg[24]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[25]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 4.152ns (logic 1.534ns (36.946%) route 2.618ns (63.054%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.798 4.152 led_reg_i_2_n_0
|
||||
SLICE_X42Y94 FDCE f count_reg[25]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[26]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 4.152ns (logic 1.534ns (36.946%) route 2.618ns (63.054%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.798 4.152 led_reg_i_2_n_0
|
||||
SLICE_X42Y94 FDCE f count_reg[26]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[27]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 4.152ns (logic 1.534ns (36.946%) route 2.618ns (63.054%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.798 4.152 led_reg_i_2_n_0
|
||||
SLICE_X42Y94 FDCE f count_reg[27]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[20]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 3.700ns (logic 1.534ns (41.461%) route 2.166ns (58.539%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.346 3.700 led_reg_i_2_n_0
|
||||
SLICE_X42Y93 FDCE f count_reg[20]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[21]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 3.700ns (logic 1.534ns (41.461%) route 2.166ns (58.539%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.346 3.700 led_reg_i_2_n_0
|
||||
SLICE_X42Y93 FDCE f count_reg[21]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[22]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 3.700ns (logic 1.534ns (41.461%) route 2.166ns (58.539%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.346 3.700 led_reg_i_2_n_0
|
||||
SLICE_X42Y93 FDCE f count_reg[22]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[23]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 3.700ns (logic 1.534ns (41.461%) route 2.166ns (58.539%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.346 3.700 led_reg_i_2_n_0
|
||||
SLICE_X42Y93 FDCE f count_reg[23]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[3]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[28]/CLR
|
||||
Path Group: (none)
|
||||
Path Type: Max at Slow Process Corner
|
||||
Data Path Delay: 3.691ns (logic 1.534ns (41.562%) route 2.157ns (58.438%))
|
||||
Logic Levels: 6 (CARRY4=4 FDCE=1 LUT2=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[3]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.518 0.518 f count_reg[3]/Q
|
||||
net (fo=5, routed) 0.820 1.338 count_reg[3]
|
||||
SLICE_X43Y89 LUT2 (Prop_lut2_I1_O) 0.124 1.462 r led_reg_i_58/O
|
||||
net (fo=1, routed) 0.000 1.462 led_reg_i_58_n_0
|
||||
SLICE_X43Y89 CARRY4 (Prop_carry4_S[1]_CO[3])
|
||||
0.550 2.012 r led_reg_i_39/CO[3]
|
||||
net (fo=1, routed) 0.000 2.012 led_reg_i_39_n_0
|
||||
SLICE_X43Y90 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.126 r led_reg_i_25/CO[3]
|
||||
net (fo=1, routed) 0.000 2.126 led_reg_i_25_n_0
|
||||
SLICE_X43Y91 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.240 r led_reg_i_11/CO[3]
|
||||
net (fo=1, routed) 0.000 2.240 led_reg_i_11_n_0
|
||||
SLICE_X43Y92 CARRY4 (Prop_carry4_CI_CO[3])
|
||||
0.114 2.354 f led_reg_i_2/CO[3]
|
||||
net (fo=33, routed) 1.337 3.691 led_reg_i_2_n_0
|
||||
SLICE_X42Y95 FDCE f count_reg[28]/CLR
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Min Delay Paths
|
||||
--------------------------------------------------------------------------------------
|
||||
Slack: inf
|
||||
Source: count_reg[18]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[18]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.401ns (logic 0.274ns (68.412%) route 0.127ns (31.588%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y92 FDCE 0.000 0.000 r count_reg[18]/C
|
||||
SLICE_X42Y92 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[18]/Q
|
||||
net (fo=5, routed) 0.127 0.291 count_reg[18]
|
||||
SLICE_X42Y92 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.401 r count_reg[16]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.401 count_reg[16]_i_1_n_5
|
||||
SLICE_X42Y92 FDCE r count_reg[18]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[26]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[26]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.401ns (logic 0.274ns (68.401%) route 0.127ns (31.599%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y94 FDCE 0.000 0.000 r count_reg[26]/C
|
||||
SLICE_X42Y94 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[26]/Q
|
||||
net (fo=4, routed) 0.127 0.291 count_reg[26]
|
||||
SLICE_X42Y94 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.401 r count_reg[24]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.401 count_reg[24]_i_1_n_5
|
||||
SLICE_X42Y94 FDCE r count_reg[26]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[30]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[30]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.401ns (logic 0.274ns (68.401%) route 0.127ns (31.599%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y95 FDCE 0.000 0.000 r count_reg[30]/C
|
||||
SLICE_X42Y95 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[30]/Q
|
||||
net (fo=5, routed) 0.127 0.291 count_reg[30]
|
||||
SLICE_X42Y95 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.401 r count_reg[28]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.401 count_reg[28]_i_1_n_5
|
||||
SLICE_X42Y95 FDCE r count_reg[30]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[6]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[6]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.412ns (logic 0.274ns (66.556%) route 0.138ns (33.444%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y89 FDCE 0.000 0.000 r count_reg[6]/C
|
||||
SLICE_X42Y89 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[6]/Q
|
||||
net (fo=4, routed) 0.138 0.302 count_reg[6]
|
||||
SLICE_X42Y89 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.412 r count_reg[4]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.412 count_reg[4]_i_1_n_5
|
||||
SLICE_X42Y89 FDCE r count_reg[6]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[10]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[10]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.412ns (logic 0.274ns (66.506%) route 0.138ns (33.494%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y90 FDCE 0.000 0.000 r count_reg[10]/C
|
||||
SLICE_X42Y90 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[10]/Q
|
||||
net (fo=4, routed) 0.138 0.302 count_reg[10]
|
||||
SLICE_X42Y90 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.412 r count_reg[8]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.412 count_reg[8]_i_1_n_5
|
||||
SLICE_X42Y90 FDCE r count_reg[10]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[14]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[14]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.413ns (logic 0.274ns (66.390%) route 0.139ns (33.610%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y91 FDCE 0.000 0.000 r count_reg[14]/C
|
||||
SLICE_X42Y91 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[14]/Q
|
||||
net (fo=4, routed) 0.139 0.303 count_reg[14]
|
||||
SLICE_X42Y91 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.413 r count_reg[12]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.413 count_reg[12]_i_1_n_5
|
||||
SLICE_X42Y91 FDCE r count_reg[14]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[22]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[22]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.413ns (logic 0.274ns (66.390%) route 0.139ns (33.610%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y93 FDCE 0.000 0.000 r count_reg[22]/C
|
||||
SLICE_X42Y93 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[22]/Q
|
||||
net (fo=4, routed) 0.139 0.303 count_reg[22]
|
||||
SLICE_X42Y93 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.413 r count_reg[20]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.413 count_reg[20]_i_1_n_5
|
||||
SLICE_X42Y93 FDCE r count_reg[22]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[2]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[2]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.413ns (logic 0.274ns (66.390%) route 0.139ns (33.610%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y88 FDCE 0.000 0.000 r count_reg[2]/C
|
||||
SLICE_X42Y88 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[2]/Q
|
||||
net (fo=5, routed) 0.139 0.303 count_reg[2]
|
||||
SLICE_X42Y88 CARRY4 (Prop_carry4_S[2]_O[2])
|
||||
0.110 0.413 r count_reg[0]_i_1/O[2]
|
||||
net (fo=1, routed) 0.000 0.413 count_reg[0]_i_1_n_5
|
||||
SLICE_X42Y88 FDCE r count_reg[2]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[18]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[19]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.437ns (logic 0.310ns (71.017%) route 0.127ns (28.983%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y92 FDCE 0.000 0.000 r count_reg[18]/C
|
||||
SLICE_X42Y92 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[18]/Q
|
||||
net (fo=5, routed) 0.127 0.291 count_reg[18]
|
||||
SLICE_X42Y92 CARRY4 (Prop_carry4_S[2]_O[3])
|
||||
0.146 0.437 r count_reg[16]_i_1/O[3]
|
||||
net (fo=1, routed) 0.000 0.437 count_reg[16]_i_1_n_4
|
||||
SLICE_X42Y92 FDCE r count_reg[19]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
Slack: inf
|
||||
Source: count_reg[26]/C
|
||||
(rising edge-triggered cell FDCE)
|
||||
Destination: count_reg[27]/D
|
||||
Path Group: (none)
|
||||
Path Type: Min at Fast Process Corner
|
||||
Data Path Delay: 0.437ns (logic 0.310ns (71.007%) route 0.127ns (28.993%))
|
||||
Logic Levels: 2 (CARRY4=1 FDCE=1)
|
||||
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X42Y94 FDCE 0.000 0.000 r count_reg[26]/C
|
||||
SLICE_X42Y94 FDCE (Prop_fdce_C_Q) 0.164 0.164 r count_reg[26]/Q
|
||||
net (fo=4, routed) 0.127 0.291 count_reg[26]
|
||||
SLICE_X42Y94 CARRY4 (Prop_carry4_S[2]_O[3])
|
||||
0.146 0.437 r count_reg[24]_i_1/O[3]
|
||||
net (fo=1, routed) 0.000 0.437 count_reg[24]_i_1_n_4
|
||||
SLICE_X42Y94 FDCE r count_reg[27]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,202 @@
|
||||
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
|
||||
| Date : Fri Mar 25 10:11:52 2022
|
||||
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb
|
||||
| Design : pwm_test
|
||||
| Device : xc7z010clg400-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Placed
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice LUTs | 33 | 0 | 0 | 17600 | 0.19 |
|
||||
| LUT as Logic | 33 | 0 | 0 | 17600 | 0.19 |
|
||||
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
|
||||
| Slice Registers | 33 | 0 | 0 | 35200 | 0.09 |
|
||||
| Register as Flip Flop | 32 | 0 | 0 | 35200 | 0.09 |
|
||||
| Register as Latch | 1 | 0 | 0 | 35200 | <0.01 |
|
||||
| F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 |
|
||||
+-------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 33 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+------------------------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------------------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice | 16 | 0 | 0 | 4400 | 0.36 |
|
||||
| SLICEL | 8 | 0 | | | |
|
||||
| SLICEM | 8 | 0 | | | |
|
||||
| LUT as Logic | 33 | 0 | 0 | 17600 | 0.19 |
|
||||
| using O5 output only | 0 | | | | |
|
||||
| using O6 output only | 14 | | | | |
|
||||
| using O5 and O6 | 19 | | | | |
|
||||
| LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | | |
|
||||
| LUT as Shift Register | 0 | 0 | | | |
|
||||
| Slice Registers | 33 | 0 | 0 | 35200 | 0.09 |
|
||||
| Register driven from within the Slice | 33 | | | | |
|
||||
| Register driven from outside the Slice | 0 | | | | |
|
||||
| Unique Control Sets | 2 | | 0 | 4400 | 0.05 |
|
||||
+------------------------------------------+------+-------+------------+-----------+-------+
|
||||
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 0 | 60 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 0 | 120 | 0.00 |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 80 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 2 | 2 | 0 | 100 | 2.00 |
|
||||
| IOB Master Pads | 1 | | | | |
|
||||
| IOB Slave Pads | 0 | | | | |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 96 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 100 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 48 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 8 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| LUT2 | 51 | LUT |
|
||||
| FDCE | 32 | Flop & Latch |
|
||||
| CARRY4 | 16 | CarryLogic |
|
||||
| OBUF | 1 | IO |
|
||||
| LUT1 | 1 | LUT |
|
||||
| LDCE | 1 | Flop & Latch |
|
||||
| IBUF | 1 | IO |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,40 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/Vivado/2021.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2021.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2021.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
// pre-commands:
|
||||
ISETouchFile( "init_design", "begin" );
|
||||
ISEStep( "vivado",
|
||||
"-log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace" );
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,553 @@
|
||||
|
||||
*** Running vivado
|
||||
with args -log pwm_test.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm_test.tcl -notrace
|
||||
|
||||
|
||||
|
||||
****** Vivado v2021.2 (64-bit)
|
||||
**** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
|
||||
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
|
||||
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
source pwm_test.tcl -notrace
|
||||
Command: open_checkpoint C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test.dcp
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1262.352 ; gain = 1.801
|
||||
CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
|
||||
CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:zybo-z7-10:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
|
||||
INFO: [Device 21-403] Loading part xc7z010clg400-1
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1266.320 ; gain = 0.000
|
||||
INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2021.2
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Timing 38-478] Restoring timing data from binary archive.
|
||||
INFO: [Timing 38-479] Binary timing data restore complete.
|
||||
INFO: [Project 1-856] Restoring constraints from binary archive.
|
||||
INFO: [Project 1-853] Binary constraint restore complete.
|
||||
Reading XDEF placement.
|
||||
Reading placer database...
|
||||
Reading XDEF routing.
|
||||
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
|
||||
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
|
||||
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1357.309 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1357.309 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Project 1-604] Checkpoint was created with Vivado v2021.2 (64-bit) build 3367213
|
||||
open_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1357.309 ; gain = 104.965
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1365.902 ; gain = 8.594
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: 1c056137f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1441.777 ; gain = 75.875
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 1 Retarget | Checksum: 1c056137f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
|
||||
Phase 2 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 2 Constant propagation | Checksum: 1c056137f
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 3 Sweep
|
||||
Phase 3 Sweep | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 BUFG optimization
|
||||
Phase 4 BUFG optimization | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 5 Shift Register Optimization
|
||||
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
||||
Phase 5 Shift Register Optimization | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 Post Processing Netlist
|
||||
Phase 6 Post Processing Netlist | Checksum: 1fbd34c49
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 0 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
Ending Logic Optimization Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
Ending Power Optimization Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
Ending Netlist Obfuscation Task | Checksum: 20c3576ce
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
28 Infos, 0 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1726.871 ; gain = 369.562
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1726.871 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_opt.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
|
||||
Command: report_drc -file pwm_test_drc_opted.rpt -pb pwm_test_drc_opted.pb -rpx pwm_test_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Starting Placer Task
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 13ba8a4a3
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: bc17a400
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.161 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.164 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 1 Placer Initialization | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.170 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2.2 Update Timing before SLR Path Opt
|
||||
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2.3 Post-Processing in Floorplanning
|
||||
Phase 2.3 Post-Processing in Floorplanning | Checksum: 18da1b6ca
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.179 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 2.4 Global Placement Core
|
||||
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
|
||||
Phase 2.4 Global Placement Core | Checksum: 12ed945d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.657 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 2 Global Placement | Checksum: 12ed945d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.661 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 12ed945d9
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.664 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.677 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.720 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.725 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.726 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 3 Detail Placement | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.727 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.745 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.748 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion
|
||||
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
||||
____________________________________________________
|
||||
| | Global Congestion | Short Congestion |
|
||||
| Direction | Region Size | Region Size |
|
||||
|___________|___________________|___________________|
|
||||
| North| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| South| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| East| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| West| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 4.3 Placer Reporting | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.750 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1707a0fa3
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.751 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Ending Placer Task | Checksum: deb5d7c7
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.752 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
47 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_placed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_io -file pwm_test_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [runtcl-4] Executing : report_utilization -file pwm_test_utilization_placed.rpt -pb pwm_test_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file pwm_test_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
Command: phys_opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
55 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
phys_opt_design completed successfully
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1766.074 ; gain = 0.000
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_physopt.dcp' has been generated.
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Checksum: PlaceDB: 584981bf ConstDB: 0 ShapeSum: 866c5608 RouteDB: 0
|
||||
Post Restoration Checksum: NetGraph: 32e9d585 NumContArr: cff0ca0e Constraints: 0 Timing: 0
|
||||
Phase 1 Build RT Design | Checksum: 102da9f93
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1799.160 ; gain = 26.402
|
||||
|
||||
Phase 2 Router Initialization
|
||||
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: 102da9f93
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: 102da9f93
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1805.191 ; gain = 32.434
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0 %
|
||||
Global Horizontal Routing Utilization = 0 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 48
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 48
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 2 Router Initialization | Checksum: a88dbed9
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 3 Initial Routing
|
||||
|
||||
Phase 3.1 Global Routing
|
||||
Phase 3.1 Global Routing | Checksum: a88dbed9
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
Phase 3 Initial Routing | Checksum: 105c3e9d5
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 0
|
||||
Phase 4.1 Global Iteration 0 | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
Phase 4 Rip-up And Reroute | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
Phase 5 Delay and Skew Optimization | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
Phase 6.1 Hold Fix Iter | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
Phase 6 Post Hold Fix | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0115428 %
|
||||
Global Horizontal Routing Utilization = 0.0284926 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Congestion Report
|
||||
North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
|
||||
South Dir 1x1 Area, Max Cong = 6.30631%, No Congested Regions.
|
||||
East Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
|
||||
West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
|
||||
|
||||
------------------------------
|
||||
Reporting congestion hotspots
|
||||
------------------------------
|
||||
Direction: North
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: South
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: East
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
Direction: West
|
||||
----------------
|
||||
Congested clusters found at Level 0
|
||||
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1809.602 ; gain = 36.844
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: ec175c67
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 8d29afef
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 37.930
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
65 Infos, 1 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:13 . Memory (MB): peak = 1810.688 ; gain = 44.613
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Writing placer database...
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1820.504 ; gain = 9.816
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_routed.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
|
||||
Command: report_drc -file pwm_test_drc_routed.rpt -pb pwm_test_drc_routed.pb -rpx pwm_test_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file pwm_test_methodology_drc_routed.rpt -pb pwm_test_methodology_drc_routed.pb -rpx pwm_test_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 2 threads
|
||||
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/pwm_test_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
INFO: [runtcl-4] Executing : report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
|
||||
Command: report_power -file pwm_test_power_routed.rpt -pb pwm_test_power_summary_routed.pb -rpx pwm_test_power_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
|
||||
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
77 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
INFO: [runtcl-4] Executing : report_route_status -file pwm_test_route_status.rpt -pb pwm_test_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file pwm_test_timing_summary_routed.rpt -pb pwm_test_timing_summary_routed.pb -rpx pwm_test_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file pwm_test_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file pwm_test_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pwm_test_bus_skew_routed.rpt -pb pwm_test_bus_skew_routed.pb -rpx pwm_test_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
|
||||
Command: write_bitstream -force pwm_test.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 2 threads
|
||||
WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./pwm_test.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
12 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 2293.621 ; gain = 439.371
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Mar 25 10:12:18 2022...
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user