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Bibliotheken/digilent-xdc-master/Arty-A7-100-Master.xdc
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Bibliotheken/digilent-xdc-master/Arty-A7-100-Master.xdc
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## This file is a general .xdc for the Arty A7-100 Rev. D
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
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#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
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## Switches
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#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
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#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
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#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
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#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
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## RGB LEDs
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#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
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#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
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#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
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#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
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#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
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#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
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#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
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#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
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#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
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#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
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#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
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#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
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## LEDs
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#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
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#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
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#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
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#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
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## Buttons
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#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
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#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
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#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
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#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
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## Pmod Header JA
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#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
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#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
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#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
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#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
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#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
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#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
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#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
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## Pmod Header JB
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#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
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#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
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#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
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#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
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#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
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#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
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#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
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#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
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## Pmod Header JC
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#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
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#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
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#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
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#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
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#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
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#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
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#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
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#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
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## Pmod Header JD
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#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
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#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
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#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
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#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
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#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
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#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
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#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
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#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
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## USB-UART Interface
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#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
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#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
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## ChipKit Outer Digital Header
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#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
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#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
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#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
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#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
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#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
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#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
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#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
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#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
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#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
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#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
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#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
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#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
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#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
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#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
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## ChipKit Inner Digital Header
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#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
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#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
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#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
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#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
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#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
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#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
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#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
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#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
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#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
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#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
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#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
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#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
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#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
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#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
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#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
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#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
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## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
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## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
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## WARNING: Do not use both sets of constraints at the same time!
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## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
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#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
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#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
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#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
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#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
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#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
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#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
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#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
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#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
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#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
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#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
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#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
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#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
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## ChipKit Outer Analog Header - as Digital I/O
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## NOTE: The following constraints should be used when using these ports as digital I/O.
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#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
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#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
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#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
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#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
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#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
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#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
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## ChipKit Inner Analog Header - as Differential Analog Inputs
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## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
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## WARNING: Do not use both sets of constraints at the same time!
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## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
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#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
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#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
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#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
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#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
216
Bibliotheken/digilent-xdc-master/Arty-A7-35-Master.xdc
Normal file
216
Bibliotheken/digilent-xdc-master/Arty-A7-35-Master.xdc
Normal file
@ -0,0 +1,216 @@
|
||||
## This file is a general .xdc for the Arty A7-35 Rev. D
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: the following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] ChipKit pin=A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit Analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: the following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io20 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io21 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io22 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io23 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io24 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io25 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
216
Bibliotheken/digilent-xdc-master/Arty-Master.xdc
Normal file
216
Bibliotheken/digilent-xdc-master/Arty-Master.xdc
Normal file
@ -0,0 +1,216 @@
|
||||
## This file is a general .xdc for the ARTY Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_n }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { vaux7_p }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
|
||||
## SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Power Measurements
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
|
||||
195
Bibliotheken/digilent-xdc-master/Arty-S7-25-Master.xdc
Normal file
195
Bibliotheken/digilent-xdc-master/Arty-S7-25-Master.xdc
Normal file
@ -0,0 +1,195 @@
|
||||
## This file is a general .xdc for the Arty S7-25 Rev. E
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signals
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
|
||||
#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L4P_T0_D04_14 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L5P_T0_D06_14 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L5N_T0_D07_14 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L7P_T1_D09_14 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L7N_T1_D10_14 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[9]
|
||||
|
||||
## ChipKit SPI Header
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
## NOTE: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN J10 } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
|
||||
#set_property -dict { PACKAGE_PIN K9 } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L5P_T0_AD9P_15 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L5N_T0_AD9N_15 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L7P_T1_AD2P_15 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L7N_T1_AD2N_15 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L8P_T1_AD10P_15 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L8N_T1_AD10N_15 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L10P_T1_AD11P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L10N_T1_AD11N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3] ChipKit pin=A9
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15 Sch=ck_a10_r (Cannot be used as an analog input)
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15 Sch=ck_a11_r (Cannot be used as an analog input)
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15
|
||||
|
||||
## Quad SPI Flash
|
||||
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
|
||||
## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
|
||||
## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
|
||||
## and to be able to use this pin as an ordinary I/O the following property must
|
||||
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
|
||||
## used the internal reference is set to half that value (i.e. 0.675v). Note that
|
||||
## this property must be set even if SW3 is not used in the design.
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
195
Bibliotheken/digilent-xdc-master/Arty-S7-50-Master.xdc
Normal file
195
Bibliotheken/digilent-xdc-master/Arty-S7-50-Master.xdc
Normal file
@ -0,0 +1,195 @@
|
||||
## This file is a general .xdc for the Arty S7-50 Rev. E
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signals
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { CLK12MHZ }]; #IO_L13P_T2_MRCC_15 Sch=uclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.333 -waveform {0 41.667} [get_ports { CLK12MHZ }];
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
|
||||
#create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000} [get_ports { CLK100MHZ }];
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN M5 IOSTANDARD SSTL135 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L16P_T2_A28_15 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L15P_T2_DQS_15 Sch=led1_b
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L4P_T0_D04_14 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L5P_T0_D06_14 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L5N_T0_D07_14 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L7P_T1_D09_14 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L7N_T1_D10_14 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L9P_T1_DQS_14 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L9N_T1_DQS_D13_14 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_D14_14 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L10N_T1_D15_14 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11P_T1_SRCC_14 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L11N_T1_SRCC_14 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L12P_T1_MRCC_14 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L12N_T1_MRCC_14 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
|
||||
## USB-UART Interface
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_25_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_0_14 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[9]
|
||||
|
||||
## ChipKit SPI Header
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13. Do not use both at the same time.
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L22P_T3_A17_15 Sch=ck_io10_ss
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L22N_T3_A16_15 Sch=ck_io11_mosi
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L23P_T3_FOE_B_15 Sch=ck_io12_miso
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L14P_T2_SRCC_15 Sch=ck_io13_sck
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
## Note: these pins are shared with PMOD Headers JC and JD and cannot be used at the same time as the applicable PMOD interface(s)
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L24P_T3_A01_D17_14 Sch=jd10/ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L23N_T3_A02_D18_14 Sch=jd9/ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L23P_T3_A03_D19_14 Sch=jd8/ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L22N_T3_A04_D20_14 Sch=jd7/ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A05_D21_14 Sch=jd4/ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jd3/ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L21P_T3_DQS_14 Sch=jd2/ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_A07_D23_14 Sch=jd1/ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L20P_T3_A08_D24_14 Sch=jc10/ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=jc9/ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN P13 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L19P_T3_A10_D26_14 Sch=jc8/ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L16P_T2_CSI_B_14 Sch=jc7/ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=jc4/ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=jc3/ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L18N_T2_A11_D27_14 Sch=jc2/ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18P_T2_A12_D28_14 Sch=jc1/ck_io[41]
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN J10 } [get_ports { vp_in }]; #IO_L1P_T0_AD4P_35 Sch=v_p
|
||||
#set_property -dict { PACKAGE_PIN K9 } [get_ports { vn_in }]; #IO_L1N_T0_AD4N_35 Sch=v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_15 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_15 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L7P_T1_AD2P_15 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L7N_T1_AD2N_15 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L8P_T1_AD10P_15 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L8N_T1_AD10N_15 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L10P_T1_AD11P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L10N_T1_AD11N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_15 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_15 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_15 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_15 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_15 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_15 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3] ChipKit pin=A9
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L2P_T0_AD8P_15 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L2N_T0_AD8N_15 Sch=ad_n[8]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L9P_T1_DQS_AD3P_15 Sch=ad_p[3]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L9N_T1_DQS_AD3N_15 Sch=ad_n[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L12P_T1_MRCC_15 Sch=ck_a10_r (Cannot be used as an analog input)
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L12N_T1_MRCC_15 Sch=ck_a11_r (Cannot be used as an analog input)
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_RS0_15 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_RS1_15 Sch=ck_sda
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_25_15 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L11N_T1_SRCC_15
|
||||
|
||||
## Quad SPI Flash
|
||||
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
|
||||
## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
|
||||
## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
|
||||
## and to be able to use this pin as an ordinary I/O the following property must
|
||||
## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
|
||||
## used the internal reference is set to half that value (i.e. 0.675v). Note that
|
||||
## this property must be set even if SW3 is not used in the design.
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
154
Bibliotheken/digilent-xdc-master/Arty-Z7-10-Master.xdc
Normal file
154
Bibliotheken/digilent-xdc-master/Arty-Z7-10-Master.xdc
Normal file
@ -0,0 +1,154 @@
|
||||
## This file is a general .xdc for the ARTY Z7-10 Rev.B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N (Pin 10)
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N (Pin 10)
|
||||
|
||||
## Audio Out
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA
|
||||
|
||||
## HDMI RX Signals
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA
|
||||
|
||||
## HDMI TX Signals
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L5P_T0_34 Sch=CK_IO0
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L2N_T0_34 Sch=CK_IO1
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L3N_T0_DQS_34 Sch=CK_IO3
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L10P_T1_34 Sch=CK_IO4
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L5N_T0_34 Sch=CK_IO5
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19P_T3_34 Sch=CK_IO6
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L9N_T1_DQS_34 Sch=CK_IO7
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L21P_T3_DQS_34 Sch=CK_IO8
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L21N_T3_DQS_34 Sch=CK_IO9
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34 Sch=CK_IO10
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34 Sch=CK_IO11
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34 Sch=CK_IO12
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34 Sch=CK_IO13
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
## Not Connected on Z7-10 Variant
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports should be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) with the XADC IP core.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=CK_AN1_N ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=CK_AN1_P ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=CK_AN2_N ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=CK_AN2_P ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=CK_AN3_N ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=CK_AN3_P ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=CK_AN4_N ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=CK_AN4_P ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=CK_AN5_N ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=CK_AN5_P ChipKit pin=A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=CK_SCK
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=CK_SS
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA
|
||||
|
||||
## Not Connected Pins
|
||||
#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35
|
||||
#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35
|
||||
185
Bibliotheken/digilent-xdc-master/Arty-Z7-20-Master.xdc
Normal file
185
Bibliotheken/digilent-xdc-master/Arty-Z7-20-Master.xdc
Normal file
@ -0,0 +1,185 @@
|
||||
## This file is a general .xdc for the ARTY Z7-20 Rev.B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L7N_T1_AD2N_35 Sch=SW0
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L7P_T1_AD2P_35 Sch=SW1
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]; #IO_L22N_T3_AD7P_35 Sch=LED4_B
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]; #IO_L16P_T2_35 Sch=LED4_G
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=LED4_R
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_0_35 Sch=LED5_B
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L22P_T3_AD7P_35 Sch=LED5_G
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L23N_T3_35 Sch=LED5_R
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L6N_T0_VREF_34 Sch=LED0
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L6P_T0_34 Sch=LED1
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=LED2
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L23P_T3_35 Sch=LED3
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4P_T0_35 Sch=BTN0
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4N_T0_35 Sch=BTN1
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=BTN2
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=BTN3
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L17P_T2_34 Sch=JA1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L17N_T2_34 Sch=JA1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L7P_T1_34 Sch=JA2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L7N_T1_34 Sch=JA2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L12P_T1_MRCC_34 Sch=JA3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L12N_T1_MRCC_34 Sch=JA3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja_p[4] }]; #IO_L22P_T3_34 Sch=JA4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja_n[4] }]; #IO_L22N_T3_34 Sch=JA4_N (Pin 10)
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P (Pin 1)
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N (Pin 2)
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P (Pin 3)
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N (Pin 4)
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P (Pin 7)
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N (Pin 8)
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P (Pin 9)
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N (Pin 10)
|
||||
|
||||
## Audio Out
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L20N_T3_34 Sch=AUD_PWM
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L20P_T3_34 Sch=AUD_SD
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_25_35 Sch=CRYPTO_SDA
|
||||
|
||||
## HDMI RX Signals
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_RX_CEC
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_34 Sch=HDMI_RX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_34 Sch=HDMI_RX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[0] }]; #IO_L16N_T2_34 Sch=HDMI_RX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[0] }]; #IO_L16P_T2_34 Sch=HDMI_RX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[1] }]; #IO_L15N_T2_DQS_34 Sch=HDMI_RX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[1] }]; #IO_L15P_T2_DQS_34 Sch=HDMI_RX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=HDMI_RX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_d_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=HDMI_RX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_25_34 Sch=HDMI_RX_HPD
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=HDMI_RX_SCL
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L11N_T1_SRCC_34 Sch=HDMI_RX_SDA
|
||||
|
||||
## HDMI TX Signals
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L19N_T3_VREF_35 Sch=HDMI_TX_CEC
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L11N_T1_SRCC_35 Sch=HDMI_TX_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L11P_T1_SRCC_35 Sch=HDMI_TX_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[0] }]; #IO_L12N_T1_MRCC_35 Sch=HDMI_TX_D0_N
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[0] }]; #IO_L12P_T1_MRCC_35 Sch=HDMI_TX_D0_P
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[1] }]; #IO_L10N_T1_AD11N_35 Sch=HDMI_TX_D1_N
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[1] }]; #IO_L10P_T1_AD11P_35 Sch=HDMI_TX_D1_P
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_n[2] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=HDMI_TX_D2_N
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_d_p[2] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=HDMI_TX_D2_P
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]; #IO_0_34 Sch=HDMI_TX_HDPN
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L8P_T1_AD10P_35 Sch=HDMI_TX_SCL
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L8N_T1_AD10N_35 Sch=HDMI_TX_SDA
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L5P_T0_34 Sch=CK_IO0
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L2N_T0_34 Sch=CK_IO1
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=CK_IO2
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L3N_T0_DQS_34 Sch=CK_IO3
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L10P_T1_34 Sch=CK_IO4
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L5N_T0_34 Sch=CK_IO5
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19P_T3_34 Sch=CK_IO6
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L9N_T1_DQS_34 Sch=CK_IO7
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L21P_T3_DQS_34 Sch=CK_IO8
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L21N_T3_DQS_34 Sch=CK_IO9
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L9P_T1_DQS_34 Sch=CK_IO10
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L19N_T3_VREF_34 Sch=CK_IO11
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L23N_T3_34 Sch=CK_IO12
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L23P_T3_34 Sch=CK_IO13
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_VREF_13 Sch=CK_IO26
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L6N_T0_VREF_13 Sch=CK_IO27
|
||||
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L22P_T3_13 Sch=CK_IO28
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L11P_T1_SRCC_13 Sch=CK_IO29
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L11N_T1_SRCC_13 Sch=CK_IO30
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L17N_T2_13 Sch=CK_IO31
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L15P_T2_DQS_13 Sch=CK_IO32
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L21N_T3_DQS_13 Sch=CK_IO33
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L16P_T2_13 Sch=CK_IO34
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L22N_T3_13 Sch=CK_IO35
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L13N_T2_MRCC_13 Sch=CK_IO36
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L13P_T2_MRCC_13 Sch=cCK_IO37
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L15N_T2_DQS_13 Sch=CK_IO38
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_SRCC_13 Sch=CK_IO39
|
||||
#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_13 Sch=CK_IO40
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L14P_T2_SRCC_13 Sch=CK_IO41
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=CK_AN0_N ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=CK_AN0_P ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=CK_AN1_N ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=CK_AN1_P ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=CK_AN2_N ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=CK_AN2_P ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=CK_AN3_N ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=CK_AN3_P ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=CK_AN4_N ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=CK_AN4_P ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=CK_AN5_N ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=CK_AN5_P ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L18N_T2_13 Sch=CK_A0
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L20P_T3_13 Sch=CK_A1
|
||||
#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L18P_T2_13 Sch=CK_A2
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L21P_T3_DQS_13 Sch=CK_A3
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L19P_T3_13 Sch=CK_A4
|
||||
#set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L12N_T1_MRCC_13 Sch=CK_A5
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=AD12_P
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=AD12_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L1P_T0_AD0P_35 Sch=AD0_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L1N_T0_AD0N_35 Sch=AD0_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=AD8_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=AD8_N
|
||||
|
||||
## ChipKit SPI
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=CK_MISO
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=CK_SCK
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=CK_SS
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=CK_SCL
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=CK_SDA
|
||||
|
||||
## Misc. ChipKit Ports
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L20N_T3_13 Sch=CK_IOA
|
||||
|
||||
## Not Connected Pins
|
||||
#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]; #IO_L6N_T0_VREF_35
|
||||
#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]; #IO_L16N_T2_35
|
||||
#set_property PACKAGE_PIN T9 [get_ports {netic20_t9}]; #IO_L12P_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U9 [get_ports {netic20_u9}]; #IO_L17P_T2_13
|
||||
154
Bibliotheken/digilent-xdc-master/Basys-3-Master.xdc
Normal file
154
Bibliotheken/digilent-xdc-master/Basys-3-Master.xdc
Normal file
@ -0,0 +1,154 @@
|
||||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {sw[2]}]
|
||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {sw[3]}]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {sw[4]}]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {sw[5]}]
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {sw[6]}]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {sw[7]}]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {sw[8]}]
|
||||
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {sw[9]}]
|
||||
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {sw[10]}]
|
||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {sw[11]}]
|
||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports {sw[12]}]
|
||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports {sw[13]}]
|
||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {sw[14]}]
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]
|
||||
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports {led[2]}]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports {led[3]}]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports {led[4]}]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports {led[5]}]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports {led[6]}]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports {led[7]}]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports {led[8]}]
|
||||
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports {led[9]}]
|
||||
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports {led[10]}]
|
||||
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports {led[11]}]
|
||||
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports {led[12]}]
|
||||
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]}]
|
||||
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
|
||||
|
||||
|
||||
##7 Segment Display
|
||||
#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {seg[0]}]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {seg[1]}]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {seg[2]}]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {seg[3]}]
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {seg[4]}]
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {seg[5]}]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {seg[6]}]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports dp]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {an[0]}]
|
||||
#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {an[1]}]
|
||||
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {an[2]}]
|
||||
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {an[3]}]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports {JA[0]}];#Sch name = JA1
|
||||
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports {JA[1]}];#Sch name = JA2
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports {JA[2]}];#Sch name = JA3
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports {JA[3]}];#Sch name = JA4
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports {JA[4]}];#Sch name = JA7
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports {JA[5]}];#Sch name = JA8
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports {JA[6]}];#Sch name = JA9
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports {JA[7]}];#Sch name = JA10
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports {JB[0]}];#Sch name = JB1
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports {JB[1]}];#Sch name = JB2
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports {JB[2]}];#Sch name = JB3
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports {JB[3]}];#Sch name = JB4
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports {JB[4]}];#Sch name = JB7
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports {JB[5]}];#Sch name = JB8
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports {JB[6]}];#Sch name = JB9
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {JB[7]}];#Sch name = JB10
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {JC[0]}];#Sch name = JC1
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports {JC[1]}];#Sch name = JC2
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports {JC[2]}];#Sch name = JC3
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports {JC[3]}];#Sch name = JC4
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports {JC[4]}];#Sch name = JC7
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports {JC[5]}];#Sch name = JC8
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports {JC[6]}];#Sch name = JC9
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports {JC[7]}];#Sch name = JC10
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[0]}];#Sch name = XA1_P
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[1]}];#Sch name = XA2_P
|
||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[2]}];#Sch name = XA3_P
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports {JXADC[3]}];#Sch name = XA4_P
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[4]}];#Sch name = XA1_N
|
||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports {JXADC[5]}];#Sch name = XA2_N
|
||||
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[6]}];#Sch name = XA3_N
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports {JXADC[7]}];#Sch name = XA4_N
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports Hsync]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Clk]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[0]}]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[1]}]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[2]}]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports {QspiDB[3]}]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports QspiCSn]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
132
Bibliotheken/digilent-xdc-master/Cmod-A7-Master.xdc
Normal file
132
Bibliotheken/digilent-xdc-master/Cmod-A7-Master.xdc
Normal file
@ -0,0 +1,132 @@
|
||||
## This file is a general .xdc for the CmodA7 rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 12 MHz Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L14N_T2_SRCC_16 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10]
|
||||
|
||||
## Analog XADC Pins
|
||||
## Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
|
||||
|
||||
## GPIO Pins
|
||||
## Pins 15 and 16 should remain commented if using them as analog inputs
|
||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio1 }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { pio2 }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { pio3 }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports { pio4 }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { pio5 }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { pio6 }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { pio7 }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { pio8 }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { pio9 }]; #IO_L6P_T0_16 Sch=pio[09]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { pio10 }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { pio11 }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { pio12 }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { pio13 }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
|
||||
#set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { pio14 }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
|
||||
#set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { pio17 }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
|
||||
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { pio18 }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
|
||||
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { pio19 }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
|
||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { pio20 }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { pio21 }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { pio22 }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
|
||||
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { pio23 }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
|
||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { pio26 }]; #IO_L2P_T0_34 Sch=pio[26]
|
||||
#set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { pio27 }]; #IO_L2N_T0_34 Sch=pio[27]
|
||||
#set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { pio28 }]; #IO_L1P_T0_34 Sch=pio[28]
|
||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { pio29 }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
|
||||
#set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { pio30 }]; #IO_L1N_T0_34 Sch=pio[30]
|
||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { pio31 }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
|
||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports { pio32 }]; #IO_L5N_T0_34 Sch=pio[32]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { pio33 }]; #IO_L5P_T0_34 Sch=pio[33]
|
||||
#set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { pio34 }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
|
||||
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { pio35 }]; #IO_L6P_T0_34 Sch=pio[35]
|
||||
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { pio36 }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
|
||||
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { pio37 }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
|
||||
#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports { pio38 }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { pio39 }]; #IO_L16N_T2_34 Sch=pio[39]
|
||||
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports { pio40 }]; #IO_L12N_T1_MRCC_34 Sch=pio[40]
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { pio41 }]; #IO_L16P_T2_34 Sch=pio[41]
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports { pio42 }]; #IO_L9N_T1_DQS_34 Sch=pio[42]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { pio43 }]; #IO_L13N_T2_MRCC_34 Sch=pio[43]
|
||||
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { pio44 }]; #IO_L9P_T1_DQS_34 Sch=pio[44]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { pio45 }]; #IO_L19P_T3_34 Sch=pio[45]
|
||||
#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { pio46 }]; #IO_L13P_T2_MRCC_34 Sch=pio[46]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { pio47 }]; #IO_L14P_T2_SRCC_34 Sch=pio[47]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { pio48 }]; #IO_L14N_T2_SRCC_34 Sch=pio[48]
|
||||
|
||||
## UART
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
|
||||
|
||||
## Crypto 1 Wire Interface
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
|
||||
|
||||
## QSPI
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Cellular RAM
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0] }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1] }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2] }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3] }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4] }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5] }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6] }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7] }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
|
||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { MemDB[0] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { MemDB[1] }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[2] }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { MemDB[3] }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { MemDB[4] }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { MemDB[5] }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[6] }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[7] }]; #IO_25_14 Sch=sram-dq[7]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { RamOEn }]; #IO_L10P_T1_D14_14 Sch=sram-oe
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { RamWEn }]; #IO_L10N_T1_D15_14 Sch=sram-we
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { RamCEn }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce
|
||||
|
||||
90
Bibliotheken/digilent-xdc-master/Cmod-S7-25-Master.xdc
Normal file
90
Bibliotheken/digilent-xdc-master/Cmod-S7-25-Master.xdc
Normal file
@ -0,0 +1,90 @@
|
||||
## This file is a general .xdc for the Cmod S7-25 Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 12 MHz System Clock
|
||||
#set_property -dict { PACKAGE_PIN M9 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_14 Sch=gclk
|
||||
#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { clk }];
|
||||
|
||||
## Push Buttons
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6P_T0_34 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN D1 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L6N_T0_VREF_34 Sch=btn[1]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L10N_T1_34 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L9N_T1_DQS_34 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN F2 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L10P_T1_34 Sch=led0_r
|
||||
|
||||
## 4 LEDs
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L8P_T1_34 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L16P_T2_34 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L16N_T2_34 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8N_T1_34 Sch=led[4]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L14P_T2_SRCC_34 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L14N_T2_SRCC_34 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L13P_T2_MRCC_34 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L11N_T1_SRCC_34 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L13N_T2_MRCC_34 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12P_T1_MRCC_34 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L12N_T1_MRCC_34 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L11P_T1_SRCC_34 Sch=ja[10]
|
||||
|
||||
## USB UART
|
||||
## Note: Port names are from the perspoctive of the FPGA.
|
||||
#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L6N_T0_D08_VREF_14 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L5N_T0_D07_14 Sch=uart_txd_in
|
||||
|
||||
## Analog Inputs on PIO Pins 32 and 33
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=ain_p[32]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=ain_n[32]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=ain_p[33]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=ain_n[33]
|
||||
|
||||
## Dedicated Digital I/O on the PIO Headers
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { pio1 }]; #IO_L18N_T2_34 Sch=pio[01]
|
||||
#set_property -dict { PACKAGE_PIN M4 IOSTANDARD LVCMOS33 } [get_ports { pio2 }]; #IO_L19P_T3_34 Sch=pio[02]
|
||||
#set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { pio3 }]; #IO_L19N_T3_VREF_34 Sch=pio[03]
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { pio4 }]; #IO_L20P_T3_34 Sch=pio[04]
|
||||
#set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { pio5 }]; #IO_L20N_T3_34 Sch=pio[05]
|
||||
#set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { pio6 }]; #IO_L21P_T3_DQS_34 Sch=pio[06]
|
||||
#set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { pio7 }]; #IO_L21N_T3_DQS_34 Sch=pio[07]
|
||||
#set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { pio8 }]; #IO_L22P_T3_34 Sch=pio[08]
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { pio9 }]; #IO_L22N_T3_34 Sch=pio[09]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { pio16 }]; #IO_L11P_T1_SRCC_14 Sch=pio[16]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { pio17 }]; #IO_L11N_T1_SRCC_14 Sch=pio[17]
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { pio18 }]; #IO_L8N_T1_D12_14 Sch=pio[18]
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { pio19 }]; #IO_L10N_T1_D15_14 Sch=pio[19]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { pio20 }]; #IO_L10P_T1_D14_14 Sch=pio[20]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { pio21 }]; #IO_L9N_T1_DQS_D13_14 Sch=pio[21]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { pio22 }]; #IO_L9P_T1_DQS_14 Sch=pio[22]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { pio23 }]; #IO_L4N_T0_D05_14 Sch=pio[23]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { pio26 }]; #IO_L7N_T1_D10_14 Sch=pio[26]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { pio27 }]; #IO_L4P_T0_D04_14 Sch=pio[27]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pio28 }]; #IO_L5P_T0_D06_14 Sch=pio[28]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { pio29 }]; #IO_L7P_T1_D09_14 Sch=pio[29]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { pio30 }]; #IO_L8P_T1_D11_14 Sch=pio[30]
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS33 } [get_ports { pio31 }]; #IO_0_14 Sch=pio[31]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { pio40 }]; #IO_L5P_T0_34 Sch=pio[40]
|
||||
#set_property -dict { PACKAGE_PIN A2 IOSTANDARD LVCMOS33 } [get_ports { pio41 }]; #IO_L2N_T0_34 Sch=pio[41]
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { pio42 }]; #IO_L2P_T0_34 Sch=pio[42]
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { pio43 }]; #IO_L4N_T0_34 Sch=pio[43]
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { pio44 }]; #IO_L4P_T0_34 Sch=pio[44]
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { pio45 }]; #IO_L3N_T0_DQS_34 Sch=pio[45]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { pio46 }]; #IO_L3P_T0_DQS_34 Sch=pio[46]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { pio47 }]; #IO_L1N_T0_34 Sch=pio[47]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { pio48 }]; #IO_L1P_T0_34 Sch=pio[48]
|
||||
|
||||
## Quad SPI Flash
|
||||
## Note: QSPI clock can only be accessed through the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN L11 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
150
Bibliotheken/digilent-xdc-master/Cora-Z7-07S-Master.xdc
Normal file
150
Bibliotheken/digilent-xdc-master/Cora-Z7-07S-Master.xdc
Normal file
@ -0,0 +1,150 @@
|
||||
## This file is a general .xdc for the Cora Z7-07S Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## PL System Clock
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
|
||||
#set_property -dict { PACKAGE_PIN L10 IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
|
||||
|
||||
##Misc. ChipKit signals
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
|
||||
|
||||
## User Digital I/O Header J1
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
|
||||
152
Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
Normal file
152
Bibliotheken/digilent-xdc-master/Cora-Z7-10-Master.xdc
Normal file
@ -0,0 +1,152 @@
|
||||
## This file is a general .xdc for the Cora Z7-10 Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## PL System Clock
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];#set
|
||||
|
||||
## RGB LEDs
|
||||
set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
|
||||
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L16P_T2_35 Sch=led0_g
|
||||
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports led]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_0_35 Sch=led1_b
|
||||
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L22P_T3_AD7P_35 Sch=led1_g
|
||||
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L23N_T3_35 Sch=led1_r
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L4N_T0_35 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L4P_T0_35 Sch=btn[1]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L17P_T2_34 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L17N_T2_34 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L7P_T1_34 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L7N_T1_34 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L12P_T1_MRCC_34 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L12N_T1_MRCC_34 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22P_T3_34 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22N_T3_34 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8P_T1_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L8N_T1_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_T0_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L1N_T0_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L18P_T2_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L18N_T2_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L4P_T0_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L4N_T0_34 Sch=jb_n[4]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }];
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVCMOS33 } [get_ports { v_p }]; #VP_0 Sch=xadc_v_p
|
||||
#set_property -dict { PACKAGE_PIN L10 IOSTANDARD LVCMOS33 } [get_ports { v_n }]; #VN_0 Sch=xadc_v_n
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { vaux6_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vaux5_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L10N_T1_AD11N_35 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L12P_T1_MRCC_35 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L6P_T0_34 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L1P_T0_AD0P_35 Sch=ad_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L1N_T0_AD0N_35 Sch=ad_n[0]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L15P_T2_DQS_AD12P_35 Sch=ad_p[12]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L15N_T2_DQS_AD12N_35 Sch=ad_n[12]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L2P_T0_AD8P_35 Sch=ad_p[8]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L2N_T0_AD8N_35 Sch=ad_n[8]
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L5P_T0_34 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_L5N_T0_34 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L21P_T3_DQS_34 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L21N_T3_DQS_34 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L19N_T3_VREF_34 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19P_T3_34 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L2N_T0_34 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_L10P_T1_34 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L9P_T1_DQS_34 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L9N_T1_DQS_34 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L20P_T3_34 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L20N_T3_34 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L23N_T3_34 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L23P_T3_34 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_AD10P_35 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L11N_T1_SRCC_35 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L13N_T2_MRCC_35 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16N_T2_35 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9N_T1_DQS_AD3N_35 Sch=ck_io[41]
|
||||
|
||||
## ChipKit SPI
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L10N_T1_34 Sch=ck_miso
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L2P_T0_34 Sch=ck_mosi
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L19P_T3_35 Sch=ck_sck
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L6P_T0_35 Sch=ck_ss
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L24N_T3_34 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L24P_T3_34 Sch=ck_sda
|
||||
|
||||
##Misc. ChipKit signals
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L7N_T1_AD2N_35 Sch=ck_ioa
|
||||
|
||||
## User Digital I/O Header J1
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[1] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=user_dio[1]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[2] }]; #IO_L7P_T1_AD2P_35 Sch=user_dio[2]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[3] }]; #IO_L14P_T2_SRCC_34 Sch=user_dio[3]
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[4] }]; #IO_L14N_T2_SRCC_34 Sch=user_dio[4]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[5] }]; #IO_L13N_T2_MRCC_34 Sch=user_dio[5]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[6] }]; #IO_0_34 Sch=user_dio[6]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[7] }]; #IO_L15P_T2_DQS_34 Sch=user_dio[7]
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[8] }]; #IO_25_34 Sch=user_dio[8]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[9] }]; #IO_L15N_T2_DQS_34 Sch=user_dio[9]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[10] }]; #IO_L16P_T2_34 Sch=user_dio[10]
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { user_dio[11] }]; #IO_L16N_T2_34 Sch=user_dio[11]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { user_dio[12] }]; #IO_L10P_T1_AD11P_35 Sch=user_dio[12]
|
||||
|
||||
115
Bibliotheken/digilent-xdc-master/Eclypse-Z7-Master.xdc
Normal file
115
Bibliotheken/digilent-xdc-master/Eclypse-Z7-Master.xdc
Normal file
@ -0,0 +1,115 @@
|
||||
## This file is a general .xdc for the Eclypse Z7 Rev. B.0
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 125MHz Clock from Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L11P_T1_SRCC Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11N_T1_SRCC Sch=btn[1]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L9N_T1_DQS_AD3N Sch=led0_b
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L8P_T1_AD10P Sch=led0_g
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L8N_T1_AD10N Sch=led0_r
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L9P_T1_DQS_AD3P Sch=led1_b
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L10P_T1_AD11P Sch=led1_g
|
||||
#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L10N_T1_AD11N Sch=led1_r
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0 Sch=ja1_fpga
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_25 Sch=ja2_fpga
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L1N_T0_AD0N Sch=ja3_fpga
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L1P_T0_AD0P Sch=ja4_fpga
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L2N_T0_AD8N Sch=ja7_fpga
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L2P_T0_AD8P Sch=ja8_fpga
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L3N_T0_DQS_AD1N Sch=ja9_fpga
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L3P_T0_DQS_AD1P Sch=ja10_fpga
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L4N_T0 Sch=jb1_fpga
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L4P_T0 Sch=jb2_fpga
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6N_T0_VREF Sch=jb7_fpga
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L6P_T0 Sch=jb8_fpga
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L7N_T1_AD2N Sch=jb9_fpga
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L7P_T1_AD2P Sch=jb10_fpga
|
||||
|
||||
## Syzygy Port A
|
||||
#set_property -dict { PACKAGE_PIN N20 } [get_ports { syzygy_a_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
|
||||
#set_property -dict { PACKAGE_PIN N19 } [get_ports { syzygy_a_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN T17 } [get_ports { syzygy_a_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN T16 } [get_ports { syzygy_a_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN T19 } [get_ports { syzygy_a_d_n[1] }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R19 } [get_ports { syzygy_a_d_p[1] }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN T18 } [get_ports { syzygy_a_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN R18 } [get_ports { syzygy_a_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN P18 } [get_ports { syzygy_a_d_n[3] }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN P17 } [get_ports { syzygy_a_d_p[3] }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN R16 } [get_ports { syzygy_a_d_n[4] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 } [get_ports { syzygy_a_d_p[4] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P15 } [get_ports { syzygy_a_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN N15 } [get_ports { syzygy_a_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN K18 } [get_ports { syzygy_a_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN J18 } [get_ports { syzygy_a_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN K21 } [get_ports { syzygy_a_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN J20 } [get_ports { syzygy_a_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN M19 } [get_ports { syzygy_a_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN L19 } [get_ports { syzygy_a_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
|
||||
#set_property -dict { PACKAGE_PIN K20 } [get_ports { syzygy_a_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
|
||||
#set_property -dict { PACKAGE_PIN L18 } [get_ports { syzygy_a_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
|
||||
#set_property -dict { PACKAGE_PIN K19 } [get_ports { syzygy_a_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
|
||||
#set_property -dict { PACKAGE_PIN L22 } [get_ports { syzygy_a_s[20] }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
|
||||
#set_property -dict { PACKAGE_PIN J22 } [get_ports { syzygy_a_s[21] }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
|
||||
#set_property -dict { PACKAGE_PIN L21 } [get_ports { syzygy_a_s[22] }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
|
||||
#set_property -dict { PACKAGE_PIN J21 } [get_ports { syzygy_a_s[23] }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
|
||||
#set_property -dict { PACKAGE_PIN N22 } [get_ports { syzygy_a_s[24] }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
|
||||
#set_property -dict { PACKAGE_PIN P22 } [get_ports { syzygy_a_s[25] }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
|
||||
#set_property -dict { PACKAGE_PIN M21 } [get_ports { syzygy_a_s[26] }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
|
||||
#set_property -dict { PACKAGE_PIN M22 } [get_ports { syzygy_a_s[27] }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]
|
||||
|
||||
## Syzygy Port B
|
||||
#set_property -dict { PACKAGE_PIN Y16 } [get_ports { syzygy_b_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_b_c2p_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W16 } [get_ports { syzygy_b_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_b_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y15 } [get_ports { syzygy_b_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_b_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN W15 } [get_ports { syzygy_b_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_b_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN W13 } [get_ports { syzygy_b_d_n[1] }]; #IO_L20N_T3 Sch=syzygy_b_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V13 } [get_ports { syzygy_b_d_p[1] }]; #IO_L20P_T3 Sch=syzygy_b_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AA13 } [get_ports { syzygy_b_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_b_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN Y13 } [get_ports { syzygy_b_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_b_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 } [get_ports { syzygy_b_d_n[3] }]; #IO_L24N_T3 Sch=syzygy_b_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AB14 } [get_ports { syzygy_b_d_p[3] }]; #IO_L24P_T3 Sch=syzygy_b_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AA14 } [get_ports { syzygy_b_d_n[4] }]; #IO_L22N_T3 Sch=syzygy_b_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN Y14 } [get_ports { syzygy_b_d_p[4] }]; #IO_L22P_T3 Sch=syzygy_b_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN V15 } [get_ports { syzygy_b_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_b_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V14 } [get_ports { syzygy_b_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_b_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN AB22 } [get_ports { syzygy_b_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_b_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN AA22 } [get_ports { syzygy_b_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_b_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN Y21 } [get_ports { syzygy_b_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_b_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN Y20 } [get_ports { syzygy_b_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_b_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN W18 } [get_ports { syzygy_b_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_b_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W17 } [get_ports { syzygy_b_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AA18 } [get_ports { syzygy_b_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_b_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AA19 } [get_ports { syzygy_b_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_b_s[17]
|
||||
#set_property -dict { PACKAGE_PIN Y18 } [get_ports { syzygy_b_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_b_s[18]
|
||||
#set_property -dict { PACKAGE_PIN Y19 } [get_ports { syzygy_b_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_b_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AB20 } [get_ports { syzygy_b_s[20] }]; #IO_L10N_T1 Sch=syzygy_b_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AB21 } [get_ports { syzygy_b_s[21] }]; #IO_L8N_T1 Sch=syzygy_b_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AB19 } [get_ports { syzygy_b_s[22] }]; #IO_L10P_T1 Sch=syzygy_b_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AA21 } [get_ports { syzygy_b_s[23] }]; #IO_L8P_T1 Sch=syzygy_b_s[23]
|
||||
#set_property -dict { PACKAGE_PIN U16 } [get_ports { syzygy_b_s[24] }]; #IO_L15N_T2_DQS Sch=syzygy_b_s[24]
|
||||
#set_property -dict { PACKAGE_PIN U15 } [get_ports { syzygy_b_s[25] }]; #IO_L15P_T2_DQS Sch=syzygy_b_s[25]
|
||||
#set_property -dict { PACKAGE_PIN V17 } [get_ports { syzygy_b_s[26] }]; #IO_L16N_T2 Sch=syzygy_b_s[26]
|
||||
#set_property -dict { PACKAGE_PIN U17 } [get_ports { syzygy_b_s[27] }]; #IO_L16P_T2 Sch=syzygy_b_s[27]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L16P_T2 Sch=crypto_sda
|
||||
|
||||
## Miscellaneous
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[0] }]; #IO_L18N_T2_AD13N Sch=mcu_rsvd[1]
|
||||
#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L18P_T2_AD13P Sch=mcu_rsvd[2]
|
||||
437
Bibliotheken/digilent-xdc-master/Genesys-2-Master.xdc
Normal file
437
Bibliotheken/digilent-xdc-master/Genesys-2-Master.xdc
Normal file
@ -0,0 +1,437 @@
|
||||
#### This file is a general .xdc for the Genesys 2 Rev. H
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_0_17 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L19P_T3_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L6P_T0_17 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L19P_T3_A22_15 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_25_15 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L8P_T1_D11_14 Sch=sw[7]
|
||||
|
||||
## USB HIDs For Both Mouse and Keyboard
|
||||
#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0]
|
||||
#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0]
|
||||
|
||||
## UART
|
||||
#set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L1P_T0_12 Sch=uart_rx_out
|
||||
#set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_0_12 Sch=uart_tx_in
|
||||
|
||||
## SD Card
|
||||
#set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
|
||||
#set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
|
||||
|
||||
## Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0]
|
||||
#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1]
|
||||
#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata
|
||||
#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda
|
||||
|
||||
## Ethernet
|
||||
#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
|
||||
#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
|
||||
#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en
|
||||
|
||||
## VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4]
|
||||
#set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5]
|
||||
#set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6]
|
||||
#set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4]
|
||||
#set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5]
|
||||
#set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6]
|
||||
#set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4]
|
||||
#set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5]
|
||||
#set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6]
|
||||
#set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs
|
||||
|
||||
## HDMI in
|
||||
#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec
|
||||
#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L14P_T2_SRCC_13 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_hpa
|
||||
#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17P_T2_13 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_13 Sch=hdmi_rx_sda
|
||||
#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L21N_T3_DQS_13 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L21P_T3_DQS_13 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[2]
|
||||
|
||||
## HDMI out
|
||||
#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L1N_T0_12 Sch=hdmi_tx_cec
|
||||
#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L6N_T0_VREF_12 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L6P_T0_12 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L23N_T3_13 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L23P_T3_13 Sch=hdmi_tx_sda
|
||||
#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_12 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_12 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L4N_T0_12 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L4P_T0_12 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L7N_T1_12 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L7P_T1_12 Sch=hdmi_tx_p[2]
|
||||
|
||||
## OLED Display
|
||||
#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { oled_dc }]; #IO_L18N_T2_32 Sch=oled_dc
|
||||
#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { oled_res }]; #IO_L18P_T2_32 Sch=oled_res
|
||||
#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { oled_sclk }]; #IO_L12P_T1_MRCC_32 Sch=oled_sclk
|
||||
#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { oled_sdin }]; #IO_L24N_T3_32 Sch=oled_sdin
|
||||
#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_L3P_T0_DQS_12 Sch=oled_vbat
|
||||
#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { oled_vdd }]; #IO_L12N_T1_MRCC_32 Sch=oled_vdd
|
||||
|
||||
## PMOD Header JA
|
||||
#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4]
|
||||
|
||||
## PMOD Header JB
|
||||
#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4]
|
||||
|
||||
## PMOD Header JC
|
||||
#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L19P_T3_13 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20P_T3_13 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L18N_T2_13 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15P_T2_DQS_13 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L19N_T3_VREF_13 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L18P_T2_13 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L15N_T2_DQS_13 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_13 Sch=jc[10]
|
||||
|
||||
## PMOD Header JD
|
||||
#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L1P_T0_13 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10]
|
||||
|
||||
## XADC Header
|
||||
#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xadc0r_n
|
||||
#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xadc0r_p
|
||||
#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xadc1r_n
|
||||
#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xadc1r_p
|
||||
#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xadc8r_n
|
||||
#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xadc8r_p
|
||||
#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L4N_T0_AD9N_15 Sch=xadc9r_n
|
||||
#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L4P_T0_AD9P_15 Sch=xadc9r_p
|
||||
|
||||
## FMC
|
||||
#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { FMC_CLK_DIR }]; #IO_L10N_T1_13 Sch=fmc_clk_dir
|
||||
#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_17 Sch=fmc_clk0_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_17 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L14N_T2_SRCC_16 Sch=fmc_clk1_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L14P_T2_SRCC_16 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_N[2] }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2]
|
||||
#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_P[2] }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2]
|
||||
#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[00] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_ha_n[00]
|
||||
#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[00] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_ha_p[00]
|
||||
#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[01] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_ha_n[01]
|
||||
#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[01] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_ha_p[01]
|
||||
#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[02] }]; #IO_L22N_T3_A16_15 Sch=fmc_ha_n[02]
|
||||
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[02] }]; #IO_L22P_T3_A17_15 Sch=fmc_ha_p[02]
|
||||
#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[03] }]; #IO_L18N_T2_A23_15 Sch=fmc_ha_n[03]
|
||||
#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[03] }]; #IO_L18P_T2_A24_15 Sch=fmc_ha_p[03]
|
||||
#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[04] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_ha_n[04]
|
||||
#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[04] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_ha_p[04]
|
||||
#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[05] }]; #IO_L7N_T1_AD10N_15 Sch=fmc_ha_n[05]
|
||||
#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[05] }]; #IO_L7P_T1_AD10P_15 Sch=fmc_ha_p[05]
|
||||
#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[06] }]; #IO_L17N_T2_A25_15 Sch=fmc_ha_n[06]
|
||||
#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[06] }]; #IO_L17P_T2_A26_15 Sch=fmc_ha_p[06]
|
||||
#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[07] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_ha_n[07]
|
||||
#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[07] }]; #IO_L15P_T2_DQS_15 Sch=fmc_ha_p[07]
|
||||
#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[08] }]; #IO_L8N_T1_AD3N_15 Sch=fmc_ha_n[08]
|
||||
#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[08] }]; #IO_L8P_T1_AD3P_15 Sch=fmc_ha_p[08]
|
||||
#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[09] }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fmc_ha_n[09]
|
||||
#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[09] }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fmc_ha_p[09]
|
||||
#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[10] }]; #IO_L20N_T3_A19_15 Sch=fmc_ha_n[10]
|
||||
#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[10] }]; #IO_L20P_T3_A20_15 Sch=fmc_ha_p[10]
|
||||
#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[11] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_ha_n[11]
|
||||
#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[11] }]; #IO_L21P_T3_DQS_15 Sch=fmc_ha_p[11]
|
||||
#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[12] }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=fmc_ha_n[12]
|
||||
#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[12] }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=fmc_ha_p[12]
|
||||
#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[13] }]; #IO_L10N_T1_AD4N_15 Sch=fmc_ha_n[13]
|
||||
#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[13] }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13]
|
||||
#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[14] }]; #IO_L16N_T2_A27_15 Sch=fmc_ha_n[14]
|
||||
#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[14] }]; #IO_L16P_T2_A28_15 Sch=fmc_ha_p[14]
|
||||
#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[15] }]; #IO_L5N_T0_AD2N_15 Sch=fmc_ha_n[15]
|
||||
#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[15] }]; #IO_L5P_T0_AD2P_15 Sch=fmc_ha_p[15]
|
||||
#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[16] }]; #IO_L24N_T3_RS0_15 Sch=fmc_ha_n[16]
|
||||
#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[16] }]; #IO_L24P_T3_RS1_15 Sch=fmc_ha_p[16]
|
||||
#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[17] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_ha_n[17]
|
||||
#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[17] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_ha_p[17]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[18] }]; #IO_L14N_T2_SRCC_17 Sch=fmc_ha_n[18]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[18] }]; #IO_L14P_T2_SRCC_17 Sch=fmc_ha_p[18]
|
||||
#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[19] }]; #IO_L22N_T3_16 Sch=fmc_ha_n[19]
|
||||
#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[19] }]; #IO_L22P_T3_16 Sch=fmc_ha_p[19]
|
||||
#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[20] }]; #IO_L21N_T3_DQS_16 Sch=fmc_ha_n[20]
|
||||
#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[20] }]; #IO_L21P_T3_DQS_16 Sch=fmc_ha_p[20]
|
||||
#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[21] }]; #IO_L20N_T3_16 Sch=fmc_ha_n[21]
|
||||
#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[21] }]; #IO_L20P_T3_16 Sch=fmc_ha_p[21]
|
||||
#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[22] }]; #IO_L8N_T1_17 Sch=fmc_ha_n[22]
|
||||
#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[22] }]; #IO_L8P_T1_17 Sch=fmc_ha_p[22]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[23] }]; #IO_L16N_T2_17 Sch=fmc_ha_n[23]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[23] }]; #IO_L16P_T2_17 Sch=fmc_ha_p[23]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[00] }]; #IO_L12N_T1_MRCC_18 Sch=fmc_hb_n[00]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[00] }]; #IO_L12P_T1_MRCC_18 Sch=fmc_hb_p[00]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[01] }]; #IO_L7N_T1_18 Sch=fmc_hb_n[01]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[01] }]; #IO_L7P_T1_18 Sch=fmc_hb_p[01]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[02] }]; #IO_L2N_T0_18 Sch=fmc_hb_n[02]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[02] }]; #IO_L2P_T0_18 Sch=fmc_hb_p[02]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[03] }]; #IO_L11N_T1_SRCC_18 Sch=fmc_hb_n[03]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[03] }]; #IO_L11P_T1_SRCC_18 Sch=fmc_hb_p[03]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[04] }]; #IO_L9N_T1_DQS_18 Sch=fmc_hb_n[04]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[04] }]; #IO_L9P_T1_DQS_18 Sch=fmc_hb_p[04]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[05] }]; #IO_L1N_T0_18 Sch=fmc_hb_n[05]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[05] }]; #IO_L1P_T0_18 Sch=fmc_hb_p[05]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[06] }]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[06] }]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[07] }]; #IO_L22N_T3_18 Sch=fmc_hb_n[07]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[07] }]; #IO_L22P_T3_18 Sch=fmc_hb_p[07]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[08] }]; #IO_L5N_T0_18 Sch=fmc_hb_n[08]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[08] }]; #IO_L5P_T0_18 Sch=fmc_hb_p[08]
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[09] }]; #IO_L23N_T3_18 Sch=fmc_hb_n[09]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[09] }]; #IO_L23P_T3_18 Sch=fmc_hb_p[09]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[10] }]; #IO_L8N_T1_18 Sch=fmc_hb_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[10] }]; #IO_L8P_T1_18 Sch=fmc_hb_p[10]
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[11] }]; #IO_L18N_T2_18 Sch=fmc_hb_n[11]
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[11] }]; #IO_L18P_T2_18 Sch=fmc_hb_p[11]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[12] }]; #IO_L17N_T2_18 Sch=fmc_hb_n[12]
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[12] }]; #IO_L17P_T2_18 Sch=fmc_hb_p[12]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[13] }]; #IO_L15N_T2_DQS_18 Sch=fmc_hb_n[13]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[13] }]; #IO_L15P_T2_DQS_18 Sch=fmc_hb_p[13]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[14] }]; #IO_L10N_T1_18 Sch=fmc_hb_n[14]
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[14] }]; #IO_L10P_T1_18 Sch=fmc_hb_p[14]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[15] }]; #IO_L3N_T0_DQS_18 Sch=fmc_hb_n[15]
|
||||
#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[15] }]; #IO_L3P_T0_DQS_18 Sch=fmc_hb_p[15]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[16] }]; #IO_L4N_T0_18 Sch=fmc_hb_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[16] }]; #IO_L4P_T0_18 Sch=fmc_hb_p[16]
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[17] }]; #IO_L13N_T2_MRCC_18 Sch=fmc_hb_n[17]
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[17] }]; #IO_L13P_T2_MRCC_18 Sch=fmc_hb_p[17]
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[18] }]; #IO_L20N_T3_18 Sch=fmc_hb_n[18]
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[18] }]; #IO_L20P_T3_18 Sch=fmc_hb_p[18]
|
||||
#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[19] }]; #IO_L16N_T2_18 Sch=fmc_hb_n[19]
|
||||
#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[19] }]; #IO_L16P_T2_18 Sch=fmc_hb_p[19]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[20] }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20]
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[20] }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[21] }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[21] }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21]
|
||||
#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[00] }]; #IO_L13N_T2_MRCC_16 Sch=fmc_la_n[00]
|
||||
#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[00] }]; #IO_L13P_T2_MRCC_16 Sch=fmc_la_p[00]
|
||||
#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[01] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la_n[01]
|
||||
#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[01] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la_p[01]
|
||||
#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L24N_T3_16 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN H30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L24P_T3_16 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L18N_T2_16 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L18P_T2_16 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L23N_T3_16 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L23P_T3_16 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L17N_T2_16 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L17P_T2_16 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L16N_T2_16 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L16P_T2_16 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L7N_T1_16 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L7P_T1_16 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L10N_T1_16 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L10P_T1_16 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L5N_T0_16 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L5P_T0_16 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L4N_T0_16 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L4P_T0_16 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L1N_T0_16 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L1P_T0_16 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L2N_T0_16 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L2P_T0_16 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[17] }]; #IO_L11N_T1_SRCC_17 Sch=fmc_la_n[17]
|
||||
#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[17] }]; #IO_L11P_T1_SRCC_17 Sch=fmc_la_p[17]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[18] }]; #IO_L13N_T2_MRCC_17 Sch=fmc_la_n[18]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[18] }]; #IO_L13P_T2_MRCC_17 Sch=fmc_la_p[18]
|
||||
#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L7N_T1_17 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L7P_T1_17 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L9N_T1_DQS_17 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L9P_T1_DQS_17 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L5N_T0_17 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L5P_T0_17 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0_DQS_17 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0_DQS_17 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L18N_T2_17 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L18P_T2_17 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L2N_T0_17 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L2P_T0_17 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L10N_T1_17 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L10P_T1_17 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L23N_T3_17 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L23P_T3_17 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L21N_T3_DQS_17 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L21P_T3_DQS_17 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L4N_T0_17 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L4P_T0_17 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L22N_T3_17 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L22P_T3_17 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L20N_T3_17 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L20P_T3_17 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L17N_T2_17 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L17P_T2_17 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L1N_T0_17 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L1P_T0_17 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L15N_T2_DQS_17 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L15P_T2_DQS_17 Sch=fmc_la_p[33]
|
||||
#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SCL }]; #IO_L9P_T1_DQS_12 Sch=fmc_scl
|
||||
#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SDA }]; #IO_L9N_T1_DQS_12 Sch=fmc_sda
|
||||
|
||||
## Fan Control
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { FAN_PWM }]; #IO_25_14 Sch=fan_pwm
|
||||
#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tach
|
||||
|
||||
## DPTI
|
||||
## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins.
|
||||
#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { PROG_CLKO }]; #IO_L12P_T1_MRCC_13 Sch=prog_clko
|
||||
#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[0] }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck
|
||||
#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[1] }]; #IO_L2P_T0_13 Sch=prog_d1/mosi
|
||||
#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[2] }]; #IO_L2N_T0_13 Sch=prog_d2/miso
|
||||
#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[3] }]; #IO_L4P_T0_13 Sch=prog_d3/ss
|
||||
#set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[4] }]; #IO_L4N_T0_13 Sch=prog_d[4]
|
||||
#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[5] }]; #IO_L3P_T0_DQS_13 Sch=prog_d[5]
|
||||
#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[6] }]; #IO_L3N_T0_DQS_13 Sch=prog_d[6]
|
||||
#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[7] }]; #IO_L1N_T0_13 Sch=prog_d[7]
|
||||
#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { PROG_OEN }]; #IO_L7N_T1_13 Sch=prog_oen
|
||||
#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { PROG_RDN }]; #IO_L6N_T0_VREF_13 Sch=prog_rdn
|
||||
#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { PROG_RXFN }]; #IO_L10P_T1_13 Sch=prog_rxfn
|
||||
#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { PROG_SIWUN }]; #IO_L5N_T0_13 Sch=prog_siwun
|
||||
#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien
|
||||
#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { PROG_TXEN }]; #IO_L6P_T0_13 Sch=prog_txen
|
||||
#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { PROG_WRN }]; #IO_L12N_T1_MRCC_13 Sch=prog_wrn
|
||||
|
||||
## DSPI
|
||||
## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins.
|
||||
#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien
|
||||
#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_SCK }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck
|
||||
#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_MOSI }]; #IO_L2P_T0_13 Sch=prog_d1/mosi
|
||||
#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_MISO }]; #IO_L2N_T0_13 Sch=prog_d2/miso
|
||||
#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SS }]; #IO_L4P_T0_13 Sch=prog_d3/ss
|
||||
|
||||
## QSPI
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
|
||||
#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
|
||||
#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
|
||||
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]
|
||||
|
||||
## IIC Bus
|
||||
#set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { SYS_SCL }]; #IO_L16P_T2_13 Sch=sys_scl
|
||||
#set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { SYS_SDA }]; #IO_L16N_T2_13 Sch=sys_sda
|
||||
|
||||
## Display Port IN
|
||||
#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_N }]; #IO_L15N_T2_DQS_32 Sch=rx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_P }]; #IO_L17P_T2_32 Sch=rx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_P }]; #IO_L15P_T2_DQS_32 Sch=rx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { RX_HPD }]; #IO_L10N_T1_12 Sch=rx_hpd
|
||||
|
||||
## Display Port OUT
|
||||
#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_N }]; #IO_L14N_T2_SRCC_32 Sch=tx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_N }]; #IO_L16N_T2_32 Sch=tx_aux_ch_n
|
||||
#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_P }]; #IO_L16P_T2_32 Sch=tx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_P }]; #IO_L14P_T2_SRCC_32 Sch=tx_aux_ch_p
|
||||
#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { TX_HPD }]; #IO_L10P_T1_12 Sch=tx_hpd
|
||||
|
||||
## USB
|
||||
#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_CLK }]; #IO_L13P_T2_MRCC_32 Sch=usb_otg_clk
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[0] }]; #IO_L19N_T3_VREF_32 Sch=usb_otg_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[1] }]; #IO_L19P_T3_32 Sch=usb_otg_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[2] }]; #IO_L21N_T3_DQS_32 Sch=usb_otg_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[3] }]; #IO_L21P_T3_DQS_32 Sch=usb_otg_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[4] }]; #IO_L20N_T3_32 Sch=usb_otg_d[4]
|
||||
#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[5] }]; #IO_L20P_T3_32 Sch=usb_otg_d[5]
|
||||
#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[6] }]; #IO_L22N_T3_32 Sch=usb_otg_d[6]
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[7] }]; #IO_L22P_T3_32 Sch=usb_otg_d[7]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_DIR }]; #IO_L24P_T3_32 Sch=usb_otg_dir
|
||||
#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_NXT }]; #IO_L23N_T3_32 Sch=usb_otg_nxt
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_RESETB }]; #IO_25_VRP_32 Sch=usb_otg_resetb
|
||||
#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_STP }]; #IO_L23P_T3_32 Sch=usb_otg_stp
|
||||
#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_VBUSOC }]; #IO_L6N_T0_VREF_32 Sch=usb_otg_vbusoc
|
||||
|
||||
272
Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-D-Master.xdc
Normal file
272
Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-D-Master.xdc
Normal file
@ -0,0 +1,272 @@
|
||||
#### This file is a general .xdc for the Genesys ZU-3EG Rev. D
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
|
||||
## Crypto
|
||||
#set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
|
||||
|
||||
# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
|
||||
# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
|
||||
# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
|
||||
# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
|
||||
# Might need CLOCK_DEDICATED_ROUTE FALSE
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
|
||||
|
||||
## MIPI A Port
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
|
||||
##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
|
||||
##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
|
||||
|
||||
## MIPI B Port
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
|
||||
##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
|
||||
##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
|
||||
|
||||
## Audio CODEC I2S, I2C
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
|
||||
|
||||
## PMOD XADC
|
||||
## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
|
||||
#set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
|
||||
#set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
|
||||
|
||||
## Platform MCU signals
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
|
||||
#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
|
||||
#set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
|
||||
|
||||
##DisplayPort AUX channel over EMIO
|
||||
#set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
|
||||
#set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
|
||||
|
||||
## Mini PCIe Auxiliary
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }]; #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
|
||||
|
||||
## USB 2.0 Overcurrent EMIO
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
|
||||
|
||||
## Ethernet JTAG
|
||||
#set_property -dict { PACKAGE_PIN F7 LVCMOS12 } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
|
||||
#set_property -dict { PACKAGE_PIN F8 LVCMOS12 } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
|
||||
#set_property -dict { PACKAGE_PIN E8 LVCMOS12 } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
|
||||
#set_property -dict { PACKAGE_PIN E9 LVCMOS12 } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
|
||||
|
||||
## PMOD JB
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
|
||||
|
||||
## PMOD JC
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
|
||||
|
||||
## PMOD JD
|
||||
#set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
|
||||
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
|
||||
#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
|
||||
#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
|
||||
#set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
|
||||
#set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
|
||||
#set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
|
||||
#set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
|
||||
|
||||
## LED
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
|
||||
|
||||
## GTH reference clock jitter filter auxiliary
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
|
||||
|
||||
## MUX I2C
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
|
||||
|
||||
## SYZYGY
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AE3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AD7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AG6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }]; #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AF3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AE7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN AG5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }]; #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
|
||||
#set_property -dict { PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AD5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
|
||||
|
||||
## FMC connector
|
||||
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN L7 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN K4 IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN J9 IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN T7 IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN L8 IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN M8 IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN J7 IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN N7 IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN P6 IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN P7 IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN K7 IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K8 IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN AD1 IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AD2 IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AH9 IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AG9 IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AC3 IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN AG1 IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN AF1 IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN AC8 IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN AH1 IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN AH2 IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN AF6 IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN AF7 IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN AH3 IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN AG3 IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN AD9 IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN AC9 IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN AH4 IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN AG4 IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN AE8 IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN AE9 IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN AH7 IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN AH8 IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN AC7 IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN AG8 IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN AC6 IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
|
||||
|
||||
## Power-good input for VADJ supply rail
|
||||
#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { pg_vadj_r }]; #IO_L12N_AD8N_44/24 Sch=pg_vadj_r
|
||||
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
|
||||
|
||||
#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
|
||||
|
||||
|
||||
|
||||
|
||||
269
Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-Master.xdc
Normal file
269
Bibliotheken/digilent-xdc-master/Genesys-ZU-3EG-Master.xdc
Normal file
@ -0,0 +1,269 @@
|
||||
#### This file is a general .xdc for the Genesys ZU-3EG Rev. B
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
|
||||
## Crypto
|
||||
#set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
|
||||
|
||||
# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
|
||||
# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
|
||||
# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
|
||||
# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
|
||||
# Might need CLOCK_DEDICATED_ROUTE FALSE
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
|
||||
|
||||
## MIPI A Port
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
|
||||
##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
|
||||
##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
|
||||
|
||||
## MIPI B Port
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
|
||||
##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
|
||||
##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
|
||||
|
||||
## Audio CODEC I2S, I2C
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
|
||||
|
||||
## PMOD XADC
|
||||
## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
|
||||
#set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
|
||||
#set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
|
||||
|
||||
## Platform MCU signals
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
|
||||
#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
|
||||
#set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
|
||||
|
||||
##DisplayPort AUX channel over EMIO
|
||||
#set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
|
||||
#set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
|
||||
|
||||
## Mini PCIe Auxiliary
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }]; #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
|
||||
|
||||
## USB 2.0 Overcurrent EMIO
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
|
||||
|
||||
## Ethernet JTAG
|
||||
#set_property -dict { PACKAGE_PIN F7 LVCMOS12 } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
|
||||
#set_property -dict { PACKAGE_PIN F8 LVCMOS12 } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
|
||||
#set_property -dict { PACKAGE_PIN E8 LVCMOS12 } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
|
||||
#set_property -dict { PACKAGE_PIN E9 LVCMOS12 } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
|
||||
|
||||
## PMOD JB
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
|
||||
|
||||
## PMOD JC
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
|
||||
|
||||
## PMOD JD
|
||||
#set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
|
||||
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
|
||||
#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
|
||||
#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
|
||||
#set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
|
||||
#set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
|
||||
#set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
|
||||
#set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
|
||||
|
||||
## LED
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
|
||||
|
||||
## GTH reference clock jitter filter auxiliary
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
|
||||
|
||||
## MUX I2C
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
|
||||
|
||||
## SYZYGY
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AE3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AD7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AG6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }]; #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AF3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AE7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN AG5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }]; #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
|
||||
#set_property -dict { PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AD5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
|
||||
|
||||
## FMC connector
|
||||
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN L7 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN K4 IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN J9 IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN T7 IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN L8 IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN M8 IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN J7 IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN N7 IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN P6 IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN P7 IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN K7 IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K8 IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN AD1 IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AD2 IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AH9 IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AG9 IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AC3 IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN AG1 IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN AF1 IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN AC8 IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN AH1 IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN AH2 IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN AF6 IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN AF7 IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN AH3 IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN AG3 IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN AD9 IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN AC9 IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN AH4 IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN AG4 IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN AE8 IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN AE9 IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN AH7 IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN AH8 IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN AC7 IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN AG8 IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN AC6 IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
|
||||
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
|
||||
|
||||
#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
|
||||
|
||||
|
||||
|
||||
|
||||
272
Bibliotheken/digilent-xdc-master/Genesys-ZU-5EV-D-Master.xdc
Normal file
272
Bibliotheken/digilent-xdc-master/Genesys-ZU-5EV-D-Master.xdc
Normal file
@ -0,0 +1,272 @@
|
||||
#### This file is a general .xdc for the Genesys ZU-5EV Rev. D
|
||||
#### To use it in a project:
|
||||
#### - uncomment the lines corresponding to used pins
|
||||
#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
#set_property DCI_CASCADE {64} [get_iobanks 65]
|
||||
|
||||
## Crypto
|
||||
#set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L5P_HDGC_44/24 Sch=crypto_sda
|
||||
|
||||
# Sysclk is a 125 MHz PL reference clock generated by the external Ethernet PHY
|
||||
# It connects to an HDGC pin, so it has direct connection only to BUFG primitives.
|
||||
# When using it as input clock to CMT primitives (MMCM/PLL), it needs to go through
|
||||
# BUFG first. Choose "Global Buffer" in Clocking Wizard IP customization.
|
||||
# Might need CLOCK_DEDICATED_ROUTE FALSE
|
||||
#set_property -dict { PACKAGE_PIN E12 IOSTANDARD LVCMOS18 } [get_ports { sysclk }];
|
||||
|
||||
## MIPI A Port
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS12 } [get_ports { mipi_a_pwup_ls }]; #IO_L22N_T3U_N7_DBC_AD0N_66 Sch=mipi_a_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN G1 [get_ports mipi_a_clk_p] #IO_L1P_T0L_N0_DBC_66 Sch=mipi_a_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_clk_n]
|
||||
##set_property PACKAGE_PIN E1 [get_ports mipi_a_lane_p[0]] #IO_L2P_T0L_N2_66 Sch=mipi_a_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[0]]
|
||||
##set_property PACKAGE_PIN F2 [get_ports mipi_a_lane_p[1]] #IO_L3P_T0L_N4_AD15P_66 Sch=mipi_a_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_a_lane_n[1]]]
|
||||
|
||||
## MIPI B Port
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS12 } [get_ports { mipi_b_pwup_ls }]; #IO_L23P_T3U_N8_66 Sch=mipi_b_pwup_ls
|
||||
## Commented, since it will be defined in IP XDC.
|
||||
##set_property PACKAGE_PIN B5 [get_ports mipi_b_clk_p] #IO_L19P_T3L_N0_DBC_AD9P_66 Sch=mipi_b_clk_p
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_p]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_clk_n]
|
||||
##set_property PACKAGE_PIN C6 [get_ports mipi_b_lane_p[0]] #IO_L20P_T3L_N2_AD1P_66 Sch=mipi_b_lane_p[0]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[0]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[0]]
|
||||
##set_property PACKAGE_PIN A7 [get_ports mipi_b_lane_p[1]] #IO_L21P_T3L_N4_AD8P_66 Sch=mipi_b_lane_p[1]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_p[1]]
|
||||
##set_property IOSTANDARD MIPI_DPHY_DCI [get_ports mipi_b_lane_n[1]]
|
||||
|
||||
## Audio CODEC I2S, I2C
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L11N_AD9N_45/25 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS18 } [get_ports { aud_sda_io }]; #IO_L12P_AD8P_45/25 Sch=aud_sda
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_AD10N_45/25 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L12N_AD8N_45/25 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L9P_AD11P_45/25 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L10P_AD10P_45/25 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L8N_HDGC_45/25 Sch=aud_dac_sdata
|
||||
|
||||
## PMOD XADC
|
||||
## Commented because pins are contrained by System Management Wizard. Only >2018.2 lets us select bank 43.
|
||||
#set_property -dict { PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_n }]; #IO_L10N_AD2N_43/44 Sch=ja1_r_n
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { ja1_r_p }]; #IO_L10P_AD2P_43/44 Sch=ja1_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_n }]; #IO_L9N_AD3N_43/44 Sch=ja2_r_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD LVCMOS18 } [get_ports { ja2_r_p }]; #IO_L9P_AD3P_43/44 Sch=ja2_r_p
|
||||
#set_property -dict { PACKAGE_PIN AB9 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_n }]; #IO_L12N_AD0N_43/44 Sch=ja3_r_n
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD LVCMOS18 } [get_ports { ja3_r_p }]; #IO_L12P_AD0P_43/44 Sch=ja3_r_p
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_n }]; #IO_L11N_AD1N_43/44 Sch=ja4_r_n
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports { ja4_r_p }]; #IO_L11P_AD1P_43/44 Sch=ja4_r_p
|
||||
|
||||
## Platform MCU signals
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[0] }]; #IO_L6P_HDGC_44/24 Sch=vadj_level[0]
|
||||
#set_property -dict { PACKAGE_PIN AC13 IOSTANDARD LVCMOS33 } [get_ports { vadj_level[1] }]; #IO_L6N_HDGC_44/24 Sch=vadj_level[1]
|
||||
#set_property -dict { PACKAGE_PIN G10 IOSTANDARD LVCMOS18 } [get_ports { vadj_auton }]; #IO_L3N_AD13N_45/25 Sch=vadj_auton
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_detectedn }]; #IO_L3P_AD13P_45/25 Sch=syzygy_detectedn
|
||||
|
||||
##DisplayPort AUX channel over EMIO
|
||||
#set_property -dict { PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_din }]; #IO_L2N_AD14N_45/25 Sch=dp_aux_din
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_doe }]; #IO_L2P_AD14P_45/25 Sch=dp_aux_doe
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_dout }]; #IO_L1P_AD15P_45/25 Sch=dp_aux_dout
|
||||
#set_property -dict { PACKAGE_PIN J10 IOSTANDARD LVCMOS18 } [get_ports { dp_aux_hotplug_detect }]; #IO_L1N_AD15N_45/25 Sch=dp_aux_hotplug_detect
|
||||
|
||||
## Mini PCIe Auxiliary
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pcie_w_disable2n }]; #IO_L12P_AD8P_44/24 Sch=pcie_w_disable2n
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS12 } [get_ports { pcie_w_disable[1] }]; #IO_L9P_T1L_N4_AD12P_66 Sch=pcie_w_disable[1]
|
||||
|
||||
## USB 2.0 Overcurrent EMIO
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS12 PULLUP true } [get_ports { usb20_ocn }];#IO_L18N_T2U_N11_AD2N_66 Sch=usb20_ocn
|
||||
|
||||
## Ethernet JTAG
|
||||
#set_property -dict { PACKAGE_PIN F7 LVCMOS12 } [get_ports { eth_tms_ls }]; #IO_L16N_T2U_N7_QBC_AD3N_66 Sch=eth_tms_ls
|
||||
#set_property -dict { PACKAGE_PIN F8 LVCMOS12 } [get_ports { eth_tdi_ls }]; #IO_L17P_T2U_N8_AD10P_66 Sch=eth_tdi_ls
|
||||
#set_property -dict { PACKAGE_PIN E8 LVCMOS12 } [get_ports { eth_tck_ls }]; #IO_L17N_T2U_N9_AD10N_66 Sch=eth_tck_ls
|
||||
#set_property -dict { PACKAGE_PIN E9 LVCMOS12 } [get_ports { eth_tdo_ls }]; #IO_L18P_T2U_N10_AD2P_66 Sch=eth_tdo_ls
|
||||
|
||||
## PMOD JB
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L8N_HDGC_AD4N_46/26 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L2N_AD10N_46/26 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L1P_AD11P_46/26 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN AG13 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L8P_HDGC_AD4P_46/26 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L6P_HDGC_AD6P_46/26 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN AF13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L2P_AD10P_46/26 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L5P_HDGC_AD7P_46/26 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN AH13 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L1N_AD11N_46/26 Sch=jb[10]
|
||||
|
||||
## PMOD JC
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L6N_HDGC_AD6N_46/26 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L7P_HDGC_AD5P_46/26 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L3P_AD9P_46/26 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L5N_HDGC_AD7N_46/26 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L7N_HDGC_AD5N_46/26 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L4N_AD8N_46/26 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L4P_AD8P_46/26 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L3N_AD9N_46/26 Sch=jc[10]
|
||||
|
||||
## PMOD JD
|
||||
#set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L4P_AD12P_44/24 Sch=jd[1]
|
||||
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L2P_AD14P_44/24 Sch=jd[2]
|
||||
#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L2N_AD14N_44/24 Sch=jd[3]
|
||||
#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L3P_AD13P_44/24 Sch=jd[4]
|
||||
#set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L1N_AD15N_44/24 Sch=jd[7]
|
||||
#set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L4N_AD12N_44/24 Sch=jd[8]
|
||||
#set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L1P_AD15P_44/24 Sch=jd[9]
|
||||
#set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L3N_AD13N_44/24 Sch=jd[10]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B10 IOSTANDARD LVCMOS18 } [get_ports { btn[2] }]; #IO_L9N_AD11N_45/25 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports { btn[3] }]; #IO_L4N_AD12N_45/25 Sch=btn[3]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports { btn[4] }]; #IO_L4P_AD12P_45/25 Sch=btn[4]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS18 } [get_ports { btn[5] }]; #IO_L6P_HDGC_45/25 Sch=btn[5]
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS18 } [get_ports { btn[6] }]; #IO_L11P_AD9P_45/25 Sch=btn[6]
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L8N_HDGC_44/24 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L10N_AD10N_44/24 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L11P_AD9P_44/24 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L8P_HDGC_44/24 Sch=sw[3]
|
||||
|
||||
## LED
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ld[0] }]; #IO_L12P_AD0P_46/26 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { ld[1] }]; #IO_L12N_AD0N_46/26 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ld[2] }]; #IO_L11P_AD1P_46/26 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ld[3] }]; #IO_L11N_AD1N_46/26 Sch=ld[4]
|
||||
|
||||
## RGB LED
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS12 } [get_ports { ld5_b }]; #IO_L23N_T3U_N9_66 Sch=ld5_b
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS12 } [get_ports { ld5_g }]; #IO_L24N_T3U_N11_66 Sch=ld5_g
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS12 } [get_ports { ld5_r }]; #IO_L24P_T3U_N10_66 Sch=ld5_r
|
||||
|
||||
## GTH reference clock jitter filter auxiliary
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS12 } [get_ports { clkgth_intrn_ls }]; #IO_L11N_T1U_N9_GC_66 Sch=clkgth_intrn_ls
|
||||
#set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS12 } [get_ports { clkgth_loln_ls }]; #IO_L13N_T2L_N1_GC_QBC_66 Sch=clkgth_loln_ls
|
||||
#set_property -dict { PACKAGE_PIN G8 IOSTANDARD LVCMOS12 } [get_ports { clkgth_rst }]; #IO_L16P_T2U_N6_QBC_AD3P_66 Sch=clkgth_rst
|
||||
|
||||
## MUX I2C
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS12 } [get_ports { fpga_mux_rst }]; #IO_L15N_T2L_N5_AD11N_66 Sch=fpga_mux_rst
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_scl_ls }]; #IO_L9P_AD3P_46/26 Sch=mux_scl_ls
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { mux_sda_ls }]; #IO_L9N_AD3N_46/26 Sch=mux_sda_ls
|
||||
|
||||
## SYZYGY
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[0] }]; #IO_L18P_T2U_N10_AD2P_64 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[1] }]; #IO_L22P_T3U_N6_DBC_AD0P_64 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AE3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[2] }]; #IO_L21P_T3L_N4_AD8P_64 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[3] }]; #IO_L12P_T1U_N10_GC_64 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AD7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[4] }]; #IO_L4P_T0U_N6_DBC_AD7P_64 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AG6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[5] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[6] }]; #IO_L3P_T0L_N4_AD15P_65 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_p[7] }]; #IO_L2P_T0L_N2_65 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[0] }]; #IO_L18P_T2U_N11_AD2P_64 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[1] }]; #IO_L22P_T3U_N7_DBC_AD0P_64 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AF3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[2] }]; #IO_L21P_T3L_N5_AD8P_64 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[3] }]; #IO_L12P_T1U_N11_GC_64 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AE7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[4] }]; #IO_L4P_T0U_N7_DBC_AD7P_64 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN AG5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[5] }]; #IO_L10P_T1U_N7_QBC_AD4P_64 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[6] }]; #IO_L3P_T0L_N5_AD15P_65 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_d_n[7] }]; #IO_L2P_T0L_N3_65 Sch=syzygy_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L4P_AD8P_43/44 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L6P_HDGC_AD6P_43/44 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L4N_AD8N_43/44 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L6N_HDGC_AD6N_43/44 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AF11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L2P_AD10P_43/44 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L5P_HDGC_AD7P_43/44 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L5N_HDGC_AD7N_43/44 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AH12 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L3P_AD9P_43/44 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN AG11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L2N_AD10N_43/44 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L1P_AD11P_43/44 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L3N_AD9N_43/44 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L1N_AD11N_43/44 Sch=syzygy_s[27]
|
||||
#set_property -dict { PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_n }]; #IO_L13N_T2L_N1_GC_QBC_64 Sch=syzygy_in_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AD5 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { syzygy_in_clk_p }]; #IO_L13P_T2L_N0_GC_QBC_64 Sch=syzygy_in_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_n }]; #IO_L1N_T0L_N1_DBC_65 Sch=syzygy_out_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVDS } [get_ports { syzygy_out_clk_p }]; #IO_L1P_T0L_N0_DBC_65 Sch=syzygy_out_clk_p
|
||||
|
||||
## FMC connector
|
||||
#set_property -dict { PACKAGE_PIN M6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk0_m2c_p }]; #IO_L14P_T2L_N2_GC_65 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports { fmc_clk1_m2c_p }]; #IO_L12P_T1U_N10_GC_65 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN L6 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2L_N1_GC_QBC_65 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN L7 IOSTANDARD LVDS } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2L_N0_GC_QBC_65 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H3 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_n }]; #IO_L7N_T1L_N1_QBC_AD13N_65 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVDS } [get_ports { fmc_la01_cc_p }]; #IO_L7P_T1L_N0_QBC_AD13P_65 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVDS } [get_ports { fmc_la_n[02] }]; #IO_L20N_T3L_N3_AD1N_65 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN J6 IOSTANDARD LVDS } [get_ports { fmc_la_p[02] }]; #IO_L20P_T3L_N2_AD1P_65 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVDS } [get_ports { fmc_la_n[03] }]; #IO_L11N_T1U_N9_GC_65 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN K4 IOSTANDARD LVDS } [get_ports { fmc_la_p[03] }]; #IO_L11P_T1U_N8_GC_65 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVDS } [get_ports { fmc_la_n[04] }]; #IO_L9N_T1L_N5_AD12N_65 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVDS } [get_ports { fmc_la_p[04] }]; #IO_L9P_T1L_N4_AD12P_65 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVDS } [get_ports { fmc_la_n[05] }]; #IO_L6N_T0U_N11_AD6N_65 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVDS } [get_ports { fmc_la_p[05] }]; #IO_L6P_T0U_N10_AD6P_65 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVDS } [get_ports { fmc_la_n[06] }]; #IO_L17N_T2U_N9_AD10N_65 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVDS } [get_ports { fmc_la_p[06] }]; #IO_L17P_T2U_N8_AD10P_65 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN J9 IOSTANDARD LVDS } [get_ports { fmc_la_n[07] }]; #IO_L23N_T3U_N9_65 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVDS } [get_ports { fmc_la_p[07] }]; #IO_L23P_T3U_N8_I2C_SCLK_65 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN T7 IOSTANDARD LVDS } [get_ports { fmc_la_n[08] }]; #IO_L5N_T0U_N9_AD14N_65 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN R7 IOSTANDARD LVDS } [get_ports { fmc_la_p[08] }]; #IO_L5P_T0U_N8_AD14P_65 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN L8 IOSTANDARD LVDS } [get_ports { fmc_la_n[09] }]; #IO_L18N_T2U_N11_AD2N_65 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN M8 IOSTANDARD LVDS } [get_ports { fmc_la_p[09] }]; #IO_L18P_T2U_N10_AD2P_65 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVDS } [get_ports { fmc_la_n[10] }]; #IO_L8N_T1L_N3_AD5N_65 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVDS } [get_ports { fmc_la_p[10] }]; #IO_L8P_T1L_N2_AD5P_65 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVDS } [get_ports { fmc_la_n[11] }]; #IO_L19N_T3L_N1_DBC_AD9N_65 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVDS } [get_ports { fmc_la_p[11] }]; #IO_L19P_T3L_N0_DBC_AD9P_65 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN H7 IOSTANDARD LVDS } [get_ports { fmc_la_n[12] }]; #IO_L21N_T3L_N5_AD8N_65 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN J7 IOSTANDARD LVDS } [get_ports { fmc_la_p[12] }]; #IO_L21P_T3L_N4_AD8P_65 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN N6 IOSTANDARD LVDS } [get_ports { fmc_la_n[13] }]; #IO_L15N_T2L_N5_AD11N_65 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN N7 IOSTANDARD LVDS } [get_ports { fmc_la_p[13] }]; #IO_L15P_T2L_N4_AD11P_65 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN P6 IOSTANDARD LVDS } [get_ports { fmc_la_n[14] }]; #IO_L16N_T2U_N7_QBC_AD3N_65 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN P7 IOSTANDARD LVDS } [get_ports { fmc_la_p[14] }]; #IO_L16P_T2U_N6_QBC_AD3P_65 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports { fmc_la_n[15] }]; #IO_L4N_T0U_N7_DBC_AD7N_65 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports { fmc_la_p[15] }]; #IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN K7 IOSTANDARD LVDS } [get_ports { fmc_la_n[16] }]; #IO_L22N_T3U_N7_DBC_AD0N_65 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN K8 IOSTANDARD LVDS } [get_ports { fmc_la_p[16] }]; #IO_L22P_T3U_N6_DBC_AD0P_65 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN AD1 IOSTANDARD LVDS } [get_ports { fmc_la_n[17] }]; #IO_L16N_T2U_N7_QBC_AD3N_64 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AD2 IOSTANDARD LVDS } [get_ports { fmc_la_p[17] }]; #IO_L16P_T2U_N6_QBC_AD3P_64 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AH9 IOSTANDARD LVDS } [get_ports { fmc_la_n[18] }]; #IO_L10N_T1U_N7_QBC_AD4N_64 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN AG9 IOSTANDARD LVDS } [get_ports { fmc_la_p[18] }]; #IO_L10P_T1U_N6_QBC_AD4P_64 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN AC3 IOSTANDARD LVDS } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2U_N9_AD10N_64 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2U_N8_AD10P_64 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD LVDS } [get_ports { fmc_la_n[20] }]; #IO_L15N_T2L_N5_AD11N_64 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports { fmc_la_p[20] }]; #IO_L15P_T2L_N4_AD11P_64 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN AG1 IOSTANDARD LVDS } [get_ports { fmc_la_n[21] }]; #IO_L24N_T3U_N11_64 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN AF1 IOSTANDARD LVDS } [get_ports { fmc_la_p[21] }]; #IO_L24P_T3U_N10_64 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN AC8 IOSTANDARD LVDS } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0L_N5_AD15N_64 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVDS } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0L_N4_AD15P_64 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN AH1 IOSTANDARD LVDS } [get_ports { fmc_la_n[23] }]; #IO_L23N_T3U_N9_64 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN AH2 IOSTANDARD LVDS } [get_ports { fmc_la_p[23] }]; #IO_L23P_T3U_N8_64 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN AF6 IOSTANDARD LVDS } [get_ports { fmc_la_n[24] }]; #IO_L11N_T1U_N9_GC_64 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN AF7 IOSTANDARD LVDS } [get_ports { fmc_la_p[24] }]; #IO_L11P_T1U_N8_GC_64 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN AH3 IOSTANDARD LVDS } [get_ports { fmc_la_n[25] }]; #IO_L20N_T3L_N3_AD1N_64 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN AG3 IOSTANDARD LVDS } [get_ports { fmc_la_p[25] }]; #IO_L20P_T3L_N2_AD1P_64 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN AD9 IOSTANDARD LVDS } [get_ports { fmc_la_n[26] }]; #IO_L1N_T0L_N1_DBC_64 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN AC9 IOSTANDARD LVDS } [get_ports { fmc_la_p[26] }]; #IO_L1P_T0L_N0_DBC_64 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN AH4 IOSTANDARD LVDS } [get_ports { fmc_la_n[27] }]; #IO_L19N_T3L_N1_DBC_AD9N_64 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN AG4 IOSTANDARD LVDS } [get_ports { fmc_la_p[27] }]; #IO_L19P_T3L_N0_DBC_AD9P_64 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN AE8 IOSTANDARD LVDS } [get_ports { fmc_la_n[28] }]; #IO_L2N_T0L_N3_64 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN AE9 IOSTANDARD LVDS } [get_ports { fmc_la_p[28] }]; #IO_L2P_T0L_N2_64 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN AH7 IOSTANDARD LVDS } [get_ports { fmc_la_n[29] }]; #IO_L9N_T1L_N5_AD12N_64 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN AH8 IOSTANDARD LVDS } [get_ports { fmc_la_p[29] }]; #IO_L9P_T1L_N4_AD12P_64 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN AC7 IOSTANDARD LVDS } [get_ports { fmc_la_n[30] }]; #IO_L5N_T0U_N9_AD14N_64 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVDS } [get_ports { fmc_la_p[30] }]; #IO_L5P_T0U_N8_AD14P_64 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN AG8 IOSTANDARD LVDS } [get_ports { fmc_la_n[31] }]; #IO_L8N_T1L_N3_AD5N_64 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVDS } [get_ports { fmc_la_p[31] }]; #IO_L8P_T1L_N2_AD5P_64 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports { fmc_la_n[32] }]; #IO_L14N_T2L_N3_GC_64 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD LVDS } [get_ports { fmc_la_p[32] }]; #IO_L14P_T2L_N2_GC_64 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN AC6 IOSTANDARD LVDS } [get_ports { fmc_la_n[33] }]; #IO_L6N_T0U_N11_AD6N_64 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVDS } [get_ports { fmc_la_p[33] }]; #IO_L6P_T0U_N10_AD6P_64 Sch=fmc_la_p[33]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { fmc_prsntn_m2c }]; #IO_L11N_AD9N_44/24
|
||||
|
||||
## Power-good input for VADJ supply rail
|
||||
#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33 } [get_ports { pg_vadj_r }]; #IO_L12N_AD8N_44/24 Sch=pg_vadj_r
|
||||
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y168/PAD]
|
||||
#set_property PROHIBIT true [get_bels IOB_X1Y116/PAD]
|
||||
|
||||
#set_property IOSTANDARD ANALOG [get_ports Vp_Vn_0_v_p]
|
||||
|
||||
|
||||
|
||||
|
||||
21
Bibliotheken/digilent-xdc-master/License.txt
Normal file
21
Bibliotheken/digilent-xdc-master/License.txt
Normal file
@ -0,0 +1,21 @@
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2017 Digilent
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
265
Bibliotheken/digilent-xdc-master/Nexys-4-DDR-Master.xdc
Normal file
265
Bibliotheken/digilent-xdc-master/Nexys-4-DDR-Master.xdc
Normal file
@ -0,0 +1,265 @@
|
||||
## This file is a general .xdc for the Nexys4 DDR Rev. C
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
|
||||
## LEDs
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
|
||||
##7 segment display
|
||||
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
|
||||
##Buttons
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
|
||||
##VGA Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
|
||||
##Micro SD Connector
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
|
||||
##Accelerometer
|
||||
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
722
Bibliotheken/digilent-xdc-master/Nexys-4-Master.xdc
Normal file
722
Bibliotheken/digilent-xdc-master/Nexys-4-Master.xdc
Normal file
@ -0,0 +1,722 @@
|
||||
## This file is a general .xdc for the Nexys4 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
|
||||
#set_property PACKAGE_PIN E3 [get_ports clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## Switches
|
||||
##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
|
||||
#set_property PACKAGE_PIN U9 [get_ports {sw[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
##Bank = 34, Pin name = IO_25_34, Sch name = SW1
|
||||
#set_property PACKAGE_PIN U8 [get_ports {sw[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2
|
||||
#set_property PACKAGE_PIN R7 [get_ports {sw[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3
|
||||
#set_property PACKAGE_PIN R6 [get_ports {sw[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4
|
||||
#set_property PACKAGE_PIN R5 [get_ports {sw[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5
|
||||
#set_property PACKAGE_PIN V7 [get_ports {sw[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6
|
||||
#set_property PACKAGE_PIN V6 [get_ports {sw[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7
|
||||
#set_property PACKAGE_PIN V5 [get_ports {sw[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8
|
||||
#set_property PACKAGE_PIN U4 [get_ports {sw[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9
|
||||
#set_property PACKAGE_PIN V2 [get_ports {sw[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10
|
||||
#set_property PACKAGE_PIN U2 [get_ports {sw[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11
|
||||
#set_property PACKAGE_PIN T3 [get_ports {sw[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12
|
||||
#set_property PACKAGE_PIN T1 [get_ports {sw[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13
|
||||
#set_property PACKAGE_PIN R3 [get_ports {sw[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14
|
||||
#set_property PACKAGE_PIN P3 [get_ports {sw[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
|
||||
#set_property PACKAGE_PIN P4 [get_ports {sw[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
|
||||
## LEDs
|
||||
##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
|
||||
#set_property PACKAGE_PIN T8 [get_ports {led[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
|
||||
#set_property PACKAGE_PIN V9 [get_ports {led[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
|
||||
#set_property PACKAGE_PIN R8 [get_ports {led[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
|
||||
#set_property PACKAGE_PIN T6 [get_ports {led[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4
|
||||
#set_property PACKAGE_PIN T5 [get_ports {led[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5
|
||||
#set_property PACKAGE_PIN T4 [get_ports {led[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
|
||||
#set_property PACKAGE_PIN U7 [get_ports {led[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
|
||||
#set_property PACKAGE_PIN U6 [get_ports {led[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8
|
||||
#set_property PACKAGE_PIN V4 [get_ports {led[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
|
||||
#set_property PACKAGE_PIN U3 [get_ports {led[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10
|
||||
#set_property PACKAGE_PIN V1 [get_ports {led[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
|
||||
#set_property PACKAGE_PIN R1 [get_ports {led[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12
|
||||
#set_property PACKAGE_PIN P5 [get_ports {led[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
|
||||
##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13
|
||||
#set_property PACKAGE_PIN U1 [get_ports {led[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
|
||||
##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14
|
||||
#set_property PACKAGE_PIN R2 [get_ports {led[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
|
||||
##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15
|
||||
#set_property PACKAGE_PIN P2 [get_ports {led[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
|
||||
|
||||
##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
|
||||
#set_property PACKAGE_PIN K5 [get_ports RGB1_Red]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red]
|
||||
##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G
|
||||
#set_property PACKAGE_PIN F13 [get_ports RGB1_Green]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green]
|
||||
##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B
|
||||
#set_property PACKAGE_PIN F6 [get_ports RGB1_Blue]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue]
|
||||
##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
|
||||
#set_property PACKAGE_PIN K6 [get_ports RGB2_Red]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red]
|
||||
##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
|
||||
#set_property PACKAGE_PIN H6 [get_ports RGB2_Green]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green]
|
||||
##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B
|
||||
#set_property PACKAGE_PIN L16 [get_ports RGB2_Blue]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue]
|
||||
|
||||
|
||||
|
||||
##7 segment display
|
||||
##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
|
||||
#set_property PACKAGE_PIN L3 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
|
||||
#set_property PACKAGE_PIN N1 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
|
||||
#set_property PACKAGE_PIN L5 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
|
||||
#set_property PACKAGE_PIN L4 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
|
||||
#set_property PACKAGE_PIN K3 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
|
||||
#set_property PACKAGE_PIN M2 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
|
||||
#set_property PACKAGE_PIN L6 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
|
||||
#set_property PACKAGE_PIN M4 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
|
||||
#set_property PACKAGE_PIN N6 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
|
||||
#set_property PACKAGE_PIN M6 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
|
||||
#set_property PACKAGE_PIN M3 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
|
||||
#set_property PACKAGE_PIN N5 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
|
||||
#set_property PACKAGE_PIN N2 [get_ports {an[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
|
||||
##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
|
||||
#set_property PACKAGE_PIN N4 [get_ports {an[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
|
||||
##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
|
||||
#set_property PACKAGE_PIN L1 [get_ports {an[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
|
||||
##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
|
||||
#set_property PACKAGE_PIN M1 [get_ports {an[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
|
||||
|
||||
|
||||
|
||||
##Buttons
|
||||
##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET
|
||||
#set_property PACKAGE_PIN C12 [get_ports btnCpuReset]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
|
||||
##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
|
||||
#set_property PACKAGE_PIN E16 [get_ports btnC]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU
|
||||
#set_property PACKAGE_PIN F15 [get_ports btnU]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL
|
||||
#set_property PACKAGE_PIN T16 [get_ports btnL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
##Bank = 14, Pin name = IO_25_14, Sch name = BTNR
|
||||
#set_property PACKAGE_PIN R10 [get_ports btnR]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
|
||||
#set_property PACKAGE_PIN V10 [get_ports btnD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1
|
||||
#set_property PACKAGE_PIN B13 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2
|
||||
#set_property PACKAGE_PIN F14 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3
|
||||
#set_property PACKAGE_PIN D17 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4
|
||||
#set_property PACKAGE_PIN E17 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Bank = 15, Pin name = IO_0_15, Sch name = JA7
|
||||
#set_property PACKAGE_PIN G13 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8
|
||||
#set_property PACKAGE_PIN C17 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9
|
||||
#set_property PACKAGE_PIN D18 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10
|
||||
#set_property PACKAGE_PIN E18 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1
|
||||
#set_property PACKAGE_PIN G14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2
|
||||
#set_property PACKAGE_PIN P15 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3
|
||||
#set_property PACKAGE_PIN V11 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4
|
||||
#set_property PACKAGE_PIN V15 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Bank = 15, Pin name = IO_25_15, Sch name = JB7
|
||||
#set_property PACKAGE_PIN K16 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8
|
||||
#set_property PACKAGE_PIN R16 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9
|
||||
#set_property PACKAGE_PIN T9 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10
|
||||
#set_property PACKAGE_PIN U11 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2
|
||||
#set_property PACKAGE_PIN E7 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4
|
||||
#set_property PACKAGE_PIN J4 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7
|
||||
#set_property PACKAGE_PIN K1 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8
|
||||
#set_property PACKAGE_PIN E6 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10
|
||||
#set_property PACKAGE_PIN G6 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1
|
||||
#set_property PACKAGE_PIN H4 [get_ports {JD[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}]
|
||||
##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JD[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}]
|
||||
##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3
|
||||
#set_property PACKAGE_PIN G1 [get_ports {JD[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}]
|
||||
##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JD[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}]
|
||||
##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JD[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}]
|
||||
##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8
|
||||
#set_property PACKAGE_PIN G4 [get_ports {JD[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}]
|
||||
##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JD[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}]
|
||||
##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10
|
||||
#set_property PACKAGE_PIN F3 [get_ports {JD[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P
|
||||
#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P
|
||||
#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N
|
||||
#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N
|
||||
#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0
|
||||
#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1
|
||||
#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2
|
||||
#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3
|
||||
#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0
|
||||
#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1
|
||||
#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2
|
||||
#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3
|
||||
#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0
|
||||
#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1
|
||||
#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2
|
||||
#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3
|
||||
#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS
|
||||
#set_property PACKAGE_PIN B11 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS
|
||||
#set_property PACKAGE_PIN B12 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
|
||||
##Micro SD Connector
|
||||
##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET
|
||||
#set_property PACKAGE_PIN E2 [get_ports sdReset]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdReset]
|
||||
##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
|
||||
#set_property PACKAGE_PIN A1 [get_ports sdCD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdCD]
|
||||
##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK
|
||||
#set_property PACKAGE_PIN B1 [get_ports sdSCK]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdSCK]
|
||||
##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD
|
||||
#set_property PACKAGE_PIN C1 [get_ports sdCmd]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports sdCmd]
|
||||
##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
|
||||
#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}]
|
||||
##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1
|
||||
#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}]
|
||||
##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2
|
||||
#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}]
|
||||
##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
|
||||
#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}]
|
||||
|
||||
|
||||
|
||||
##Accelerometer
|
||||
##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO
|
||||
#set_property PACKAGE_PIN D13 [get_ports aclMISO]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclMISO]
|
||||
##Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI
|
||||
#set_property PACKAGE_PIN B14 [get_ports aclMOSI]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI]
|
||||
##Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK
|
||||
#set_property PACKAGE_PIN D15 [get_ports aclSCK]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclSCK]
|
||||
##Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN
|
||||
#set_property PACKAGE_PIN C15 [get_ports aclSS]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclSS]
|
||||
##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1
|
||||
#set_property PACKAGE_PIN C16 [get_ports aclInt1]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclInt1]
|
||||
##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2
|
||||
#set_property PACKAGE_PIN E15 [get_ports aclInt2]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports aclInt2]
|
||||
|
||||
|
||||
|
||||
##Temperature Sensor
|
||||
##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL
|
||||
#set_property PACKAGE_PIN F16 [get_ports tmpSCL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL]
|
||||
##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA
|
||||
#set_property PACKAGE_PIN G16 [get_ports tmpSDA]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA]
|
||||
##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT
|
||||
#set_property PACKAGE_PIN D14 [get_ports tmpInt]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
|
||||
##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT
|
||||
#set_property PACKAGE_PIN C14 [get_ports tmpCT]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
|
||||
|
||||
|
||||
|
||||
##Omnidirectional Microphone
|
||||
##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK
|
||||
#set_property PACKAGE_PIN J5 [get_ports micClk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports micClk]
|
||||
##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA
|
||||
#set_property PACKAGE_PIN H5 [get_ports micData]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports micData]
|
||||
##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL
|
||||
#set_property PACKAGE_PIN F5 [get_ports micLRSel]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports micLRSel]
|
||||
|
||||
|
||||
|
||||
##PWM Audio Amplifier
|
||||
##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM
|
||||
#set_property PACKAGE_PIN A11 [get_ports ampPWM]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ampPWM]
|
||||
##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD
|
||||
#set_property PACKAGE_PIN D12 [get_ports ampSD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports ampSD]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN
|
||||
#set_property PACKAGE_PIN C4 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT
|
||||
#set_property PACKAGE_PIN D4 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS
|
||||
#set_property PACKAGE_PIN D3 [get_ports RsCts]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsCts]
|
||||
##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS
|
||||
#set_property PACKAGE_PIN E5 [get_ports RsRts]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRts]
|
||||
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK
|
||||
#set_property PACKAGE_PIN F4 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA
|
||||
#set_property PACKAGE_PIN B2 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC
|
||||
#set_property PACKAGE_PIN C9 [get_ports PhyMdc]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc]
|
||||
##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO
|
||||
#set_property PACKAGE_PIN A9 [get_ports PhyMdio]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio]
|
||||
##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN
|
||||
#set_property PACKAGE_PIN B3 [get_ports PhyRstn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn]
|
||||
##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV
|
||||
#set_property PACKAGE_PIN D9 [get_ports PhyCrs]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs]
|
||||
##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR
|
||||
#set_property PACKAGE_PIN C10 [get_ports PhyRxErr]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr]
|
||||
##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0
|
||||
#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}]
|
||||
##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1
|
||||
#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}]
|
||||
##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN
|
||||
#set_property PACKAGE_PIN B9 [get_ports PhyTxEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn]
|
||||
##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0
|
||||
#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}]
|
||||
##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1
|
||||
#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}]
|
||||
##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK
|
||||
#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz]
|
||||
##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN
|
||||
#set_property PACKAGE_PIN B8 [get_ports PhyIntn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn]
|
||||
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK
|
||||
#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}]
|
||||
##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0
|
||||
#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1
|
||||
#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2
|
||||
#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3
|
||||
#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN
|
||||
#set_property PACKAGE_PIN L13 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
|
||||
|
||||
|
||||
##Cellular RAM
|
||||
##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK
|
||||
#set_property PACKAGE_PIN T15 [get_ports RamCLK]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamCLK]
|
||||
##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN
|
||||
#set_property PACKAGE_PIN T13 [get_ports RamADVn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamADVn]
|
||||
##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN
|
||||
#set_property PACKAGE_PIN L18 [get_ports RamCEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamCEn]
|
||||
##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE
|
||||
#set_property PACKAGE_PIN J14 [get_ports RamCRE]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamCRE]
|
||||
##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN
|
||||
#set_property PACKAGE_PIN H14 [get_ports RamOEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamOEn]
|
||||
##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN
|
||||
#set_property PACKAGE_PIN R11 [get_ports RamWEn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamWEn]
|
||||
##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN
|
||||
#set_property PACKAGE_PIN J15 [get_ports RamLBn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamLBn]
|
||||
##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN
|
||||
#set_property PACKAGE_PIN J13 [get_ports RamUBn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamUBn]
|
||||
##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
|
||||
#set_property PACKAGE_PIN T14 [get_ports RamWait]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RamWait]
|
||||
|
||||
##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0
|
||||
#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}]
|
||||
##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1
|
||||
#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}]
|
||||
##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2
|
||||
#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}]
|
||||
##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3
|
||||
#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}]
|
||||
##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4
|
||||
#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}]
|
||||
##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5
|
||||
#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}]
|
||||
##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6
|
||||
#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}]
|
||||
##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7
|
||||
#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}]
|
||||
##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8
|
||||
#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}]
|
||||
##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9
|
||||
#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}]
|
||||
##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10
|
||||
#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}]
|
||||
##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11
|
||||
#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}]
|
||||
##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12
|
||||
#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}]
|
||||
##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13
|
||||
#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}]
|
||||
##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14
|
||||
#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}]
|
||||
##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15
|
||||
#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}]
|
||||
|
||||
##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0
|
||||
#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}]
|
||||
##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1
|
||||
#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}]
|
||||
##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2
|
||||
#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}]
|
||||
##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3
|
||||
#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}]
|
||||
##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4
|
||||
#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}]
|
||||
##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5
|
||||
#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}]
|
||||
##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6
|
||||
#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}]
|
||||
##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7
|
||||
#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}]
|
||||
##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8
|
||||
#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}]
|
||||
##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9
|
||||
#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}]
|
||||
##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10
|
||||
#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}]
|
||||
##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11
|
||||
#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}]
|
||||
##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12
|
||||
#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}]
|
||||
##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13
|
||||
#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}]
|
||||
##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14
|
||||
#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}]
|
||||
##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15
|
||||
#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}]
|
||||
##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16
|
||||
#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}]
|
||||
##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17
|
||||
#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}]
|
||||
##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18
|
||||
#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}]
|
||||
##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19
|
||||
#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}]
|
||||
##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20
|
||||
#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}]
|
||||
##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21
|
||||
#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}]
|
||||
##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22
|
||||
#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}]
|
||||
|
||||
211
Bibliotheken/digilent-xdc-master/Nexys-A7-100T-Master.xdc
Normal file
211
Bibliotheken/digilent-xdc-master/Nexys-A7-100T-Master.xdc
Normal file
@ -0,0 +1,211 @@
|
||||
## This file is a general .xdc for the Nexys A7-100T
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
##7 segment display
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
##Accelerometer
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
##Temperature Sensor
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
##PWM Audio Amplifier
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
##Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
211
Bibliotheken/digilent-xdc-master/Nexys-A7-50T-Master.xdc
Normal file
211
Bibliotheken/digilent-xdc-master/Nexys-A7-50T-Master.xdc
Normal file
@ -0,0 +1,211 @@
|
||||
## This file is a general .xdc for the Nexys A7-50T
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
##7 segment display
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
##Accelerometer
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
##Temperature Sensor
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
##PWM Audio Amplifier
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
##Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
312
Bibliotheken/digilent-xdc-master/Nexys-Video-Master.xdc
Normal file
312
Bibliotheken/digilent-xdc-master/Nexys-Video-Master.xdc
Normal file
@ -0,0 +1,312 @@
|
||||
### This file is a general .xdc for the Nexys Video Rev. A
|
||||
### To use it in a project:
|
||||
### - uncomment the lines corresponding to used pins
|
||||
### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
|
||||
## Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## FMC Transceiver clocks (Must be set to value provided by Mezzanine card, currently set to 156.25 MHz)
|
||||
## Note: This clock is attached to a MGTREFCLK pin
|
||||
#set_property -dict { PACKAGE_PIN E6 } [get_ports { GTP_CLK_N }];
|
||||
#set_property -dict { PACKAGE_PIN F6 } [get_ports { GTP_CLK_P }];
|
||||
#create_clock -add -name gtpclk0_pin -period 6.400 -waveform {0 3.200} [get_ports {GTP_CLK_P}];
|
||||
#set_property -dict { PACKAGE_PIN E10 } [get_ports { FMC_MGT_CLK_N }];
|
||||
#set_property -dict { PACKAGE_PIN F10 } [get_ports { FMC_MGT_CLK_P }];
|
||||
#create_clock -add -name mgtclk1_pin -period 6.400 -waveform {0 3.200} [get_ports {FMC_MGT_CLK_P}];
|
||||
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { led[0] }]; #IO_L15P_T2_DQS_13 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { led[1] }]; #IO_L15N_T2_DQS_13 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { led[2] }]; #IO_L17P_T2_13 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { led[3] }]; #IO_L17N_T2_13 Sch=led[3]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { led[4] }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { led[5] }]; #IO_L16N_T2_13 Sch=led[5]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { led[6] }]; #IO_L16P_T2_13 Sch=led[6]
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { led[7] }]; #IO_L5P_T0_13 Sch=led[7]
|
||||
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_L20N_T3_16 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_L22N_T3_16 Sch=btnd
|
||||
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L20P_T3_16 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L6P_T0_16 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_0_16 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { cpu_resetn }]; #IO_L12N_T1_MRCC_35 Sch=cpu_resetn
|
||||
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS12 } [get_ports { sw[0] }]; #IO_L22P_T3_16 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { sw[1] }]; #IO_25_16 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS12 } [get_ports { sw[2] }]; #IO_L24P_T3_16 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { sw[3] }]; #IO_L24N_T3_16 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { sw[4] }]; #IO_L6P_T0_15 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { sw[5] }]; #IO_0_15 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { sw[6] }]; #IO_L19P_T3_A22_15 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS12 } [get_ports { sw[7] }]; #IO_25_15 Sch=sw[7]
|
||||
|
||||
|
||||
## OLED Display
|
||||
#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { oled_dc }]; #IO_L7N_T1_D10_14 Sch=oled_dc
|
||||
#set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { oled_res }]; #IO_L4N_T0_D05_14 Sch=oled_res
|
||||
#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { oled_sclk }]; #IO_L7P_T1_D09_14 Sch=oled_sclk
|
||||
#set_property -dict { PACKAGE_PIN Y22 IOSTANDARD LVCMOS33 } [get_ports { oled_sdin }]; #IO_L9N_T1_DQS_D13_14 Sch=oled_sdin
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_0_14 Sch=oled_vbat
|
||||
#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { oled_vdd }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=oled_vdd
|
||||
|
||||
|
||||
## HDMI in
|
||||
#set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
|
||||
#set_property -dict { PACKAGE_PIN W4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN V4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
|
||||
#set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
|
||||
#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
|
||||
#set_property -dict { PACKAGE_PIN AA3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN Y3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN Y2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN W2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
|
||||
|
||||
|
||||
## HDMI out
|
||||
#set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
|
||||
#set_property -dict { PACKAGE_PIN U1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN T1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
|
||||
#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
|
||||
#set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
|
||||
|
||||
|
||||
## Display Port
|
||||
#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_n }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
|
||||
#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_n }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
|
||||
#set_property -dict { PACKAGE_PIN AA9 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_p }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
|
||||
#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_p }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { dp_tx_hpd }]; #IO_25_14 Sch=dp_tx_hpd
|
||||
|
||||
|
||||
## Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN T4 IOSTANDARD LVCMOS33 } [get_ports { ac_adc_sdata }]; #IO_L13N_T2_MRCC_34 Sch=ac_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_L14P_T2_SRCC_34 Sch=ac_bclk
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ac_dac_sdata }]; #IO_L15P_T2_DQS_34 Sch=ac_dac_sdata
|
||||
#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ac_lrclk }]; #IO_L14N_T2_SRCC_34 Sch=ac_lrclk
|
||||
#set_property -dict { PACKAGE_PIN U6 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L16P_T2_34 Sch=ac_mclk
|
||||
|
||||
|
||||
## Pmod header JA
|
||||
#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L10N_T1_D15_14 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L10P_T1_D14_14 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
|
||||
|
||||
|
||||
## Pmod header JB
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L19P_T3_34 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L24P_T3_34 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L24N_T3_34 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L23P_T3_34 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L23N_T3_34 Sch=jb_n[4]
|
||||
|
||||
|
||||
## Pmod header JC
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L18P_T2_34 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22N_T3_34 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L17P_T2_34 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L17N_T2_34 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L20P_T3_34 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_34 Sch=jc_n[4]
|
||||
|
||||
|
||||
## XADC Header
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
|
||||
|
||||
|
||||
## UART
|
||||
#set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
|
||||
|
||||
|
||||
## Ethernet
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
|
||||
#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_25_34 Sch=eth_rst_b
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
|
||||
#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
|
||||
#set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
|
||||
#set_property -dict { PACKAGE_PIN AB11 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
|
||||
#set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
|
||||
|
||||
|
||||
## Fan PWM
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
|
||||
|
||||
|
||||
## DPTI/DSPI
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { prog_d[0]}]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/mosi
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/miso
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[3]}]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
|
||||
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { prog_siwun }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=prog_siwun
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { prog_spien }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=prog_spien
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { prog_txen }]; #IO_L13N_T2_MRCC_14 Sch=prog_txen
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { prog_wrn }]; #IO_L5N_T0_D07_14 Sch=prog_wrn
|
||||
|
||||
|
||||
## HID port
|
||||
#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data
|
||||
|
||||
|
||||
## QSPI
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
|
||||
## SD card
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cclk }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
|
||||
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
|
||||
|
||||
|
||||
## I2C
|
||||
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { scl }]; #IO_L15N_T2_DQS_34 Sch=scl
|
||||
#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { sda }]; #IO_L16N_T2_34 Sch=sda
|
||||
|
||||
|
||||
## Voltage Adjust
|
||||
#set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
|
||||
#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
|
||||
|
||||
|
||||
## FMC
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
|
||||
#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_n }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_p }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
|
||||
#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
|
||||
#set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
|
||||
#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
|
||||
#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
|
||||
#set_property -dict { PACKAGE_PIN K22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
|
||||
#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
|
||||
#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
|
||||
#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_n }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_p }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_n }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_p }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
|
||||
#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
|
||||
#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
|
||||
#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
|
||||
#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
|
||||
#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
|
||||
#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
4
Bibliotheken/digilent-xdc-master/README.md
Normal file
4
Bibliotheken/digilent-xdc-master/README.md
Normal file
@ -0,0 +1,4 @@
|
||||
# digilent-xdc
|
||||
A collection of Master XDC files for Digilent FPGA and Zynq boards.
|
||||
|
||||
Documentation for these boards, including schematics and reference manuals, can be found through the [Programmable Logic](https://digilent.com/reference/programmable-logic/start) landing page on the Digilent Reference site.
|
||||
521
Bibliotheken/digilent-xdc-master/Sword-Master.xdc
Normal file
521
Bibliotheken/digilent-xdc-master/Sword-Master.xdc
Normal file
@ -0,0 +1,521 @@
|
||||
## This file is a general .xdc for the Sword Rev. B
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 200MHz Differential Clock Signal
|
||||
#set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { clk_p }]; #IO_L12P_T1_MRCC_33 Sch=fpga_sysclk_p
|
||||
#set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { clk_n }]; #IO_L12N_T1_MRCC_33 Sch=fpga_sysclk_n
|
||||
#create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_p]
|
||||
|
||||
## User Reset Button
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS15 } [get_ports { rst }]; #IO_0_VRN_33 Sch=user_rst
|
||||
|
||||
## Switches
|
||||
#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { sw[0] }]; #IO_L8P_T1_32 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { sw[1] }]; #IO_L8N_T1_32 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN AH17 IOSTANDARD LVCMOS18 } [get_ports { sw[2] }]; #IO_L5P_T0_32 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { sw[3] }]; #IO_L6N_T0_VREF_32 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN AH16 IOSTANDARD LVCMOS18 } [get_ports { sw[4] }]; #IO_L3P_T0_DQS_32 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN AE16 IOSTANDARD LVCMOS18 } [get_ports { sw[5] }]; #IO_L6P_T0_32 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { sw[6] }]; #IO_L7P_T1_32 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { sw[7] }]; #IO_L7N_T1_32 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN AJ17 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L5N_T0_32 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN AJ16 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_L3N_T0_DQS_32 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { sw[10] }]; #IO_L1P_T0_32 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { sw[11] }]; #IO_L1N_T0_32 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN AG15 IOSTANDARD LVCMOS18 } [get_ports { sw[12] }]; #IO_L2P_T0_32 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN AH15 IOSTANDARD LVCMOS18 } [get_ports { sw[13] }]; #IO_L2N_T0_32 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN AG14 IOSTANDARD LVCMOS18 } [get_ports { sw[14] }]; #IO_L4N_T0_32 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN AF15 IOSTANDARD LVCMOS18 } [get_ports { sw[15] }]; #IO_L4P_T0_32 Sch=sw[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L19P_T3_18 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L20P_T3_18 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L19N_T3_VREF_18 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L20N_T3_18 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_L21N_T3_DQS_18 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L21P_T3_DQS_18 Sch=led17_r
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L9P_T1_DQS_18 Sch=ld[0]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L9N_T1_DQS_18 Sch=ld[1]
|
||||
#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L10P_T1_18 Sch=ld[2]
|
||||
#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L10N_T1_18 Sch=ld[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L11P_T1_SRCC_18 Sch=ld[4]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L11N_T1_SRCC_18 Sch=ld[5]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L12P_T1_MRCC_18 Sch=ld[6]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L12N_T1_MRCC_18 Sch=ld[7]
|
||||
#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L14P_T2_SRCC_18 Sch=ld[8]
|
||||
#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_18 Sch=ld[9]
|
||||
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L15P_T2_DQS_18 Sch=ld[10]
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_18 Sch=ld[11]
|
||||
#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_18 Sch=ld[12]
|
||||
#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L12P_T1_MRCC_13 Sch=ld[13]
|
||||
#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L12N_T1_MRCC_13 Sch=ld[14]
|
||||
#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L24N_T3_16 Sch=ld[15]
|
||||
|
||||
## Twenty-Five Button Keypad
|
||||
#set_property -dict { PACKAGE_PIN AE13 IOSTANDARD LVCMOS15 } [get_ports { btn_c[0] }]; #IO_L19P_T3_33 Sch=btn_c[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { btn_c[1] }]; #IO_L21N_T3_DQS_33 Sch=btn_c[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { btn_c[2] }]; #IO_L22P_T3_33 Sch=btn_c[2]
|
||||
#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { btn_c[3] }]; #IO_L21P_T3_DQS_33 Sch=btn_c[3]
|
||||
#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { btn_c[4] }]; #IO_L23N_T3_33 Sch=btn_c[4]
|
||||
#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { btn_r[0] }]; #IO_L20P_T3_33 Sch=btn_r[0]
|
||||
#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { btn_r[1] }]; #IO_L20N_T3_33 Sch=btn_r[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { btn_r[2] }]; #IO_L22N_T3_33 Sch=btn_r[2]
|
||||
#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { btn_r[3] }]; #IO_L23P_T3_33 Sch=btn_r[3]
|
||||
#set_property -dict { PACKAGE_PIN AH10 IOSTANDARD LVCMOS15 } [get_ports { btn_r[4] }]; #IO_L13N_T2_MRCC_33 Sch=btn_r[4]
|
||||
|
||||
## Seven Segment Display
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { sseg_clk }]; #IO_L17P_T2_18 Sch=7seg_clk
|
||||
#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS33 } [get_ports { sseg_en }]; #IO_L17N_T2_18 Sch=7seg_en
|
||||
#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports { sseg_sdo }]; #IO_L16N_T2_18 Sch=7seg_sdo
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L4P_T0_16 Sch=ja_p[1]
|
||||
#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L4N_T0_16 Sch=ja_n[1]
|
||||
#set_property -dict { PACKAGE_PIN G23 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L6P_T0_16 Sch=ja_p[2]
|
||||
#set_property -dict { PACKAGE_PIN G24 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L6N_T0_VREF_16 Sch=ja_n[2]
|
||||
#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L5P_T0_16 Sch=ja_p[3]
|
||||
#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L5N_T0_16 Sch=ja_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L7P_T1_16 Sch=ja_p[4]
|
||||
#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L7N_T1_16 Sch=ja_n[4]
|
||||
|
||||
## Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L9P_T1_DQS_16 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L9N_T1_DQS_16 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L10P_T1_16 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L10N_T1_16 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L11P_T1_SRCC_16 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L11N_T1_SRCC_16 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L12P_T1_MRCC_16 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L12N_T1_MRCC_16 Sch=jb_n[4]
|
||||
|
||||
## Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L14P_T2_SRCC_16 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L14N_T2_SRCC_16 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L15P_T2_DQS_16 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15N_T2_DQS_16 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L16P_T2_16 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L16N_T2_16 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L17P_T2_16 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L17N_T2_16 Sch=jc[10]
|
||||
|
||||
## Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L18P_T2_16 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L18N_T2_16 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L19P_T3_16 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN H25 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L19N_T3_VREF_16 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L20P_T3_16 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20N_T3_16 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_16 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_16 Sch=jd[10]
|
||||
|
||||
## USB-UART Interface
|
||||
## NOTE:
|
||||
#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS33 } [get_ports { uart_tx }]; #IO_L22N_T3_16 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS33 } [get_ports { uart_rx }]; #IO_L22P_T3_16 Sch=uart_txd_in
|
||||
|
||||
## USB-HID PS/2 Interface for Keyboard
|
||||
#set_property -dict { PACKAGE_PIN AF23 IOSTANDARD LVCMOS33 } [get_ports { ps2_keyboard_clk }]; #IO_L11N_T1_SRCC_12 Sch=ps2_clk[0]
|
||||
#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 } [get_ports { ps2_keyboard_data }]; #IO_L12P_T1_MRCC_12 Sch=ps2_data[0]
|
||||
|
||||
## USB-HID PS/2 Interface for Mouse
|
||||
#set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { ps2_mouse_clk }]; #IO_L12N_T1_MRCC_12 Sch=ps2_clk[1]
|
||||
#set_property -dict { PACKAGE_PIN AF22 IOSTANDARD LVCMOS33 } [get_ports { ps2_mouse_data }]; #IO_L13P_T2_MRCC_12 Sch=ps2_data[1]
|
||||
|
||||
## Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L9P_T1_DQS_32 Sch=aud_adc_sdata
|
||||
#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L11P_T1_SRCC_32 Sch=aud_adr[0]
|
||||
#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L11N_T1_SRCC_32 Sch=aud_adr[1]
|
||||
#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L10P_T1_32 Sch=aud_bclk
|
||||
#set_property -dict { PACKAGE_PIN AK18 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L9N_T1_DQS_32 Sch=aud_dac_sdata
|
||||
#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L10N_T1_32 Sch=aud_lrclk
|
||||
#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L12P_T1_MRCC_32 Sch=aud_mclk
|
||||
#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_25_VRP_32 Sch=aud_scl
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_0_VRN_32 Sch=aud_sda
|
||||
|
||||
## Dedicated Analog Inputs
|
||||
#set_property -dict { PACKAGE_PIN R15 } [get_ports { v_p }]; #VP_0 Sch=v_p
|
||||
#set_property -dict { PACKAGE_PIN T14 } [get_ports { v_n }]; #VN_0 Sch=v_n
|
||||
|
||||
## ChipKit Outer Digital Header
|
||||
#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS33 } [get_ports { ck_io0 }]; #IO_L20N_T3_A19_15 Sch=ck_io[0]
|
||||
#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS33 } [get_ports { ck_io1 }]; #IO_L18P_T2_A24_15 Sch=ck_io[1]
|
||||
#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { ck_io2 }]; #IO_L22N_T3_A16_15 Sch=ck_io[2]
|
||||
#set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS33 } [get_ports { ck_io3 }]; #IO_25_16 Sch=ck_io[3]
|
||||
#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS33 } [get_ports { ck_io4 }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=ck_io[4]
|
||||
#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS33 } [get_ports { ck_io5 }]; #IO_L23N_T3_FWE_B_15 Sch=ck_io[5]
|
||||
#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS33 } [get_ports { ck_io6 }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=ck_io[6]
|
||||
#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS33 } [get_ports { ck_io7 }]; #IO_L13N_T2_MRCC_15 Sch=ck_io[7]
|
||||
#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS33 } [get_ports { ck_io8 }]; #IO_L15P_T2_DQS_15 Sch=ck_io[8]
|
||||
#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS33 } [get_ports { ck_io9 }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=ck_io[9]
|
||||
|
||||
## ChipKit SPI Header
|
||||
## NOTE: The ChipKit SPI header ports can also be used as digital I/O and share FPGA pins with ck_io10-13
|
||||
#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS33 } [get_ports { ck_io10_ss }]; #IO_L14N_T2_SRCC_15 Sch=ck_io10_ss
|
||||
#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS33 } [get_ports { ck_io11_mosi }]; #IO_L16N_T2_A27_15 Sch=ck_io11_mosi
|
||||
#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS33 } [get_ports { ck_io12_miso }]; #IO_L17P_T2_A26_15 Sch=ck_io12_miso
|
||||
#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS33 } [get_ports { ck_io13_sck }]; #IO_L17N_T2_A25_15 Sch=ck_io13_sck
|
||||
|
||||
## ChipKit Inner Digital Header
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L6P_T0_15 Sch=ck_io[26]
|
||||
#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L21N_T3_DQS_A18_15 Sch=ck_io[27]
|
||||
#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L21P_T3_DQS_15 Sch=ck_io[28]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_0_15 Sch=ck_io[29]
|
||||
#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_L22P_T3_A17_15 Sch=ck_io[30]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L19N_T3_A21_VREF_15 Sch=ck_io[31]
|
||||
#set_property -dict { PACKAGE_PIN F23 IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_0_16 Sch=ck_io[32]
|
||||
#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_15 Sch=ck_io[33]
|
||||
#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=ck_io[34]
|
||||
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L19P_T3_A22_15 Sch=ck_io[35]
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_25_15 Sch=ck_io[36]
|
||||
#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L14P_T2_SRCC_15 Sch=ck_io[37]
|
||||
#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L24P_T3_RS1_15 Sch=ck_io[38]
|
||||
#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L24N_T3_RS0_15 Sch=ck_io[39]
|
||||
#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L16P_T2_A28_15 Sch=ck_io[40]
|
||||
#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L18N_T2_A23_15 Sch=ck_io[41]
|
||||
|
||||
## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
|
||||
## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS33 } [get_ports { vaux10_p }]; #IO_L7P_T1_AD10P_15 Sch=ck_an_p[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS33 } [get_ports { vaux10_n }]; #IO_L7N_T1_AD10N_15 Sch=ck_an_n[0] ChipKit pin=A0
|
||||
#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { vaux8_p }]; #IO_L2P_T0_AD8P_15 Sch=ck_an_p[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { vaux8_n }]; #IO_L2N_T0_AD8N_15 Sch=ck_an_n[1] ChipKit pin=A1
|
||||
#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { vaux0_p }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { vaux0_n }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[2] ChipKit pin=A2
|
||||
#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { vaux1_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_an_p[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { vaux1_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ck_an_n[3] ChipKit pin=A3
|
||||
#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { vaux9_p }]; #IO_L4P_T0_AD9P_15 Sch=ck_an_p[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { vaux9_n }]; #IO_L4N_T0_AD9N_15 Sch=ck_an_n[4] ChipKit pin=A4
|
||||
#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS33 } [get_ports { vaux2_p }]; #IO_L5P_T0_AD2P_15 Sch=ck_an_p[5] ChipKit pin=A5
|
||||
#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS33 } [get_ports { vaux2_n }]; #IO_L5N_T0_AD2N_15 Sch=ck_an_n[5] ChipKit pin=A5
|
||||
## ChipKit Outer Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using these ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_L1P_T0_16 Sch=ck_a[0]
|
||||
#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L1N_T0_16 Sch=ck_a[1]
|
||||
#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L2P_T0_16 Sch=ck_a[2]
|
||||
#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L2N_T0_16 Sch=ck_a[3]
|
||||
#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L3P_T0_DQS_16 Sch=ck_a[4]
|
||||
#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L3N_T0_DQS_16 Sch=ck_a[5]
|
||||
|
||||
## ChipKit Inner Analog Header - as Differential Analog Inputs
|
||||
## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
|
||||
## WARNING: Do not use both sets of constraints at the same time!
|
||||
## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
|
||||
#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS33 } [get_ports { vaux3_p }]; #IO_L8P_T1_AD3P_15 Sch=fpga_ad_p[3] ChipKit pin=A6
|
||||
#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS33 } [get_ports { vaux3_n }]; #IO_L8N_T1_AD3N_15 Sch=fpga_ad_n[3] ChipKit pin=A7
|
||||
#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS33 } [get_ports { vaux11_p }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fpga_ad_p[11] ChipKit pin=A8
|
||||
#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS33 } [get_ports { vaux11_n }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fpga_ad_n[11] ChipKit pin=A9
|
||||
#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS33 } [get_ports { vaux4_p }]; #IO_L10P_T1_AD4P_15 Sch=fpga_ad_p[4] ChipKit pin=A10
|
||||
#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS33 } [get_ports { vaux4_n }]; #IO_L10N_T1_AD4N_15 Sch=fpga_ad_n[4] ChipKit pin=A11
|
||||
## ChipKit Inner Analog Header - as Digital I/O
|
||||
## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
|
||||
#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS33 } [get_ports { ck_a6 }]; #IO_L8N_T1_AD3N_15 Sch=fpga_ad_n[3]
|
||||
#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS33 } [get_ports { ck_a7 }]; #IO_L8P_T1_AD3P_15 Sch=fpga_ad_p[3]
|
||||
#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS33 } [get_ports { ck_a8 }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fpga_ad_n[11]
|
||||
#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS33 } [get_ports { ck_a9 }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fpga_ad_p[11]
|
||||
#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L10N_T1_AD4N_15 Sch=fpga_ad_n[4]
|
||||
#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L10P_T1_AD4P_15 Sch=fpga_ad_p[4]
|
||||
|
||||
## ChipKit I2C
|
||||
#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=ck_scl
|
||||
#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L20P_T3_A20_15 Sch=ck_sda
|
||||
|
||||
## Misc. ChipKit signals
|
||||
#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L23P_T3_FOE_B_15 Sch=ck_ioa
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L6N_T0_VREF_15 Sch=ck_rst
|
||||
|
||||
## Fan Control
|
||||
#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_L23N_T3_16 Sch=fan_pwm
|
||||
#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS33 } [get_ports { fan_tach }]; #IO_L23P_T3_16 Sch=fan_tach
|
||||
|
||||
## USB Host Port
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { usbh_gpx }]; #IO_L22P_T3_18 Sch=usbh_gpx
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { usbh_int }]; #IO_L22N_T3_18 Sch=usbh_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { usbh_miso }]; #IO_L24P_T3_18 Sch=usbh_miso
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { usbh_mosi }]; #IO_L24N_T3_18 Sch=usbh_mosi
|
||||
#set_property -dict { PACKAGE_PIN AD13 IOSTANDARD LVCMOS15 } [get_ports { usbh_rst }]; #IO_25_VRP_33 Sch=usbh_rst
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { usbh_sclk }]; #IO_L23P_T3_18 Sch=usbh_sclk
|
||||
#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { usbh_ss }]; #IO_L23N_T3_18 Sch=usbh_ss
|
||||
|
||||
## RS232 Connector
|
||||
#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS33 } [get_ports { rs232_rxd }]; #IO_L18P_T2_18 Sch=uart1_rxd
|
||||
#set_property -dict { PACKAGE_PIN G12 IOSTANDARD LVCMOS33 } [get_ports { rs232_txd }]; #IO_0_18 Sch=uart1_txd
|
||||
|
||||
# 3-Pin UART Connector (TTL-Compliant)
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ttl_rxd }]; #IO_L18N_T2_18 Sch=uart2_rxd
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ttl_txd }]; #IO_25_18 Sch=uart2_txd
|
||||
|
||||
## VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L4N_T0_12 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L9P_T1_DQS_12 Sch=vga_b[4]
|
||||
#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L9N_T1_DQS_12 Sch=vga_b[5]
|
||||
#set_property -dict { PACKAGE_PIN AB23 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L3N_T0_DQS_12 Sch=vga_b[6]
|
||||
#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L3P_T0_DQS_12 Sch=vga_b[7]
|
||||
#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L4P_T0_12 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L5N_T0_12 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2P_T0_12 Sch=vga_g[4]
|
||||
#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L5P_T0_12 Sch=vga_g[5]
|
||||
#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L6N_T0_VREF_12 Sch=vga_g[6]
|
||||
#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L6P_T0_12 Sch=vga_g[7]
|
||||
#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7N_T1_12 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7P_T1_12 Sch=vga_r[4]
|
||||
#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_12 Sch=vga_r[5]
|
||||
#set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L1P_T0_12 Sch=vga_r[6]
|
||||
#set_property -dict { PACKAGE_PIN AD22 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L8N_T1_12 Sch=vga_r[7]
|
||||
#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L10P_T1_12 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN AE23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L11P_T1_SRCC_12 Sch=vga_vs
|
||||
#set_property -dict { PACKAGE_PIN AC22 IOSTANDARD LVCMOS33 } [get_ports { vga_scl }]; #IO_L8P_T1_12 Sch=vga_scl
|
||||
#set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { vga_sda }]; #IO_L2N_T0_12 Sch=vga_sda
|
||||
|
||||
## HDMI Input
|
||||
#set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L19N_T3_VREF_12 Sch=hdmi_rx_cec
|
||||
#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_n }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVDS } [get_ports { hdmi_rx_clk_p }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L19P_T3_12 Sch=hdmi_rx_hpa
|
||||
#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[1] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[1] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVDS } [get_ports { hdmi_rx_n[2] }]; #IO_L23N_T3_13 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVDS } [get_ports { hdmi_rx_p[2] }]; #IO_L23P_T3_13 Sch=hdmi_rx_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17N_T2_12 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17P_T2_12 Sch=hdmi_rx_sda
|
||||
|
||||
## HDMI Output
|
||||
#set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L18N_T2_12 Sch=hdmi_tx_cec
|
||||
#set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_n }]; #IO_L22N_T3_12 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVDS } [get_ports { hdmi_tx_clk_p }]; #IO_L22P_T3_12 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L18P_T2_12 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[0] }]; #IO_L23N_T3_12 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN AH21 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[0] }]; #IO_L23P_T3_12 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[1] }]; #IO_L21N_T3_DQS_12 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[1] }]; #IO_L21P_T3_DQS_12 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVDS } [get_ports { hdmi_tx_n[2] }]; #IO_L20N_T3_12 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVDS } [get_ports { hdmi_tx_p[2] }]; #IO_L20P_T3_12 Sch=hdmi_tx_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L24P_T3_12 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L24N_T3_12 Sch=hdmi_tx_sda
|
||||
|
||||
## Ethernet
|
||||
#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { eth_intb }]; #IO_L16N_T2_32 Sch=eth_intb
|
||||
#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { eth_mdc }]; #IO_L16P_T2_32 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { eth_mdio }]; #IO_L15N_T2_DQS_32 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { eth_phyrst }]; #IO_L15P_T2_DQS_32 Sch=eth_phyrst
|
||||
#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { eth_pmeb }]; #IO_L17P_T2_32 Sch=eth_pmeb
|
||||
#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_clk }]; #IO_L13P_T2_MRCC_32 Sch=eth_rx_clk
|
||||
#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_ctl }]; #IO_L19N_T3_VREF_32 Sch=eth_rx_ctl
|
||||
#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[0] }]; #IO_L19P_T3_32 Sch=eth_rx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AE18 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[1] }]; #IO_L13N_T2_MRCC_32 Sch=eth_rx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[2] }]; #IO_L14N_T2_SRCC_32 Sch=eth_rx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { eth_rx_d[3] }]; #IO_L17N_T2_32 Sch=eth_rx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_clk }]; #IO_L20N_T3_32 Sch=eth_tx_clk
|
||||
#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[0] }]; #IO_L20P_T3_32 Sch=eth_tx_d[0]
|
||||
#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[1] }]; #IO_L14P_T2_SRCC_32 Sch=eth_tx_d[1]
|
||||
#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[2] }]; #IO_L12N_T1_MRCC_32 Sch=eth_tx_d[2]
|
||||
#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_d[3] }]; #IO_L18N_T2_32 Sch=eth_tx_d[3]
|
||||
#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { eth_tx_en }]; #IO_L18P_T2_32 Sch=eth_tx_en
|
||||
|
||||
## SFP+ Clock Multiplier / FPGA GTX Transceiver Clock Source
|
||||
#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { sfp_clk_alarm_b }]; #IO_L21P_T3_DQS_32 Sch=sfp_clk_alarm_b
|
||||
#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { sfp_clk_rst }]; #IO_L21N_T3_DQS_32 Sch=sfp_clk_rst
|
||||
#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 } [get_ports { sfp_clk_scl }]; #IO_25_12 Sch=sfp_clk_scl
|
||||
#set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { sfp_clk_sda }]; #IO_0_12 Sch=sfp_clk_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVDS } [get_ports { sfp_rec_clk_n }]; #IO_L13N_T2_MRCC_18 Sch=sfp_rec_clk_n
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVDS } [get_ports { sfp_rec_clk_p }]; #IO_L13P_T2_MRCC_18 Sch=sfp_rec_clk_p
|
||||
|
||||
## SFP+ Connector 1
|
||||
#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { sfp1_mod_detect }]; #IO_L23P_T3_32 Sch=sfp1_mod_detect
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { sfp1_rs[0] }]; #IO_L24P_T3_32 Sch=sfp1_rs[0]
|
||||
#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { sfp1_rs[1] }]; #IO_L24N_T3_32 Sch=sfp1_rs[1]
|
||||
#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { sfp1_rx_los }]; #IO_L23N_T3_32 Sch=sfp1_rx_los
|
||||
#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { sfp1_tx_disable }]; #IO_L22N_T3_32 Sch=sfp1_tx_disable
|
||||
#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { sfp1_tx_fault }]; #IO_L22P_T3_32 Sch=sfp1_tx_fault
|
||||
#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp1_scl }]; #IO_L13N_T2_MRCC_16 Sch=i2c_sfp1_scl
|
||||
#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp1_sda }]; #IO_L13P_T2_MRCC_16 Sch=i2c_sfp1_sda
|
||||
|
||||
## SFP+ Connector 2
|
||||
#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { sfp2_mod_detect }]; #IO_L18P_T2_33 Sch=sfp2_mod_detect
|
||||
#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { sfp2_rs[0] }]; #IO_L14P_T2_SRCC_33 Sch=sfp2_rs[0]
|
||||
#set_property -dict { PACKAGE_PIN AF10 IOSTANDARD LVCMOS15 } [get_ports { sfp2_rs[1] }]; #IO_L14N_T2_SRCC_33 Sch=sfp2_rs[1]
|
||||
#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { sfp2_rx_los }]; #IO_L18N_T2_33 Sch=sfp2_rx_los
|
||||
#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { sfp2_tx_disable }]; #IO_L17N_T2_33 Sch=sfp2_tx_disable
|
||||
#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { sfp2_tx_fault }]; #IO_L17P_T2_33 Sch=sfp2_tx_fault
|
||||
#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp2_scl }]; #IO_L8N_T1_16 Sch=i2c_sfp2_scl
|
||||
#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS33 } [get_ports { i2c_sfp2_sda }]; #IO_L8P_T1_16 Sch=i2c_sfp2_sda
|
||||
|
||||
## Quad-SPI Flash
|
||||
## NOTE: the SCK clock signal can be driven using the STARTUPE2 primitive
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
|
||||
#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1]
|
||||
#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2]
|
||||
#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_d[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3]
|
||||
|
||||
## SD Card Slot
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_25_14 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L15P_T2_DQS_12 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN AE25 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_12 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN AF25 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L16N_T2_12 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN AG24 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L14P_T2_SRCC_12 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_12 Sch=sd_dat[3]
|
||||
#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L10N_T1_12 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk }]; #IO_L15N_T2_DQS_12 Sch=sd_sclk
|
||||
|
||||
## Parallel Flash Memory
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { flash_byte }]; #IO_L19P_T3_17 Sch=flash_byte
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { flash_ce[0] }]; #IO_L18P_T2_17 Sch=flash_ce[1]
|
||||
#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { flash_ce[1] }]; #IO_L15P_T2_DQS_17 Sch=flash_ce[2]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { flash_oe }]; #IO_L15N_T2_DQS_17 Sch=flash_oe
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { flash_rst }]; #IO_L16N_T2_17 Sch=flash_rst
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { flash_ryby[0] }]; #IO_L16P_T2_17 Sch=flash_ryby[1]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { flash_ryby[1] }]; #IO_L24N_T3_17 Sch=flash_ryby[2]
|
||||
#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { flash_we }]; #IO_L9P_T1_DQS_17 Sch=flash_we
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[0] }]; #IO_L13P_T2_MRCC_17 Sch=flash_a[0]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[1] }]; #IO_L22N_T3_17 Sch=flash_a[1]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[2] }]; #IO_L17N_T2_17 Sch=flash_a[2]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { flash_a[3] }]; #IO_L20P_T3_17 Sch=flash_a[3]
|
||||
#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[4] }]; #IO_L20N_T3_17 Sch=flash_a[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[5] }]; #IO_L22P_T3_17 Sch=flash_a[5]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[6] }]; #IO_L17P_T2_17 Sch=flash_a[6]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[7] }]; #IO_L14N_T2_SRCC_17 Sch=flash_a[7]
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[8] }]; #IO_L12P_T1_MRCC_17 Sch=flash_a[8]
|
||||
#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[9] }]; #IO_L9N_T1_DQS_17 Sch=flash_a[9]
|
||||
#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[10] }]; #IO_L24P_T3_17 Sch=flash_a[10]
|
||||
#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[11] }]; #IO_L12N_T1_MRCC_17 Sch=flash_a[11]
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[12] }]; #IO_L10P_T1_17 Sch=flash_a[12]
|
||||
#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { flash_a[13] }]; #IO_L11P_T1_SRCC_17 Sch=flash_a[13]
|
||||
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[14] }]; #IO_L10N_T1_17 Sch=flash_a[14]
|
||||
#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS33 } [get_ports { flash_a[15] }]; #IO_L11N_T1_SRCC_17 Sch=flash_a[15]
|
||||
#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS33 } [get_ports { flash_a[16] }]; #IO_L21N_T3_DQS_17 Sch=flash_a[16]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[17] }]; #IO_L13N_T2_MRCC_17 Sch=flash_a[17]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { flash_a[18] }]; #IO_25_17 Sch=flash_a[18]
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[19] }]; #IO_L14P_T2_SRCC_17 Sch=flash_a[19]
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { flash_a[20] }]; #IO_L18N_T2_17 Sch=flash_a[20]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { flash_a[21] }]; #IO_0_17 Sch=flash_a[21]
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[22] }]; #IO_L23P_T3_17 Sch=flash_a[22]
|
||||
#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS33 } [get_ports { flash_a[23] }]; #IO_L23N_T3_17 Sch=flash_a[23]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[24] }]; #IO_L19N_T3_VREF_17 Sch=flash_a[24]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { flash_a[25] }]; #IO_L21P_T3_DQS_17 Sch=flash_a[25]
|
||||
#set_property -dict { PACKAGE_PIN L11 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[0] }]; #IO_L6P_T0_18 Sch=flash_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[1] }]; #IO_L4P_T0_18 Sch=flash_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[2] }]; #IO_L3P_T0_DQS_18 Sch=flash_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[3] }]; #IO_L5N_T0_18 Sch=flash_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[4] }]; #IO_L2P_T0_18 Sch=flash_dq[4]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[5] }]; #IO_L2N_T0_18 Sch=flash_dq[5]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[6] }]; #IO_L1P_T0_18 Sch=flash_dq[6]
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[7] }]; #IO_L7N_T1_18 Sch=flash_dq[7]
|
||||
#set_property -dict { PACKAGE_PIN K11 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[8] }]; #IO_L6N_T0_VREF_18 Sch=flash_dq[8]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[9] }]; #IO_L3N_T0_DQS_18 Sch=flash_dq[9]
|
||||
#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[10] }]; #IO_L8P_T1_18 Sch=flash_dq[10]
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[11] }]; #IO_L5P_T0_18 Sch=flash_dq[11]
|
||||
#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[12] }]; #IO_L8N_T1_18 Sch=flash_dq[12]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[13] }]; #IO_L7P_T1_18 Sch=flash_dq[13]
|
||||
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[14] }]; #IO_L4N_T0_18 Sch=flash_dq[14]
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[15] }]; #IO_L1N_T0_18 Sch=flash_dq[15]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[16] }]; #IO_L3P_T0_DQS_17 Sch=flash_dq[16]
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[17] }]; #IO_L3N_T0_DQS_17 Sch=flash_dq[17]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[18] }]; #IO_L6P_T0_17 Sch=flash_dq[18]
|
||||
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[19] }]; #IO_L4N_T0_17 Sch=flash_dq[19]
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[20] }]; #IO_L2N_T0_17 Sch=flash_dq[20]
|
||||
#set_property -dict { PACKAGE_PIN K20 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[21] }]; #IO_L6N_T0_VREF_17 Sch=flash_dq[21]
|
||||
#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[22] }]; #IO_L8P_T1_17 Sch=flash_dq[22]
|
||||
#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[23] }]; #IO_L8N_T1_17 Sch=flash_dq[23]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[24] }]; #IO_L5P_T0_17 Sch=flash_dq[24]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[25] }]; #IO_L1N_T0_17 Sch=flash_dq[25]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[26] }]; #IO_L1P_T0_17 Sch=flash_dq[26]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[27] }]; #IO_L4P_T0_17 Sch=flash_dq[27]
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[28] }]; #IO_L2P_T0_17 Sch=flash_dq[28]
|
||||
#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[29] }]; #IO_L7N_T1_17 Sch=flash_dq[29]
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[30] }]; #IO_L5N_T0_17 Sch=flash_dq[30]
|
||||
#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS33 } [get_ports { flash_dq[31] }]; #IO_L7P_T1_17 Sch=flash_dq[31]
|
||||
|
||||
## SRAM Memories
|
||||
#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { sram1_bhe }]; #IO_L23P_T3_A03_D19_14 Sch=sram1-bhe
|
||||
#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { sram1_ble }]; #IO_L18P_T2_13 Sch=sram1-ble
|
||||
#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { sram1_ce }]; #IO_L14P_T2_SRCC_14 Sch=sram1-ce
|
||||
#set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { sram1_oe }]; #IO_L16N_T2_13 Sch=sram1-oe
|
||||
#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD LVCMOS33 } [get_ports { sram1_we }]; #IO_L14P_T2_SRCC_13 Sch=sram1-we
|
||||
#set_property -dict { PACKAGE_PIN AC29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[0] }]; #IO_L7P_T1_13 Sch=sram1-io[0]
|
||||
#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[1] }]; #IO_L5N_T0_D07_14 Sch=sram1-io[1]
|
||||
#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[2] }]; #IO_L7N_T1_13 Sch=sram1-io[2]
|
||||
#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[3] }]; #IO_L5P_T0_D06_14 Sch=sram1-io[3]
|
||||
#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[4] }]; #IO_L19N_T3_VREF_13 Sch=sram1-io[4]
|
||||
#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[5] }]; #IO_L14N_T2_SRCC_13 Sch=sram1-io[5]
|
||||
#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[6] }]; #IO_L10P_T1_13 Sch=sram1-io[6]
|
||||
#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[7] }]; #IO_L10N_T1_13 Sch=sram1-io[7]
|
||||
#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[8] }]; #IO_L18N_T2_13 Sch=sram1-io[8]
|
||||
#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[9] }]; #IO_L17N_T2_13 Sch=sram1-io[9]
|
||||
#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[10] }]; #IO_L18P_T2_A12_D28_14 Sch=sram1-io[10]
|
||||
#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[11] }]; #IO_L23N_T3_A02_D18_14 Sch=sram1-io[11]
|
||||
#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[12] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram1-io[12]
|
||||
#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[13] }]; #IO_L22N_T3_A04_D20_14 Sch=sram1-io[13]
|
||||
#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[14] }]; #IO_L15N_T2_DQS_13 Sch=sram1-io[14]
|
||||
#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { sram1_io[15] }]; #IO_L15P_T2_DQS_13 Sch=sram1-io[15]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { sram2_bhe[0] }]; #IO_L5N_T0_13 Sch=sram2-bhe[1]
|
||||
#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { sram2_bhe[1] }]; #IO_L16P_T2_CSI_B_14 Sch=sram2-bhe[2]
|
||||
#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { sram2_ble[0] }]; #IO_L19P_T3_13 Sch=sram2-ble[1]
|
||||
#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { sram2_ble[1] }]; #IO_L2P_T0_13 Sch=sram2-ble[2]
|
||||
#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { sram2_ce[0] }]; #IO_L3P_T0_DQS_13 Sch=sram2-ce[1]
|
||||
#set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sram2_ce[1] }]; #IO_L8N_T1_D12_14 Sch=sram2-ce[2]
|
||||
#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { sram2_oe[0] }]; #IO_L6N_T0_VREF_13 Sch=sram2-oe[1]
|
||||
#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { sram2_oe[1] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram2-oe[2]
|
||||
#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { sram2_we[0] }]; #IO_L20P_T3_A08_D24_14 Sch=sram2-we[1]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sram2_we[1] }]; #IO_L4P_T0_D04_14 Sch=sram2-we[2]
|
||||
#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[0] }]; #IO_L1P_T0_13 Sch=sram2-io[0]
|
||||
#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[1] }]; #IO_L1N_T0_13 Sch=sram2-io[1]
|
||||
#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[2] }]; #IO_L13P_T2_MRCC_14 Sch=sram2-io[2]
|
||||
#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[3] }]; #IO_L3N_T0_DQS_13 Sch=sram2-io[3]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sram2-io[4]
|
||||
#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[5] }]; #IO_L18N_T2_A11_D27_14 Sch=sram2-io[5]
|
||||
#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[6] }]; #IO_L21P_T3_DQS_14 Sch=sram2-io[6]
|
||||
#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[7] }]; #IO_L10P_T1_D14_14 Sch=sram2-io[7]
|
||||
#set_property -dict { PACKAGE_PIN Y25 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[8] }]; #IO_0_13 Sch=sram2-io[8]
|
||||
#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[9] }]; #IO_L6P_T0_13 Sch=sram2-io[9]
|
||||
#set_property -dict { PACKAGE_PIN AA27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[10] }]; #IO_L5P_T0_13 Sch=sram2-io[10]
|
||||
#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[11] }]; #IO_L20N_T3_A07_D23_14 Sch=sram2-io[11]
|
||||
#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[12] }]; #IO_L24N_T3_A00_D16_14 Sch=sram2-io[12]
|
||||
#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[13] }]; #IO_L24P_T3_A01_D17_14 Sch=sram2-io[13]
|
||||
#set_property -dict { PACKAGE_PIN AD28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[14] }]; #IO_L11N_T1_SRCC_13 Sch=sram2-io[14]
|
||||
#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[15] }]; #IO_L11P_T1_SRCC_13 Sch=sram2-io[15]
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[16] }]; #IO_0_14 Sch=sram2-io[16]
|
||||
#set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[17] }]; #IO_L10N_T1_D15_14 Sch=sram2-io[17]
|
||||
#set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[18] }]; #IO_L9P_T1_DQS_14 Sch=sram2-io[18]
|
||||
#set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[19] }]; #IO_L9N_T1_DQS_D13_14 Sch=sram2-io[19]
|
||||
#set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[20] }]; #IO_L7N_T1_D10_14 Sch=sram2-io[20]
|
||||
#set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[21] }]; #IO_L11P_T1_SRCC_14 Sch=sram2-io[21]
|
||||
#set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[22] }]; #IO_L7P_T1_D09_14 Sch=sram2-io[22]
|
||||
#set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[23] }]; #IO_L8P_T1_D11_14 Sch=sram2-io[23]
|
||||
#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[24] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram2-io[24]
|
||||
#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[25] }]; #IO_L17N_T2_A13_D29_14 Sch=sram2-io[25]
|
||||
#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[26] }]; #IO_L13N_T2_MRCC_14 Sch=sram2-io[26]
|
||||
#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[27] }]; #IO_L2N_T0_13 Sch=sram2-io[27]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=sram2-io[28]
|
||||
#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[29] }]; #IO_L4N_T0_D05_14 Sch=sram2-io[29]
|
||||
#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[30] }]; #IO_L17P_T2_A14_D30_14 Sch=sram2-io[30]
|
||||
#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { sram2_io[31] }]; #IO_L4P_T0_13 Sch=sram2-io[31]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN AE29 IOSTANDARD LVCMOS33 } [get_ports { sram_a[0] }]; #IO_L9N_T1_DQS_13 Sch=sram-a[0]
|
||||
#set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { sram_a[1] }]; #IO_L16P_T2_13 Sch=sram-a[1]
|
||||
#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { sram_a[2] }]; #IO_L9P_T1_DQS_13 Sch=sram-a[2]
|
||||
#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[3] }]; #IO_L16N_T2_A15_D31_14 Sch=sram-a[3]
|
||||
#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { sram_a[4] }]; #IO_L12P_T1_MRCC_14 Sch=sram-a[4]
|
||||
#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { sram_a[5] }]; #IO_L14N_T2_SRCC_14 Sch=sram-a[5]
|
||||
#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[6] }]; #IO_L11N_T1_SRCC_14 Sch=sram-a[6]
|
||||
#set_property -dict { PACKAGE_PIN R24 IOSTANDARD LVCMOS33 } [get_ports { sram_a[7] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sram-a[7]
|
||||
#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[8] }]; #IO_L20N_T3_13 Sch=sram-a[8]
|
||||
#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[9] }]; #IO_L20P_T3_13 Sch=sram-a[9]
|
||||
#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { sram_a[10] }]; #IO_L8P_T1_13 Sch=sram-a[10]
|
||||
#set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { sram_a[11] }]; #IO_L4N_T0_13 Sch=sram-a[11]
|
||||
#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sram_a[12] }]; #IO_L19P_T3_A10_D26_14 Sch=sram-a[12]
|
||||
#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[13] }]; #IO_L21P_T3_DQS_13 Sch=sram-a[13]
|
||||
#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { sram_a[14] }]; #IO_L22P_T3_A05_D21_14 Sch=sram-a[14]
|
||||
#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[15] }]; #IO_L21N_T3_DQS_13 Sch=sram-a[15]
|
||||
#set_property -dict { PACKAGE_PIN AE26 IOSTANDARD LVCMOS33 } [get_ports { sram_a[16] }]; #IO_25_13 Sch=sram-a[16]
|
||||
#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { sram_a[17] }]; #IO_L12N_T1_MRCC_14 Sch=sram-a[17]
|
||||
#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { sram_a[18] }]; #IO_L17P_T2_13 Sch=sram-a[18]
|
||||
#set_property -dict { PACKAGE_PIN AA30 IOSTANDARD LVCMOS33 } [get_ports { sram_a[19] }]; #IO_L8N_T1_13 Sch=sram-a[19]
|
||||
186
Bibliotheken/digilent-xdc-master/USB104-A7-100T-Master.xdc
Normal file
186
Bibliotheken/digilent-xdc-master/USB104-A7-100T-Master.xdc
Normal file
@ -0,0 +1,186 @@
|
||||
## This file is a general .xdc for the USB104 A7-100T Rev. B.2
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## 100MHz Clock
|
||||
#set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk]; #IO_L12P_T1_MRCC Sch=GCLK100
|
||||
#create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
|
||||
|
||||
## Buttons
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L16N_T2_A15_D31_14 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L17P_T2_A14_D30_14 Sch=btn[1]
|
||||
|
||||
## LEDs
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L12N_T1_MRCC_14 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L13P_T2_MRCC_14 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L13N_T2_MRCC_14 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L14P_T2_SRCC_14 Sch=led[3]
|
||||
|
||||
## USB UART
|
||||
## Note: Port names are from the perspective of the FPGA.
|
||||
#set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports { uart_rx }]; #IO_L20P_T3_A08_D24_14 Sch=uart_txd_in
|
||||
#set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports { uart_tx }]; #IO_L20N_T3_A07_D23_14 Sch=uart_rxd_out
|
||||
|
||||
## DPTI/DSPI
|
||||
#set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports { prog_spien }]; #IO_L4P_T0_D04_14 Sch=prog_spien
|
||||
#set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports { prog_d[0] }]; #IO_L4N_T0_D05_14 Sch=prog_d[0]/sck
|
||||
#set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports { prog_d[1] }]; #IO_L5P_T0_D06_14 Sch=prog_d[1]/mosi
|
||||
#set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports { prog_d[2] }]; #IO_L5N_T0_D07_14 Sch=prog_d[2]/miso
|
||||
#set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports { prog_d[3] }]; #IO_L6N_T0_D08_14 Sch=prog_d[3]/ss
|
||||
#set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports { prog_d[4] }]; #IO_L7P_T1_D09_14 Sch=prog_d[4]
|
||||
#set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports { prog_d[5] }]; #IO_L7N_T1_D10_14 Sch=prog_d[5]
|
||||
#set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports { prog_d[6] }]; #IO_L8P_T1_D11_14 Sch=prog_d[6]
|
||||
#set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports { prog_d[7] }]; #IO_L8N_T1_D12_14 Sch=prog_d[7]
|
||||
#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports { prog_oen }]; #IO_L9P_T1_DQS_14 Sch=prog_oen
|
||||
#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports { prog_siwun }]; #IO_L9N_T1_DQS_D13_14 Sch=prog_siwun
|
||||
#set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports { prog_rxen }]; #IO_L10P_T1_D14_14 Sch=prog_rxen
|
||||
#set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports { prog_txen }]; #IO_L10N_T1_D15_14 Sch=prog_txen
|
||||
#set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports { prog_rdn }]; #IO_L11P_T1_SRCC_14 Sch=prog_rdn
|
||||
#set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports { prog_wrn }]; #IO_L11N_T1_SRCC_14 Sch=prog_wrn
|
||||
#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports { prog_clko }]; #IO_L12P_T1_MRCC_14 Sch=prog_clko
|
||||
|
||||
## Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }}]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { qspi_sck }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=qspi_sck
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
|
||||
## Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_35 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_35 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L14P_T2_SRCC_35 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L14N_T2_SRCC_35 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L15P_T2_DQS_35 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L15N_T2_DQS_35 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L16P_T2_35 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L16N_T2_35 Sch=ja[10]
|
||||
|
||||
### Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L7P_T1_AD6P_35 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L10N_T1_AD15N_35 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L10P_T1_AD15P_35 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L7N_T1_AD6N_35 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L8N_T1_AD14N_35 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L8P_T1_AD14P_35 Sch=jb[10]
|
||||
|
||||
### Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L1N_T0_AD4N_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L1P_T0_AD4P_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L2N_T0_AD12N_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L4N_T0_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_AD12P_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L4P_T0_35 Sch=jc[10]
|
||||
|
||||
## SYZYGY Port
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=syzygy_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=syzygy_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[1] }]; #IO_L7P_T1_AD2P_15 Sch=syzygy_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[1] }]; #IO_L7N_T1_AD2N_15 Sch=syzygy_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[2] }]; #IO_L8P_T1_AD10P_15 Sch=syzygy_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[2] }]; #IO_L8N_T1_AD10N_15 Sch=syzygy_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=syzygy_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=syzygy_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[4] }]; #IO_L11P_T1_SRCC_15 Sch=syzygy_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[4] }]; #IO_L11N_T1_SRCC_15 Sch=syzygy_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[5] }]; #IO_L12P_T1_MRCC_15 Sch=syzygy_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[5] }]; #IO_L12N_T1_MRCC_15 Sch=syzygy_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[6] }]; #IO_L20P_T3_A20_15 Sch=syzygy_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[6] }]; #IO_L20N_T3_A19_15 Sch=syzygy_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p[7] }]; #IO_L21P_T3_DQS_15 Sch=syzygy_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n[7] }]; #IO_L21N_T3_DQS_A18_15 Sch=syzygy_d_n[7]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[16] }]; #IO_L19P_T3_A22_15 Sch=syzygy_s[16]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[17] }]; #IO_L19N_T3_A21_VREF_15 Sch=syzygy_s[17]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[18] }]; #IO_L22P_T3_A17_15 Sch=syzygy_s[18]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[19] }]; #IO_L22N_T3_A16_15 Sch=syzygy_s[19]
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[20] }]; #IO_L23P_T3_FOE_B_15 Sch=syzygy_s[20]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[21] }]; #IO_L23N_T3_FWE_B_15 Sch=syzygy_s[21]
|
||||
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[22] }]; #IO_L24P_T3_RS1_15 Sch=syzygy_s[22]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[23] }]; #IO_L24N_T3_RS0_15 Sch=syzygy_s[23]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[24] }]; #IO_L15P_T2_DQS_15 Sch=syzygy_s[24]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[25] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=syzygy_s[25]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[26] }]; #IO_L16P_T2_A28_15 Sch=syzygy_s[26]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s[27] }]; #IO_L16N_T2_A27_15 Sch=syzygy_s[27]
|
||||
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_p }]; #IO_L13P_T2_MRCC_15 Sch=syzygy_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_n }]; #IO_L13N_T2_MRCC_15 Sch=syzygy_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_c2p_clk_p }]; #IO_L14P_T2_SRCC_15 Sch=syzygy_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_c2p_clk_n }]; #IO_L14N_T2_SRCC_15 Sch=syzygy_c2p_clk_n
|
||||
|
||||
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { syzygy_scl }]; #IO_L18P_T2_A12_D28_14 Sch=syzygy_scl
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 PULLUP TRUE } [get_ports { syzygy_sda }]; #IO_L18N_T2_A11_D27_14 Sch=syzygy_sda
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { syzygy_det }]; #IO_L19P_T3_A10_D26_14 Sch=syzygy_det
|
||||
|
||||
## Encryption Chip
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L18P_T2_35 Sch=crypto_sda
|
||||
|
||||
# Platform MCU Firmware Reprogramming
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { mcu_rstn }]; #IO_25_14 Sch=mcu_nrst_fpga
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { mcu_cs }]; #IO_L22N_T3_A04_D20_14 Sch=mcu_cs
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { mcu_mosi }]; #IO_L23P_T3_A03_D19_14 Sch=mcu_mosi
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { mcu_miso }]; #IO_L23N_T3_A02_D18_14 Sch=mcu_miso
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { mcu_sck }]; #IO_L24P_T3_A01_D17_14 Sch=mcu_sck
|
||||
|
||||
## Miscellaneous
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=mcu_rsvd[1]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[2] }]; #IO_L22P_T3_A05_D21_14 Sch=mcu_rsvd[2]
|
||||
|
||||
## DDR3
|
||||
#set_property -dict { PACKAGE_PIN R6 } [get_ports { ddr3_a[0] }]; #IO_L19P_T3_34 Sch=ddr3_a[0]
|
||||
#set_property -dict { PACKAGE_PIN R7 } [get_ports { ddr3_a[1] }]; #IO_L23P_T3_34 Sch=ddr3_a[1]
|
||||
#set_property -dict { PACKAGE_PIN P2 } [get_ports { ddr3_a[10] }]; #IO_L15P_T2_DQS_34 Sch=ddr3_a[10]
|
||||
#set_property -dict { PACKAGE_PIN P5 } [get_ports { ddr3_a[11] }]; #IO_L13N_T2_MRCC_34 Sch=ddr3_a[11]
|
||||
#set_property -dict { PACKAGE_PIN R1 } [get_ports { ddr3_a[12] }]; #IO_L17P_T2_34 Sch=ddr3_a[12]
|
||||
#set_property -dict { PACKAGE_PIN U8 } [get_ports { ddr3_a[13] }]; #IO_25_34 Sch=ddr3_a[13]
|
||||
#set_property -dict { PACKAGE_PIN N6 } [get_ports { ddr3_a[14] }]; #IO_L18N_T2_34 Sch=ddr3_a[14]
|
||||
#set_property -dict { PACKAGE_PIN T6 } [get_ports { ddr3_a[2] }]; #IO_L23N_T3_34 Sch=ddr3_a[2]
|
||||
#set_property -dict { PACKAGE_PIN U7 } [get_ports { ddr3_a[3] }]; #IO_L22P_T3_34 Sch=ddr3_a[3]
|
||||
#set_property -dict { PACKAGE_PIN T1 } [get_ports { ddr3_a[4] }]; #IO_L17N_T2_34 Sch=ddr3_a[4]
|
||||
#set_property -dict { PACKAGE_PIN V7 } [get_ports { ddr3_a[5] }]; #IO_L20P_T3_34 Sch=ddr3_a[5]
|
||||
#set_property -dict { PACKAGE_PIN P3 } [get_ports { ddr3_a[6] }]; #IO_L14N_T2_SRCC_34 Sch=ddr3_a[6]
|
||||
#set_property -dict { PACKAGE_PIN T8 } [get_ports { ddr3_a[7] }]; #IO_L24N_T3_34 Sch=ddr3_a[7]
|
||||
#set_property -dict { PACKAGE_PIN M6 } [get_ports { ddr3_a[8] }]; #IO_L18P_T2_34 Sch=ddr3_a[8]
|
||||
#set_property -dict { PACKAGE_PIN R8 } [get_ports { ddr3_a[9] }]; #IO_L24P_T3_34 Sch=ddr3_a[9]
|
||||
#set_property -dict { PACKAGE_PIN V6 } [get_ports { ddr3_ba[0] }]; #IO_L20N_T3_34 Sch=ddr3_ba[0]
|
||||
#set_property -dict { PACKAGE_PIN R2 } [get_ports { ddr3_ba[1] }]; #IO_L15N_T2_DQS_34 Sch=ddr3_ba[1]
|
||||
#set_property -dict { PACKAGE_PIN R5 } [get_ports { ddr3_ba[2] }]; #IO_L19N_T3_VREF_34 Sch=ddr3_ba[2]
|
||||
#set_property -dict { PACKAGE_PIN N4 } [get_ports { ddr3_cas }]; #IO_L16N_T2_34 Sch=ddr3_cas
|
||||
#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVDS } [get_ports { ddr3_ck_n }]; #IO_L21N_T3_DQS_34 Sch=ddr3_ck_n
|
||||
#set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVDS } [get_ports { ddr3_ck_p }]; #IO_L21P_T3_DQS_34 Sch=ddr3_ck_p
|
||||
#set_property -dict { PACKAGE_PIN N5 } [get_ports { ddr3_cke[0] }]; #IO_L13P_T2_MRCC_34 Sch=ddr3_cke[0]
|
||||
#set_property -dict { PACKAGE_PIN R3 } [get_ports { ddr3_d[0] }]; #IO_L11P_T1_SRCC_34 Sch=ddr3_d[0]
|
||||
#set_property -dict { PACKAGE_PIN V1 } [get_ports { ddr3_d[1] }]; #IO_L7N_T1_34 Sch=ddr3_d[1]
|
||||
#set_property -dict { PACKAGE_PIN M2 } [get_ports { ddr3_d[10] }]; #IO_L4N_T0_34 Sch=ddr3_d[10]
|
||||
#set_property -dict { PACKAGE_PIN L4 } [get_ports { ddr3_d[11] }]; #IO_L5N_T0_34 Sch=ddr3_d[11]
|
||||
#set_property -dict { PACKAGE_PIN L6 } [get_ports { ddr3_d[12] }]; #IO_L6P_T0_34 Sch=ddr3_d[12]
|
||||
#set_property -dict { PACKAGE_PIN K3 } [get_ports { ddr3_d[13] }]; #IO_L2P_T0_34 Sch=ddr3_d[13]
|
||||
#set_property -dict { PACKAGE_PIN M1 } [get_ports { ddr3_d[14] }]; #IO_L1N_T0_34 Sch=ddr3_d[14]
|
||||
#set_property -dict { PACKAGE_PIN K5 } [get_ports { ddr3_d[15] }]; #IO_L5P_T0_34 Sch=ddr3_d[15]
|
||||
#set_property -dict { PACKAGE_PIN T3 } [get_ports { ddr3_d[2] }]; #IO_L11N_T1_SRCC_34 Sch=ddr3_d[2]
|
||||
#set_property -dict { PACKAGE_PIN U4 } [get_ports { ddr3_d[3] }]; #IO_L8P_T1_34 Sch=ddr3_d[3]
|
||||
#set_property -dict { PACKAGE_PIN U3 } [get_ports { ddr3_d[4] }]; #IO_L8N_T1_34 Sch=ddr3_d[4]
|
||||
#set_property -dict { PACKAGE_PIN V5 } [get_ports { ddr3_d[5] }]; #IO_L10P_T1_34 Sch=ddr3_d[5]
|
||||
#set_property -dict { PACKAGE_PIN T5 } [get_ports { ddr3_d[6] }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_d[6]
|
||||
#set_property -dict { PACKAGE_PIN V4 } [get_ports { ddr3_d[7] }]; #IO_L10N_T1_34 Sch=ddr3_d[7]
|
||||
#set_property -dict { PACKAGE_PIN M3 } [get_ports { ddr3_d[8] }]; #IO_L4P_T0_34 Sch=ddr3_d[8]
|
||||
#set_property -dict { PACKAGE_PIN L3 } [get_ports { ddr3_d[9] }]; #IO_L2N_T0_34 Sch=ddr3_d[9]
|
||||
#set_property -dict { PACKAGE_PIN U1 } [get_ports { ddr3_dm[0] }]; #IO_L7P_T1_34 Sch=ddr3_dm[0]
|
||||
#set_property -dict { PACKAGE_PIN L1 } [get_ports { ddr3_dm[1] }]; #IO_L1P_T0_34 Sch=ddr3_dm[1]
|
||||
#set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVDS } [get_ports { ddr3_dqs_n[0] }]; #IO_L9N_T1_DQS_34 Sch=ddr3_dqs_n[0]
|
||||
#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVDS } [get_ports { ddr3_dqs_p[0] }]; #IO_L9P_T1_DQS_34 Sch=ddr3_dqs_p[0]
|
||||
#set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVDS } [get_ports { ddr3_dqs_n[1] }]; #IO_L3N_T0_DQS_34 Sch=ddr3_dqs_n[1]
|
||||
#set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVDS } [get_ports { ddr3_dqs_p[1] }]; #IO_L3P_T0_DQS_34 Sch=ddr3_dqs_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P4 } [get_ports { ddr3_odt }]; #IO_L14P_T2_SRCC_34 Sch=ddr3_odt
|
||||
#set_property -dict { PACKAGE_PIN M4 } [get_ports { ddr3_ras }]; #IO_L16P_T2_34 Sch=ddr3_ras
|
||||
#set_property -dict { PACKAGE_PIN K6 } [get_ports { ddr3_reset }]; #IO_0_34 Sch=ddr3_reset
|
||||
#set_property -dict { PACKAGE_PIN U6 } [get_ports { ddr3_we }]; #IO_L22N_T3_34 Sch=ddr3_we
|
||||
|
||||
## Bitstream Settings
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
375
Bibliotheken/digilent-xdc-master/Zedboard-Master.xdc
Normal file
375
Bibliotheken/digilent-xdc-master/Zedboard-Master.xdc
Normal file
@ -0,0 +1,375 @@
|
||||
# ----------------------------------------------------------------------------
|
||||
# _____
|
||||
# / \
|
||||
# /____ \____
|
||||
# / \===\ \==/
|
||||
# /___\===\___\/ AVNET Design Resource Center
|
||||
# \======/ www.em.avnet.com/drc
|
||||
# \====/
|
||||
# ----------------------------------------------------------------------------
|
||||
#
|
||||
# Created With Avnet UCF Generator V0.4.0
|
||||
# Date: Saturday, June 30, 2012
|
||||
# Time: 12:18:55 AM
|
||||
#
|
||||
# This design is the property of Avnet. Publication of this
|
||||
# design is not authorized without written consent from Avnet.
|
||||
#
|
||||
# Please direct any questions to:
|
||||
# ZedBoard.org Community Forums
|
||||
# http://www.zedboard.org
|
||||
#
|
||||
# Disclaimer:
|
||||
# Avnet, Inc. makes no warranty for the use of this code or design.
|
||||
# This code is provided "As Is". Avnet, Inc assumes no responsibility for
|
||||
# any errors, which may appear in this code, nor does it make a commitment
|
||||
# to update the information contained herein. Avnet, Inc specifically
|
||||
# disclaims any implied warranties of fitness for a particular purpose.
|
||||
# Copyright(c) 2012 Avnet, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 10 August 2012
|
||||
# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V,
|
||||
# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings.
|
||||
# By default, Vadj is expected to be set to 1.8V but if a different
|
||||
# voltage is used for a particular design, then the corresponding IO
|
||||
# standard within this UCF should also be updated to reflect the actual
|
||||
# Vadj jumper selection.
|
||||
#
|
||||
# 09 September 2012
|
||||
# Net names are not allowed to contain hyphen characters '-' since this
|
||||
# is not a legal VHDL87 or Verilog character within an identifier.
|
||||
# HDL net names are adjusted to contain no hyphen characters '-' but
|
||||
# rather use underscore '_' characters. Comment net name with the hyphen
|
||||
# characters will remain in place since these are intended to match the
|
||||
# schematic net names in order to better enable schematic search.
|
||||
#
|
||||
# 17 April 2014
|
||||
# Pin constraint for toggle switch SW7 was corrected to M15 location.
|
||||
#
|
||||
# 16 April 2015
|
||||
# Corrected the way that entire banks are assigned to a particular IO
|
||||
# standard so that it works with more recent versions of Vivado Design
|
||||
# Suite and moved the IO standard constraints to the end of the file
|
||||
# along with some better organization and notes like we do with our SOMs.
|
||||
#
|
||||
# 6 June 2016
|
||||
# Corrected error in signal name for package pin N19 (FMC Expansion Connector)
|
||||
#
|
||||
#
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Audio Codec - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}]; # "AC-ADR0"
|
||||
#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}]; # "AC-ADR1"
|
||||
#set_property PACKAGE_PIN Y8 [get_ports {SDATA_O}]; # "AC-GPIO0"
|
||||
#set_property PACKAGE_PIN AA7 [get_ports {SDATA_I}]; # "AC-GPIO1"
|
||||
#set_property PACKAGE_PIN AA6 [get_ports {BCLK_O}]; # "AC-GPIO2"
|
||||
#set_property PACKAGE_PIN Y6 [get_ports {LRCLK_O}]; # "AC-GPIO3"
|
||||
#set_property PACKAGE_PIN AB2 [get_ports {MCLK_O}]; # "AC-MCLK"
|
||||
#set_property PACKAGE_PIN AB4 [get_ports {iic_rtl_scl_io}]; # "AC-SCK"
|
||||
#set_property PACKAGE_PIN AB5 [get_ports {iic_rtl_sda_io}]; # "AC-SDA"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Clock Source - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y9 [get_ports {GCLK}]; # "GCLK"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JA Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y11 [get_ports {JA1}]; # "JA1"
|
||||
#set_property PACKAGE_PIN AA8 [get_ports {JA10}]; # "JA10"
|
||||
#set_property PACKAGE_PIN AA11 [get_ports {JA2}]; # "JA2"
|
||||
#set_property PACKAGE_PIN Y10 [get_ports {JA3}]; # "JA3"
|
||||
#set_property PACKAGE_PIN AA9 [get_ports {JA4}]; # "JA4"
|
||||
#set_property PACKAGE_PIN AB11 [get_ports {JA7}]; # "JA7"
|
||||
#set_property PACKAGE_PIN AB10 [get_ports {JA8}]; # "JA8"
|
||||
#set_property PACKAGE_PIN AB9 [get_ports {JA9}]; # "JA9"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JB Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W12 [get_ports {JB1}]; # "JB1"
|
||||
#set_property PACKAGE_PIN W11 [get_ports {JB2}]; # "JB2"
|
||||
#set_property PACKAGE_PIN V10 [get_ports {JB3}]; # "JB3"
|
||||
#set_property PACKAGE_PIN W8 [get_ports {JB4}]; # "JB4"
|
||||
#set_property PACKAGE_PIN V12 [get_ports {JB7}]; # "JB7"
|
||||
#set_property PACKAGE_PIN W10 [get_ports {JB8}]; # "JB8"
|
||||
#set_property PACKAGE_PIN V9 [get_ports {JB9}]; # "JB9"
|
||||
#set_property PACKAGE_PIN V8 [get_ports {JB10}]; # "JB10"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JC Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB6 [get_ports {JC1_N}]; # "JC1_N"
|
||||
#set_property PACKAGE_PIN AB7 [get_ports {JC1_P}]; # "JC1_P"
|
||||
#set_property PACKAGE_PIN AA4 [get_ports {JC2_N}]; # "JC2_N"
|
||||
#set_property PACKAGE_PIN Y4 [get_ports {JC2_P}]; # "JC2_P"
|
||||
#set_property PACKAGE_PIN T6 [get_ports {JC3_N}]; # "JC3_N"
|
||||
#set_property PACKAGE_PIN R6 [get_ports {JC3_P}]; # "JC3_P"
|
||||
#set_property PACKAGE_PIN U4 [get_ports {JC4_N}]; # "JC4_N"
|
||||
#set_property PACKAGE_PIN T4 [get_ports {JC4_P}]; # "JC4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# JD Pmod - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W7 [get_ports {JD1_N}]; # "JD1_N"
|
||||
#set_property PACKAGE_PIN V7 [get_ports {JD1_P}]; # "JD1_P"
|
||||
#set_property PACKAGE_PIN V4 [get_ports {JD2_N}]; # "JD2_N"
|
||||
#set_property PACKAGE_PIN V5 [get_ports {JD2_P}]; # "JD2_P"
|
||||
#set_property PACKAGE_PIN W5 [get_ports {JD3_N}]; # "JD3_N"
|
||||
#set_property PACKAGE_PIN W6 [get_ports {JD3_P}]; # "JD3_P"
|
||||
#set_property PACKAGE_PIN U5 [get_ports {JD4_N}]; # "JD4_N"
|
||||
#set_property PACKAGE_PIN U6 [get_ports {JD4_P}]; # "JD4_P"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# OLED Display - Bank 13
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}]; # "OLED-DC"
|
||||
#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}]; # "OLED-RES"
|
||||
#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}]; # "OLED-SCLK"
|
||||
#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}]; # "OLED-SDIN"
|
||||
#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}]; # "OLED-VBAT"
|
||||
#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}]; # "OLED-VDD"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# HDMI Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}]; # "HD-CLK"
|
||||
#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}]; # "HD-D0"
|
||||
#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}]; # "HD-D1"
|
||||
#set_property PACKAGE_PIN W13 [get_ports {HD_D10}]; # "HD-D10"
|
||||
#set_property PACKAGE_PIN W15 [get_ports {HD_D11}]; # "HD-D11"
|
||||
#set_property PACKAGE_PIN V15 [get_ports {HD_D12}]; # "HD-D12"
|
||||
#set_property PACKAGE_PIN U17 [get_ports {HD_D13}]; # "HD-D13"
|
||||
#set_property PACKAGE_PIN V14 [get_ports {HD_D14}]; # "HD-D14"
|
||||
#set_property PACKAGE_PIN V13 [get_ports {HS_D15}]; # "HD-D15"
|
||||
#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}]; # "HD-D2"
|
||||
#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}]; # "HD-D3"
|
||||
#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}]; # "HD-D4"
|
||||
#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}]; # "HD-D5"
|
||||
#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}]; # "HD-D6"
|
||||
#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}]; # "HD-D7"
|
||||
#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}]; # "HD-D8"
|
||||
#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}]; # "HD-D9"
|
||||
#set_property PACKAGE_PIN U16 [get_ports {HD_DE}]; # "HD-DE"
|
||||
#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}]; # "HD-HSYNC"
|
||||
#set_property PACKAGE_PIN W16 [get_ports {HD_INT}]; # "HD-INT"
|
||||
#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}]; # "HD-SCL"
|
||||
#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}]; # "HD-SDA"
|
||||
#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}]; # "HD-SPDIF"
|
||||
#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}]; # "HD-SPDIFO"
|
||||
#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}]; # "HD-VSYNC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User LEDs - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN T22 [get_ports {LD0}]; # "LD0"
|
||||
#set_property PACKAGE_PIN T21 [get_ports {LD1}]; # "LD1"
|
||||
#set_property PACKAGE_PIN U22 [get_ports {LD2}]; # "LD2"
|
||||
#set_property PACKAGE_PIN U21 [get_ports {LD3}]; # "LD3"
|
||||
#set_property PACKAGE_PIN V22 [get_ports {LD4}]; # "LD4"
|
||||
#set_property PACKAGE_PIN W22 [get_ports {LD5}]; # "LD5"
|
||||
#set_property PACKAGE_PIN U19 [get_ports {LD6}]; # "LD6"
|
||||
#set_property PACKAGE_PIN U14 [get_ports {LD7}]; # "LD7"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# VGA Output - Bank 33
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
|
||||
#set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
|
||||
#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
|
||||
#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
|
||||
#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
|
||||
#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
|
||||
#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
|
||||
#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
|
||||
#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
|
||||
#set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
|
||||
#set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
|
||||
#set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
|
||||
#set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
|
||||
#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# User Push Buttons - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN P16 [get_ports {BTNC}]; # "BTNC"
|
||||
#set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
|
||||
#set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
|
||||
#set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
|
||||
#set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# USB OTG Reset - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}]; # "OTG-VBUSOC"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# XADC GIO - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}]; # "XADC-GIO0"
|
||||
#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}]; # "XADC-GIO1"
|
||||
#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}]; # "XADC-GIO2"
|
||||
#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}]; # "XADC-GIO3"
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# Miscellaneous - Bank 34
|
||||
# ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}]; # "PUDC_B"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## USB OTG Reset - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}]; # "OTG-RESETN"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## User DIP Switches - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
|
||||
#set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1"
|
||||
#set_property PACKAGE_PIN H22 [get_ports {SW2}]; # "SW2"
|
||||
#set_property PACKAGE_PIN F21 [get_ports {SW3}]; # "SW3"
|
||||
#set_property PACKAGE_PIN H19 [get_ports {SW4}]; # "SW4"
|
||||
#set_property PACKAGE_PIN H18 [get_ports {SW5}]; # "SW5"
|
||||
#set_property PACKAGE_PIN H17 [get_ports {SW6}]; # "SW6"
|
||||
#set_property PACKAGE_PIN M15 [get_ports {SW7}]; # "SW7"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## XADC AD Channels - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}]; # "XADC-AD0N-R"
|
||||
#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}]; # "XADC-AD0P-R"
|
||||
#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}]; # "XADC-AD8N-R"
|
||||
#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}]; # "XADC-AD8P-R"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 13
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}]; # "FMC-SCL"
|
||||
#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}]; # "FMC-SDA"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 33
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}]; # "FMC-PRSNT"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 34
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}]; # "FMC-CLK0_N"
|
||||
#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}]; # "FMC-CLK0_P"
|
||||
#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}]; # "FMC-LA00_CC_N"
|
||||
#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}]; # "FMC-LA00_CC_P"
|
||||
#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}]; # "FMC-LA01_CC_N"
|
||||
#set_property PACKAGE_PIN N19 [get_ports {FMC_LA01_CC_P}]; # "FMC-LA01_CC_P" - corrected 6/6/16 GE
|
||||
#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}]; # "FMC-LA02_N"
|
||||
#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}]; # "FMC-LA02_P"
|
||||
#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}]; # "FMC-LA03_N"
|
||||
#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}]; # "FMC-LA03_P"
|
||||
#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}]; # "FMC-LA04_N"
|
||||
#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}]; # "FMC-LA04_P"
|
||||
#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}]; # "FMC-LA05_N"
|
||||
#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}]; # "FMC-LA05_P"
|
||||
#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}]; # "FMC-LA06_N"
|
||||
#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}]; # "FMC-LA06_P"
|
||||
#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}]; # "FMC-LA07_N"
|
||||
#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}]; # "FMC-LA07_P"
|
||||
#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}]; # "FMC-LA08_N"
|
||||
#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}]; # "FMC-LA08_P"
|
||||
#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}]; # "FMC-LA09_N"
|
||||
#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}]; # "FMC-LA09_P"
|
||||
#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}]; # "FMC-LA10_N"
|
||||
#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}]; # "FMC-LA10_P"
|
||||
#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}]; # "FMC-LA11_N"
|
||||
#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}]; # "FMC-LA11_P"
|
||||
#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}]; # "FMC-LA12_N"
|
||||
#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}]; # "FMC-LA12_P"
|
||||
#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}]; # "FMC-LA13_N"
|
||||
#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}]; # "FMC-LA13_P"
|
||||
#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}]; # "FMC-LA14_N"
|
||||
#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}]; # "FMC-LA14_P"
|
||||
#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}]; # "FMC-LA15_N"
|
||||
#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}]; # "FMC-LA15_P"
|
||||
#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}]; # "FMC-LA16_N"
|
||||
#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}]; # "FMC-LA16_P"
|
||||
|
||||
## ----------------------------------------------------------------------------
|
||||
## FMC Expansion Connector - Bank 35
|
||||
## ----------------------------------------------------------------------------
|
||||
#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}]; # "FMC-CLK1_N"
|
||||
#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}]; # "FMC-CLK1_P"
|
||||
#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}]; # "FMC-LA17_CC_N"
|
||||
#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}]; # "FMC-LA17_CC_P"
|
||||
#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}]; # "FMC-LA18_CC_N"
|
||||
#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}]; # "FMC-LA18_CC_P"
|
||||
#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}]; # "FMC-LA19_N"
|
||||
#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}]; # "FMC-LA19_P"
|
||||
#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}]; # "FMC-LA20_N"
|
||||
#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}]; # "FMC-LA20_P"
|
||||
#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}]; # "FMC-LA21_N"
|
||||
#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}]; # "FMC-LA21_P"
|
||||
#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}]; # "FMC-LA22_N"
|
||||
#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}]; # "FMC-LA22_P"
|
||||
#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}]; # "FMC-LA23_N"
|
||||
#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}]; # "FMC-LA23_P"
|
||||
#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}]; # "FMC-LA24_N"
|
||||
#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}]; # "FMC-LA24_P"
|
||||
#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}]; # "FMC-LA25_N"
|
||||
#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}]; # "FMC-LA25_P"
|
||||
#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}]; # "FMC-LA26_N"
|
||||
#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}]; # "FMC-LA26_P"
|
||||
#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}]; # "FMC-LA27_N"
|
||||
#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}]; # "FMC-LA27_P"
|
||||
#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}]; # "FMC-LA28_N"
|
||||
#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}]; # "FMC-LA28_P"
|
||||
#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}]; # "FMC-LA29_N"
|
||||
#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}]; # "FMC-LA29_P"
|
||||
#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}]; # "FMC-LA30_N"
|
||||
#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}]; # "FMC-LA30_P"
|
||||
#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}]; # "FMC-LA31_N"
|
||||
#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}]; # "FMC-LA31_P"
|
||||
#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}]; # "FMC-LA32_N"
|
||||
#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}]; # "FMC-LA32_P"
|
||||
#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}]; # "FMC-LA33_N"
|
||||
#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}]; # "FMC-LA33_P"
|
||||
|
||||
|
||||
# ----------------------------------------------------------------------------
|
||||
# IOSTANDARD Constraints
|
||||
#
|
||||
# Note that these IOSTANDARD constraints are applied to all IOs currently
|
||||
# assigned within an I/O bank. If these IOSTANDARD constraints are
|
||||
# evaluated prior to other PACKAGE_PIN constraints being applied, then
|
||||
# the IOSTANDARD specified will likely not be applied properly to those
|
||||
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
|
||||
# within the XDC file in a location that is evaluated AFTER all
|
||||
# PACKAGE_PIN constraints within the target bank have been evaluated.
|
||||
#
|
||||
# Un-comment one or more of the following IOSTANDARD constraints according to
|
||||
# the bank pin assignments that are required within a design.
|
||||
# ----------------------------------------------------------------------------
|
||||
|
||||
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
|
||||
|
||||
# Set the bank voltage for IO Bank 34 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
|
||||
|
||||
# Set the bank voltage for IO Bank 35 to 1.8V by default.
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
|
||||
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
|
||||
|
||||
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
|
||||
146
Bibliotheken/digilent-xdc-master/Zybo-Master.xdc
Normal file
146
Bibliotheken/digilent-xdc-master/Zybo-Master.xdc
Normal file
@ -0,0 +1,146 @@
|
||||
## This file is a general .xdc for the ZYBO Rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used signals according to the project
|
||||
|
||||
|
||||
##Clock signal
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=SW1
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=SW2
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L20N_T3_34 Sch=BTN0
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=BTN1
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L18P_T2_34 Sch=BTN2
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=BTN3
|
||||
|
||||
|
||||
##LEDs
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=LED0
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=LED1
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35=Sch=LED2
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
|
||||
|
||||
|
||||
##I2S Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports ac_bclk]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports ac_mclk]; #IO_25_34 Sch=AC_MCLK
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports ac_muten]; #IO_L23N_T3_34 Sch=AC_MUTEN
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports ac_pbdat]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports ac_pblrc]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports ac_recdat]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports ac_reclrc]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
|
||||
|
||||
|
||||
##Audio Codec/external EEPROM IIC bus
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports ac_scl]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports ac_sda]; #IO_L23P_T3_34 Sch=AC_SDA
|
||||
|
||||
|
||||
##Additional Ethernet signals
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports eth_int_b]; #IO_L6P_T0_35 Sch=ETH_INT_B
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports eth_rst_b]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
|
||||
|
||||
|
||||
##HDMI Signals
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_n]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports hdmi_clk_p]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports hdmi_cec]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports hdmi_hpd]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports hdmi_out_en]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports hdmi_scl]; #IO_L16P_T2_35 Sch=HDMI_SCL
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports hdmi_sda]; #IO_L16N_T2_35 Sch=HDMI_SDA
|
||||
|
||||
|
||||
##Pmod Header JA (XADC)
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
|
||||
|
||||
|
||||
##Pmod Header JE
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
|
||||
|
||||
|
||||
##USB-OTG overcurrent detect pin
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports otg_oc]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vga_hs]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vga_vs]; #IO_0_34 Sch=VGA_VS
|
||||
198
Bibliotheken/digilent-xdc-master/Zybo-Z7-Master.xdc
Normal file
198
Bibliotheken/digilent-xdc-master/Zybo-Z7-Master.xdc
Normal file
@ -0,0 +1,198 @@
|
||||
## This file is a general .xdc for the Zybo Z7 Rev. B
|
||||
## It is compatible with the Zybo Z7-20 and Zybo Z7-10
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
##Clock signal
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
|
||||
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
|
||||
#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
|
||||
#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
|
||||
#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
|
||||
|
||||
|
||||
##LEDs
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
|
||||
#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
|
||||
|
||||
|
||||
##RGB LED 5 (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
|
||||
#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
|
||||
#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
|
||||
|
||||
##RGB LED 6
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
|
||||
#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
|
||||
|
||||
|
||||
##Audio Codec
|
||||
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
|
||||
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
|
||||
#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
|
||||
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
|
||||
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
|
||||
|
||||
|
||||
##Additional Ethernet signals
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
|
||||
|
||||
|
||||
##USB-OTG over-current detect pin
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
|
||||
|
||||
|
||||
##Fan (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
|
||||
|
||||
|
||||
##HDMI RX
|
||||
#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
|
||||
#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
|
||||
#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
|
||||
#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
|
||||
|
||||
##HDMI RX CEC (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
|
||||
|
||||
|
||||
##HDMI TX
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
|
||||
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
|
||||
#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
|
||||
#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
|
||||
#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
|
||||
#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
|
||||
#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
|
||||
|
||||
##HDMI TX CEC
|
||||
#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
|
||||
|
||||
|
||||
##Pmod Header JA (XADC)
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
|
||||
#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
|
||||
#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
|
||||
#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
|
||||
|
||||
|
||||
##Pmod Header JB (Zybo Z7-20 only)
|
||||
#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
|
||||
#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
|
||||
#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
|
||||
#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
|
||||
#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
|
||||
#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
|
||||
#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
|
||||
#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
|
||||
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
|
||||
#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
|
||||
#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
|
||||
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
|
||||
#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
|
||||
#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
|
||||
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
|
||||
#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
|
||||
|
||||
|
||||
##Pmod Header JE
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
|
||||
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
|
||||
|
||||
|
||||
##Pcam MIPI CSI-2 Connector
|
||||
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
|
||||
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
|
||||
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
|
||||
|
||||
|
||||
##Unloaded Crypto Chip SWI (for future use)
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
|
||||
|
||||
|
||||
##Unconnected Pins (Zybo Z7-20 only)
|
||||
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
|
||||
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
|
||||
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
|
||||
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
|
||||
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
|
||||
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
|
||||
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
|
||||
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
|
||||
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
|
||||
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
|
||||
|
||||
|
||||
BIN
Bibliotheken/vivado-boards-master.zip
Normal file
BIN
Bibliotheken/vivado-boards-master.zip
Normal file
Binary file not shown.
@ -0,0 +1,21 @@
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
@ -0,0 +1,13 @@
|
||||
# Vivado Board Files for Digilent FPGA Boards
|
||||
|
||||
This repository contains the files used by Vivado IP Integrator to support Digilent system boards. They include board interfaces, preset configurations for the IP that can connect to those interfaces, and the constraints required to connect the pins of those interfaces to physical FPGA pins. Memory Interface Generator (MIG) project files are also included for non-Zynq boards which can be used to configure the Xilinx MIG IP for use with Microblaze systems.
|
||||
|
||||
The `old` folder is for use with Vivado versions 2014.4 and below. The `new` folder covers Vivado 2015.x and above.
|
||||
|
||||
Installation instructions for the `new` files can be found in [Section 3](https://reference.digilentinc.com/vivado/installing-vivado/start#installing_digilent_board_files) of the *Installing Vivado, Xilinx SDK, and Digilent Board Files* guide on the Digilent Wiki.
|
||||
|
||||
Installation instructions for the `old` files can be found in the [Installing Vivado Board Files for Digilent Boards (Legacy)](https://reference.digilentinc.com/vivado:boardfiles) guide on the Digilent Wiki.
|
||||
|
||||
## Notes
|
||||
|
||||
* Boards with ChipKit/Arduino headers have the pin locations of CK_IO10 and CK_SS swapped in order to support connection to the [Multi-Touch Display Shield](https://reference.digilentinc.com/reference/add-ons/mtdshield/start). This is not an ideal solution, and may be revised in future. See [Issue 5](https://github.com/Digilent/vivado-boards/issues/5) for more information.
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,156 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a100tcsg324-1L">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
|
||||
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
|
||||
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
|
||||
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
|
||||
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
|
||||
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
|
||||
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
|
||||
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
|
||||
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
|
||||
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
|
||||
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
|
||||
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
|
||||
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
|
||||
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
|
||||
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
|
||||
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
|
||||
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
|
||||
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
|
||||
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
|
||||
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
|
||||
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
|
||||
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
|
||||
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
|
||||
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
|
||||
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
|
||||
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
|
||||
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
|
||||
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
|
||||
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
|
||||
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
|
||||
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
|
||||
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
|
||||
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
|
||||
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
|
||||
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
|
||||
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
|
||||
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
|
||||
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
|
||||
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
|
||||
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
|
||||
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
|
||||
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
|
||||
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
|
||||
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
|
||||
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
|
||||
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
|
||||
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
|
||||
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
|
||||
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
|
||||
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,418 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_12bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,156 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a100tcsg324-1L">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
|
||||
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
|
||||
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
|
||||
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
|
||||
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
|
||||
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
|
||||
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
|
||||
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
|
||||
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
|
||||
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
|
||||
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
|
||||
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
|
||||
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
|
||||
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
|
||||
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
|
||||
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
|
||||
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
|
||||
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
|
||||
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
|
||||
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
|
||||
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
|
||||
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
|
||||
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
|
||||
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
|
||||
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
|
||||
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
|
||||
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
|
||||
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
|
||||
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
|
||||
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
|
||||
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
|
||||
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
|
||||
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
|
||||
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
|
||||
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
|
||||
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
|
||||
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
|
||||
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
|
||||
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
|
||||
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
|
||||
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
|
||||
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
|
||||
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
|
||||
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
|
||||
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
|
||||
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
|
||||
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
|
||||
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
|
||||
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
|
||||
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,418 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_12bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,156 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a35tcsg324-1L">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
|
||||
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
|
||||
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
|
||||
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
|
||||
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
|
||||
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
|
||||
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
|
||||
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
|
||||
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
|
||||
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
|
||||
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
|
||||
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
|
||||
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
|
||||
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
|
||||
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
|
||||
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
|
||||
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
|
||||
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
|
||||
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
|
||||
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
|
||||
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
|
||||
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
|
||||
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
|
||||
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
|
||||
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
|
||||
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
|
||||
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
|
||||
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
|
||||
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
|
||||
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
|
||||
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
|
||||
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
|
||||
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
|
||||
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
|
||||
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
|
||||
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
|
||||
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
|
||||
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
|
||||
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
|
||||
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
|
||||
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
|
||||
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
|
||||
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
|
||||
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
|
||||
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
|
||||
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
|
||||
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
|
||||
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
|
||||
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
|
||||
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,418 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_12bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,156 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a35tcsg324-1L">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
|
||||
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
|
||||
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
|
||||
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
|
||||
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
|
||||
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
|
||||
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
|
||||
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
|
||||
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
|
||||
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
|
||||
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
|
||||
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
|
||||
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
|
||||
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
|
||||
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
|
||||
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
|
||||
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
|
||||
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
|
||||
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
|
||||
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
|
||||
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
|
||||
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
|
||||
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
|
||||
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
|
||||
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
|
||||
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
|
||||
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
|
||||
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
|
||||
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
|
||||
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
|
||||
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
|
||||
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
|
||||
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
|
||||
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
|
||||
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
|
||||
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
|
||||
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
|
||||
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
|
||||
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
|
||||
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
|
||||
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
|
||||
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
|
||||
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
|
||||
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
|
||||
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
|
||||
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
|
||||
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
|
||||
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
|
||||
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
|
||||
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,418 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_12bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,112 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7s25csga324-1">
|
||||
<pins>
|
||||
<pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
|
||||
<pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
|
||||
<pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
|
||||
<pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
|
||||
<pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
|
||||
<pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
|
||||
<pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
|
||||
<pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
|
||||
<pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
|
||||
<pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
|
||||
<pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
|
||||
<pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
|
||||
<pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
|
||||
<pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
|
||||
<pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
|
||||
<pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
|
||||
<pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
|
||||
<pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
|
||||
<pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
|
||||
<pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
|
||||
<pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="52" name ="JA1" iostandard="LVCMOS33" loc="L17"/>
|
||||
<pin index="53" name ="JA2" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="54" name ="JA3" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="55" name ="JA4" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="56" name ="JA7" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="57" name ="JA8" iostandard="LVCMOS33" loc="M17"/>
|
||||
<pin index="58" name ="JA9" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
|
||||
<pin index="60" name ="JB1" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="61" name ="JB2" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="62" name ="JB3" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="63" name ="JB4" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="64" name ="JB7" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="65" name ="JB8" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="66" name ="JB9" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
|
||||
<pin index="68" name ="JC1" iostandard="LVCMOS33" loc="U15"/>
|
||||
<pin index="69" name ="JC2" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="70" name ="JC3" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="71" name ="JC4" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="72" name ="JC7" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="73" name ="JC8" iostandard="LVCMOS33" loc="P13"/>
|
||||
<pin index="74" name ="JC9" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="76" name ="JD1" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="77" name ="JD2" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="78" name ="JD3" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="79" name ="JD4" iostandard="LVCMOS33" loc="T12"/>
|
||||
<pin index="80" name ="JD7" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="81" name ="JD8" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="82" name ="JD9" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,425 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp9_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_a0_a5_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_a10_a11_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="ddr_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,112 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7s50csga324-1">
|
||||
<pins>
|
||||
<pin index="0" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="H18"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="G18"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_3" iostandard="SSTL135" loc="M5"/>
|
||||
<pin index="4" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="G15"/>
|
||||
<pin index="5" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="6" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="J16"/>
|
||||
<pin index="7" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="H13"/>
|
||||
<pin index="8" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="9" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="F13"/>
|
||||
<pin index="10" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="E13"/>
|
||||
<pin index="11" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="12" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="13" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="16" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="F18"/>
|
||||
<pin index="17" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="E14"/>
|
||||
<pin index="18" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="19" name ="usb_uart_txd" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="20" name ="qspi_csn_i" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="21" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="22" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="23" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="24" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M15"/>
|
||||
<pin index="25" name ="reset" iostandard="LVCMOS33" loc="C18"/>
|
||||
<pin index="26" name ="ddr_clk" iostandard="SSTL135" loc="R2"/>
|
||||
<pin index="27" name ="sys_clk" iostandard="LVCMOS33" loc="F14"/>
|
||||
<pin index="28" name ="shield_dp0_dp9_tri_i_0" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="29" name ="shield_dp0_dp9_tri_i_1" iostandard="LVCMOS33" loc="N13"/>
|
||||
<pin index="30" name ="shield_dp0_dp9_tri_i_2" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="31" name ="shield_dp0_dp9_tri_i_3" iostandard="LVCMOS33" loc="R14"/>
|
||||
<pin index="32" name ="shield_dp0_dp9_tri_i_4" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="33" name ="shield_dp0_dp9_tri_i_5" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="34" name ="shield_dp0_dp9_tri_i_6" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="35" name ="shield_dp0_dp9_tri_i_7" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="36" name ="shield_dp0_dp9_tri_i_8" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="37" name ="shield_dp0_dp9_tri_i_9" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="38" name ="shield_a0_a5_tri_i_0" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="39" name ="shield_a0_a5_tri_i_1" iostandard="LVCMOS33" loc="B16"/>
|
||||
<pin index="40" name ="shield_a0_a5_tri_i_2" iostandard="LVCMOS33" loc="A16"/>
|
||||
<pin index="41" name ="shield_a0_a5_tri_i_3" iostandard="LVCMOS33" loc="C13"/>
|
||||
<pin index="42" name ="shield_a0_a5_tri_i_4" iostandard="LVCMOS33" loc="C14"/>
|
||||
<pin index="43" name ="shield_a0_a5_tri_i_5" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="44" name ="shield_a10_a11_tri_i_0" iostandard="LVCMOS33" loc="D14"/>
|
||||
<pin index="45" name ="shield_a10_a11_tri_i_1" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="46" name ="spi_miso_i" iostandard="LVCMOS33" loc="K14"/>
|
||||
<pin index="47" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="48" name ="spi_sclk_i" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="49" name ="spi_ss_i" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="50" name ="i2c_scl_i" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="51" name ="i2c_sda_i" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="52" name ="JA1" iostandard="LVCMOS33" loc="L17"/>
|
||||
<pin index="53" name ="JA2" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="54" name ="JA3" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="55" name ="JA4" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="56" name ="JA7" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="57" name ="JA8" iostandard="LVCMOS33" loc="M17"/>
|
||||
<pin index="58" name ="JA9" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="59" name ="JA10" iostandard="LVCMOS33" loc="N18"/>
|
||||
<pin index="60" name ="JB1" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="61" name ="JB2" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="62" name ="JB3" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="63" name ="JB4" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="64" name ="JB7" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="65" name ="JB8" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="66" name ="JB9" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="67" name ="JB10" iostandard="LVCMOS33" loc="P16"/>
|
||||
<pin index="68" name ="JC1" iostandard="LVCMOS33" loc="U15"/>
|
||||
<pin index="69" name ="JC2" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="70" name ="JC3" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="71" name ="JC4" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="72" name ="JC7" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="73" name ="JC8" iostandard="LVCMOS33" loc="P13"/>
|
||||
<pin index="74" name ="JC9" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="75" name ="JC10" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="76" name ="JD1" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="77" name ="JD2" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="78" name ="JD3" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="79" name ="JD4" iostandard="LVCMOS33" loc="T12"/>
|
||||
<pin index="80" name ="JD7" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="81" name ="JD8" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="82" name ="JD9" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="83" name ="JD10" iostandard="LVCMOS33" loc="U11"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,425 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp9_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="10"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="10"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_a0_a5_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_a10_a11_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="ddr_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
</ip_presets>
|
||||
@ -0,0 +1,588 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-10" display_name="Arty Z7-10" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">A.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Arty Z7-10 </description>
|
||||
<components>
|
||||
<component name="part0" display_name="Arty Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
|
||||
</interface>
|
||||
<interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sys_clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="125000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
|
||||
<description>Shield I2C</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
|
||||
<description>2 RGB LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_sclk_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_sclk_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_sclk_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Buttons 3 to 0</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>LEDs 3 to 0</description>
|
||||
</component>
|
||||
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">
|
||||
<description>DIP Switches 1 to 0</description>
|
||||
</component>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
|
||||
</component>
|
||||
|
||||
<component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">
|
||||
<description>Shield i2c</description>
|
||||
</component>
|
||||
<component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
|
||||
</component>
|
||||
<component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP0 through DP13</description>
|
||||
</component>
|
||||
<component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
|
||||
<description>Shield SPI</description>
|
||||
</component>
|
||||
|
||||
</components>
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
<connections>
|
||||
<connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
|
||||
<connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
|
||||
<connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">
|
||||
<connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jb" component1="part0" component2="jb">
|
||||
<connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_i2c" component1="part0" component2="i2c">
|
||||
<connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
|
||||
<connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
|
||||
<connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>
|
||||
</connection>
|
||||
<connection name="part0_spi" component1="part0" component2="spi">
|
||||
<connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,81 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7z010clg400-1">
|
||||
<pins>
|
||||
<pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
|
||||
<pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
|
||||
<pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
|
||||
<pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
|
||||
<pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
|
||||
<pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
|
||||
<pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
|
||||
<pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
|
||||
<pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
|
||||
<pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
|
||||
<pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
|
||||
<pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
|
||||
<pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
|
||||
<pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
|
||||
<pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
|
||||
<pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
|
||||
<pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
|
||||
<pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
|
||||
<pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
|
||||
<pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
|
||||
<pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
|
||||
<pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
|
||||
<pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
|
||||
<pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
|
||||
<pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,661 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="arty-z7-20" display_name="Arty Z7-20" url="https://digilent.com/reference/programmable-logic/arty-z7/start" preset_file="preset.xml" >
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">A.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Arty Z7-20 </description>
|
||||
<components>
|
||||
<component name="part0" display_name="Arty Z7-20" type="fpga" part_name="xc7z020clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/arty-z7/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="btns_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_4bits" preset_proc="push_buttons_4bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btns_4bits_tri_i" dir="in" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btns_4bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btns_4bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="btns_4bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="btns_4bits_tri_i_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="leds_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="leds_4bits" preset_proc="led_4bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="leds_4bits_tri_o" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="leds_4bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="leds_4bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="leds_4bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="leds_4bits_tri_o_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
|
||||
</interface>
|
||||
<interface mode="master" name="sws_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="sws_2bits" preset_proc="dip_switches_2bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="sws_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sws_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="sws_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sys_clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="125000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="i2c">
|
||||
<description>Shield I2C</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="SDA_I" physical_port="i2c_sda_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_O" physical_port="i2c_sda_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_T" physical_port="i2c_sda_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_I" physical_port="i2c_scl_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_O" physical_port="i2c_scl_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_T" physical_port="i2c_scl_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_6bits_preset">
|
||||
<description>2 RGB LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="5" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="rgb_led_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="rgb_led_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="rgb_led_tri_o_5"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="spi" preset_proc="spi_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="spi_mosi_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="spi_mosi_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="spi_mosi_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="spi_miso_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="spi_miso_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="spi_miso_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_I" physical_port="spi_sclk_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_sclk_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_O" physical_port="spi_sclk_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_sclk_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_T" physical_port="spi_sclk_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_sclk_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<component name="btns_4bits" display_name="4 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Buttons 3 to 0</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="leds_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>LEDs 3 to 0</description>
|
||||
</component>
|
||||
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="sws_2bits" display_name="2 Switches" type="chip" sub_type="switch" major_group="GPIO">
|
||||
<description>DIP Switches 1 to 0</description>
|
||||
</component>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
|
||||
</component>
|
||||
|
||||
<component name="i2c" display_name="I2C on J2" type="chip" sub_type="mux" major_group="I2C">
|
||||
<description>Shield i2c</description>
|
||||
</component>
|
||||
<component name="rgb_led" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
|
||||
</component>
|
||||
<component name="shield_dp0_dp13" display_name="Shield Pins 0 through 13" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP0 through DP13</description>
|
||||
</component>
|
||||
<component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP26 through DP41</description>
|
||||
</component>
|
||||
<component name="spi" display_name="SPI connector J6" type="chip" sub_type="mux" major_group="SPI">
|
||||
<description>Shield SPI</description>
|
||||
</component>
|
||||
|
||||
</components>
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
<connections>
|
||||
<connection name="part0_btns_4bits" component1="part0" component2="btns_4bits">
|
||||
<connection_map name="part0_btns_4bits_1" c1_st_index="0" c1_end_index="3" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_leds_4bits" component1="part0" component2="leds_4bits">
|
||||
<connection_map name="part0_leds_4bits_1" c1_st_index="4" c1_end_index="7" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_sws_2bits" component1="part0" component2="sws_2bits">
|
||||
<connection_map name="part0_sws_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="10" c1_end_index="10" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="11" c1_end_index="18" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jb" component1="part0" component2="jb">
|
||||
<connection_map name="part0_jb_1" c1_st_index="19" c1_end_index="26" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_i2c" component1="part0" component2="i2c">
|
||||
<connection_map name="part0_i2c_1" c1_st_index="27" c1_end_index="28" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
|
||||
<connection_map name="part0_rgb_led_1" c1_st_index="29" c1_end_index="34" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
|
||||
<connection_map name="part0_shield_dp0_dp13_1" c1_st_index="35" c1_end_index="48" c2_st_index="0" c2_end_index="13"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
|
||||
<connection_map name="part0_shield_dp26_dp41_1" c1_st_index="49" c1_end_index="64" c2_st_index="0" c2_end_index="15"/>
|
||||
</connection>
|
||||
<connection name="part0_spi" component1="part0" component2="spi">
|
||||
<connection_map name="part0_spi_1" c1_st_index="65" c1_end_index="68" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,97 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7z020clg400-1">
|
||||
<pins>
|
||||
<pin index="0" name ="btns_4bits_tri_i_0" iostandard="LVCMOS33" loc="D19"/>
|
||||
<pin index="1" name ="btns_4bits_tri_i_1" iostandard="LVCMOS33" loc="D20"/>
|
||||
<pin index="2" name ="btns_4bits_tri_i_2" iostandard="LVCMOS33" loc="L20"/>
|
||||
<pin index="3" name ="btns_4bits_tri_i_3" iostandard="LVCMOS33" loc="L19"/>
|
||||
<pin index="4" name ="leds_4bits_tri_o_0" iostandard="LVCMOS33" loc="R14"/>
|
||||
<pin index="5" name ="leds_4bits_tri_o_1" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="6" name ="leds_4bits_tri_o_2" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="7" name ="leds_4bits_tri_o_3" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="8" name ="sws_2bits_tri_i_0" iostandard="LVCMOS33" loc="M20"/>
|
||||
<pin index="9" name ="sws_2bits_tri_i_1" iostandard="LVCMOS33" loc="M19"/>
|
||||
<pin index="10" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="11" name ="JA1" iostandard="LVCMOS33" loc="Y18"/>
|
||||
<pin index="12" name ="JA2" iostandard="LVCMOS33" loc="Y19"/>
|
||||
<pin index="13" name ="JA3" iostandard="LVCMOS33" loc="Y16"/>
|
||||
<pin index="14" name ="JA4" iostandard="LVCMOS33" loc="Y17"/>
|
||||
<pin index="15" name ="JA7" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="16" name ="JA8" iostandard="LVCMOS33" loc="U19"/>
|
||||
<pin index="17" name ="JA9" iostandard="LVCMOS33" loc="W18"/>
|
||||
<pin index="18" name ="JA10" iostandard="LVCMOS33" loc="W19"/>
|
||||
<pin index="19" name ="JB1" iostandard="LVCMOS33" loc="W14"/>
|
||||
<pin index="20" name ="JB2" iostandard="LVCMOS33" loc="Y14"/>
|
||||
<pin index="21" name ="JB3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="22" name ="JB4" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="23" name ="JB7" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="24" name ="JB8" iostandard="LVCMOS33" loc="W16"/>
|
||||
<pin index="25" name ="JB9" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="26" name ="JB10" iostandard="LVCMOS33" loc="W13"/>
|
||||
<pin index="27" name ="i2c_scl_i" iostandard="LVCMOS33" loc="P16"/>
|
||||
<pin index="28" name ="i2c_sda_i" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="29" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="L15"/>
|
||||
<pin index="30" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="31" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="32" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="33" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="34" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="M15"/>
|
||||
<pin index="35" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="36" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="37" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="38" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="39" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="40" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="41" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="42" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="43" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="44" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="V18"/>
|
||||
<pin index="45" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="46" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="47" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="48" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="49" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U5"/>
|
||||
<pin index="50" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V5"/>
|
||||
<pin index="51" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="V6"/>
|
||||
<pin index="52" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="U7"/>
|
||||
<pin index="53" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="V7"/>
|
||||
<pin index="54" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U8"/>
|
||||
<pin index="55" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="V8"/>
|
||||
<pin index="56" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="57" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="W10"/>
|
||||
<pin index="58" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="W6"/>
|
||||
<pin index="59" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="Y6"/>
|
||||
<pin index="60" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="Y7"/>
|
||||
<pin index="61" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="W8"/>
|
||||
<pin index="62" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="Y8"/>
|
||||
<pin index="63" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="W9"/>
|
||||
<pin index="64" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="Y9"/>
|
||||
<pin index="65" name ="spi_miso_i" iostandard="LVCMOS33" loc="W15"/>
|
||||
<pin index="66" name ="spi_mosi_i" iostandard="LVCMOS33" loc="T12"/>
|
||||
<pin index="67" name ="spi_sclk_i" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="68" name ="spi_ss_i" iostandard="LVCMOS33" loc="T16"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,156 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a35tcsg324-1L">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="E3"/>
|
||||
<pin index="1" name ="dip_switches_4bits_tri_i_0" iostandard="LVCMOS33" loc="A8"/>
|
||||
<pin index="2" name ="dip_switches_4bits_tri_i_1" iostandard="LVCMOS33" loc="C11"/>
|
||||
<pin index="3" name ="dip_switches_4bits_tri_i_2" iostandard="LVCMOS33" loc="C10"/>
|
||||
<pin index="4" name ="dip_switches_4bits_tri_i_3" iostandard="LVCMOS33" loc="A10"/>
|
||||
<pin index="5" name ="eth_col" iostandard="LVCMOS33" loc="D17"/>
|
||||
<pin index="6" name ="eth_crs" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="7" name ="eth_mdc" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="8" name ="eth_mdio_i" iostandard="LVCMOS33" loc="K13"/>
|
||||
<pin index="9" name ="eth_rstn" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="10" name ="eth_rxd_0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="11" name ="eth_rxd_1" iostandard="LVCMOS33" loc="E17"/>
|
||||
<pin index="12" name ="eth_rxd_2" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="13" name ="eth_rxd_3" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="14" name ="eth_rx_clk" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="15" name ="eth_rx_dv" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="16" name ="eth_rx_er" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="17" name ="eth_txd_0" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="18" name ="eth_txd_1" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="19" name ="eth_txd_2" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="20" name ="eth_txd_3" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="21" name ="eth_tx_clk" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="22" name ="eth_tx_en" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="23" name ="i2c_pullup_0" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="24" name ="i2c_pullup_1" iostandard="LVCMOS33" loc="A13"/>
|
||||
<pin index="25" name ="i2c_scl_i" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="26" name ="i2c_sda_i" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="27" name ="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="H5"/>
|
||||
<pin index="28" name ="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="J5"/>
|
||||
<pin index="29" name ="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
|
||||
<pin index="30" name ="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="31" name ="push_buttons_4bits_tri_i_0" iostandard="LVCMOS33" loc="D9"/>
|
||||
<pin index="32" name ="push_buttons_4bits_tri_i_1" iostandard="LVCMOS33" loc="C9"/>
|
||||
<pin index="33" name ="push_buttons_4bits_tri_i_2" iostandard="LVCMOS33" loc="B9"/>
|
||||
<pin index="34" name ="push_buttons_4bits_tri_i_3" iostandard="LVCMOS33" loc="B8"/>
|
||||
<pin index="35" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="36" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="37" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="38" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="39" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="40" name ="qspi_sclk_i" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="41" name ="reset" iostandard="LVCMOS33" loc="C2"/>
|
||||
<pin index="42" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="E1"/>
|
||||
<pin index="43" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="F6"/>
|
||||
<pin index="44" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="G6"/>
|
||||
<pin index="45" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="G4"/>
|
||||
<pin index="46" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="J4"/>
|
||||
<pin index="47" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="48" name ="rgb_led_tri_o_6" iostandard="LVCMOS33" loc="H4"/>
|
||||
<pin index="49" name ="rgb_led_tri_o_7" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="50" name ="rgb_led_tri_o_8" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="51" name ="rgb_led_tri_o_9" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="52" name ="rgb_led_tri_o_10" iostandard="LVCMOS33" loc="H6"/>
|
||||
<pin index="53" name ="rgb_led_tri_o_11" iostandard="LVCMOS33" loc="K1"/>
|
||||
<pin index="54" name ="shield_dp0_dp19_tri_i_0" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="55" name ="shield_dp0_dp19_tri_i_1" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="56" name ="shield_dp0_dp19_tri_i_2" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="57" name ="shield_dp0_dp19_tri_i_3" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="58" name ="shield_dp0_dp19_tri_i_4" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="59" name ="shield_dp0_dp19_tri_i_5" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="60" name ="shield_dp0_dp19_tri_i_6" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="61" name ="shield_dp0_dp19_tri_i_7" iostandard="LVCMOS33" loc="T16"/>
|
||||
<pin index="62" name ="shield_dp0_dp19_tri_i_8" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="63" name ="shield_dp0_dp19_tri_i_9" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>
|
||||
<pin index="65" name ="shield_dp0_dp19_tri_i_11" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="66" name ="shield_dp0_dp19_tri_i_12" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="67" name ="shield_dp0_dp19_tri_i_13" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="68" name ="shield_dp0_dp19_tri_i_14" iostandard="LVCMOS33" loc="F5"/>
|
||||
<pin index="69" name ="shield_dp0_dp19_tri_i_15" iostandard="LVCMOS33" loc="D8"/>
|
||||
<pin index="70" name ="shield_dp0_dp19_tri_i_16" iostandard="LVCMOS33" loc="C7"/>
|
||||
<pin index="71" name ="shield_dp0_dp19_tri_i_17" iostandard="LVCMOS33" loc="E7"/>
|
||||
<pin index="72" name ="shield_dp0_dp19_tri_i_18" iostandard="LVCMOS33" loc="D7"/>
|
||||
<pin index="73" name ="shield_dp0_dp19_tri_i_19" iostandard="LVCMOS33" loc="D5"/>
|
||||
<pin index="74" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="U11"/>
|
||||
<pin index="75" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="76" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="77" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="R10"/>
|
||||
<pin index="78" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="79" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="80" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="81" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="82" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="83" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="84" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="85" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="86" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="87" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="88" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="89" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="90" name ="spi_miso_i" iostandard="LVCMOS33" loc="G1"/>
|
||||
<pin index="91" name ="spi_mosi_i" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="92" name ="spi_sclk_i" iostandard="LVCMOS33" loc="F1"/>
|
||||
<pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="94" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="A9"/>
|
||||
<pin index="95" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D10"/>
|
||||
<pin index="96" name ="JA1" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="97" name ="JA2" iostandard="LVCMOS33" loc="B11"/>
|
||||
<pin index="98" name ="JA3" iostandard="LVCMOS33" loc="A11"/>
|
||||
<pin index="99" name ="JA4" iostandard="LVCMOS33" loc="D12"/>
|
||||
<pin index="100" name ="JA7" iostandard="LVCMOS33" loc="D13"/>
|
||||
<pin index="101" name ="JA8" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="102" name ="JA9" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="103" name ="JA10" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="104" name ="JB1" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="105" name ="JB2" iostandard="LVCMOS33" loc="E16"/>
|
||||
<pin index="106" name ="JB3" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="107" name ="JB4" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="108" name ="JB7" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="109" name ="JB8" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="110" name ="JB9" iostandard="LVCMOS33" loc="K15"/>
|
||||
<pin index="111" name ="JB10" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="112" name ="JC1" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="113" name ="JC2" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="114" name ="JC3" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="115" name ="JC4" iostandard="LVCMOS33" loc="V11"/>
|
||||
<pin index="116" name ="JC7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="117" name ="JC8" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="118" name ="JC9" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="119" name ="JC10" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="120" name ="JD1" iostandard="LVCMOS33" loc="D4"/>
|
||||
<pin index="121" name ="JD2" iostandard="LVCMOS33" loc="D3"/>
|
||||
<pin index="122" name ="JD3" iostandard="LVCMOS33" loc="F4"/>
|
||||
<pin index="123" name ="JD4" iostandard="LVCMOS33" loc="F3"/>
|
||||
<pin index="124" name ="JD7" iostandard="LVCMOS33" loc="E2"/>
|
||||
<pin index="125" name ="JD8" iostandard="LVCMOS33" loc="D2"/>
|
||||
<pin index="126" name ="JD9" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="127" name ="JD10" iostandard="LVCMOS33" loc="G2"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,414 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_12bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="12"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp19_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="20"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_uartlite" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_BAUDRATE" value="115200"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
@ -0,0 +1,827 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="basys3" display_name="Basys3" url="https://digilent.com/reference/programmable-logic/basys-3/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">C.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.2</file_version>
|
||||
<description>Basys3</description>
|
||||
<components>
|
||||
<component name="part0" display_name="Basys3" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/basys-3/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="dip_switches_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="dip_switches_16bits" preset_proc="dip_switches_16bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="dip_switches_16bits_tri_i" dir="in" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="dip_switches_16bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="dip_switches_16bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="dip_switches_16bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="dip_switches_16bits_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="dip_switches_16bits_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="dip_switches_16bits_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="dip_switches_16bits_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="dip_switches_16bits_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="dip_switches_16bits_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="dip_switches_16bits_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="dip_switches_16bits_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="dip_switches_16bits_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="dip_switches_16bits_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="dip_switches_16bits_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="dip_switches_16bits_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="dip_switches_16bits_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="led_16bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_16bits" preset_proc="led_16bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_16bits_tri_o" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_16bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="led_16bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="led_16bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="led_16bits_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="led_16bits_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="led_16bits_tri_o_5"/>
|
||||
<pin_map port_index="6" component_pin="led_16bits_tri_o_6"/>
|
||||
<pin_map port_index="7" component_pin="led_16bits_tri_o_7"/>
|
||||
<pin_map port_index="8" component_pin="led_16bits_tri_o_8"/>
|
||||
<pin_map port_index="9" component_pin="led_16bits_tri_o_9"/>
|
||||
<pin_map port_index="10" component_pin="led_16bits_tri_o_10"/>
|
||||
<pin_map port_index="11" component_pin="led_16bits_tri_o_11"/>
|
||||
<pin_map port_index="12" component_pin="led_16bits_tri_o_12"/>
|
||||
<pin_map port_index="13" component_pin="led_16bits_tri_o_13"/>
|
||||
<pin_map port_index="14" component_pin="led_16bits_tri_o_14"/>
|
||||
<pin_map port_index="15" component_pin="led_16bits_tri_o_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_4bits" preset_proc="push_buttons_4bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_4bits_tri_i" dir="in" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_5bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="push_buttons_5bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="push_buttons_5bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="push_buttons_5bits_tri_i_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
|
||||
<description>Quad SPI Flash</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="qspi_db0_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="qspi_db0_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="qspi_db0_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="qspi_db1_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="qspi_db1_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="qspi_db1_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_I" physical_port="qspi_db2_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_O" physical_port="qspi_db2_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_T" physical_port="qspi_db2_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_I" physical_port="qspi_db3_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_O" physical_port="qspi_db3_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_T" physical_port="qspi_db3_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="qspi_csn_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="qspi_csn_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="qspi_csn_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
|
||||
<port_maps>
|
||||
<port_map logical_port="RST" physical_port="reset" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="reset"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="rst_polarity" value="1" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="seven_seg_led_an" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_an" preset_proc="seven_seg_led_an_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="seven_seg_led_an_tri_o" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="seven_seg_led_an_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="seven_seg_led_an_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="seven_seg_led_an_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="seven_seg_led_an_tri_o_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="seven_seg_led_disp" type="xilinx.com:interface:gpio_rtl:1.0" of_component="seven_seg_led_disp" preset_proc="seven_seg_led_seg_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="seven_seg_led_disp_tri_o" dir="out" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="seven_seg_led_disp_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="seven_seg_led_disp_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="seven_seg_led_disp_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="seven_seg_led_disp_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="seven_seg_led_disp_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="seven_seg_led_disp_tri_o_5"/>
|
||||
<pin_map port_index="6" component_pin="seven_seg_led_disp_tri_o_6"/>
|
||||
<pin_map port_index="7" component_pin="seven_seg_led_disp_tri_o_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="100000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_txd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_rxd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jc">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jxadc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jxadc">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JXADC1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JXADC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JXADC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JXADC2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JXADC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JXADC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JXADC3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JXADC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JXADC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JXADC4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JXADC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JXADC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JXADC7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JXADC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JXADC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JXADC8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JXADC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JXADC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JXADC9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JXADC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JXADC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JXADC10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JXADC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JXADC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JXADC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
<component name="dip_switches_16bits" display_name="16 Switches" type="chip" sub_type="switch" major_group="GPIO">
|
||||
<description>Switches 15 to 0</description>
|
||||
</component>
|
||||
<component name="led_16bits" display_name="16 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>LEDs 15 to 0</description>
|
||||
</component>
|
||||
<component name="push_buttons_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Push buttons 3 to 0 [Down Right Left Up]</description>
|
||||
</component>
|
||||
<component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
|
||||
<description>QSPI Flash</description>
|
||||
</component>
|
||||
<component name="reset" display_name="Reset Signal (BTNC)" type="chip" sub_type="reset" major_group="Reset">
|
||||
<description>Reset button (BTNC)</description>
|
||||
</component>
|
||||
<component name="seven_seg_led_an" display_name="7 Segment Display - Anodes" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Seven Segment Anodes</description>
|
||||
</component>
|
||||
<component name="seven_seg_led_disp" display_name="7 Segment Display - Segments" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Seven Segment display segments</description>
|
||||
</component>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>100 MHz System Clock</description>
|
||||
</component>
|
||||
<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
|
||||
<description>USB UART</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="jc" display_name="Connector JC" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JC</description>
|
||||
</component>
|
||||
<component name="jxadc" display_name="Connector JXADC" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JXADC</description>
|
||||
</component>
|
||||
</components>
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
<connections>
|
||||
<connection name="part0_dip_switches_16bits" component1="part0" component2="dip_switches_16bits">
|
||||
<connection_map name="part0_dip_switches_16bits_1" c1_st_index="1" c1_end_index="16" c2_st_index="0" c2_end_index="15"/>
|
||||
</connection>
|
||||
<connection name="part0_led_16bits" component1="part0" component2="led_16bits">
|
||||
<connection_map name="part0_led_16bits_1" c1_st_index="17" c1_end_index="32" c2_st_index="0" c2_end_index="15"/>
|
||||
</connection>
|
||||
<connection name="part0_push_buttons_5bits" component1="part0" component2="push_buttons_5bits">
|
||||
<connection_map name="part0_push_buttons_5bits_1" c1_st_index="33" c1_end_index="36" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
|
||||
<connection_map name="part0_qspi_flash_1" c1_st_index="37" c1_end_index="41" c2_st_index="0" c2_end_index="4"/>
|
||||
</connection>
|
||||
<connection name="part0_reset" component1="part0" component2="reset">
|
||||
<connection_map name="part0_reset_1" c1_st_index="42" c1_end_index="42" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_seven_seg_led_an" component1="part0" component2="seven_seg_led_an">
|
||||
<connection_map name="part0_seven_seg_led_an_1" c1_st_index="43" c1_end_index="46" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_seven_seg_led_disp" component1="part0" component2="seven_seg_led_disp">
|
||||
<connection_map name="part0_seven_seg_led_disp_1" c1_st_index="47" c1_end_index="54" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
|
||||
<connection_map name="part0_usb_uart_1" c1_st_index="55" c1_end_index="56" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="57" c1_end_index="64" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jb" component1="part0" component2="jb">
|
||||
<connection_map name="part0_jb_1" c1_st_index="65" c1_end_index="72" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jc" component1="part0" component2="jc">
|
||||
<connection_map name="part0_jc_1" c1_st_index="73" c1_end_index="80" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jxadc" component1="part0" component2="jxadc">
|
||||
<connection_map name="part0_jxadc_1" c1_st_index="81" c1_end_index="88" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,117 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a35tcpg236-1">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="W5"/>
|
||||
<pin index="1" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="2" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="3" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="W16"/>
|
||||
<pin index="4" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="W17"/>
|
||||
<pin index="5" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="W15"/>
|
||||
<pin index="6" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="7" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="W14"/>
|
||||
<pin index="8" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="W13"/>
|
||||
<pin index="9" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS33" loc="V2"/>
|
||||
<pin index="10" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS33" loc="T3"/>
|
||||
<pin index="11" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="T2"/>
|
||||
<pin index="12" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="R3"/>
|
||||
<pin index="13" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="W2"/>
|
||||
<pin index="14" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U1"/>
|
||||
<pin index="15" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="T1"/>
|
||||
<pin index="16" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="R2"/>
|
||||
<pin index="17" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="18" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="E19"/>
|
||||
<pin index="19" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="U19"/>
|
||||
<pin index="20" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="V19"/>
|
||||
<pin index="21" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="W18"/>
|
||||
<pin index="22" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="U15"/>
|
||||
<pin index="23" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="24" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="25" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="26" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="V3"/>
|
||||
<pin index="27" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="W3"/>
|
||||
<pin index="28" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="U3"/>
|
||||
<pin index="29" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="P3"/>
|
||||
<pin index="30" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="N3"/>
|
||||
<pin index="31" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="P1"/>
|
||||
<pin index="32" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="L1"/>
|
||||
<pin index="33" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="34" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="W19"/>
|
||||
<pin index="35" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="T17"/>
|
||||
<pin index="36" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="37" name ="qspi_csn_i" iostandard="LVCMOS33" loc="K19"/>
|
||||
<pin index="38" name ="qspi_db0_i" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="39" name ="qspi_db1_i" iostandard="LVCMOS33" loc="D19"/>
|
||||
<pin index="40" name ="qspi_db2_i" iostandard="LVCMOS33" loc="G18"/>
|
||||
<pin index="41" name ="qspi_db3_i" iostandard="LVCMOS33" loc="F18"/>
|
||||
<pin index="42" name ="reset" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="43" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="U2"/>
|
||||
<pin index="44" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="U4"/>
|
||||
<pin index="45" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="V4"/>
|
||||
<pin index="46" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="W4"/>
|
||||
<pin index="47" name ="seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="W7"/>
|
||||
<pin index="48" name ="seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="W6"/>
|
||||
<pin index="49" name ="seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="U8"/>
|
||||
<pin index="50" name ="seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="V8"/>
|
||||
<pin index="51" name ="seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="U5"/>
|
||||
<pin index="52" name ="seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="V5"/>
|
||||
<pin index="53" name ="seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="U7"/>
|
||||
<pin index="54" name ="seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="V7"/>
|
||||
<pin index="55" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="56" name ="usb_uart_txd" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="57" name ="JA1" iostandard="LVCMOS33" loc="J1"/>
|
||||
<pin index="58" name ="JA2" iostandard="LVCMOS33" loc="L2"/>
|
||||
<pin index="59" name ="JA3" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="60" name ="JA4" iostandard="LVCMOS33" loc="G2"/>
|
||||
<pin index="61" name ="JA7" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="62" name ="JA8" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="63" name ="JA9" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="64" name ="JA10" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="65" name ="JB1" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="66" name ="JB2" iostandard="LVCMOS33" loc="A16"/>
|
||||
<pin index="67" name ="JB3" iostandard="LVCMOS33" loc="B15"/>
|
||||
<pin index="68" name ="JB4" iostandard="LVCMOS33" loc="B16"/>
|
||||
<pin index="69" name ="JB7" iostandard="LVCMOS33" loc="A15"/>
|
||||
<pin index="70" name ="JB8" iostandard="LVCMOS33" loc="A17"/>
|
||||
<pin index="71" name ="JB9" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="72" name ="JB10" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="73" name ="JC1" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="74" name ="JC2" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="75" name ="JC3" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="76" name ="JC4" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="77" name ="JC7" iostandard="LVCMOS33" loc="L17"/>
|
||||
<pin index="78" name ="JC8" iostandard="LVCMOS33" loc="M19"/>
|
||||
<pin index="79" name ="JC9" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="80" name ="JC10" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="81" name ="JXADC1" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="82" name ="JXADC2" iostandard="LVCMOS33" loc="L3"/>
|
||||
<pin index="83" name ="JXADC3" iostandard="LVCMOS33" loc="M2"/>
|
||||
<pin index="84" name ="JXADC4" iostandard="LVCMOS33" loc="N2"/>
|
||||
<pin index="85" name ="JXADC7" iostandard="LVCMOS33" loc="K3"/>
|
||||
<pin index="86" name ="JXADC8" iostandard="LVCMOS33" loc="M3"/>
|
||||
<pin index="87" name ="JXADC9" iostandard="LVCMOS33" loc="M1"/>
|
||||
<pin index="88" name ="JXADC10" iostandard="LVCMOS33" loc="N1"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,338 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_16bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_16bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="seven_seg_led_an_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="seven_seg_led_seg_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2" version="2.0">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.RESET_TYPE" value="ACTIVE_LOW"/>
|
||||
<user_parameter name="CONFIG.RESET_PORT" value="resetn"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
</ip_presets>
|
||||
@ -0,0 +1,416 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="cmod-s7-25" display_name="Cmod S7-25" url="https://digilent.com/reference/programmable-logic/cmod-s7/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.0</file_version>
|
||||
<description>Cmod S7-25</description>
|
||||
<components>
|
||||
<component name="part0" display_name="Cmod S7-25" type="fpga" part_name="xc7s25csga225-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-s7/start">
|
||||
<interfaces>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<description>12 MHz Single-Ended System Clock</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="12000000"/>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
|
||||
<description>BTN0 used as Active High System Reset</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="RST" physical_port="reset_btn0" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="rst_polarity" value="1"/>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="output_4bits_preset">
|
||||
<description>4 LEDs</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_4bits_tri_io" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_4bits_tri_io_0"/>
|
||||
<pin_map port_index="1" component_pin="led_4bits_tri_io_1"/>
|
||||
<pin_map port_index="2" component_pin="led_4bits_tri_io_2"/>
|
||||
<pin_map port_index="3" component_pin="led_4bits_tri_io_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_led_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led_3bits" preset_proc="rgb_led_3bits_preset">
|
||||
<description>RGB LED</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_led_3bits_tri_io" dir="out" left="2" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_led_3bits_tri_io_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_led_3bits_tri_io_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_led_3bits_tri_io_2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="input_2bits_preset">
|
||||
<description>2 Push Buttons</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="input_1bit_preset">
|
||||
<description>Only BTN1</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<!-- Add "pio_32bits" ? -->
|
||||
<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="usb_uart_preset">
|
||||
<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_txd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_rxd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_flash_preset">
|
||||
<description>Quad SPI Flash</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_I" physical_port="qspi_sck" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_sck"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_O" physical_port="qspi_sck" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_sck"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_T" physical_port="qspi_sck" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_sck"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<description>Pmod Connector JA</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>12 MHz System Clock</description>
|
||||
</component>
|
||||
<component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
|
||||
<description>Configure BTN0 as System Reset button, active high</description>
|
||||
</component>
|
||||
<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>LEDs 3 to 0</description>
|
||||
</component>
|
||||
<component name="rgb_led_3bits" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB LED 2 downto 0 (ordered RGB)</description>
|
||||
</component>
|
||||
|
||||
<component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Push Buttons 1 to 0</description>
|
||||
<component_modes>
|
||||
<component_mode name="2_btns" display_name="2 Buttons (No Reset)">
|
||||
<interfaces>
|
||||
<interface name="push_buttons_2bits" order="0"/>
|
||||
</interfaces>
|
||||
</component_mode>
|
||||
<component_mode name="1_btn" display_name="Only BTN1">
|
||||
<interfaces>
|
||||
<interface name="push_buttons_1bit" order="0"/>
|
||||
</interfaces>
|
||||
</component_mode>
|
||||
</component_modes>
|
||||
</component>
|
||||
<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
|
||||
<description>USB UART</description>
|
||||
</component>
|
||||
<component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
|
||||
<description>QSPI Flash</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
</components>
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
<connections>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_reset" component1="part0" component2="reset">
|
||||
<connection_map name="part0_reset_1" c1_st_index="8" c1_end_index="8" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
|
||||
<connection_map name="part0_led_4bits_1" c1_st_index="1" c1_end_index="4" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_led_3bits" component1="part0" component2="rgb_led_3bits">
|
||||
<connection_map name="part0_rgb_led_3bits_1" c1_st_index="5" c1_end_index="7" c2_st_index="0" c2_end_index="2"/>
|
||||
</connection>
|
||||
<connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
|
||||
<connection_map name="part0_push_buttons_2bits_1" c1_st_index="8" c1_end_index="9" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
|
||||
<connection_map name="part0_usb_uart_1" c1_st_index="10" c1_end_index="11" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
|
||||
<connection_map name="part0_qspi_flash_1" c1_st_index="12" c1_end_index="17" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="18" c1_end_index="25" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,60 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7s25csga225-1">
|
||||
<pins>
|
||||
<pin index="0" name="clk" iostandard="LVCMOS33" loc="M9"/> <!-- Schematic Name: GCLK -->
|
||||
|
||||
<pin index="1" name="led_4bits_tri_io_0" iostandard="LVCMOS33" loc="E2"/> <!-- Schematic Name: LED1 -->
|
||||
<pin index="2" name="led_4bits_tri_io_1" iostandard="LVCMOS33" loc="K1"/> <!-- Schematic Name: LED2 -->
|
||||
<pin index="3" name="led_4bits_tri_io_2" iostandard="LVCMOS33" loc="J1"/> <!-- Schematic Name: LED3 -->
|
||||
<pin index="4" name="led_4bits_tri_io_3" iostandard="LVCMOS33" loc="E1"/> <!-- Schematic Name: LED4 -->
|
||||
|
||||
<pin index="5" name="rgb_led_3bits_tri_io_0" iostandard="LVCMOS33" loc="F1"/> <!-- Schematic Name: LED0_B -->
|
||||
<pin index="6" name="rgb_led_3bits_tri_io_1" iostandard="LVCMOS33" loc="D3"/> <!-- Schematic Name: LED0_G -->
|
||||
<pin index="7" name="rgb_led_3bits_tri_io_2" iostandard="LVCMOS33" loc="F2"/> <!-- Schematic Name: LED0_R -->
|
||||
|
||||
<pin index="8" name="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="D2"/> <!-- Schematic Name: BTN0 -->
|
||||
<pin index="9" name="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="D1"/> <!-- Schematic Name: BTN1 -->
|
||||
|
||||
<pin index="10" name="usb_uart_txd" iostandard="LVCMOS33" loc="L12"/> <!-- Schematic Name: UART_RXD_OUT -->
|
||||
<pin index="11" name="usb_uart_rxd" iostandard="LVCMOS33" loc="K15"/> <!-- Schematic Name: UART_TXD_IN -->
|
||||
|
||||
<pin index="12" name="qspi_db0" iostandard="LVCMOS33" loc="H14"/> <!-- Schematic Name: QSPI_DQ0 -->
|
||||
<pin index="13" name="qspi_db1" iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: QSPI_DQ1 -->
|
||||
<pin index="14" name="qspi_db2" iostandard="LVCMOS33" loc="J12"/> <!-- Schematic Name: QSPI_DQ2 -->
|
||||
<pin index="15" name="qspi_db3" iostandard="LVCMOS33" loc="K13"/> <!-- Schematic Name: QSPI_DQ3 -->
|
||||
<pin index="16" name="qspi_csn" iostandard="LVCMOS33" loc="L11"/> <!-- Schematic Name: QSPI_CS -->
|
||||
<pin index="17" name="qspi_sck" iostandard="LVCMOS33" loc="K12"/> <!-- Schematic Name: QSPI_CS -->
|
||||
|
||||
<pin index="18" name="JA1" iostandard="LVCMOS33" loc="J2"/> <!-- Schematic Name: JA1 -->
|
||||
<pin index="19" name="JA2" iostandard="LVCMOS33" loc="H2"/> <!-- Schematic Name: JA2 -->
|
||||
<pin index="20" name="JA3" iostandard="LVCMOS33" loc="H4"/> <!-- Schematic Name: JA3 -->
|
||||
<pin index="21" name="JA4" iostandard="LVCMOS33" loc="F3"/> <!-- Schematic Name: JA4 -->
|
||||
<pin index="22" name="JA7" iostandard="LVCMOS33" loc="H3"/> <!-- Schematic Name: JA7 -->
|
||||
<pin index="23" name="JA8" iostandard="LVCMOS33" loc="H1"/> <!-- Schematic Name: JA8 -->
|
||||
<pin index="24" name="JA9" iostandard="LVCMOS33" loc="G1"/> <!-- Schematic Name: JA9 -->
|
||||
<pin index="25" name="JA10" iostandard="LVCMOS33" loc="F4"/> <!-- Schematic Name: JA10 -->
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,326 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="12"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="12"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_4bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="4"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="4"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="rgb_led_3bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="3"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="input_1bit_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI3_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI4_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="input_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="usb_uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_flash_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
@ -0,0 +1,478 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-15t" display_name="Cmod A7-15t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.2</file_version>
|
||||
<description>Cmod A7-15t</description>
|
||||
<components>
|
||||
<component name="part0" display_name="Cmod A7-15t" type="fpga" part_name="xc7a15tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
|
||||
<description>512KB SRAM</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_addr_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_addr_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_addr_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_addr_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_addr_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_addr_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_addr_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_addr_7"/>
|
||||
<pin_map port_index="8" component_pin="cellular_ram_addr_8"/>
|
||||
<pin_map port_index="9" component_pin="cellular_ram_addr_9"/>
|
||||
<pin_map port_index="10" component_pin="cellular_ram_addr_10"/>
|
||||
<pin_map port_index="11" component_pin="cellular_ram_addr_11"/>
|
||||
<pin_map port_index="12" component_pin="cellular_ram_addr_12"/>
|
||||
<pin_map port_index="13" component_pin="cellular_ram_addr_13"/>
|
||||
<pin_map port_index="14" component_pin="cellular_ram_addr_14"/>
|
||||
<pin_map port_index="15" component_pin="cellular_ram_addr_15"/>
|
||||
<pin_map port_index="16" component_pin="cellular_ram_addr_16"/>
|
||||
<pin_map port_index="17" component_pin="cellular_ram_addr_17"/>
|
||||
<pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_oen"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_wen"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_ce_n"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">
|
||||
<description>RGB LED</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
|
||||
<description>Quad SPI Flash</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
|
||||
<description>Use BTN0 as System Reset, active high</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="RST" physical_port="reset_btn0" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="rst_polarity" value="1" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<description>12 MHz Single-Ended System Clock</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="12000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
|
||||
<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_txd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_rxd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
<component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
|
||||
<description>512KB SRAM</description>
|
||||
</component>
|
||||
<component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>LEDs 1 to 0</description>
|
||||
</component>
|
||||
<component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB led 2 downto 0 [R G B]</description>
|
||||
</component>
|
||||
<component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Push buttons 1 to 0</description>
|
||||
<component_modes>
|
||||
<component_mode name="2_btns" display_name="2 Buttons (No Reset)">
|
||||
<interfaces>
|
||||
<interface name="push_buttons_2bits" order="0"/>
|
||||
</interfaces>
|
||||
</component_mode>
|
||||
<component_mode name="1_btn" display_name="Just use BTN1">
|
||||
<interfaces>
|
||||
<interface name="push_buttons_1bit" order="0"/>
|
||||
</interfaces>
|
||||
</component_mode>
|
||||
</component_modes>
|
||||
</component>
|
||||
<component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
|
||||
<description>QSPI Flash</description>
|
||||
</component>
|
||||
<component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
|
||||
<description>Configure BTN0 as System Reset button, active high</description>
|
||||
</component>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>12 MHz System Clock</description>
|
||||
</component>
|
||||
<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
|
||||
<description>USB UART</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
</components>
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
<connections>
|
||||
<connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
|
||||
<connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>
|
||||
</connection>
|
||||
<connection name="part0_led_2bits" component1="part0" component2="led_2bits">
|
||||
<connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
|
||||
<connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>
|
||||
</connection>
|
||||
<connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
|
||||
<connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
|
||||
<connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>
|
||||
</connection>
|
||||
<connection name="part0_reset" component1="part0" component2="reset">
|
||||
<connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
|
||||
<connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,81 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a15tcpg236-1">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
|
||||
<pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
|
||||
<pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
|
||||
<pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
|
||||
<pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
|
||||
<pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
|
||||
<pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
|
||||
<pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
|
||||
<pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
|
||||
<pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
|
||||
<pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
|
||||
<pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
|
||||
<pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
|
||||
<pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
|
||||
<pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
|
||||
<pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
|
||||
<pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
|
||||
<pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
|
||||
<pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
|
||||
<pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
|
||||
<pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
|
||||
<pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
|
||||
<pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
|
||||
<pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="45" name ="JA1" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="46" name ="JA2" iostandard="LVCMOS33" loc="G19"/>
|
||||
<pin index="47" name ="JA3" iostandard="LVCMOS33" loc="N18"/>
|
||||
<pin index="48" name ="JA4" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="49" name ="JA7" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="50" name ="JA8" iostandard="LVCMOS33" loc="H19"/>
|
||||
<pin index="51" name ="JA9" iostandard="LVCMOS33" loc="J19"/>
|
||||
<pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,301 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="sram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_emc">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
|
||||
<user_parameter name="CONFIG.C_MEM0_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="3000"/>
|
||||
<user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="8000"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_3bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_1bit_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
@ -0,0 +1,478 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="cmod_a7-35t" display_name="Cmod A7-35t" url="https://digilent.com/reference/programmable-logic/cmod-a7/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.2</file_version>
|
||||
<description>Cmod A7-35t</description>
|
||||
<components>
|
||||
<component name="part0" display_name="Cmod A7-35t" type="fpga" part_name="xc7a35tcpg236-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/cmod-a7/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="cellular_ram" type="xilinx.com:interface:emc_rtl:1.0" of_component="cellular_ram" preset_proc="sram_preset">
|
||||
<description>512KB SRAM</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="ADDR" physical_port="cellular_ram_addr" dir="inout" left="18" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_addr_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_addr_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_addr_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_addr_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_addr_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_addr_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_addr_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_addr_7"/>
|
||||
<pin_map port_index="8" component_pin="cellular_ram_addr_8"/>
|
||||
<pin_map port_index="9" component_pin="cellular_ram_addr_9"/>
|
||||
<pin_map port_index="10" component_pin="cellular_ram_addr_10"/>
|
||||
<pin_map port_index="11" component_pin="cellular_ram_addr_11"/>
|
||||
<pin_map port_index="12" component_pin="cellular_ram_addr_12"/>
|
||||
<pin_map port_index="13" component_pin="cellular_ram_addr_13"/>
|
||||
<pin_map port_index="14" component_pin="cellular_ram_addr_14"/>
|
||||
<pin_map port_index="15" component_pin="cellular_ram_addr_15"/>
|
||||
<pin_map port_index="16" component_pin="cellular_ram_addr_16"/>
|
||||
<pin_map port_index="17" component_pin="cellular_ram_addr_17"/>
|
||||
<pin_map port_index="18" component_pin="cellular_ram_addr_18"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="DQ_O" physical_port="cellular_ram_dq_o" dir="out" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="DQ_I" physical_port="cellular_ram_dq_i" dir="in" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="DQ_T" physical_port="cellular_ram_dq_t" dir="out" left="7" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_dq_0"/>
|
||||
<pin_map port_index="1" component_pin="cellular_ram_dq_1"/>
|
||||
<pin_map port_index="2" component_pin="cellular_ram_dq_2"/>
|
||||
<pin_map port_index="3" component_pin="cellular_ram_dq_3"/>
|
||||
<pin_map port_index="4" component_pin="cellular_ram_dq_4"/>
|
||||
<pin_map port_index="5" component_pin="cellular_ram_dq_5"/>
|
||||
<pin_map port_index="6" component_pin="cellular_ram_dq_6"/>
|
||||
<pin_map port_index="7" component_pin="cellular_ram_dq_7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="OEN" physical_port="cellular_ram_oen" dir="inout">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_oen"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="WEN" physical_port="cellular_ram_wen" dir="inout">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_wen"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="CE_N" physical_port="cellular_ram_ce_n" dir="inout">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="cellular_ram_ce_n"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="led_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_2bits" preset_proc="led_2bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_2bits_tri_o" dir="out" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_2bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="led_2bits_tri_o_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_led" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_led" preset_proc="output_3bits_preset">
|
||||
<description>RGB LED</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_led_tri_o" dir="out" left="2" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_led_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_led_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_led_tri_o_2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_2bits_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="push_buttons_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="push_buttons_1bit" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_buttons_2bits" preset_proc="push_buttons_1bit_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="push_buttons_2bits_tri_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_preset">
|
||||
<description>Quad SPI Flash</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="qspi_db0" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="qspi_db0" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="qspi_db0" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="qspi_db1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="qspi_db1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="qspi_db1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_I" physical_port="qspi_db2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_O" physical_port="qspi_db2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO2_T" physical_port="qspi_db2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_I" physical_port="qspi_db3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_O" physical_port="qspi_db3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO3_T" physical_port="qspi_db3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_db3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="qspi_csn" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="qspi_csn" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="qspi_csn" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="qspi_csn"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
|
||||
<description>Use BTN0 as System Reset, active high</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="RST" physical_port="reset_btn0" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="push_buttons_2bits_tri_i_0"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="rst_polarity" value="1" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<description>12 MHz Single-Ended System Clock</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="12000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
|
||||
<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
|
||||
<port_maps>
|
||||
<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_txd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="usb_uart_rxd"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
<component name="cellular_ram" display_name="Cell RAM" type="chip" sub_type="memory_flash_bpi" major_group="External Memory">
|
||||
<description>512KB SRAM</description>
|
||||
</component>
|
||||
<component name="led_2bits" display_name="2 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>LEDs 1 to 0</description>
|
||||
</component>
|
||||
<component name="rgb_led" display_name="RGB LED" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB led 2 downto 0 [R G B]</description>
|
||||
</component>
|
||||
<component name="push_buttons_2bits" display_name="Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Push buttons 1 to 0</description>
|
||||
<component_modes>
|
||||
<component_mode name="2_btns" display_name="2 Buttons (No Reset)">
|
||||
<interfaces>
|
||||
<interface name="push_buttons_2bits" order="0"/>
|
||||
</interfaces>
|
||||
</component_mode>
|
||||
<component_mode name="1_btn" display_name="Just use BTN1">
|
||||
<interfaces>
|
||||
<interface name="push_buttons_1bit" order="0"/>
|
||||
</interfaces>
|
||||
</component_mode>
|
||||
</component_modes>
|
||||
</component>
|
||||
<component name="qspi_flash" display_name="QSPI Flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory">
|
||||
<description>QSPI Flash</description>
|
||||
</component>
|
||||
<component name="reset" display_name="Reset (BTN0)" type="chip" sub_type="reset" major_group="Reset">
|
||||
<description>Configure BTN0 as System Reset button, active high</description>
|
||||
</component>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>12 MHz System Clock</description>
|
||||
</component>
|
||||
<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
|
||||
<description>USB UART</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
</components>
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
<connections>
|
||||
<connection name="part0_cellular_ram" component1="part0" component2="cellular_ram">
|
||||
<connection_map name="part0_cellular_ram_1" c1_st_index="1" c1_end_index="30" c2_st_index="0" c2_end_index="29"/>
|
||||
</connection>
|
||||
<connection name="part0_led_2bits" component1="part0" component2="led_2bits">
|
||||
<connection_map name="part0_led_16bits_1" c1_st_index="31" c1_end_index="32" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_led" component1="part0" component2="rgb_led">
|
||||
<connection_map name="part0_rgb_led_1" c1_st_index="33" c1_end_index="35" c2_st_index="0" c2_end_index="2"/>
|
||||
</connection>
|
||||
<connection name="part0_push_buttons_2bits" component1="part0" component2="push_buttons_2bits">
|
||||
<connection_map name="part0_push_buttons_2bits_1" c1_st_index="41" c1_end_index="42" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
|
||||
<connection_map name="part0_qspi_flash_1" c1_st_index="36" c1_end_index="40" c2_st_index="0" c2_end_index="4"/>
|
||||
</connection>
|
||||
<connection name="part0_reset" component1="part0" component2="reset">
|
||||
<connection_map name="part0_reset_1" c1_st_index="41" c1_end_index="41" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
|
||||
<connection_map name="part0_usb_uart_1" c1_st_index="43" c1_end_index="44" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="45" c1_end_index="52" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,81 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a35tcpg236-1">
|
||||
<pins>
|
||||
<pin index="0" name ="clk" iostandard="LVCMOS33" loc="L17"/>
|
||||
<pin index="1" name ="cellular_ram_addr_0" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="2" name ="cellular_ram_addr_1" iostandard="LVCMOS33" loc="M19"/>
|
||||
<pin index="3" name ="cellular_ram_addr_2" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="4" name ="cellular_ram_addr_3" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="5" name ="cellular_ram_addr_4" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="6" name ="cellular_ram_addr_5" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="7" name ="cellular_ram_addr_6" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="8" name ="cellular_ram_addr_7" iostandard="LVCMOS33" loc="W19"/>
|
||||
<pin index="9" name ="cellular_ram_addr_8" iostandard="LVCMOS33" loc="U19"/>
|
||||
<pin index="10" name ="cellular_ram_addr_9" iostandard="LVCMOS33" loc="V19"/>
|
||||
<pin index="11" name ="cellular_ram_addr_10" iostandard="LVCMOS33" loc="W18"/>
|
||||
<pin index="12" name ="cellular_ram_addr_11" iostandard="LVCMOS33" loc="T17"/>
|
||||
<pin index="13" name ="cellular_ram_addr_12" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="14" name ="cellular_ram_addr_13" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="15" name ="cellular_ram_addr_14" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="16" name ="cellular_ram_addr_15" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="17" name ="cellular_ram_addr_16" iostandard="LVCMOS33" loc="W16"/>
|
||||
<pin index="18" name ="cellular_ram_addr_17" iostandard="LVCMOS33" loc="W17"/>
|
||||
<pin index="19" name ="cellular_ram_addr_18" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="20" name ="cellular_ram_dq_0" iostandard="LVCMOS33" loc="W15"/>
|
||||
<pin index="21" name ="cellular_ram_dq_1" iostandard="LVCMOS33" loc="W13"/>
|
||||
<pin index="22" name ="cellular_ram_dq_2" iostandard="LVCMOS33" loc="W14"/>
|
||||
<pin index="23" name ="cellular_ram_dq_3" iostandard="LVCMOS33" loc="U15"/>
|
||||
<pin index="24" name ="cellular_ram_dq_4" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="25" name ="cellular_ram_dq_5" iostandard="LVCMOS33" loc="V13"/>
|
||||
<pin index="26" name ="cellular_ram_dq_6" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="27" name ="cellular_ram_dq_7" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="28" name ="cellular_ram_oen" iostandard="LVCMOS33" loc="P19"/>
|
||||
<pin index="29" name ="cellular_ram_wen" iostandard="LVCMOS33" loc="R19"/>
|
||||
<pin index="30" name ="cellular_ram_ce_n" iostandard="LVCMOS33" loc="N19"/>
|
||||
<pin index="31" name ="led_2bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/>
|
||||
<pin index="32" name ="led_2bits_tri_o_1" iostandard="LVCMOS33" loc="C16"/>
|
||||
<pin index="33" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="B17"/>
|
||||
<pin index="34" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="B16"/>
|
||||
<pin index="35" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="36" name ="qspi_csn" iostandard="LVCMOS33" loc="K19"/>
|
||||
<pin index="37" name ="qspi_db0" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="38" name ="qspi_db1" iostandard="LVCMOS33" loc="D19"/>
|
||||
<pin index="39" name ="qspi_db2" iostandard="LVCMOS33" loc="G18"/>
|
||||
<pin index="40" name ="qspi_db3" iostandard="LVCMOS33" loc="F18"/>
|
||||
<pin index="41" name ="push_buttons_2bits_tri_i_0" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="42" name ="push_buttons_2bits_tri_i_1" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="43" name ="usb_uart_txd" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="44" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="45" name ="JA1" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="46" name ="JA2" iostandard="LVCMOS33" loc="G19"/>
|
||||
<pin index="47" name ="JA3" iostandard="LVCMOS33" loc="N18"/>
|
||||
<pin index="48" name ="JA4" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="49" name ="JA7" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="50" name ="JA8" iostandard="LVCMOS33" loc="H19"/>
|
||||
<pin index="51" name ="JA9" iostandard="LVCMOS33" loc="J19"/>
|
||||
<pin index="52" name ="JA10" iostandard="LVCMOS33" loc="K18"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,301 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="sram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_emc">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_MAX_MEM_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_MEM0_TYPE" value="1"/>
|
||||
<user_parameter name="CONFIG.C_MEM0_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_TAVDV_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_TCEDV_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_THZCE_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_THZOE_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_TLZWE_PS_MEM_0" value="3000"/>
|
||||
<user_parameter name="CONFIG.C_TWC_PS_MEM_0" value="8000"/>
|
||||
<user_parameter name="CONFIG.C_TWP_PS_MEM_0" value="8000"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_3bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="3"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_1bit_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="100"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
|
||||
</ip_presets>
|
||||
@ -0,0 +1,691 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-07s" display_name="Cora Z7-07S" url="https://digilent.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Cora Z7-07S</description>
|
||||
<components>
|
||||
<component name="part0" display_name="Cora Z7-07S" type="fpga" part_name="xc7z007sclg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/cora-z7/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sys_clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="125000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="btns_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_2bits" preset_proc="input_2bits_preset">
|
||||
<description>2 Push Buttons</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btns_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btns_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btns_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_leds" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_leds" preset_proc="output_6bits_preset">
|
||||
<description>2 RGB LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="shield_i2c">
|
||||
<description>Shield I2C</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="SDA_I" physical_port="shield_i2c_sda_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_O" physical_port="shield_i2c_sda_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_T" physical_port="shield_i2c_sda_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_I" physical_port="shield_i2c_scl_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_O" physical_port="shield_i2c_scl_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_T" physical_port="shield_i2c_scl_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="shield_spi" preset_proc="shield_spi_preset">
|
||||
<description>Shield SPI</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="shield_spi_mosi_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="shield_spi_mosi_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="shield_spi_mosi_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="shield_spi_miso_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="shield_spi_miso_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="shield_spi_miso_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_I" physical_port="shield_spi_sck_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_sck_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_O" physical_port="shield_spi_sck_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_sck_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_T" physical_port="shield_spi_sck_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_sck_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="shield_spi_ss_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="shield_spi_ss_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="shield_spi_ss_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="user_dio" type="xilinx.com:interface:gpio_rtl:1.0" of_component="user_dio" preset_proc="user_dio_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="user_dio_tri_i" dir="in" left="11" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="user_dio_tri_o" dir="out" left="11" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="user_dio_tri_t" dir="out" left="11" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
|
||||
</component>
|
||||
<component name="btns_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Buttons 1 to 0</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="rgb_leds" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB LEDs 5 to 0 (3 bits per LED, ordered "RGBRGB")</description>
|
||||
</component>
|
||||
<component name="shield_i2c" display_name="Shield I2C on J3" type="chip" sub_type="mux" major_group="I2C">
|
||||
<description>Shield I2C</description>
|
||||
</component>
|
||||
<component name="shield_spi" display_name="Shield SPI on J7" type="chip" sub_type="mux" major_group="SPI">
|
||||
<description>Shield SPI</description>
|
||||
</component>
|
||||
<component name="shield_dp0_dp13" display_name="Shield Pins 0 to 13" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP0 through DP13</description>
|
||||
</component>
|
||||
<component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP26 through DP41</description>
|
||||
</component>
|
||||
<component name="user_dio" display_name="User Digital I/O on J1" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>User Digital I/O pins 1 through 12</description>
|
||||
</component>
|
||||
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_btns_2bits" component1="part0" component2="btns_2bits">
|
||||
<connection_map name="part0_btns_2bits_1" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_leds" component1="part0" component2="rgb_leds">
|
||||
<connection_map name="part0_rgb_leds_1" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jb" component1="part0" component2="jb">
|
||||
<connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_i2c" component1="part0" component2="shield_i2c">
|
||||
<connection_map name="part0_shield_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
|
||||
<connection_map name="part0_shield_dp0_dp13_1" c1_st_index="27" c1_end_index="40" c2_st_index="0" c2_end_index="13"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
|
||||
<connection_map name="part0_shield_dp26_dp41_1" c1_st_index="41" c1_end_index="56" c2_st_index="0" c2_end_index="15"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_spi" component1="part0" component2="shield_spi">
|
||||
<connection_map name="part0_shield_spi_1" c1_st_index="57" c1_end_index="60" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_user_dio" component1="part0" component2="user_dio">
|
||||
<connection_map name="part0_user_dio_1" c1_st_index="61" c1_end_index="72" c2_st_index="0" c2_end_index="11"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,113 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7z007sclg400-1">
|
||||
<pins>
|
||||
<pin index="0" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/> <!-- Schematic Name: SYSCLK -->
|
||||
|
||||
<pin index="1" name ="btns_2bits_tri_i_0" iostandard="LVCMOS33" loc="D20"/> <!-- Schematic Name: BTN0 -->
|
||||
<pin index="2" name ="btns_2bits_tri_i_1" iostandard="LVCMOS33" loc="D19"/> <!-- Schematic Name: BTN1 -->
|
||||
|
||||
<pin index="3" name ="rgb_leds_tri_o_0" iostandard="LVCMOS33" loc="N15"/> <!-- Schematic Name: LED0_R -->
|
||||
<pin index="4" name ="rgb_leds_tri_o_1" iostandard="LVCMOS33" loc="G17"/> <!-- Schematic Name: LED0_G -->
|
||||
<pin index="5" name ="rgb_leds_tri_o_2" iostandard="LVCMOS33" loc="L15"/> <!-- Schematic Name: LED0_B -->
|
||||
<pin index="6" name ="rgb_leds_tri_o_3" iostandard="LVCMOS33" loc="M15"/> <!-- Schematic Name: LED1_R -->
|
||||
<pin index="7" name ="rgb_leds_tri_o_4" iostandard="LVCMOS33" loc="L14"/> <!-- Schematic Name: LED1_G -->
|
||||
<pin index="8" name ="rgb_leds_tri_o_5" iostandard="LVCMOS33" loc="G14"/> <!-- Schematic Name: LED1_B -->
|
||||
|
||||
<pin index="9" name ="JA1" iostandard="LVCMOS33" loc="Y18"/> <!-- Schematic Name: JA1_P -->
|
||||
<pin index="10" name ="JA2" iostandard="LVCMOS33" loc="Y19"/> <!-- Schematic Name: JA1_N -->
|
||||
<pin index="11" name ="JA3" iostandard="LVCMOS33" loc="Y16"/> <!-- Schematic Name: JA2_P -->
|
||||
<pin index="12" name ="JA4" iostandard="LVCMOS33" loc="Y17"/> <!-- Schematic Name: JA2_N -->
|
||||
<pin index="13" name ="JA7" iostandard="LVCMOS33" loc="U18"/> <!-- Schematic Name: JA3_P -->
|
||||
<pin index="14" name ="JA8" iostandard="LVCMOS33" loc="U19"/> <!-- Schematic Name: JA3_N -->
|
||||
<pin index="15" name ="JA9" iostandard="LVCMOS33" loc="W18"/> <!-- Schematic Name: JA4_P -->
|
||||
<pin index="16" name ="JA10" iostandard="LVCMOS33" loc="W19"/> <!-- Schematic Name: JA4_N -->
|
||||
|
||||
<pin index="17" name ="JB1" iostandard="LVCMOS33" loc="W14"/> <!-- Schematic Name: JB1_P -->
|
||||
<pin index="18" name ="JB2" iostandard="LVCMOS33" loc="Y14"/> <!-- Schematic Name: JB1_N -->
|
||||
<pin index="19" name ="JB3" iostandard="LVCMOS33" loc="T11"/> <!-- Schematic Name: JB2_P -->
|
||||
<pin index="20" name ="JB4" iostandard="LVCMOS33" loc="T10"/> <!-- Schematic Name: JB2_N -->
|
||||
<pin index="21" name ="JB7" iostandard="LVCMOS33" loc="V16"/> <!-- Schematic Name: JB3_P -->
|
||||
<pin index="22" name ="JB8" iostandard="LVCMOS33" loc="W16"/> <!-- Schematic Name: JB3_N -->
|
||||
<pin index="23" name ="JB9" iostandard="LVCMOS33" loc="V12"/> <!-- Schematic Name: JB4_P -->
|
||||
<pin index="24" name ="JB10" iostandard="LVCMOS33" loc="W13"/> <!-- Schematic Name: JB4_N -->
|
||||
|
||||
<pin index="25" name ="shield_i2c_sda_i" iostandard="LVCMOS33" loc="P15"/> <!-- Schematic Name: CK_SDA -->
|
||||
<pin index="26" name ="shield_i2c_scl_i" iostandard="LVCMOS33" loc="P16"/> <!-- Schematic Name: CK_SCL -->
|
||||
|
||||
<pin index="27" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="U14"/> <!-- Schematic Name: CK_IO0 -->
|
||||
<pin index="28" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="V13"/> <!-- Schematic Name: CK_IO1 -->
|
||||
<pin index="29" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="T14"/> <!-- Schematic Name: CK_IO2 -->
|
||||
<pin index="30" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="T15"/> <!-- Schematic Name: CK_IO3 -->
|
||||
<pin index="31" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V17"/> <!-- Schematic Name: CK_IO4 -->
|
||||
<pin index="33" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="V18"/> <!-- Schematic Name: CK_IO5 -->
|
||||
<pin index="33" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R17"/> <!-- Schematic Name: CK_IO6 -->
|
||||
<pin index="34" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="R14"/> <!-- Schematic Name: CK_IO7 -->
|
||||
<pin index="35" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="N18"/> <!-- Schematic Name: CK_IO8 -->
|
||||
<pin index="36" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="M18"/> <!-- Schematic Name: CK_IO9 -->
|
||||
<pin index="37" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="U15"/> <!-- Schematic Name: CK_IO10 -->
|
||||
<pin index="38" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="K18"/> <!-- Schematic Name: CK_IO11 -->
|
||||
<pin index="39" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="J18"/> <!-- Schematic Name: CK_IO12 -->
|
||||
<pin index="40" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="G15"/> <!-- Schematic Name: CK_IO13 -->
|
||||
|
||||
<pin index="41" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="R16"/> <!-- Schematic Name: CK_IO26 -->
|
||||
<pin index="42" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="U12"/> <!-- Schematic Name: CK_IO27 -->
|
||||
<pin index="43" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="U13"/> <!-- Schematic Name: CK_IO28 -->
|
||||
<pin index="44" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="V15"/> <!-- Schematic Name: CK_IO29 -->
|
||||
<pin index="45" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="T16"/> <!-- Schematic Name: CK_IO30 -->
|
||||
<pin index="46" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U17"/> <!-- Schematic Name: CK_IO31 -->
|
||||
<pin index="47" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="T17"/> <!-- Schematic Name: CK_IO32 -->
|
||||
<pin index="48" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="R18"/> <!-- Schematic Name: CK_IO33 -->
|
||||
<pin index="49" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="P18"/> <!-- Schematic Name: CK_IO34 -->
|
||||
<pin index="50" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N17"/> <!-- Schematic Name: CK_IO35 -->
|
||||
<pin index="51" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="M17"/> <!-- Schematic Name: CK_IO36 -->
|
||||
<pin index="52" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="L17"/> <!-- Schematic Name: CK_IO37 -->
|
||||
<pin index="53" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="H17"/> <!-- Schematic Name: CK_IO38 -->
|
||||
<pin index="54" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="H18"/> <!-- Schematic Name: CK_IO39 -->
|
||||
<pin index="55" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="G18"/> <!-- Schematic Name: CK_IO40 -->
|
||||
<pin index="56" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="L20"/> <!-- Schematic Name: CK_IO41 -->
|
||||
|
||||
<pin index="57" name ="shield_spi_miso_i" iostandard="LVCMOS33" loc="W15"/> <!-- Schematic Name: CK_MISO -->
|
||||
<pin index="58" name ="shield_spi_mosi_i" iostandard="LVCMOS33" loc="T12"/> <!-- Schematic Name: CK_MOSI -->
|
||||
<pin index="59" name ="shield_spi_sck_i" iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: CK_SCK -->
|
||||
<pin index="60" name ="shield_spi_ss_i" iostandard="LVCMOS33" loc="F16"/> <!-- Schematic Name: CK_SS -->
|
||||
|
||||
<pin index="61" name ="user_dio_tri_i_0" iostandard="LVCMOS33" loc="L19"/> <!-- Schematic Name: USER_DIO1 -->
|
||||
<pin index="62" name ="user_dio_tri_i_1" iostandard="LVCMOS33" loc="M19"/> <!-- Schematic Name: USER_DIO2 -->
|
||||
<pin index="63" name ="user_dio_tri_i_2" iostandard="LVCMOS33" loc="N20"/> <!-- Schematic Name: USER_DIO3 -->
|
||||
<pin index="64" name ="user_dio_tri_i_3" iostandard="LVCMOS33" loc="P20"/> <!-- Schematic Name: USER_DIO4 -->
|
||||
<pin index="65" name ="user_dio_tri_i_4" iostandard="LVCMOS33" loc="P19"/> <!-- Schematic Name: USER_DIO5 -->
|
||||
<pin index="66" name ="user_dio_tri_i_5" iostandard="LVCMOS33" loc="R19"/> <!-- Schematic Name: USER_DIO6 -->
|
||||
<pin index="67" name ="user_dio_tri_i_6" iostandard="LVCMOS33" loc="T20"/> <!-- Schematic Name: USER_DIO7 -->
|
||||
<pin index="68" name ="user_dio_tri_i_7" iostandard="LVCMOS33" loc="T19"/> <!-- Schematic Name: USER_DIO8 -->
|
||||
<pin index="69" name ="user_dio_tri_i_8" iostandard="LVCMOS33" loc="U20"/> <!-- Schematic Name: USER_DIO9 -->
|
||||
<pin index="70" name ="user_dio_tri_i_9" iostandard="LVCMOS33" loc="V20"/> <!-- Schematic Name: USER_DIO10 -->
|
||||
<pin index="71" name ="user_dio_tri_i_10" iostandard="LVCMOS33" loc="W20"/> <!-- Schematic Name: USER_DIO11 -->
|
||||
<pin index="72" name ="user_dio_tri_i_11" iostandard="LVCMOS33" loc="K19"/> <!-- Schematic Name: USER_DIO12 -->
|
||||
|
||||
|
||||
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,617 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ps7_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
|
||||
<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
|
||||
<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
|
||||
<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
|
||||
<user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
|
||||
<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
|
||||
<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
|
||||
<user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
|
||||
<user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="10"/>
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100"/>
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="15.8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="15.8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
|
||||
<user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.USE_RESET" value="false"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.USE_RESET" value="false"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="input_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp13_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="user_dio_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
@ -0,0 +1,691 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="cora-z7-10" display_name="Cora Z7-10" url="https://digilent.com/reference/programmable-logic/cora-z7/start" preset_file="preset.xml" >
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Cora Z7-10</description>
|
||||
<components>
|
||||
<component name="part0" display_name="Cora Z7-10" type="fpga" part_name="xc7z010clg400-1" pin_map_file="part0_pins.xml" vendor="xilinx.com" spec_url="https://digilent.com/reference/programmable-logic/cora-z7/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
|
||||
</interface>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sys_clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="125000000" />
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="btns_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btns_2bits" preset_proc="input_2bits_preset">
|
||||
<description>2 Push Buttons</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btns_2bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btns_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btns_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgb_leds" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgb_leds" preset_proc="output_6bits_preset">
|
||||
<description>2 RGB LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgb_leds_tri_o" dir="out" left="5" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgb_leds_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgb_leds_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgb_leds_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="rgb_leds_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="rgb_leds_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="rgb_leds_tri_o_5"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_i2c" type="xilinx.com:interface:iic_rtl:1.0" of_component="shield_i2c">
|
||||
<description>Shield I2C</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_iic" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="SDA_I" physical_port="shield_i2c_sda_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_O" physical_port="shield_i2c_sda_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SDA_T" physical_port="shield_i2c_sda_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_sda_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_I" physical_port="shield_i2c_scl_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_O" physical_port="shield_i2c_scl_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCL_T" physical_port="shield_i2c_scl_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_i2c_scl_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_spi" type="xilinx.com:interface:spi_rtl:1.0" of_component="shield_spi" preset_proc="shield_spi_preset">
|
||||
<description>Shield SPI</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="IO0_I" physical_port="shield_spi_mosi_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_O" physical_port="shield_spi_mosi_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO0_T" physical_port="shield_spi_mosi_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_mosi_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_I" physical_port="shield_spi_miso_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_O" physical_port="shield_spi_miso_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="IO1_T" physical_port="shield_spi_miso_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_miso_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_I" physical_port="shield_spi_sck_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_sck_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_O" physical_port="shield_spi_sck_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_sck_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SCK_T" physical_port="shield_spi_sck_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_sck_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_I" physical_port="shield_spi_ss_i" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_O" physical_port="shield_spi_ss_o" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="SS_T" physical_port="shield_spi_ss_t" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_spi_ss_i"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp0_dp13" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp0_dp13" preset_proc="shield_dp0_dp13_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp0_dp13_tri_i" dir="in" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp0_dp13_tri_o" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp0_dp13_tri_t" dir="out" left="13" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp0_dp13_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp0_dp13_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp0_dp13_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp0_dp13_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp0_dp13_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp0_dp13_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp0_dp13_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp0_dp13_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp0_dp13_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp0_dp13_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp0_dp13_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp0_dp13_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp0_dp13_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp0_dp13_tri_i_13"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="shield_dp26_dp41" type="xilinx.com:interface:gpio_rtl:1.0" of_component="shield_dp26_dp41" preset_proc="shield_dp26_dp41_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="shield_dp26_dp41_tri_i" dir="in" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="shield_dp26_dp41_tri_o" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="shield_dp26_dp41_tri_t" dir="out" left="15" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="shield_dp26_dp41_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="shield_dp26_dp41_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="shield_dp26_dp41_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="shield_dp26_dp41_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="shield_dp26_dp41_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="shield_dp26_dp41_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="shield_dp26_dp41_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="shield_dp26_dp41_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="shield_dp26_dp41_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="shield_dp26_dp41_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="shield_dp26_dp41_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="shield_dp26_dp41_tri_i_11"/>
|
||||
<pin_map port_index="12" component_pin="shield_dp26_dp41_tri_i_12"/>
|
||||
<pin_map port_index="13" component_pin="shield_dp26_dp41_tri_i_13"/>
|
||||
<pin_map port_index="14" component_pin="shield_dp26_dp41_tri_i_14"/>
|
||||
<pin_map port_index="15" component_pin="shield_dp26_dp41_tri_i_15"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="user_dio" type="xilinx.com:interface:gpio_rtl:1.0" of_component="user_dio" preset_proc="user_dio_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="user_dio_tri_i" dir="in" left="11" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_O" physical_port="user_dio_tri_o" dir="out" left="11" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="TRI_T" physical_port="user_dio_tri_t" dir="out" left="11" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="user_dio_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="user_dio_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="user_dio_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="user_dio_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="user_dio_tri_i_4"/>
|
||||
<pin_map port_index="5" component_pin="user_dio_tri_i_5"/>
|
||||
<pin_map port_index="6" component_pin="user_dio_tri_i_6"/>
|
||||
<pin_map port_index="7" component_pin="user_dio_tri_i_7"/>
|
||||
<pin_map port_index="8" component_pin="user_dio_tri_i_8"/>
|
||||
<pin_map port_index="9" component_pin="user_dio_tri_i_9"/>
|
||||
<pin_map port_index="10" component_pin="user_dio_tri_i_10"/>
|
||||
<pin_map port_index="11" component_pin="user_dio_tri_i_11"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>3.3V Single-Ended 125 MHz oscillator used as system clock on the board</description>
|
||||
</component>
|
||||
<component name="btns_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Buttons 1 to 0</description>
|
||||
</component>
|
||||
<component name="ja" display_name="Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="jb" display_name="Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="rgb_leds" display_name="2 RGB LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB LEDs 5 to 0 (3 bits per LED, ordered "RGBRGB")</description>
|
||||
</component>
|
||||
<component name="shield_i2c" display_name="Shield I2C on J3" type="chip" sub_type="mux" major_group="I2C">
|
||||
<description>Shield I2C</description>
|
||||
</component>
|
||||
<component name="shield_spi" display_name="Shield SPI on J7" type="chip" sub_type="mux" major_group="SPI">
|
||||
<description>Shield SPI</description>
|
||||
</component>
|
||||
<component name="shield_dp0_dp13" display_name="Shield Pins 0 to 13" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP0 through DP13</description>
|
||||
</component>
|
||||
<component name="shield_dp26_dp41" display_name="Shield Pins 26 to 41" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>Digital Shield pins DP26 through DP41</description>
|
||||
</component>
|
||||
<component name="user_dio" display_name="User Digital I/O on J1" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>User Digital I/O pins 1 through 12</description>
|
||||
</component>
|
||||
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections>
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_btns_2bits" component1="part0" component2="btns_2bits">
|
||||
<connection_map name="part0_btns_2bits_1" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgb_leds" component1="part0" component2="rgb_leds">
|
||||
<connection_map name="part0_rgb_leds_1" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_ja" component1="part0" component2="ja">
|
||||
<connection_map name="part0_ja_1" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_jb" component1="part0" component2="jb">
|
||||
<connection_map name="part0_jb_1" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_i2c" component1="part0" component2="shield_i2c">
|
||||
<connection_map name="part0_shield_i2c_1" c1_st_index="25" c1_end_index="26" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp0_dp13" component1="part0" component2="shield_dp0_dp13">
|
||||
<connection_map name="part0_shield_dp0_dp13_1" c1_st_index="27" c1_end_index="40" c2_st_index="0" c2_end_index="13"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_dp26_dp41" component1="part0" component2="shield_dp26_dp41">
|
||||
<connection_map name="part0_shield_dp26_dp41_1" c1_st_index="41" c1_end_index="56" c2_st_index="0" c2_end_index="15"/>
|
||||
</connection>
|
||||
<connection name="part0_shield_spi" component1="part0" component2="shield_spi">
|
||||
<connection_map name="part0_shield_spi_1" c1_st_index="57" c1_end_index="60" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_user_dio" component1="part0" component2="user_dio">
|
||||
<connection_map name="part0_user_dio_1" c1_st_index="61" c1_end_index="72" c2_st_index="0" c2_end_index="11"/>
|
||||
</connection>
|
||||
</connections>
|
||||
</board>
|
||||
@ -0,0 +1,113 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7z010clg400-1">
|
||||
<pins>
|
||||
<pin index="0" name ="sys_clk" iostandard="LVCMOS33" loc="H16"/> <!-- Schematic Name: SYSCLK -->
|
||||
|
||||
<pin index="1" name ="btns_2bits_tri_i_0" iostandard="LVCMOS33" loc="D20"/> <!-- Schematic Name: BTN0 -->
|
||||
<pin index="2" name ="btns_2bits_tri_i_1" iostandard="LVCMOS33" loc="D19"/> <!-- Schematic Name: BTN1 -->
|
||||
|
||||
<pin index="3" name ="rgb_leds_tri_o_0" iostandard="LVCMOS33" loc="N15"/> <!-- Schematic Name: LED0_R -->
|
||||
<pin index="4" name ="rgb_leds_tri_o_1" iostandard="LVCMOS33" loc="G17"/> <!-- Schematic Name: LED0_G -->
|
||||
<pin index="5" name ="rgb_leds_tri_o_2" iostandard="LVCMOS33" loc="L15"/> <!-- Schematic Name: LED0_B -->
|
||||
<pin index="6" name ="rgb_leds_tri_o_3" iostandard="LVCMOS33" loc="M15"/> <!-- Schematic Name: LED1_R -->
|
||||
<pin index="7" name ="rgb_leds_tri_o_4" iostandard="LVCMOS33" loc="L14"/> <!-- Schematic Name: LED1_G -->
|
||||
<pin index="8" name ="rgb_leds_tri_o_5" iostandard="LVCMOS33" loc="G14"/> <!-- Schematic Name: LED1_B -->
|
||||
|
||||
<pin index="9" name ="JA1" iostandard="LVCMOS33" loc="Y18"/> <!-- Schematic Name: JA1_P -->
|
||||
<pin index="10" name ="JA2" iostandard="LVCMOS33" loc="Y19"/> <!-- Schematic Name: JA1_N -->
|
||||
<pin index="11" name ="JA3" iostandard="LVCMOS33" loc="Y16"/> <!-- Schematic Name: JA2_P -->
|
||||
<pin index="12" name ="JA4" iostandard="LVCMOS33" loc="Y17"/> <!-- Schematic Name: JA2_N -->
|
||||
<pin index="13" name ="JA7" iostandard="LVCMOS33" loc="U18"/> <!-- Schematic Name: JA3_P -->
|
||||
<pin index="14" name ="JA8" iostandard="LVCMOS33" loc="U19"/> <!-- Schematic Name: JA3_N -->
|
||||
<pin index="15" name ="JA9" iostandard="LVCMOS33" loc="W18"/> <!-- Schematic Name: JA4_P -->
|
||||
<pin index="16" name ="JA10" iostandard="LVCMOS33" loc="W19"/> <!-- Schematic Name: JA4_N -->
|
||||
|
||||
<pin index="17" name ="JB1" iostandard="LVCMOS33" loc="W14"/> <!-- Schematic Name: JB1_P -->
|
||||
<pin index="18" name ="JB2" iostandard="LVCMOS33" loc="Y14"/> <!-- Schematic Name: JB1_N -->
|
||||
<pin index="19" name ="JB3" iostandard="LVCMOS33" loc="T11"/> <!-- Schematic Name: JB2_P -->
|
||||
<pin index="20" name ="JB4" iostandard="LVCMOS33" loc="T10"/> <!-- Schematic Name: JB2_N -->
|
||||
<pin index="21" name ="JB7" iostandard="LVCMOS33" loc="V16"/> <!-- Schematic Name: JB3_P -->
|
||||
<pin index="22" name ="JB8" iostandard="LVCMOS33" loc="W16"/> <!-- Schematic Name: JB3_N -->
|
||||
<pin index="23" name ="JB9" iostandard="LVCMOS33" loc="V12"/> <!-- Schematic Name: JB4_P -->
|
||||
<pin index="24" name ="JB10" iostandard="LVCMOS33" loc="W13"/> <!-- Schematic Name: JB4_N -->
|
||||
|
||||
<pin index="25" name ="shield_i2c_sda_i" iostandard="LVCMOS33" loc="P15"/> <!-- Schematic Name: CK_SDA -->
|
||||
<pin index="26" name ="shield_i2c_scl_i" iostandard="LVCMOS33" loc="P16"/> <!-- Schematic Name: CK_SCL -->
|
||||
|
||||
<pin index="27" name ="shield_dp0_dp13_tri_i_0" iostandard="LVCMOS33" loc="U14"/> <!-- Schematic Name: CK_IO0 -->
|
||||
<pin index="28" name ="shield_dp0_dp13_tri_i_1" iostandard="LVCMOS33" loc="V13"/> <!-- Schematic Name: CK_IO1 -->
|
||||
<pin index="29" name ="shield_dp0_dp13_tri_i_2" iostandard="LVCMOS33" loc="T14"/> <!-- Schematic Name: CK_IO2 -->
|
||||
<pin index="30" name ="shield_dp0_dp13_tri_i_3" iostandard="LVCMOS33" loc="T15"/> <!-- Schematic Name: CK_IO3 -->
|
||||
<pin index="31" name ="shield_dp0_dp13_tri_i_4" iostandard="LVCMOS33" loc="V17"/> <!-- Schematic Name: CK_IO4 -->
|
||||
<pin index="33" name ="shield_dp0_dp13_tri_i_5" iostandard="LVCMOS33" loc="V18"/> <!-- Schematic Name: CK_IO5 -->
|
||||
<pin index="33" name ="shield_dp0_dp13_tri_i_6" iostandard="LVCMOS33" loc="R17"/> <!-- Schematic Name: CK_IO6 -->
|
||||
<pin index="34" name ="shield_dp0_dp13_tri_i_7" iostandard="LVCMOS33" loc="R14"/> <!-- Schematic Name: CK_IO7 -->
|
||||
<pin index="35" name ="shield_dp0_dp13_tri_i_8" iostandard="LVCMOS33" loc="N18"/> <!-- Schematic Name: CK_IO8 -->
|
||||
<pin index="36" name ="shield_dp0_dp13_tri_i_9" iostandard="LVCMOS33" loc="M18"/> <!-- Schematic Name: CK_IO9 -->
|
||||
<pin index="37" name ="shield_dp0_dp13_tri_i_10" iostandard="LVCMOS33" loc="U15"/> <!-- Schematic Name: CK_IO10 -->
|
||||
<pin index="38" name ="shield_dp0_dp13_tri_i_11" iostandard="LVCMOS33" loc="K18"/> <!-- Schematic Name: CK_IO11 -->
|
||||
<pin index="39" name ="shield_dp0_dp13_tri_i_12" iostandard="LVCMOS33" loc="J18"/> <!-- Schematic Name: CK_IO12 -->
|
||||
<pin index="40" name ="shield_dp0_dp13_tri_i_13" iostandard="LVCMOS33" loc="G15"/> <!-- Schematic Name: CK_IO13 -->
|
||||
|
||||
<pin index="41" name ="shield_dp26_dp41_tri_i_0" iostandard="LVCMOS33" loc="R16"/> <!-- Schematic Name: CK_IO26 -->
|
||||
<pin index="42" name ="shield_dp26_dp41_tri_i_1" iostandard="LVCMOS33" loc="U12"/> <!-- Schematic Name: CK_IO27 -->
|
||||
<pin index="43" name ="shield_dp26_dp41_tri_i_2" iostandard="LVCMOS33" loc="U13"/> <!-- Schematic Name: CK_IO28 -->
|
||||
<pin index="44" name ="shield_dp26_dp41_tri_i_3" iostandard="LVCMOS33" loc="V15"/> <!-- Schematic Name: CK_IO29 -->
|
||||
<pin index="45" name ="shield_dp26_dp41_tri_i_4" iostandard="LVCMOS33" loc="T16"/> <!-- Schematic Name: CK_IO30 -->
|
||||
<pin index="46" name ="shield_dp26_dp41_tri_i_5" iostandard="LVCMOS33" loc="U17"/> <!-- Schematic Name: CK_IO31 -->
|
||||
<pin index="47" name ="shield_dp26_dp41_tri_i_6" iostandard="LVCMOS33" loc="T17"/> <!-- Schematic Name: CK_IO32 -->
|
||||
<pin index="48" name ="shield_dp26_dp41_tri_i_7" iostandard="LVCMOS33" loc="R18"/> <!-- Schematic Name: CK_IO33 -->
|
||||
<pin index="49" name ="shield_dp26_dp41_tri_i_8" iostandard="LVCMOS33" loc="P18"/> <!-- Schematic Name: CK_IO34 -->
|
||||
<pin index="50" name ="shield_dp26_dp41_tri_i_9" iostandard="LVCMOS33" loc="N17"/> <!-- Schematic Name: CK_IO35 -->
|
||||
<pin index="51" name ="shield_dp26_dp41_tri_i_10" iostandard="LVCMOS33" loc="M17"/> <!-- Schematic Name: CK_IO36 -->
|
||||
<pin index="52" name ="shield_dp26_dp41_tri_i_11" iostandard="LVCMOS33" loc="L17"/> <!-- Schematic Name: CK_IO37 -->
|
||||
<pin index="53" name ="shield_dp26_dp41_tri_i_12" iostandard="LVCMOS33" loc="H17"/> <!-- Schematic Name: CK_IO38 -->
|
||||
<pin index="54" name ="shield_dp26_dp41_tri_i_13" iostandard="LVCMOS33" loc="H18"/> <!-- Schematic Name: CK_IO39 -->
|
||||
<pin index="55" name ="shield_dp26_dp41_tri_i_14" iostandard="LVCMOS33" loc="G18"/> <!-- Schematic Name: CK_IO40 -->
|
||||
<pin index="56" name ="shield_dp26_dp41_tri_i_15" iostandard="LVCMOS33" loc="L20"/> <!-- Schematic Name: CK_IO41 -->
|
||||
|
||||
<pin index="57" name ="shield_spi_miso_i" iostandard="LVCMOS33" loc="W15"/> <!-- Schematic Name: CK_MISO -->
|
||||
<pin index="58" name ="shield_spi_mosi_i" iostandard="LVCMOS33" loc="T12"/> <!-- Schematic Name: CK_MOSI -->
|
||||
<pin index="59" name ="shield_spi_sck_i" iostandard="LVCMOS33" loc="H15"/> <!-- Schematic Name: CK_SCK -->
|
||||
<pin index="60" name ="shield_spi_ss_i" iostandard="LVCMOS33" loc="F16"/> <!-- Schematic Name: CK_SS -->
|
||||
|
||||
<pin index="61" name ="user_dio_tri_i_0" iostandard="LVCMOS33" loc="L19"/> <!-- Schematic Name: USER_DIO1 -->
|
||||
<pin index="62" name ="user_dio_tri_i_1" iostandard="LVCMOS33" loc="M19"/> <!-- Schematic Name: USER_DIO2 -->
|
||||
<pin index="63" name ="user_dio_tri_i_2" iostandard="LVCMOS33" loc="N20"/> <!-- Schematic Name: USER_DIO3 -->
|
||||
<pin index="64" name ="user_dio_tri_i_3" iostandard="LVCMOS33" loc="P20"/> <!-- Schematic Name: USER_DIO4 -->
|
||||
<pin index="65" name ="user_dio_tri_i_4" iostandard="LVCMOS33" loc="P19"/> <!-- Schematic Name: USER_DIO5 -->
|
||||
<pin index="66" name ="user_dio_tri_i_5" iostandard="LVCMOS33" loc="R19"/> <!-- Schematic Name: USER_DIO6 -->
|
||||
<pin index="67" name ="user_dio_tri_i_6" iostandard="LVCMOS33" loc="T20"/> <!-- Schematic Name: USER_DIO7 -->
|
||||
<pin index="68" name ="user_dio_tri_i_7" iostandard="LVCMOS33" loc="T19"/> <!-- Schematic Name: USER_DIO8 -->
|
||||
<pin index="69" name ="user_dio_tri_i_8" iostandard="LVCMOS33" loc="U20"/> <!-- Schematic Name: USER_DIO9 -->
|
||||
<pin index="70" name ="user_dio_tri_i_9" iostandard="LVCMOS33" loc="V20"/> <!-- Schematic Name: USER_DIO10 -->
|
||||
<pin index="71" name ="user_dio_tri_i_10" iostandard="LVCMOS33" loc="W20"/> <!-- Schematic Name: USER_DIO11 -->
|
||||
<pin index="72" name ="user_dio_tri_i_11" iostandard="LVCMOS33" loc="K19"/> <!-- Schematic Name: USER_DIO12 -->
|
||||
|
||||
|
||||
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,617 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ps7_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PCW_APU_CLK_RATIO_ENABLE" value="6:2:1"/>
|
||||
<user_parameter name="CONFIG.PCW_APU_PERIPHERAL_FREQMHZ" value="650"/>
|
||||
<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="26"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE" value="667"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1300.000"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_CLKSRC" value="ARM PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_CLKSRC" value="DDR PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="52"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ" value="10.159"/>
|
||||
<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="21"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1050.000"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION" value="HPR(0)/LPR(32)"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" value="15"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_CLKSRC" value="DDR PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_RAM_BASEADDR" value="0x00100000"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x1FFFFFFF"/>
|
||||
<user_parameter name="CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" value="2"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ" value="1000 Mbps"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_POLARITY" value="Active Low"/>
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin"/>
|
||||
<user_parameter name="CONFIG.PCW_EN_4K_TIMER" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO"/>
|
||||
<user_parameter name="CONFIG.PCW_GPIO_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="20"/>
|
||||
<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000"/>
|
||||
<user_parameter name="CONFIG.PCW_IRQ_F2P_MODE" value="DIRECT"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow"/>
|
||||
<user_parameter name="CONFIG.PCW_OVERRIDE_BASIC_CLOCK" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5"/>
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ" value="200"/>
|
||||
<user_parameter name="CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_PLL_BYPASSMODE_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_PRESET_BANK0_VOLTAGE" value="LVCMOS 3.3V"/>
|
||||
<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45"/>
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="10"/>
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="100"/>
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ" value="100"/>
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC" value="External"/>
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ" value="200"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_BAUD_RATE" value="115200"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15"/>
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_CLKSRC" value="IO PLL"/>
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10"/>
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_AL" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.223"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.212"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.085"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.092"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH" value="16 Bit"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="15.8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="15.8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="80.4535"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="15.6"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="105.056"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="18.8"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="66.904"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="89.1715"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="113.63"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.040"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.058"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="-0.009"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="-0.033"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="16.5"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="98.503"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="18"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="68.5855"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="90.295"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="103.977"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="160"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ECC" value="Disabled"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ" value="525"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP" value="Normal (0-85)"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7"/>
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46"/>
|
||||
<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39"/>
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1"/>
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_POLARITY" value="Active Low"/>
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin"/>
|
||||
<user_parameter name="CONFIG.PCW_USE_AXI_NONSECURE" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_USE_CROSS_TRIGGER" value="0"/>
|
||||
<user_parameter name="CONFIG.PCW_USE_M_AXI_GP0" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.USE_RESET" value="false"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin"/>
|
||||
<user_parameter name="CONFIG.USE_RESET" value="false"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="input_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPO4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPO4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPO4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPO4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp0_dp13_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="14"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="14"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="shield_dp26_dp41_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="user_dio_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="12"/>
|
||||
<user_parameter name="CONFIG.C_INTERRUPT_PRESENT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
@ -0,0 +1,376 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://www.digilentinc.com" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">A.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.0</file_version>
|
||||
<description>Eclypse Z7</description>
|
||||
|
||||
<components>
|
||||
<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
|
||||
<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.digilentinc.com">
|
||||
<interfaces>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sys_clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="125000000"/>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
|
||||
<description>Buttons</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
|
||||
<description>8 LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<!-- Descriptions of components that will appear in the IPI Board tab -->
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
|
||||
</component>
|
||||
<component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Buttons 1 to 0</description>
|
||||
</component>
|
||||
<component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
|
||||
</component>
|
||||
<component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
|
||||
<connection_map name="part0_btn_2bits_map" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
|
||||
<connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
|
||||
<connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
|
||||
<connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
|
||||
</board>
|
||||
@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7z020clg484-1">
|
||||
<pins>
|
||||
<pin index="0" name="sys_clk" iostandard="LVCMOS33" loc="D18"/> <!-- Sch=sysclk -->
|
||||
|
||||
<pin index="1" name="btn_2bits_tri_i_0" iostandard="LVCMOS33" loc="C17"/> <!-- Sch=btn[0] -->
|
||||
<pin index="2" name="btn_2bits_tri_i_1" iostandard="LVCMOS33" loc="C18"/> <!-- Sch=btn[1] -->
|
||||
|
||||
<pin index="3" name="rgbled_6bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/> <!-- Sch=led0_b -->
|
||||
<pin index="4" name="rgbled_6bits_tri_o_1" iostandard="LVCMOS33" loc="B16"/> <!-- Sch=led0_g -->
|
||||
<pin index="5" name="rgbled_6bits_tri_o_2" iostandard="LVCMOS33" loc="B17"/> <!-- Sch=led0_r -->
|
||||
<pin index="6" name="rgbled_6bits_tri_o_3" iostandard="LVCMOS33" loc="A16"/> <!-- Sch=led1_b -->
|
||||
<pin index="7" name="rgbled_6bits_tri_o_4" iostandard="LVCMOS33" loc="A18"/> <!-- Sch=led1_g -->
|
||||
<pin index="8" name="rgbled_6bits_tri_o_5" iostandard="LVCMOS33" loc="A19"/> <!-- Sch=led1_r -->
|
||||
|
||||
<pin index="9" name="JA1" iostandard="LVCMOS33" loc="H17"/> <!-- Sch=ja1_fpga -->
|
||||
<pin index="10" name="JA2" iostandard="LVCMOS33" loc="H18"/> <!-- Sch=ja2_fpga -->
|
||||
<pin index="11" name="JA3" iostandard="LVCMOS33" loc="E16"/> <!-- Sch=ja3_fpga -->
|
||||
<pin index="12" name="JA4" iostandard="LVCMOS33" loc="F16"/> <!-- Sch=ja4_fpga -->
|
||||
<pin index="13" name="JA7" iostandard="LVCMOS33" loc="D17"/> <!-- Sch=ja7_fpga -->
|
||||
<pin index="14" name="JA8" iostandard="LVCMOS33" loc="D16"/> <!-- Sch=ja8_fpga -->
|
||||
<pin index="15" name="JA9" iostandard="LVCMOS33" loc="D15"/> <!-- Sch=ja9_fpga -->
|
||||
<pin index="16" name="JA10" iostandard="LVCMOS33" loc="E15"/> <!-- Sch=ja10_fpga -->
|
||||
|
||||
<pin index="17" name="JB1" iostandard="LVCMOS33" loc="G16"/> <!-- Sch=jb1_fpga -->
|
||||
<pin index="18" name="JB2" iostandard="LVCMOS33" loc="G15"/> <!-- Sch=jb2_fpga -->
|
||||
<pin index="19" name="JB3" iostandard="LVCMOS33" loc="E18"/> <!-- Sch=jb3_fpga -->
|
||||
<pin index="20" name="JB4" iostandard="LVCMOS33" loc="F18"/> <!-- Sch=jb4_fpga -->
|
||||
<pin index="21" name="JB7" iostandard="LVCMOS33" loc="F17"/> <!-- Sch=jb7_fpga -->
|
||||
<pin index="22" name="JB8" iostandard="LVCMOS33" loc="G17"/> <!-- Sch=jb8_fpga -->
|
||||
<pin index="23" name="JB9" iostandard="LVCMOS33" loc="B15"/> <!-- Sch=jb9_fpga -->
|
||||
<pin index="24" name="JB10" iostandard="LVCMOS33" loc="C15"/> <!-- Sch=jb10_fpga -->
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,608 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<!-- Contains IP configurations for Block/Connection Automation flows -->
|
||||
<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
|
||||
<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
|
||||
<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ps7_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="666.666687" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.158730" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="40" />
|
||||
<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1333.333" />
|
||||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2" />
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15" />
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32" />
|
||||
<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667" />
|
||||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2" />
|
||||
<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9" />
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_ENET0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_GPIO" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_I2C1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_QSPI" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_SDIO0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_UART0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_USB0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100" />
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO" />
|
||||
<user_parameter name="CONFIG.PCW_I2C0_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_GRP_INT_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" value="MIO 12 .. 13" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_I2C_RESET_SELECT" value="Share reset pin" />
|
||||
<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30" />
|
||||
<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#I2C 1#I2C 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
|
||||
<user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="0.029" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="0.031" />
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5" />
|
||||
<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45" />
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20" />
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50" />
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" value="x4" />
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15" />
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10" />
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100" />
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="533.333374" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="63.2909" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="63.2909" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="49.1639" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="49.1639" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="32.2611" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="32.2666" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="44.6376" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="44.3743" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="0.029" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="0.031" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="32.5236" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="32.3526" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="44.4929" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="44.4683" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39" />
|
||||
<user_parameter name="CONFIG.PCW_USB1_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin" />
|
||||
<!--
|
||||
<user_parameter name="CONFIG.PCW_USE_DMA0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" value="5" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" value="2" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000" />
|
||||
<user_parameter name="CONFIG.PCW_CLK1_FREQ" value="10000000" />
|
||||
<user_parameter name="CONFIG.PCW_CLK2_FREQ" value="10000000" />
|
||||
<user_parameter name="CONFIG.PCW_CLK3_FREQ" value="10000000" />
|
||||
-->
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125" />
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin" />
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true" />
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125" />
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin" />
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="btn_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="rgbled_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
@ -0,0 +1,376 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.0" vendor="digilentinc.com" name="eclypse-z7" display_name="Eclypse Z7" url="https://digilent.com/reference/programmable-logic/eclypse-z7/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Eclypse Z7</description>
|
||||
|
||||
<components>
|
||||
<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
|
||||
<component name="part0" display_name="Eclypse Z7" type="fpga" part_name="xc7z020clg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/eclypse-z7/start">
|
||||
<interfaces>
|
||||
<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
|
||||
<port_maps>
|
||||
<port_map logical_port="CLK" physical_port="sys_clk" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="sys_clk"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
<parameters>
|
||||
<parameter name="frequency" value="125000000"/>
|
||||
</parameters>
|
||||
</interface>
|
||||
<interface mode="master" name="btn_2bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_2bits" preset_proc="btn_2bits_preset">
|
||||
<description>Buttons</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="dip_switches_8bits_tri_i" dir="in" left="1" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btn_2bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btn_2bits_tri_i_1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgbled_6bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_6bits" preset_proc="rgbled_6bits_preset">
|
||||
<description>8 LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgbled_6bits_tri_o" dir="out" left="5" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgbled_6bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgbled_6bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgbled_6bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="rgbled_6bits_tri_o_3"/>
|
||||
<pin_map port_index="4" component_pin="rgbled_6bits_tri_o_4"/>
|
||||
<pin_map port_index="5" component_pin="rgbled_6bits_tri_o_5"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_ja" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_ja">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JA1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JA1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JA2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JA2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JA3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JA3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JA4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JA4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JA7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JA7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JA8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JA8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JA9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JA9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JA10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JA10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JA10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="ps7_fixedio" type="xilinx.com:display_processing_system7:fixedio_rtl:1.0" of_component="ps7_fixedio" preset_proc="ps7_preset">
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<!-- Descriptions of components that will appear in the IPI Board tab -->
|
||||
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
|
||||
<description>3.3V Single-Ended 125 MHz clock from Ethernet PHY</description>
|
||||
</component>
|
||||
<component name="btn_2bits" display_name="2 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>Buttons 1 to 0</description>
|
||||
</component>
|
||||
<component name="rgbled_6bits" display_name="2 RGB LEDS" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>RGB leds 5 to 0 (3 per LED, Ordered "RGBRGB")</description>
|
||||
</component>
|
||||
<component name="pmod_ja" display_name="Pmod Connector JA" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JA</description>
|
||||
</component>
|
||||
<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="ps7_fixedio" display_name="ps7_fixedio" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
|
||||
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
|
||||
<connection_map name="part0_sys_clock_map" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
|
||||
</connection>
|
||||
<connection name="part0_btn_2bits" component1="part0" component2="btn_2bits">
|
||||
<connection_map name="part0_btn_2bits_map" c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
|
||||
</connection>
|
||||
<connection name="part0_rgbled_6bits" component1="part0" component2="rgbled_6bits">
|
||||
<connection_map name="part0_rgbled_6bits_map" c1_st_index="3" c1_end_index="8" c2_st_index="0" c2_end_index="5"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_ja" component1="part0" component2="pmod_ja">
|
||||
<connection_map name="part0_pmod_ja_map" c1_st_index="9" c1_end_index="16" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
|
||||
<connection_map name="part0_pmod_jb_map" c1_st_index="17" c1_end_index="24" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
|
||||
</board>
|
||||
@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7z020clg484-1">
|
||||
<pins>
|
||||
<pin index="0" name="sys_clk" iostandard="LVCMOS33" loc="D18"/> <!-- Sch=sysclk -->
|
||||
|
||||
<pin index="1" name="btn_2bits_tri_i_0" iostandard="LVCMOS33" loc="C17"/> <!-- Sch=btn[0] -->
|
||||
<pin index="2" name="btn_2bits_tri_i_1" iostandard="LVCMOS33" loc="C18"/> <!-- Sch=btn[1] -->
|
||||
|
||||
<pin index="3" name="rgbled_6bits_tri_o_0" iostandard="LVCMOS33" loc="A17"/> <!-- Sch=led0_b -->
|
||||
<pin index="4" name="rgbled_6bits_tri_o_1" iostandard="LVCMOS33" loc="B16"/> <!-- Sch=led0_g -->
|
||||
<pin index="5" name="rgbled_6bits_tri_o_2" iostandard="LVCMOS33" loc="B17"/> <!-- Sch=led0_r -->
|
||||
<pin index="6" name="rgbled_6bits_tri_o_3" iostandard="LVCMOS33" loc="A16"/> <!-- Sch=led1_b -->
|
||||
<pin index="7" name="rgbled_6bits_tri_o_4" iostandard="LVCMOS33" loc="A18"/> <!-- Sch=led1_g -->
|
||||
<pin index="8" name="rgbled_6bits_tri_o_5" iostandard="LVCMOS33" loc="A19"/> <!-- Sch=led1_r -->
|
||||
|
||||
<pin index="9" name="JA1" iostandard="LVCMOS33" loc="B15"/> <!-- Sch=ja1_fpga -->
|
||||
<pin index="10" name="JA2" iostandard="LVCMOS33" loc="C15"/> <!-- Sch=ja2_fpga -->
|
||||
<pin index="11" name="JA3" iostandard="LVCMOS33" loc="D15"/> <!-- Sch=ja3_fpga -->
|
||||
<pin index="12" name="JA4" iostandard="LVCMOS33" loc="E16"/> <!-- Sch=ja4_fpga -->
|
||||
<pin index="13" name="JA7" iostandard="LVCMOS33" loc="E15"/> <!-- Sch=ja7_fpga -->
|
||||
<pin index="14" name="JA8" iostandard="LVCMOS33" loc="F17"/> <!-- Sch=ja8_fpga -->
|
||||
<pin index="15" name="JA9" iostandard="LVCMOS33" loc="F16"/> <!-- Sch=ja9_fpga -->
|
||||
<pin index="16" name="JA10" iostandard="LVCMOS33" loc="G16"/> <!-- Sch=ja10_fpga -->
|
||||
|
||||
<pin index="17" name="JB1" iostandard="LVCMOS33" loc="G15"/> <!-- Sch=jb1_fpga -->
|
||||
<pin index="18" name="JB2" iostandard="LVCMOS33" loc="D16"/> <!-- Sch=jb2_fpga -->
|
||||
<pin index="19" name="JB3" iostandard="LVCMOS33" loc="D17"/> <!-- Sch=jb3_fpga -->
|
||||
<pin index="20" name="JB4" iostandard="LVCMOS33" loc="E18"/> <!-- Sch=jb4_fpga -->
|
||||
<pin index="21" name="JB7" iostandard="LVCMOS33" loc="F18"/> <!-- Sch=jb7_fpga -->
|
||||
<pin index="22" name="JB8" iostandard="LVCMOS33" loc="G17"/> <!-- Sch=jb8_fpga -->
|
||||
<pin index="23" name="JB9" iostandard="LVCMOS33" loc="H18"/> <!-- Sch=jb9_fpga -->
|
||||
<pin index="24" name="JB10" iostandard="LVCMOS33" loc="H17"/> <!-- Sch=jb10_fpga -->
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,608 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!-- Contains IP configurations for Block/Connection Automation flows -->
|
||||
<!-- Each <ip_preset> contains a list of ways the IPs can be connected to an <interface> -->
|
||||
<!-- Each <ip> contains an IP that can be connected to the <interface> via the specified ip_interface -->
|
||||
<!-- Each <user_parameters> list contains required parameter values for the specified connection -->
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ps7_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="processing_system7" version="*">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ" value="666.666687" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ" value="10.158730" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ" value="125.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" value="100.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" value="200.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ" value="200.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" value="50.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" value="10.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" value="200.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ" value="100.000000" />
|
||||
<user_parameter name="CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_ARMPLL_CTRL_FBDIV" value="40" />
|
||||
<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_CPU_CPU_PLL_FREQMHZ" value="1333.333" />
|
||||
<user_parameter name="CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0" value="2" />
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0" value="15" />
|
||||
<user_parameter name="CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_DDRPLL_CTRL_FBDIV" value="32" />
|
||||
<user_parameter name="CONFIG.PCW_DDR_DDR_PLL_FREQMHZ" value="1066.667" />
|
||||
<user_parameter name="CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0" value="2" />
|
||||
<user_parameter name="CONFIG.PCW_DDR_RAM_HIGHADDR" value="0x3FFFFFFF" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC" value="IO PLL" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0" value="8" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ" value="1000 Mbps" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET0_RESET_IO" value="MIO 9" />
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET1_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_ENET_RESET_SELECT" value="Share reset pin" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_CD_SDIO0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_ENET0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_I2C1" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_EMIO_UART0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_EN_ENET0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_GPIO" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_I2C1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_QSPI" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_SDIO0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_UART0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_EN_USB0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100" />
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_GPIO_MIO_GPIO_IO" value="MIO" />
|
||||
<user_parameter name="CONFIG.PCW_I2C0_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_GRP_INT_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_I2C1_IO" value="MIO 12 .. 13" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_I2C1_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ" value="111.111115" />
|
||||
<user_parameter name="CONFIG.PCW_I2C_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_I2C_RESET_SELECT" value="Share reset pin" />
|
||||
<user_parameter name="CONFIG.PCW_IOPLL_CTRL_FBDIV" value="30" />
|
||||
<user_parameter name="CONFIG.PCW_IO_IO_PLL_FREQMHZ" value="1000.000" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_0_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_10_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_11_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_12_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_13_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_14_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_15_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_16_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_17_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_18_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_19_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_1_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_20_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_21_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_22_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_23_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_24_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_25_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_26_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_27_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_28_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_29_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_2_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_30_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_31_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_32_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_33_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_34_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_35_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_36_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_37_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_38_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_39_SLEW" value="fast" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_3_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_40_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_41_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_42_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_43_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_44_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_45_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_46_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_DIRECTION" value="in" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_47_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_48_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_49_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_4_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_50_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_51_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_52_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_IOTYPE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_53_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_DIRECTION" value="inout" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_5_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_6_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_7_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_PULLUP" value="disabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_8_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_DIRECTION" value="out" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_IOTYPE" value="LVCMOS 3.3V" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_PULLUP" value="enabled" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_9_SLEW" value="slow" />
|
||||
<user_parameter name="CONFIG.PCW_MIO_TREE_PERIPHERALS" value="GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#I2C 1#I2C 1#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0"/>
|
||||
<user_parameter name="CONFIG.PCW_MIO_TREE_SIGNALS" value="gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#scl#sda#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio"/>
|
||||
<user_parameter name="CONFIG.PCW_NAND_GRP_D8_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NAND_PERIPHERAL_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_A25_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_CS0_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_CS1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_NOR_PERIPHERAL_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="0.029" />
|
||||
<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="0.031" />
|
||||
<user_parameter name="CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0" value="5" />
|
||||
<user_parameter name="CONFIG.PCW_PRESET_BANK1_VOLTAGE" value="LVCMOS 1.8V" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_FBCLK_IO" value="MIO 8" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_IO1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO" value="MIO 1 .. 6" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_GRP_SS1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0" value="5" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ" value="200" />
|
||||
<user_parameter name="CONFIG.PCW_QSPI_QSPI_IO" value="MIO 1 .. 6" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_CD_IO" value="MIO 47" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_POW_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_GRP_WP_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SD0_SD0_IO" value="MIO 40 .. 45" />
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0" value="20" />
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ" value="50" />
|
||||
<user_parameter name="CONFIG.PCW_SDIO_PERIPHERAL_VALID" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SINGLE_QSPI_DATA_MODE" value="x4" />
|
||||
<user_parameter name="CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_UART0_GRP_FULL_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UART0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_UART0_UART0_IO" value="MIO 14 .. 15" />
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_DIVISOR0" value="10" />
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_FREQMHZ" value="100" />
|
||||
<user_parameter name="CONFIG.PCW_UART_PERIPHERAL_VALID" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" value="533.333374" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" value="3" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BL" value="8" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1" value="0.311" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3" value="0.304" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CL" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" value="63.2909" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" value="63.2909" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" value="49.1639" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" value="49.1639" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT" value="10" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_CWL" value="6" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY" value="4096 MBits" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" value="32.2611" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" value="32.2666" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" value="44.6376" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" value="44.3743" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" value="0.202" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" value="0.029" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" value="0.031" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" value="32.5236" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" value="32.3526" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" value="44.4929" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" value="44.4683" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" value="165.1" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH" value="16 Bits" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE" value="DDR 3 (Low Voltage)" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_PARTNO" value="MT41K256M16 RE-125" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" value="15" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_SPEED_BIN" value="DDR3_1066F" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_FAW" value="40.0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN" value="35.0" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RC" value="48.75" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RCD" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_UIPARAM_DDR_T_RP" value="7" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ" value="60" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_RESET_IO" value="MIO 46" />
|
||||
<user_parameter name="CONFIG.PCW_USB0_USB0_IO" value="MIO 28 .. 39" />
|
||||
<user_parameter name="CONFIG.PCW_USB1_RESET_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_USB_RESET_SELECT" value="Share reset pin" />
|
||||
<!--
|
||||
<user_parameter name="CONFIG.PCW_USE_DMA0" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK0_ENABLE" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK1_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK2_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FPGA_FCLK3_ENABLE" value="0" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0" value="5" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1" value="2" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1" value="1" />
|
||||
<user_parameter name="CONFIG.PCW_CLK0_FREQ" value="100000000" />
|
||||
<user_parameter name="CONFIG.PCW_CLK1_FREQ" value="10000000" />
|
||||
<user_parameter name="CONFIG.PCW_CLK2_FREQ" value="10000000" />
|
||||
<user_parameter name="CONFIG.PCW_CLK3_FREQ" value="10000000" />
|
||||
-->
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="sys_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="125" />
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Single_ended_clock_capable_pin" />
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="clk_in2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true" />
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="125" />
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Single_ended_clock_capable_pin" />
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="btn_2bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="2"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="2"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="rgbled_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
@ -0,0 +1,535 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">B.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.0</file_version>
|
||||
<description>Genesys ZU-3EG</description>
|
||||
|
||||
<components>
|
||||
<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
|
||||
<component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
|
||||
</preferred_ips>
|
||||
</interface>
|
||||
<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
|
||||
<description>5 PL Buttons (Ordered "UCDLR")</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
|
||||
<description>4 PL Switches</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
|
||||
<description>PL RGB LED (ordered RGB)</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
|
||||
<description>4 LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<!-- Descriptions of components that will appear in the IPI Board tab -->
|
||||
<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>5 Buttons (Ordered "UCDLR")</description>
|
||||
</component>
|
||||
<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
|
||||
<description>4 Switches</description>
|
||||
</component>
|
||||
<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>1 RGB LED (Ordered "RGB")</description>
|
||||
</component>
|
||||
<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>4 LEDs</description>
|
||||
</component>
|
||||
<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JC</description>
|
||||
</component>
|
||||
<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JD</description>
|
||||
</component>
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
|
||||
<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
|
||||
<connection_map name="part0_btn_5bits_map" c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
|
||||
</connection>
|
||||
<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
|
||||
<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
|
||||
<connection_map name="part0_rgbled_3bits_map" c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
|
||||
</connection>
|
||||
<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
|
||||
<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
|
||||
<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
|
||||
<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
|
||||
<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
|
||||
</board>
|
||||
@ -0,0 +1,74 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xczu3eg-sfvc784-1-e">
|
||||
<pins>
|
||||
<pin index="0" name="btn_5bits_tri_i_0" iostandard="LVCMOS18" loc="A12"/> <!-- Sch=BTNR -->
|
||||
<pin index="1" name="btn_5bits_tri_i_1" iostandard="LVCMOS18" loc="F12"/> <!-- Sch=BTNL -->
|
||||
<pin index="2" name="btn_5bits_tri_i_2" iostandard="LVCMOS18" loc="J12"/> <!-- Sch=BTND -->
|
||||
<pin index="3" name="btn_5bits_tri_i_3" iostandard="LVCMOS18" loc="H12"/> <!-- Sch=BTNC -->
|
||||
<pin index="4" name="btn_5bits_tri_i_4" iostandard="LVCMOS18" loc="B10"/> <!-- Sch=BTNU -->
|
||||
|
||||
<pin index="5" name="switch_4bits_tri_i_0" iostandard="LVCMOS33" loc="AB15"/> <!-- Sch=SW0 -->
|
||||
<pin index="6" name="switch_4bits_tri_i_1" iostandard="LVCMOS33" loc="W12"/> <!-- Sch=SW1 -->
|
||||
<pin index="7" name="switch_4bits_tri_i_2" iostandard="LVCMOS33" loc="Y13"/> <!-- Sch=SW2 -->
|
||||
<pin index="8" name="switch_4bits_tri_i_3" iostandard="LVCMOS33" loc="AB14"/> <!-- Sch=SW3 -->
|
||||
|
||||
<pin index="9" name="rgbled_3bits_tri_o_0" iostandard="LVCMOS12" loc="A8"/> <!-- Sch=LD5_B -->
|
||||
<pin index="10" name="rgbled_3bits_tri_o_1" iostandard="LVCMOS12" loc="B9"/> <!-- Sch=LD5_G -->
|
||||
<pin index="11" name="rgbled_3bits_tri_o_2" iostandard="LVCMOS12" loc="C9"/> <!-- Sch=LD5_R -->
|
||||
|
||||
<pin index="12" name="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="J14"/> <!-- Sch=LD1 -->
|
||||
<pin index="13" name="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="K14"/> <!-- Sch=LD2 -->
|
||||
<pin index="14" name="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="L13"/> <!-- Sch=LD3 -->
|
||||
<pin index="15" name="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="L14"/> <!-- Sch=LD4 -->
|
||||
|
||||
<pin index="16" name="JB1" iostandard="LVCMOS33" loc="AE13"/> <!-- Sch=JB1 -->
|
||||
<pin index="17" name="JB2" iostandard="LVCMOS33" loc="AG14"/> <!-- Sch=JB2 -->
|
||||
<pin index="18" name="JB3" iostandard="LVCMOS33" loc="AH14"/> <!-- Sch=JB3 -->
|
||||
<pin index="19" name="JB4" iostandard="LVCMOS33" loc="AG13"/> <!-- Sch=JB4 -->
|
||||
<pin index="20" name="JB7" iostandard="LVCMOS33" loc="AE14"/> <!-- Sch=JB7 -->
|
||||
<pin index="21" name="JB8" iostandard="LVCMOS33" loc="AF13"/> <!-- Sch=JB8 -->
|
||||
<pin index="22" name="JB9" iostandard="LVCMOS33" loc="AE15"/> <!-- Sch=JB9 -->
|
||||
<pin index="23" name="JB10" iostandard="LVCMOS33" loc="AH13"/> <!-- Sch=JB10 -->
|
||||
|
||||
<pin index="24" name="JC1" iostandard="LVCMOS33" loc="E13"/> <!-- Sch=JC1 -->
|
||||
<pin index="25" name="JC2" iostandard="LVCMOS33" loc="G13"/> <!-- Sch=JC2 -->
|
||||
<pin index="26" name="JC3" iostandard="LVCMOS33" loc="B13"/> <!-- Sch=JC3 -->
|
||||
<pin index="27" name="JC4" iostandard="LVCMOS33" loc="D14"/> <!-- Sch=JC4 -->
|
||||
<pin index="28" name="JC7" iostandard="LVCMOS33" loc="F13"/> <!-- Sch=JC7 -->
|
||||
<pin index="29" name="JC8" iostandard="LVCMOS33" loc="C13"/> <!-- Sch=JC8 -->
|
||||
<pin index="30" name="JC9" iostandard="LVCMOS33" loc="C14"/> <!-- Sch=JC9 -->
|
||||
<pin index="31" name="JC10" iostandard="LVCMOS33" loc="A13"/> <!-- Sch=JC10 -->
|
||||
|
||||
<pin index="32" name="JD1" iostandard="LVCMOS33" loc="E15"/> <!-- Sch=JD1 -->
|
||||
<pin index="33" name="JD2" iostandard="LVCMOS33" loc="A14"/> <!-- Sch=JD2 -->
|
||||
<pin index="34" name="JD3" iostandard="LVCMOS33" loc="B15"/> <!-- Sch=JD3 -->
|
||||
<pin index="35" name="JD4" iostandard="LVCMOS33" loc="F15"/> <!-- Sch=JD4 -->
|
||||
<pin index="36" name="JD7" iostandard="LVCMOS33" loc="E14"/> <!-- Sch=JD7 -->
|
||||
<pin index="37" name="JD8" iostandard="LVCMOS33" loc="B14"/> <!-- Sch=JD8 -->
|
||||
<pin index="38" name="JD9" iostandard="LVCMOS33" loc="D15"/> <!-- Sch=JD9 -->
|
||||
<pin index="39" name="JD10" iostandard="LVCMOS33" loc="A15"/> <!-- Sch=JD10 -->
|
||||
</pins>
|
||||
</part_info>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,535 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2022 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.1" vendor="digilentinc.com" name="gzu_3eg" display_name="Genesys ZU-3EG" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">D.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Genesys ZU-3EG</description>
|
||||
|
||||
<components>
|
||||
<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
|
||||
<component name="part0" display_name="Genesys ZU-3EG" type="fpga" part_name="xczu3eg-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
|
||||
</preferred_ips>
|
||||
</interface>
|
||||
<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
|
||||
<description>5 PL Buttons (Ordered "UCDLR")</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
|
||||
<description>4 PL Switches</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
|
||||
<description>PL RGB LED (ordered RGB)</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
|
||||
<description>4 LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<!-- Descriptions of components that will appear in the IPI Board tab -->
|
||||
<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>5 Buttons (Ordered "UCDLR")</description>
|
||||
</component>
|
||||
<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
|
||||
<description>4 Switches</description>
|
||||
</component>
|
||||
<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>1 RGB LED (Ordered "RGB")</description>
|
||||
</component>
|
||||
<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>4 LEDs</description>
|
||||
</component>
|
||||
<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JC</description>
|
||||
</component>
|
||||
<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JD</description>
|
||||
</component>
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
|
||||
<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
|
||||
<connection_map name="part0_btn_5bits_map" c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
|
||||
</connection>
|
||||
<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
|
||||
<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
|
||||
<connection_map name="part0_rgbled_3bits_map" c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
|
||||
</connection>
|
||||
<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
|
||||
<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
|
||||
<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
|
||||
<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
|
||||
<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
|
||||
</board>
|
||||
@ -0,0 +1,74 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2022 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xczu3eg-sfvc784-1-e">
|
||||
<pins>
|
||||
<pin index="0" name="btn_5bits_tri_i_0" iostandard="LVCMOS18" loc="A12"/> <!-- Sch=BTNR -->
|
||||
<pin index="1" name="btn_5bits_tri_i_1" iostandard="LVCMOS18" loc="F12"/> <!-- Sch=BTNL -->
|
||||
<pin index="2" name="btn_5bits_tri_i_2" iostandard="LVCMOS18" loc="J12"/> <!-- Sch=BTND -->
|
||||
<pin index="3" name="btn_5bits_tri_i_3" iostandard="LVCMOS18" loc="H12"/> <!-- Sch=BTNC -->
|
||||
<pin index="4" name="btn_5bits_tri_i_4" iostandard="LVCMOS18" loc="B10"/> <!-- Sch=BTNU -->
|
||||
|
||||
<pin index="5" name="switch_4bits_tri_i_0" iostandard="LVCMOS33" loc="AB15"/> <!-- Sch=SW0 -->
|
||||
<pin index="6" name="switch_4bits_tri_i_1" iostandard="LVCMOS33" loc="W12"/> <!-- Sch=SW1 -->
|
||||
<pin index="7" name="switch_4bits_tri_i_2" iostandard="LVCMOS33" loc="Y13"/> <!-- Sch=SW2 -->
|
||||
<pin index="8" name="switch_4bits_tri_i_3" iostandard="LVCMOS33" loc="AB14"/> <!-- Sch=SW3 -->
|
||||
|
||||
<pin index="9" name="rgbled_3bits_tri_o_0" iostandard="LVCMOS12" loc="A8"/> <!-- Sch=LD5_B -->
|
||||
<pin index="10" name="rgbled_3bits_tri_o_1" iostandard="LVCMOS12" loc="B9"/> <!-- Sch=LD5_G -->
|
||||
<pin index="11" name="rgbled_3bits_tri_o_2" iostandard="LVCMOS12" loc="C9"/> <!-- Sch=LD5_R -->
|
||||
|
||||
<pin index="12" name="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="J14"/> <!-- Sch=LD1 -->
|
||||
<pin index="13" name="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="K14"/> <!-- Sch=LD2 -->
|
||||
<pin index="14" name="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="L13"/> <!-- Sch=LD3 -->
|
||||
<pin index="15" name="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="L14"/> <!-- Sch=LD4 -->
|
||||
|
||||
<pin index="16" name="JB1" iostandard="LVCMOS33" loc="AE13"/> <!-- Sch=JB1 -->
|
||||
<pin index="17" name="JB2" iostandard="LVCMOS33" loc="AG14"/> <!-- Sch=JB2 -->
|
||||
<pin index="18" name="JB3" iostandard="LVCMOS33" loc="AH14"/> <!-- Sch=JB3 -->
|
||||
<pin index="19" name="JB4" iostandard="LVCMOS33" loc="AG13"/> <!-- Sch=JB4 -->
|
||||
<pin index="20" name="JB7" iostandard="LVCMOS33" loc="AE14"/> <!-- Sch=JB7 -->
|
||||
<pin index="21" name="JB8" iostandard="LVCMOS33" loc="AF13"/> <!-- Sch=JB8 -->
|
||||
<pin index="22" name="JB9" iostandard="LVCMOS33" loc="AE15"/> <!-- Sch=JB9 -->
|
||||
<pin index="23" name="JB10" iostandard="LVCMOS33" loc="AH13"/> <!-- Sch=JB10 -->
|
||||
|
||||
<pin index="24" name="JC1" iostandard="LVCMOS33" loc="E13"/> <!-- Sch=JC1 -->
|
||||
<pin index="25" name="JC2" iostandard="LVCMOS33" loc="G13"/> <!-- Sch=JC2 -->
|
||||
<pin index="26" name="JC3" iostandard="LVCMOS33" loc="B13"/> <!-- Sch=JC3 -->
|
||||
<pin index="27" name="JC4" iostandard="LVCMOS33" loc="D14"/> <!-- Sch=JC4 -->
|
||||
<pin index="28" name="JC7" iostandard="LVCMOS33" loc="F13"/> <!-- Sch=JC7 -->
|
||||
<pin index="29" name="JC8" iostandard="LVCMOS33" loc="C13"/> <!-- Sch=JC8 -->
|
||||
<pin index="30" name="JC9" iostandard="LVCMOS33" loc="C14"/> <!-- Sch=JC9 -->
|
||||
<pin index="31" name="JC10" iostandard="LVCMOS33" loc="A13"/> <!-- Sch=JC10 -->
|
||||
|
||||
<pin index="32" name="JD1" iostandard="LVCMOS33" loc="E15"/> <!-- Sch=JD1 -->
|
||||
<pin index="33" name="JD2" iostandard="LVCMOS33" loc="A14"/> <!-- Sch=JD2 -->
|
||||
<pin index="34" name="JD3" iostandard="LVCMOS33" loc="B15"/> <!-- Sch=JD3 -->
|
||||
<pin index="35" name="JD4" iostandard="LVCMOS33" loc="F15"/> <!-- Sch=JD4 -->
|
||||
<pin index="36" name="JD7" iostandard="LVCMOS33" loc="E14"/> <!-- Sch=JD7 -->
|
||||
<pin index="37" name="JD8" iostandard="LVCMOS33" loc="B14"/> <!-- Sch=JD8 -->
|
||||
<pin index="38" name="JD9" iostandard="LVCMOS33" loc="D15"/> <!-- Sch=JD9 -->
|
||||
<pin index="39" name="JD10" iostandard="LVCMOS33" loc="A15"/> <!-- Sch=JD10 -->
|
||||
</pins>
|
||||
</part_info>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,535 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2022 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<board schema_version="2.1" vendor="digilentinc.com" name="gzu_5ev" display_name="Genesys ZU-5EV" url="https://digilent.com/reference/programmable-logic/genesys-zu/start" preset_file="preset.xml">
|
||||
<compatible_board_revisions>
|
||||
<revision id="0">C.0</revision>
|
||||
</compatible_board_revisions>
|
||||
<file_version>1.1</file_version>
|
||||
<description>Genesys ZU-5EV</description>
|
||||
|
||||
<components>
|
||||
<!-- Defines BD interfaces that can be used to connect the FPGA to a particular <component> -->
|
||||
<component name="part0" display_name="Genesys ZU-5EV" type="fpga" part_name="xczu5ev-sfvc784-1-e" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="https://digilent.com/reference/programmable-logic/genesys-zu/start">
|
||||
<interfaces>
|
||||
<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="zynq_ultra_ps_e_preset">
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="zynq_ultra_ps_e" order="0"/>
|
||||
</preferred_ips>
|
||||
</interface>
|
||||
<interface mode="master" name="btn_5bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="btn_5bits" preset_proc="btn_5bits_preset">
|
||||
<description>5 PL Buttons (Ordered "UCDLR")</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="btn_5bits_tri_i" dir="in" left="4" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="btn_5bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="btn_5bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="btn_5bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="btn_5bits_tri_i_3"/>
|
||||
<pin_map port_index="4" component_pin="btn_5bits_tri_i_4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="switch_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="switch_4bits" preset_proc="switch_4bits_preset">
|
||||
<description>4 PL Switches</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_I" physical_port="switch_4bits_tri_i" dir="in" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="switch_4bits_tri_i_0"/>
|
||||
<pin_map port_index="1" component_pin="switch_4bits_tri_i_1"/>
|
||||
<pin_map port_index="2" component_pin="switch_4bits_tri_i_2"/>
|
||||
<pin_map port_index="3" component_pin="switch_4bits_tri_i_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="rgbled_3bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="rgbled_3bits" preset_proc="rgbled_3bits_preset">
|
||||
<description>PL RGB LED (ordered RGB)</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="rgbled_3bits_tri_o" dir="out" left="2" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="rgbled_3bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="rgbled_3bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="rgbled_3bits_tri_o_2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
|
||||
<description>4 LEDs</description>
|
||||
<preferred_ips>
|
||||
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
|
||||
</preferred_ips>
|
||||
<port_maps>
|
||||
<port_map logical_port="TRI_O" physical_port="led_4bits_tri_o" dir="out" left="3" right="0">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="led_4bits_tri_o_0"/>
|
||||
<pin_map port_index="1" component_pin="led_4bits_tri_o_1"/>
|
||||
<pin_map port_index="2" component_pin="led_4bits_tri_o_2"/>
|
||||
<pin_map port_index="3" component_pin="led_4bits_tri_o_3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jb" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jb">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JB1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JB1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JB2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JB2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JB3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JB3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JB4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JB4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JB7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JB7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JB8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JB8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JB9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JB9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JB10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JB10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JB10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jc" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jc">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JC1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JC1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JC2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JC2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JC3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JC3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JC4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JC4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JC7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JC7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JC8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JC8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JC9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JC9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JC10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JC10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JC10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
<interface mode="master" name="pmod_jd" type="digilentinc.com:interface:pmod_rtl:1.0" of_component="pmod_jd">
|
||||
<port_maps>
|
||||
<port_map logical_port="PIN1_I" physical_port="JD1" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_O" physical_port="JD1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN1_T" physical_port="JD1" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD1"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_I" physical_port="JD2" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_O" physical_port="JD2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN2_T" physical_port="JD2" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD2"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_I" physical_port="JD3" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_O" physical_port="JD3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN3_T" physical_port="JD3" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD3"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_I" physical_port="JD4" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_O" physical_port="JD4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN4_T" physical_port="JD4" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD4"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_I" physical_port="JD7" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_O" physical_port="JD7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN7_T" physical_port="JD7" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD7"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_I" physical_port="JD8" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_O" physical_port="JD8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN8_T" physical_port="JD8" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD8"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_I" physical_port="JD9" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_O" physical_port="JD9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN9_T" physical_port="JD9" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD9"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_I" physical_port="JD10" dir="in">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_O" physical_port="JD10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
<port_map logical_port="PIN10_T" physical_port="JD10" dir="out">
|
||||
<pin_maps>
|
||||
<pin_map port_index="0" component_pin="JD10"/>
|
||||
</pin_maps>
|
||||
</port_map>
|
||||
</port_maps>
|
||||
</interface>
|
||||
</interfaces>
|
||||
</component>
|
||||
|
||||
<!-- Descriptions of components that will appear in the IPI Board tab -->
|
||||
<component name="ps8_fixedio" display_name="PS8 Fixed IO" type="chip" sub_type="fixed_io" major_group=""/>
|
||||
<component name="btn_5bits" display_name="5 Buttons" type="chip" sub_type="push_button" major_group="GPIO">
|
||||
<description>5 Buttons (Ordered "UCDLR")</description>
|
||||
</component>
|
||||
<component name="switch_4bits" display_name="4 Switches" type="chip" sub_type="switch" major_group="GPIO">
|
||||
<description>4 Switches</description>
|
||||
</component>
|
||||
<component name="rgbled_3bits" display_name="1 RGB LED" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>1 RGB LED (Ordered "RGB")</description>
|
||||
</component>
|
||||
<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
|
||||
<description>4 LEDs</description>
|
||||
</component>
|
||||
<component name="pmod_jb" display_name="Pmod Connector JB" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JB</description>
|
||||
</component>
|
||||
<component name="pmod_jc" display_name="Pmod Connector JC" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JC</description>
|
||||
</component>
|
||||
<component name="pmod_jd" display_name="Pmod Connector JD" type="chip" sub_type="chip" major_group="Pmod">
|
||||
<description>Pmod Connector JD</description>
|
||||
</component>
|
||||
</components>
|
||||
|
||||
<jtag_chains>
|
||||
<jtag_chain name="chain1">
|
||||
<position name="0" component="part0"/>
|
||||
</jtag_chain>
|
||||
</jtag_chains>
|
||||
|
||||
<connections> <!-- Defines index alignment between <port_map> (above) and <pins> (part0_pins.xml) -->
|
||||
<connection name="part0_btn_5bits" component1="part0" component2="btn_5bits">
|
||||
<connection_map name="part0_btn_5bits_map" c1_st_index="0" c1_end_index="4" c2_st_index="0" c2_end_index="4"/>
|
||||
</connection>
|
||||
<connection name="part0_switch_4bits" component1="part0" component2="switch_4bits">
|
||||
<connection_map name="part0_switch_4bits_map" c1_st_index="5" c1_end_index="8" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="rgbled_3bits" component1="part0" component2="rgbled_3bits">
|
||||
<connection_map name="part0_rgbled_3bits_map" c1_st_index="9" c1_end_index="11" c2_st_index="0" c2_end_index="2"/>
|
||||
</connection>
|
||||
<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
|
||||
<connection_map name="part0_led_4bits_map" c1_st_index="12" c1_end_index="15" c2_st_index="0" c2_end_index="3"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jb" component1="part0" component2="pmod_jb">
|
||||
<connection_map name="part0_pmod_jb_map" c1_st_index="16" c1_end_index="23" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jc" component1="part0" component2="pmod_jc">
|
||||
<connection_map name="part0_pmod_jc_map" c1_st_index="24" c1_end_index="31" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
<connection name="part0_pmod_jd" component1="part0" component2="pmod_jd">
|
||||
<connection_map name="part0_pmod_jd_map" c1_st_index="32" c1_end_index="39" c2_st_index="0" c2_end_index="7"/>
|
||||
</connection>
|
||||
</connections>
|
||||
|
||||
</board>
|
||||
@ -0,0 +1,2 @@
|
||||
1.1 Fixed PSU__DDRC__DDR4_ADDR_MAPPING appearing twice and with conflicting values that was causing a silent FSBL failure in the boot process.
|
||||
1.0. Genesys ZU-ZU5EV initial board support for rev C.
|
||||
@ -0,0 +1,74 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2022 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xczu5ev-sfvc784-1-e">
|
||||
<pins>
|
||||
<pin index="0" name="btn_5bits_tri_i_0" iostandard="LVCMOS18" loc="A12"/> <!-- Sch=BTNR -->
|
||||
<pin index="1" name="btn_5bits_tri_i_1" iostandard="LVCMOS18" loc="F12"/> <!-- Sch=BTNL -->
|
||||
<pin index="2" name="btn_5bits_tri_i_2" iostandard="LVCMOS18" loc="J12"/> <!-- Sch=BTND -->
|
||||
<pin index="3" name="btn_5bits_tri_i_3" iostandard="LVCMOS18" loc="H12"/> <!-- Sch=BTNC -->
|
||||
<pin index="4" name="btn_5bits_tri_i_4" iostandard="LVCMOS18" loc="B10"/> <!-- Sch=BTNU -->
|
||||
|
||||
<pin index="5" name="switch_4bits_tri_i_0" iostandard="LVCMOS33" loc="AB15"/> <!-- Sch=SW0 -->
|
||||
<pin index="6" name="switch_4bits_tri_i_1" iostandard="LVCMOS33" loc="W12"/> <!-- Sch=SW1 -->
|
||||
<pin index="7" name="switch_4bits_tri_i_2" iostandard="LVCMOS33" loc="Y13"/> <!-- Sch=SW2 -->
|
||||
<pin index="8" name="switch_4bits_tri_i_3" iostandard="LVCMOS33" loc="AB14"/> <!-- Sch=SW3 -->
|
||||
|
||||
<pin index="9" name="rgbled_3bits_tri_o_0" iostandard="LVCMOS12" loc="A8"/> <!-- Sch=LD5_B -->
|
||||
<pin index="10" name="rgbled_3bits_tri_o_1" iostandard="LVCMOS12" loc="B9"/> <!-- Sch=LD5_G -->
|
||||
<pin index="11" name="rgbled_3bits_tri_o_2" iostandard="LVCMOS12" loc="C9"/> <!-- Sch=LD5_R -->
|
||||
|
||||
<pin index="12" name="led_4bits_tri_o_0" iostandard="LVCMOS33" loc="J14"/> <!-- Sch=LD1 -->
|
||||
<pin index="13" name="led_4bits_tri_o_1" iostandard="LVCMOS33" loc="K14"/> <!-- Sch=LD2 -->
|
||||
<pin index="14" name="led_4bits_tri_o_2" iostandard="LVCMOS33" loc="L13"/> <!-- Sch=LD3 -->
|
||||
<pin index="15" name="led_4bits_tri_o_3" iostandard="LVCMOS33" loc="L14"/> <!-- Sch=LD4 -->
|
||||
|
||||
<pin index="16" name="JB1" iostandard="LVCMOS33" loc="AE13"/> <!-- Sch=JB1 -->
|
||||
<pin index="17" name="JB2" iostandard="LVCMOS33" loc="AG14"/> <!-- Sch=JB2 -->
|
||||
<pin index="18" name="JB3" iostandard="LVCMOS33" loc="AH14"/> <!-- Sch=JB3 -->
|
||||
<pin index="19" name="JB4" iostandard="LVCMOS33" loc="AG13"/> <!-- Sch=JB4 -->
|
||||
<pin index="20" name="JB7" iostandard="LVCMOS33" loc="AE14"/> <!-- Sch=JB7 -->
|
||||
<pin index="21" name="JB8" iostandard="LVCMOS33" loc="AF13"/> <!-- Sch=JB8 -->
|
||||
<pin index="22" name="JB9" iostandard="LVCMOS33" loc="AE15"/> <!-- Sch=JB9 -->
|
||||
<pin index="23" name="JB10" iostandard="LVCMOS33" loc="AH13"/> <!-- Sch=JB10 -->
|
||||
|
||||
<pin index="24" name="JC1" iostandard="LVCMOS33" loc="E13"/> <!-- Sch=JC1 -->
|
||||
<pin index="25" name="JC2" iostandard="LVCMOS33" loc="G13"/> <!-- Sch=JC2 -->
|
||||
<pin index="26" name="JC3" iostandard="LVCMOS33" loc="B13"/> <!-- Sch=JC3 -->
|
||||
<pin index="27" name="JC4" iostandard="LVCMOS33" loc="D14"/> <!-- Sch=JC4 -->
|
||||
<pin index="28" name="JC7" iostandard="LVCMOS33" loc="F13"/> <!-- Sch=JC7 -->
|
||||
<pin index="29" name="JC8" iostandard="LVCMOS33" loc="C13"/> <!-- Sch=JC8 -->
|
||||
<pin index="30" name="JC9" iostandard="LVCMOS33" loc="C14"/> <!-- Sch=JC9 -->
|
||||
<pin index="31" name="JC10" iostandard="LVCMOS33" loc="A13"/> <!-- Sch=JC10 -->
|
||||
|
||||
<pin index="32" name="JD1" iostandard="LVCMOS33" loc="E15"/> <!-- Sch=JD1 -->
|
||||
<pin index="33" name="JD2" iostandard="LVCMOS33" loc="A14"/> <!-- Sch=JD2 -->
|
||||
<pin index="34" name="JD3" iostandard="LVCMOS33" loc="B15"/> <!-- Sch=JD3 -->
|
||||
<pin index="35" name="JD4" iostandard="LVCMOS33" loc="F15"/> <!-- Sch=JD4 -->
|
||||
<pin index="36" name="JD7" iostandard="LVCMOS33" loc="E14"/> <!-- Sch=JD7 -->
|
||||
<pin index="37" name="JD8" iostandard="LVCMOS33" loc="B14"/> <!-- Sch=JD8 -->
|
||||
<pin index="38" name="JD9" iostandard="LVCMOS33" loc="D15"/> <!-- Sch=JD9 -->
|
||||
<pin index="39" name="JD10" iostandard="LVCMOS33" loc="A15"/> <!-- Sch=JD10 -->
|
||||
</pins>
|
||||
</part_info>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,164 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7k325tffg900-2">
|
||||
<pins>
|
||||
<pin index="0" name ="aud_scl_i" iostandard="LVCMOS18" loc="AE19"/>
|
||||
<pin index="1" name ="aud_sda_i" iostandard="LVCMOS18" loc="AF18"/>
|
||||
<pin index="2" name ="clk_n" iostandard="LVDS" loc="AD11"/>
|
||||
<pin index="3" name ="clk_p" iostandard="LVDS" loc="AD12"/>
|
||||
<pin index="4" name ="dip_switches_8bits_tri_i_0" iostandard="LVCMOS12" loc="G19"/>
|
||||
<pin index="5" name ="dip_switches_8bits_tri_i_1" iostandard="LVCMOS12" loc="G25"/>
|
||||
<pin index="6" name ="dip_switches_8bits_tri_i_2" iostandard="LVCMOS12" loc="H24"/>
|
||||
<pin index="7" name ="dip_switches_8bits_tri_i_3" iostandard="LVCMOS12" loc="K19"/>
|
||||
<pin index="8" name ="dip_switches_8bits_tri_i_4" iostandard="LVCMOS12" loc="N19"/>
|
||||
<pin index="9" name ="dip_switches_8bits_tri_i_5" iostandard="LVCMOS12" loc="P19"/>
|
||||
<pin index="10" name ="dip_switches_8bits_tri_i_6" iostandard="LVCMOS33" loc="P26"/>
|
||||
<pin index="11" name ="dip_switches_8bits_tri_i_7" iostandard="LVCMOS33" loc="P27"/>
|
||||
<pin index="12" name ="hdmi_rx_hpd" iostandard="LVCMOS33" loc="AH29"/>
|
||||
<pin index="13" name ="TMDS_IN_clk_p" iostandard="TMDS_33" loc="AE28"/>
|
||||
<pin index="14" name ="TMDS_IN_clk_n" iostandard="TMDS_33" loc="AF28"/>
|
||||
<pin index="15" name ="TMDS_IN_data_p_0" iostandard="TMDS_33" loc="AJ26"/>
|
||||
<pin index="16" name ="TMDS_IN_data_p_1" iostandard="TMDS_33" loc="AG27"/>
|
||||
<pin index="17" name ="TMDS_IN_data_p_2" iostandard="TMDS_33" loc="AH26"/>
|
||||
<pin index="18" name ="TMDS_IN_data_n_0" iostandard="TMDS_33" loc="AK26"/>
|
||||
<pin index="19" name ="TMDS_IN_data_n_1" iostandard="TMDS_33" loc="AG28"/>
|
||||
<pin index="20" name ="TMDS_IN_data_n_2" iostandard="TMDS_33" loc="AH27"/>
|
||||
<pin index="21" name ="hdmi_tx_hpd" iostandard="LVCMOS18" loc="AG29"/>
|
||||
<pin index="22" name ="eth_mdc" iostandard="LVCMOS15" loc="AF12"/>
|
||||
<pin index="23" name ="eth_mdio_i" iostandard="LVCMOS15" loc="AG12"/>
|
||||
<pin index="24" name ="eth_rgmii_rd_0" iostandard="LVCMOS15" loc="AJ14"/>
|
||||
<pin index="25" name ="eth_rgmii_rd_1" iostandard="LVCMOS15" loc="AH14"/>
|
||||
<pin index="26" name ="eth_rgmii_rd_2" iostandard="LVCMOS15" loc="AK13"/>
|
||||
<pin index="27" name ="eth_rgmii_rd_3" iostandard="LVCMOS15" loc="AJ13"/>
|
||||
<pin index="28" name ="eth_rgmii_rxc" iostandard="LVCMOS15" loc="AG10"/>
|
||||
<pin index="29" name ="eth_rgmii_rx_ctl" iostandard="LVCMOS15" loc="AH11"/>
|
||||
<pin index="30" name ="eth_rgmii_td_0" iostandard="LVCMOS15" loc="AJ12"/>
|
||||
<pin index="31" name ="eth_rgmii_td_1" iostandard="LVCMOS15" loc="AK11"/>
|
||||
<pin index="32" name ="eth_rgmii_td_2" iostandard="LVCMOS15" loc="AJ11"/>
|
||||
<pin index="33" name ="eth_rgmii_td_3" iostandard="LVCMOS15" loc="AK10"/>
|
||||
<pin index="34" name ="eth_rgmii_txc" iostandard="LVCMOS15" loc="AE10"/>
|
||||
<pin index="35" name ="eth_rgmii_tx_ctl" iostandard="LVCMOS15" loc="AK14"/>
|
||||
<pin index="36" name ="led_8bits_tri_o_0" iostandard="LVCMOS33" loc="T28"/>
|
||||
<pin index="37" name ="led_8bits_tri_o_1" iostandard="LVCMOS33" loc="V19"/>
|
||||
<pin index="38" name ="led_8bits_tri_o_2" iostandard="LVCMOS33" loc="U30"/>
|
||||
<pin index="39" name ="led_8bits_tri_o_3" iostandard="LVCMOS33" loc="U29"/>
|
||||
<pin index="40" name ="led_8bits_tri_o_4" iostandard="LVCMOS33" loc="V20"/>
|
||||
<pin index="41" name ="led_8bits_tri_o_5" iostandard="LVCMOS33" loc="V26"/>
|
||||
<pin index="42" name ="led_8bits_tri_o_6" iostandard="LVCMOS33" loc="W24"/>
|
||||
<pin index="43" name ="led_8bits_tri_o_7" iostandard="LVCMOS33" loc="W23"/>
|
||||
<pin index="44" name ="miso_i" iostandard="LVCMOS33" loc="W28"/>
|
||||
<pin index="45" name ="mosi_i" iostandard="LVCMOS33" loc="W27"/>
|
||||
<pin index="46" name ="otg_clk_m" iostandard="LVCMOS18" loc="AD18"/>
|
||||
<pin index="47" name ="otg_data_i_0" iostandard="LVCMOS18" loc="AE14"/>
|
||||
<pin index="48" name ="otg_data_i_1" iostandard="LVCMOS18" loc="AE15"/>
|
||||
<pin index="49" name ="otg_data_i_2" iostandard="LVCMOS18" loc="AC15"/>
|
||||
<pin index="50" name ="otg_data_i_3" iostandard="LVCMOS18" loc="AC16"/>
|
||||
<pin index="51" name ="otg_data_i_4" iostandard="LVCMOS18" loc="AB15"/>
|
||||
<pin index="52" name ="otg_data_i_5" iostandard="LVCMOS18" loc="AA15"/>
|
||||
<pin index="53" name ="otg_data_i_6" iostandard="LVCMOS18" loc="AD14"/>
|
||||
<pin index="54" name ="otg_data_i_7" iostandard="LVCMOS18" loc="AC14"/>
|
||||
<pin index="55" name ="otg_dir_m" iostandard="LVCMOS18" loc="Y16"/>
|
||||
<pin index="56" name ="otg_next_m" iostandard="LVCMOS18" loc="AA16"/>
|
||||
<pin index="57" name ="otg_rst_m" iostandard="LVCMOS18" loc="AB14"/>
|
||||
<pin index="58" name ="otg_stop_m" iostandard="LVCMOS18" loc="AA17"/>
|
||||
<pin index="59" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS12" loc="E18"/>
|
||||
<pin index="60" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS12" loc="B19"/>
|
||||
<pin index="61" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS12" loc="M20"/>
|
||||
<pin index="62" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS12" loc="C19"/>
|
||||
<pin index="63" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS12" loc="M19"/>
|
||||
<pin index="64" name ="qspi_csn_i" iostandard="LVCMOS33" loc="U19"/>
|
||||
<pin index="65" name ="qspi_db0_i" iostandard="LVCMOS33" loc="P24"/>
|
||||
<pin index="66" name ="qspi_db1_i" iostandard="LVCMOS33" loc="R25"/>
|
||||
<pin index="67" name ="qspi_db2_i" iostandard="LVCMOS33" loc="R20"/>
|
||||
<pin index="68" name ="qspi_db3_i" iostandard="LVCMOS33" loc="R21"/>
|
||||
<pin index="69" name ="reset" iostandard="LVCMOS33" loc="R19"/>
|
||||
<pin index="70" name ="sclk_i" iostandard="LVCMOS33" loc="AD27"/>
|
||||
<pin index="71" name ="scl_i" iostandard="LVCMOS33" loc="AE30"/>
|
||||
<pin index="72" name ="sda_i" iostandard="LVCMOS33" loc="AF30"/>
|
||||
<pin index="73" name ="sd_miso_i" iostandard="LVCMOS33" loc="R26"/>
|
||||
<pin index="74" name ="sd_mosi_i" iostandard="LVCMOS33" loc="R29"/>
|
||||
<pin index="75" name ="sd_sclk_i" iostandard="LVCMOS33" loc="R28"/>
|
||||
<pin index="76" name ="sd_ss_i" iostandard="LVCMOS33" loc="T30"/>
|
||||
<pin index="77" name ="ss_i" iostandard="LVCMOS33" loc="W29"/>
|
||||
<pin index="78" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="Y20"/>
|
||||
<pin index="79" name ="usb_uart_txd" iostandard="LVCMOS33" loc="Y23"/>
|
||||
<pin index="80" name ="phy_reset_n" iostandard="LVCMOS33" loc="AH24"/>
|
||||
<pin index="81" name ="TMDS_OUT_clk_p" iostandard="LVCMOS33" loc="AA20"/>
|
||||
<pin index="82" name ="TMDS_OUT_clk_n" iostandard="LVCMOS33" loc="AB20"/>
|
||||
<pin index="83" name ="TMDS_OUT_data_p_0" iostandard="LVCMOS33" loc="AC20"/>
|
||||
<pin index="84" name ="TMDS_OUT_data_p_1" iostandard="LVCMOS33" loc="AA22"/>
|
||||
<pin index="85" name ="TMDS_OUT_data_p_2" iostandard="LVCMOS33" loc="AB24"/>
|
||||
<pin index="86" name ="TMDS_OUT_data_n_0" iostandard="LVCMOS33" loc="AC21"/>
|
||||
<pin index="87" name ="TMDS_OUT_data_n_1" iostandard="LVCMOS33" loc="AA23"/>
|
||||
<pin index="88" name ="TMDS_OUT_data_n_2" iostandard="LVCMOS33" loc="AC25"/>
|
||||
<pin index="89" name ="hdmi_in_ddc_scl" iostandard="LVCMOS33" loc="AJ28"/>
|
||||
<pin index="90" name ="hdmi_in_ddc_sda" iostandard="LVCMOS33" loc="AJ29"/>
|
||||
<pin index="91" name ="JC1" iostandard="LVCMOS33" loc="AC26"/>
|
||||
<pin index="92" name ="JC2" iostandard="LVCMOS33" loc="AJ27"/>
|
||||
<pin index="93" name ="JC3" iostandard="LVCMOS33" loc="AH30"/>
|
||||
<pin index="94" name ="JC4" iostandard="LVCMOS33" loc="AK29"/>
|
||||
<pin index="95" name ="JC7" iostandard="LVCMOS33" loc="AD26"/>
|
||||
<pin index="96" name ="JC8" iostandard="LVCMOS33" loc="AG30"/>
|
||||
<pin index="97" name ="JC9" iostandard="LVCMOS33" loc="AK30"/>
|
||||
<pin index="98" name ="JC10" iostandard="LVCMOS33" loc="AK28"/>
|
||||
<pin index="99" name ="JD1" iostandard="LVCMOS33" loc="V27"/>
|
||||
<pin index="100" name ="JD2" iostandard="LVCMOS33" loc="Y30"/>
|
||||
<pin index="101" name ="JD3" iostandard="LVCMOS33" loc="V24"/>
|
||||
<pin index="102" name ="JD4" iostandard="LVCMOS33" loc="W22"/>
|
||||
<pin index="103" name ="JD7" iostandard="LVCMOS33" loc="U24"/>
|
||||
<pin index="104" name ="JD8" iostandard="LVCMOS33" loc="Y26"/>
|
||||
<pin index="105" name ="JD9" iostandard="LVCMOS33" loc="V22"/>
|
||||
<pin index="106" name ="JD10" iostandard="LVCMOS33" loc="W21"/>
|
||||
<pin index="107" name ="JB1" iostandard="LVCMOS33" loc="V29"/>
|
||||
<pin index="108" name ="JB2" iostandard="LVCMOS33" loc="V30"/>
|
||||
<pin index="109" name ="JB3" iostandard="LVCMOS33" loc="V25"/>
|
||||
<pin index="110" name ="JB4" iostandard="LVCMOS33" loc="W26"/>
|
||||
<pin index="111" name ="JB7" iostandard="LVCMOS33" loc="T25"/>
|
||||
<pin index="112" name ="JB8" iostandard="LVCMOS33" loc="U25"/>
|
||||
<pin index="113" name ="JB9" iostandard="LVCMOS33" loc="U22"/>
|
||||
<pin index="114" name ="JB10" iostandard="LVCMOS33" loc="U23"/>
|
||||
<pin index="115" name ="JA1" iostandard="LVCMOS33" loc="U27"/>
|
||||
<pin index="116" name ="JA2" iostandard="LVCMOS33" loc="U28"/>
|
||||
<pin index="117" name ="JA3" iostandard="LVCMOS33" loc="T26"/>
|
||||
<pin index="118" name ="JA4" iostandard="LVCMOS33" loc="T27"/>
|
||||
<pin index="119" name ="JA7" iostandard="LVCMOS33" loc="T22"/>
|
||||
<pin index="120" name ="JA8" iostandard="LVCMOS33" loc="T23"/>
|
||||
<pin index="121" name ="JA9" iostandard="LVCMOS33" loc="T20"/>
|
||||
<pin index="122" name ="JA10" iostandard="LVCMOS33" loc="T21"/>
|
||||
<pin index="123" name ="OLED2" iostandard="LVCMOS18" loc="Y15"/>
|
||||
<pin index="124" name ="OLED4" iostandard="LVCMOS18" loc="AF17"/>
|
||||
<pin index="125" name ="OLED7" iostandard="LVCMOS18" loc="AC17"/>
|
||||
<pin index="126" name ="OLED8" iostandard="LVCMOS18" loc="AB17"/>
|
||||
<pin index="127" name ="OLED9" iostandard="LVCMOS33" loc="AB22"/>
|
||||
<pin index="128" name ="OLED10" iostandard="LVCMOS18" loc="AG17"/>
|
||||
<pin index="129" name ="SD1" iostandard="LVCMOS33" loc="T30"/>
|
||||
<pin index="130" name ="SD2" iostandard="LVCMOS33" loc="R29"/>
|
||||
<pin index="131" name ="SD3" iostandard="LVCMOS33" loc="R26"/>
|
||||
<pin index="132" name ="SD4" iostandard="LVCMOS33" loc="R28"/>
|
||||
<pin index="133" name ="SD7" iostandard="LVCMOS33" loc="R30"/>
|
||||
<pin index="134" name ="SD8" iostandard="LVCMOS33" loc="P29"/>
|
||||
<pin index="135" name ="SD9" iostandard="LVCMOS33" loc="P28"/>
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,337 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr3_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="oled_preset">
|
||||
<ip vendor="digilentinc.com" library="ip" name="pmod_bridge" ip_interface="Pmod_out">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Top_Row_Interface" value="SPI"/>
|
||||
<user_parameter name="CONFIG.Bottom_Row_Interface" value="GPIO"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="1"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="output_1bit_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_8bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_5bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="led_8bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="mii_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_ethernet" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PHY_TYPE" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="tri_mode_ethernet_mac" ip_interface="mii">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.Physical_Interface" value="MII"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="sys_diff_clock_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN1_D">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.PRIM_IN_FREQ" value="200"/>
|
||||
<user_parameter name="CONFIG.PRIM_SOURCE" value="Differential_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="clk_wiz" ip_interface="CLK_IN2_D">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_INCLK_SWITCHOVER" value="true"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_IN_FREQ" value="200"/>
|
||||
<user_parameter name="CONFIG.SECONDARY_SOURCE" value="Differential_clock_capable_pin"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="hdmi_in_preset">
|
||||
<ip vendor="digilentinc.com" library="ip" name="dvi2rgb">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.kRstActiveHigh" value="false"/>
|
||||
<user_parameter name="CONFIG.kClkRange" value="2"/>
|
||||
<user_parameter name="CONFIG.kAddBUFG" value="false"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,162 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<part_info part_name="xc7a100tcsg324-1">
|
||||
<pins>
|
||||
<pin index="0" name ="acl_miso_i" iostandard="LVCMOS33" loc="E15"/>
|
||||
<pin index="1" name ="acl_mosi_i" iostandard="LVCMOS33" loc="F14"/>
|
||||
<pin index="2" name ="acl_sclk_i" iostandard="LVCMOS33" loc="F15"/>
|
||||
<pin index="3" name ="acl_ss_i" iostandard="LVCMOS33" loc="D15"/>
|
||||
<pin index="4" name ="clk" iostandard="LVCMOS33" loc="E3"/>
|
||||
<pin index="5" name ="dip_switches_16bits_tri_i_0" iostandard="LVCMOS33" loc="J15"/>
|
||||
<pin index="6" name ="dip_switches_16bits_tri_i_1" iostandard="LVCMOS33" loc="L16"/>
|
||||
<pin index="7" name ="dip_switches_16bits_tri_i_2" iostandard="LVCMOS33" loc="M13"/>
|
||||
<pin index="8" name ="dip_switches_16bits_tri_i_3" iostandard="LVCMOS33" loc="R15"/>
|
||||
<pin index="9" name ="dip_switches_16bits_tri_i_4" iostandard="LVCMOS33" loc="R17"/>
|
||||
<pin index="10" name ="dip_switches_16bits_tri_i_5" iostandard="LVCMOS33" loc="T18"/>
|
||||
<pin index="11" name ="dip_switches_16bits_tri_i_6" iostandard="LVCMOS33" loc="U18"/>
|
||||
<pin index="12" name ="dip_switches_16bits_tri_i_7" iostandard="LVCMOS33" loc="R13"/>
|
||||
<pin index="13" name ="dip_switches_16bits_tri_i_8" iostandard="LVCMOS18" loc="T8"/>
|
||||
<pin index="14" name ="dip_switches_16bits_tri_i_9" iostandard="LVCMOS18" loc="U8"/>
|
||||
<pin index="15" name ="dip_switches_16bits_tri_i_10" iostandard="LVCMOS33" loc="R16"/>
|
||||
<pin index="16" name ="dip_switches_16bits_tri_i_11" iostandard="LVCMOS33" loc="T13"/>
|
||||
<pin index="17" name ="dip_switches_16bits_tri_i_12" iostandard="LVCMOS33" loc="H6"/>
|
||||
<pin index="18" name ="dip_switches_16bits_tri_i_13" iostandard="LVCMOS33" loc="U12"/>
|
||||
<pin index="19" name ="dip_switches_16bits_tri_i_14" iostandard="LVCMOS33" loc="U11"/>
|
||||
<pin index="20" name ="dip_switches_16bits_tri_i_15" iostandard="LVCMOS33" loc="V10"/>
|
||||
<pin index="21" name ="dual_seven_seg_led_disp_tri_o_0" iostandard="LVCMOS33" loc="T10"/>
|
||||
<pin index="22" name ="dual_seven_seg_led_disp_tri_o_1" iostandard="LVCMOS33" loc="R10"/>
|
||||
<pin index="23" name ="dual_seven_seg_led_disp_tri_o_2" iostandard="LVCMOS33" loc="K16"/>
|
||||
<pin index="24" name ="dual_seven_seg_led_disp_tri_o_3" iostandard="LVCMOS33" loc="K13"/>
|
||||
<pin index="25" name ="dual_seven_seg_led_disp_tri_o_4" iostandard="LVCMOS33" loc="P15"/>
|
||||
<pin index="26" name ="dual_seven_seg_led_disp_tri_o_5" iostandard="LVCMOS33" loc="T11"/>
|
||||
<pin index="27" name ="dual_seven_seg_led_disp_tri_o_6" iostandard="LVCMOS33" loc="L18"/>
|
||||
<pin index="28" name ="dual_seven_seg_led_disp_tri_o_7" iostandard="LVCMOS33" loc="H15"/>
|
||||
<pin index="29" name ="eth_mdc" iostandard="LVCMOS33" loc="C9"/>
|
||||
<pin index="30" name ="eth_mdio_i" iostandard="LVCMOS33" loc="A9"/>
|
||||
<pin index="31" name ="eth_rmii_crs_dv" iostandard="LVCMOS33" loc="D9"/>
|
||||
<pin index="32" name ="eth_rmii_rxd_0" iostandard="LVCMOS33" loc="C11"/>
|
||||
<pin index="33" name ="eth_rmii_rxd_1" iostandard="LVCMOS33" loc="D10"/>
|
||||
<pin index="34" name ="eth_rmii_rx_er" iostandard="LVCMOS33" loc="C10"/>
|
||||
<pin index="35" name ="eth_rmii_txd_0" iostandard="LVCMOS33" loc="A10"/>
|
||||
<pin index="36" name ="eth_rmii_txd_1" iostandard="LVCMOS33" loc="A8"/>
|
||||
<pin index="37" name ="eth_rmii_tx_en" iostandard="LVCMOS33" loc="B9"/>
|
||||
<pin index="38" name ="led_16bits_tri_o_0" iostandard="LVCMOS33" loc="H17"/>
|
||||
<pin index="39" name ="led_16bits_tri_o_1" iostandard="LVCMOS33" loc="K15"/>
|
||||
<pin index="40" name ="led_16bits_tri_o_2" iostandard="LVCMOS33" loc="J13"/>
|
||||
<pin index="41" name ="led_16bits_tri_o_3" iostandard="LVCMOS33" loc="N14"/>
|
||||
<pin index="42" name ="led_16bits_tri_o_4" iostandard="LVCMOS33" loc="R18"/>
|
||||
<pin index="43" name ="led_16bits_tri_o_5" iostandard="LVCMOS33" loc="V17"/>
|
||||
<pin index="44" name ="led_16bits_tri_o_6" iostandard="LVCMOS33" loc="U17"/>
|
||||
<pin index="45" name ="led_16bits_tri_o_7" iostandard="LVCMOS33" loc="U16"/>
|
||||
<pin index="46" name ="led_16bits_tri_o_8" iostandard="LVCMOS33" loc="V16"/>
|
||||
<pin index="47" name ="led_16bits_tri_o_9" iostandard="LVCMOS33" loc="T15"/>
|
||||
<pin index="48" name ="led_16bits_tri_o_10" iostandard="LVCMOS33" loc="U14"/>
|
||||
<pin index="49" name ="led_16bits_tri_o_11" iostandard="LVCMOS33" loc="T16"/>
|
||||
<pin index="50" name ="led_16bits_tri_o_12" iostandard="LVCMOS33" loc="V15"/>
|
||||
<pin index="51" name ="led_16bits_tri_o_13" iostandard="LVCMOS33" loc="V14"/>
|
||||
<pin index="52" name ="led_16bits_tri_o_14" iostandard="LVCMOS33" loc="V12"/>
|
||||
<pin index="53" name ="led_16bits_tri_o_15" iostandard="LVCMOS33" loc="V11"/>
|
||||
<pin index="54" name ="push_buttons_5bits_tri_i_0" iostandard="LVCMOS33" loc="N17"/>
|
||||
<pin index="55" name ="push_buttons_5bits_tri_i_1" iostandard="LVCMOS33" loc="M18"/>
|
||||
<pin index="56" name ="push_buttons_5bits_tri_i_2" iostandard="LVCMOS33" loc="P17"/>
|
||||
<pin index="57" name ="push_buttons_5bits_tri_i_3" iostandard="LVCMOS33" loc="M17"/>
|
||||
<pin index="58" name ="push_buttons_5bits_tri_i_4" iostandard="LVCMOS33" loc="P18"/>
|
||||
<pin index="59" name ="qspi_csn_i" iostandard="LVCMOS33" loc="L13"/>
|
||||
<pin index="60" name ="qspi_db0_i" iostandard="LVCMOS33" loc="K17"/>
|
||||
<pin index="61" name ="qspi_db1_i" iostandard="LVCMOS33" loc="K18"/>
|
||||
<pin index="62" name ="qspi_db2_i" iostandard="LVCMOS33" loc="L14"/>
|
||||
<pin index="63" name ="qspi_db3_i" iostandard="LVCMOS33" loc="M14"/>
|
||||
<pin index="64" name ="reset" iostandard="LVCMOS33" loc="C12"/>
|
||||
<pin index="65" name ="rgb_led_tri_o_0" iostandard="LVCMOS33" loc="N15"/>
|
||||
<pin index="66" name ="rgb_led_tri_o_1" iostandard="LVCMOS33" loc="M16"/>
|
||||
<pin index="67" name ="rgb_led_tri_o_2" iostandard="LVCMOS33" loc="R12"/>
|
||||
<pin index="68" name ="rgb_led_tri_o_3" iostandard="LVCMOS33" loc="N16"/>
|
||||
<pin index="69" name ="rgb_led_tri_o_4" iostandard="LVCMOS33" loc="R11"/>
|
||||
<pin index="70" name ="rgb_led_tri_o_5" iostandard="LVCMOS33" loc="G14"/>
|
||||
<pin index="71" name ="seven_seg_led_an_tri_o_0" iostandard="LVCMOS33" loc="J17"/>
|
||||
<pin index="72" name ="seven_seg_led_an_tri_o_1" iostandard="LVCMOS33" loc="J18"/>
|
||||
<pin index="73" name ="seven_seg_led_an_tri_o_2" iostandard="LVCMOS33" loc="T9"/>
|
||||
<pin index="74" name ="seven_seg_led_an_tri_o_3" iostandard="LVCMOS33" loc="J14"/>
|
||||
<pin index="75" name ="seven_seg_led_an_tri_o_4" iostandard="LVCMOS33" loc="P14"/>
|
||||
<pin index="76" name ="seven_seg_led_an_tri_o_5" iostandard="LVCMOS33" loc="T14"/>
|
||||
<pin index="77" name ="seven_seg_led_an_tri_o_6" iostandard="LVCMOS33" loc="K2"/>
|
||||
<pin index="78" name ="seven_seg_led_an_tri_o_7" iostandard="LVCMOS33" loc="U13"/>
|
||||
<pin index="79" name ="temp_scl_i" iostandard="LVCMOS33" loc="C14"/>
|
||||
<pin index="80" name ="temp_sda_i" iostandard="LVCMOS33" loc="C15"/>
|
||||
<pin index="81" name ="usb_uart_rxd" iostandard="LVCMOS33" loc="C4"/>
|
||||
<pin index="82" name ="usb_uart_txd" iostandard="LVCMOS33" loc="D4"/>
|
||||
<pin index="83" name ="JA1" iostandard="LVCMOS33" loc="C17"/>
|
||||
<pin index="84" name ="JA2" iostandard="LVCMOS33" loc="D18"/>
|
||||
<pin index="85" name ="JA3" iostandard="LVCMOS33" loc="E18"/>
|
||||
<pin index="86" name ="JA4" iostandard="LVCMOS33" loc="G17"/>
|
||||
<pin index="87" name ="JA7" iostandard="LVCMOS33" loc="D17"/>
|
||||
<pin index="88" name ="JA8" iostandard="LVCMOS33" loc="E17"/>
|
||||
<pin index="89" name ="JA9" iostandard="LVCMOS33" loc="F18"/>
|
||||
<pin index="90" name ="JA10" iostandard="LVCMOS33" loc="G18"/>
|
||||
<pin index="91" name ="JB1" iostandard="LVCMOS33" loc="D14"/>
|
||||
<pin index="92" name ="JB2" iostandard="LVCMOS33" loc="F16"/>
|
||||
<pin index="93" name ="JB3" iostandard="LVCMOS33" loc="G16"/>
|
||||
<pin index="94" name ="JB4" iostandard="LVCMOS33" loc="H14"/>
|
||||
<pin index="95" name ="JB7" iostandard="LVCMOS33" loc="E16"/>
|
||||
<pin index="96" name ="JB8" iostandard="LVCMOS33" loc="F13"/>
|
||||
<pin index="97" name ="JB9" iostandard="LVCMOS33" loc="G13"/>
|
||||
<pin index="98" name ="JB10" iostandard="LVCMOS33" loc="H16"/>
|
||||
<pin index="99" name ="JC1" iostandard="LVCMOS33" loc="K1"/>
|
||||
<pin index="100" name ="JC2" iostandard="LVCMOS33" loc="F6"/>
|
||||
<pin index="101" name ="JC3" iostandard="LVCMOS33" loc="J2"/>
|
||||
<pin index="102" name ="JC4" iostandard="LVCMOS33" loc="G6"/>
|
||||
<pin index="103" name ="JC7" iostandard="LVCMOS33" loc="E7"/>
|
||||
<pin index="104" name ="JC8" iostandard="LVCMOS33" loc="J3"/>
|
||||
<pin index="105" name ="JC9" iostandard="LVCMOS33" loc="J4"/>
|
||||
<pin index="106" name ="JC10" iostandard="LVCMOS33" loc="E6"/>
|
||||
<pin index="107" name ="JD1" iostandard="LVCMOS33" loc="H4"/>
|
||||
<pin index="108" name ="JD2" iostandard="LVCMOS33" loc="H1"/>
|
||||
<pin index="109" name ="JD3" iostandard="LVCMOS33" loc="G1"/>
|
||||
<pin index="110" name ="JD4" iostandard="LVCMOS33" loc="G3"/>
|
||||
<pin index="111" name ="JD7" iostandard="LVCMOS33" loc="H2"/>
|
||||
<pin index="112" name ="JD8" iostandard="LVCMOS33" loc="G4"/>
|
||||
<pin index="113" name ="JD9" iostandard="LVCMOS33" loc="G2"/>
|
||||
<pin index="114" name ="JD10" iostandard="LVCMOS33" loc="F3"/>
|
||||
<pin index="115" name ="JXADC1" iostandard="LVCMOS33" loc="A13"/>
|
||||
<pin index="116" name ="JXADC2" iostandard="LVCMOS33" loc="A15"/>
|
||||
<pin index="117" name ="JXADC3" iostandard="LVCMOS33" loc="B16"/>
|
||||
<pin index="118" name ="JXADC4" iostandard="LVCMOS33" loc="B18"/>
|
||||
<pin index="119" name ="JXADC7" iostandard="LVCMOS33" loc="A14"/>
|
||||
<pin index="120" name ="JXADC8" iostandard="LVCMOS33" loc="A16"/>
|
||||
<pin index="121" name ="JXADC9" iostandard="LVCMOS33" loc="B17"/>
|
||||
<pin index="122" name ="JXADC10" iostandard="LVCMOS33" loc="A18"/>
|
||||
<pin index="171" name ="SD1" iostandard="LVCMOS33" loc="D2"/>
|
||||
<pin index="172" name ="SD2" iostandard="LVCMOS33" loc="C1"/>
|
||||
<pin index="173" name ="SD3" iostandard="LVCMOS33" loc="C2"/>
|
||||
<pin index="174" name ="SD4" iostandard="LVCMOS33" loc="B1"/>
|
||||
<pin index="175" name ="SD7" iostandard="LVCMOS33" loc="E1"/>
|
||||
<pin index="176" name ="SD8" iostandard="LVCMOS33" loc="F1"/>
|
||||
<pin index="177" name ="SD9" iostandard="LVCMOS33" loc="A1"/>
|
||||
<pin index="178" name ="SD10" iostandard="LVCMOS33" loc="E2"/>
|
||||
<pin index="179" name ="usb_uart_rts" iostandard="LVCMOS33" loc="E5"/>
|
||||
<pin index="180" name ="usb_uart_cts" iostandard="LVCMOS33" loc="D3"/>
|
||||
|
||||
</pins>
|
||||
</part_info>
|
||||
@ -0,0 +1,398 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<!--
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2021 Digilent, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
-->
|
||||
<ip_presets schema="1.0">
|
||||
<ip_preset preset_proc_name="ddr2_sdram_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="mig_7series">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.XML_INPUT_FILE" value="mig.prj" value_type="file"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="qspi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MEMORY" value="2"/>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="2"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="2"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="spi_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_quad_spi">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_SPI_MODE" value="0"/>
|
||||
<user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP" value="0"/>
|
||||
<user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
<ip_preset preset_proc_name="dip_switches_16bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="push_buttons_5bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="5"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="5"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="0"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="5"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_8bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="8"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="8"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_6bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="6"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="6"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="output_16bits_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_GPIO_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="axi_gpio" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_IS_DUAL" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPIO2_WIDTH" value="16"/>
|
||||
<user_parameter name="CONFIG.C_ALL_INPUTS_2" value="0"/>
|
||||
<user_parameter name="CONFIG.C_ALL_OUTPUTS_2" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI3_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.C_GPI4_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO1">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI1" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO2">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI2" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO3">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI3" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI1_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="GPIO4">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_GPI4" value="1"/>
|
||||
<user_parameter name="CONFIG.GPI2_SIZE" value="16"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
|
||||
<ip_preset preset_proc_name="uart_preset">
|
||||
<ip vendor="xilinx.com" library="ip" name="iomodule" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.C_USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.C_USE_UART_TX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
<ip vendor="xilinx.com" library="ip" name="microblaze_mcs" ip_interface="UART">
|
||||
<user_parameters>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
<user_parameter name="CONFIG.USE_UART_RX" value="1"/>
|
||||
</user_parameters>
|
||||
</ip>
|
||||
</ip_preset>
|
||||
</ip_presets>
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user