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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
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| version:1 | version:1 | ||||
| 57656254616c6b5472616e736d697373696f6e417474656d70746564:13 | 57656254616c6b5472616e736d697373696f6e417474656d70746564:13 | ||||
| 6d6f64655f636f756e7465727c4755494d6f6465:31 | |||||
| 6d6f64655f636f756e7465727c4755494d6f6465:40 | |||||
| eof: | eof: |
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/synthesis.wdf
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| 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 | ||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_104.xml
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| <?xml version="1.0"?> | |||||
| <Runs Version="1" Minor="0"> | |||||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||||
| <Parameters> | |||||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||||
| </Parameters> | |||||
| </Runs> | |||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_105.xml
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| <?xml version="1.0"?> | |||||
| <Runs Version="1" Minor="0"> | |||||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||||
| <Parameters> | |||||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||||
| </Parameters> | |||||
| </Runs> | |||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_106.xml
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| <?xml version="1.0"?> | |||||
| <Runs Version="1" Minor="0"> | |||||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||||
| <Parameters> | |||||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||||
| </Parameters> | |||||
| </Runs> | |||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_107.xml
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| <?xml version="1.0"?> | |||||
| <Runs Version="1" Minor="0"> | |||||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||||
| <Parameters> | |||||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||||
| </Parameters> | |||||
| </Runs> | |||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_108.xml
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| <?xml version="1.0"?> | |||||
| <Runs Version="1" Minor="0"> | |||||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||||
| <Parameters> | |||||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||||
| </Parameters> | |||||
| </Runs> | |||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/.jobs/vrs_config_109.xml
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| <?xml version="1.0"?> | |||||
| <Runs Version="1" Minor="0"> | |||||
| <Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> | |||||
| <Parameters> | |||||
| <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> | |||||
| <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> | |||||
| </Parameters> | |||||
| </Runs> | |||||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/.vivado.begin.rst
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| <?xml version="1.0"?> | <?xml version="1.0"?> | ||||
| <ProcessHandle Version="1" Minor="0"> | <ProcessHandle Version="1" Minor="0"> | ||||
| <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="25900" HostCore="12" HostMemory="016927088640"> | |||||
| <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="18920" HostCore="12" HostMemory="016927088640"> | |||||
| </Process> | </Process> | ||||
| </ProcessHandle> | </ProcessHandle> |
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml
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| <?xml version="1.0" encoding="UTF-8"?> | <?xml version="1.0" encoding="UTF-8"?> | ||||
| <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1653339519" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp"> | |||||
| <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1654026672" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp"> | |||||
| <File Type="PA-TCL" Name="regler.tcl"/> | <File Type="PA-TCL" Name="regler.tcl"/> | ||||
| <File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/> | <File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/> | ||||
| <File Type="REPORTS-TCL" Name="regler_reports.tcl"/> | <File Type="REPORTS-TCL" Name="regler_reports.tcl"/> | ||||
| <Attr Name="UsedIn" Val="simulation"/> | <Attr Name="UsedIn" Val="simulation"/> | ||||
| </FileInfo> | </FileInfo> | ||||
| </File> | </File> | ||||
| <File Path="$PSRCDIR/sources_1/new/autoTuning.vhd"> | |||||
| <FileInfo> | |||||
| <Attr Name="AutoDisabled" Val="1"/> | |||||
| <Attr Name="UsedIn" Val="synthesis"/> | |||||
| <Attr Name="UsedIn" Val="simulation"/> | |||||
| </FileInfo> | |||||
| </File> | |||||
| <Config> | <Config> | ||||
| <Option Name="DesignMode" Val="RTL"/> | <Option Name="DesignMode" Val="RTL"/> | ||||
| <Option Name="TopModule" Val="regler"/> | <Option Name="TopModule" Val="regler"/> |
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/project.wdf
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| version:1 | version:1 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 | |||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 | |||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313630:00:00 | |||||
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| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 | ||||
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| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 | ||||
| 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 | ||||
| 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3035343861623234333065633433623139386531656634383534326531333964:506172656e742050412070726f6a656374204944:00 | ||||
| eof:186662213 | |||||
| eof:1339287396 |
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds
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| # Vivado v2021.2 (64-bit) | # Vivado v2021.2 (64-bit) | ||||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | ||||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | ||||
| # Start of session at: Mon May 23 22:58:42 2022 | |||||
| # Process ID: 23388 | |||||
| # Start of session at: Tue May 31 21:51:15 2022 | |||||
| # Process ID: 7140 | |||||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | ||||
| # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl | # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl | ||||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds | # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds | ||||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | ||||
| #----------------------------------------------------------- | #----------------------------------------------------------- | ||||
| source regler.tcl -notrace | source regler.tcl -notrace | ||||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 8.066 | |||||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859 | |||||
| Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp | Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp | ||||
| INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis | INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis | ||||
| INFO: [Vivado 12-7989] Please ensure there are no constraint changes | INFO: [Vivado 12-7989] Please ensure there are no constraint changes | ||||
| INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | ||||
| INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. | INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. | ||||
| INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes | INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes | ||||
| INFO: [Synth 8-7075] Helper process launched with PID 25492 | |||||
| INFO: [Synth 8-7075] Helper process launched with PID 7236 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48] | |||||
| WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:110] | |||||
| WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:121] | |||||
| INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48] | |||||
| INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] | |||||
| WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115] | |||||
| WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:126] | |||||
| INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] | |||||
| WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Handling Custom Attributes | Start Handling Custom Attributes | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| INFO: [Project 1-570] Preparing netlist for logic optimization | INFO: [Project 1-570] Preparing netlist for logic optimization | ||||
| Processing XDC Constraints | Processing XDC Constraints | ||||
| Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | ||||
| Completed Processing XDC Constraints | Completed Processing XDC Constraints | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1273.594 ; gain = 0.000 | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000 | |||||
| INFO: [Project 1-111] Unisim Transformation Summary: | INFO: [Project 1-111] Unisim Transformation Summary: | ||||
| No Unisim elements were transformed. | No Unisim elements were transformed. | ||||
| Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1273.594 ; gain = 0.000 | |||||
| Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000 | |||||
| WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis | WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis | ||||
| INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Loading Part and Timing Information | Start Loading Part and Timing Information | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Loading part: xc7z010clg400-1 | Loading part: xc7z010clg400-1 | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Applying 'set_property' XDC Constraints | Start Applying 'set_property' XDC Constraints | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start RTL Component Statistics | Start RTL Component Statistics | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Detailed RTL Component Info : | Detailed RTL Component Info : | ||||
| +---Adders : | +---Adders : | ||||
| 10 Input 148 Bit Adders := 1 | |||||
| 2 Input 148 Bit Adders := 2 | 2 Input 148 Bit Adders := 2 | ||||
| 3 Input 64 Bit Adders := 1 | 3 Input 64 Bit Adders := 1 | ||||
| 2 Input 64 Bit Adders := 1 | 2 Input 64 Bit Adders := 1 | ||||
| +---Registers : | +---Registers : | ||||
| 64 Bit Registers := 1 | 64 Bit Registers := 1 | ||||
| +---Multipliers : | +---Multipliers : | ||||
| 41x64 Multipliers := 1 | |||||
| 20x64 Multipliers := 1 | |||||
| 10x64 Multipliers := 1 | 10x64 Multipliers := 1 | ||||
| +---Muxes : | +---Muxes : | ||||
| 2 Input 148 Bit Muxes := 2 | |||||
| 2 Input 148 Bit Muxes := 1 | |||||
| 2 Input 64 Bit Muxes := 3 | |||||
| 2 Input 20 Bit Muxes := 2 | 2 Input 20 Bit Muxes := 2 | ||||
| 2 Input 10 Bit Muxes := 1 | 2 Input 10 Bit Muxes := 1 | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Cross Boundary and Area Optimization | Start Cross Boundary and Area Optimization | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| WARNING: [Synth 8-7080] Parallel synthesis criteria is not met | WARNING: [Synth 8-7080] Parallel synthesis criteria is not met | ||||
| DSP Report: Generating DSP I_k5, operation Mode is: (A:0xf4240)*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP u3, operation Mode is: A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: Generating DSP u3, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: Generating DSP u3, operation Mode is: A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: Generating DSP u3, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start ROM, RAM, DSP, Shift Register and Retiming Reporting | Start ROM, RAM, DSP, Shift Register and Retiming Reporting | ||||
| +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | ||||
| |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | | |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | | ||||
| +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | ||||
| |regler | (A:0xf4240)*B | 21 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 24 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 20 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 16 | 13 | - | - | 29 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 18 | 13 | - | - | 46 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | (PCIN>>17)+A*B | 13 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | (PCIN>>17)+A*B | 13 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| Start Applying XDC Timing Constraints | Start Applying XDC Timing Constraints | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1288.984 ; gain = 27.941 | |||||
| Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Timing Optimization | Start Timing Optimization | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1297.449 ; gain = 36.406 | |||||
| Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Technology Mapping | Start Technology Mapping | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1507.957 ; gain = 246.914 | |||||
| Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start IO Insertion | Start IO Insertion | ||||
| Finished Final Netlist Cleanup | Finished Final Netlist Cleanup | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Renaming Generated Instances | Start Renaming Generated Instances | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Rebuilding User Hierarchy | Start Rebuilding User Hierarchy | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Renaming Generated Ports | Start Renaming Generated Ports | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Handling Custom Attributes | Start Handling Custom Attributes | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Renaming Generated Nets | Start Renaming Generated Nets | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Writing Synthesis Report | Start Writing Synthesis Report | ||||
| | |Cell |Count | | | |Cell |Count | | ||||
| +------+--------+------+ | +------+--------+------+ | ||||
| |1 |BUFG | 1| | |1 |BUFG | 1| | ||||
| |2 |CARRY4 | 1613| | |||||
| |3 |DSP48E1 | 13| | |||||
| |4 |LUT1 | 165| | |||||
| |5 |LUT2 | 1000| | |||||
| |6 |LUT3 | 2638| | |||||
| |7 |LUT4 | 2484| | |||||
| |8 |LUT5 | 799| | |||||
| |9 |LUT6 | 3246| | |||||
| |10 |FDRE | 128| | |||||
| |11 |IBUF | 159| | |||||
| |2 |CARRY4 | 2830| | |||||
| |3 |DSP48E1 | 28| | |||||
| |4 |LUT1 | 235| | |||||
| |5 |LUT2 | 665| | |||||
| |6 |LUT3 | 460| | |||||
| |7 |LUT4 | 564| | |||||
| |8 |LUT5 | 9401| | |||||
| |9 |LUT6 | 140| | |||||
| |10 |FDRE | 212| | |||||
| |11 |IBUF | 224| | |||||
| |12 |OBUF | 64| | |12 |OBUF | 64| | ||||
| +------+--------+------+ | +------+--------+------+ | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. | Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. | ||||
| Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 1517.203 ; gain = 243.609 | |||||
| Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137 | |||||
| Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| INFO: [Project 1-571] Translating synthesized netlist | INFO: [Project 1-571] Translating synthesized netlist | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1517.203 ; gain = 0.000 | |||||
| INFO: [Netlist 29-17] Analyzing 1626 Unisim elements for replacement | |||||
| INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000 | |||||
| INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement | |||||
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |||||
| WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. | WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. | ||||
| INFO: [Project 1-570] Preparing netlist for logic optimization | INFO: [Project 1-570] Preparing netlist for logic optimization | ||||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1517.203 ; gain = 0.000 | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000 | |||||
| INFO: [Project 1-111] Unisim Transformation Summary: | INFO: [Project 1-111] Unisim Transformation Summary: | ||||
| No Unisim elements were transformed. | No Unisim elements were transformed. | ||||
| Synth Design complete, checksum: b5ea81b7 | |||||
| Synth Design complete, checksum: 6d8170b6 | |||||
| INFO: [Common 17-83] Releasing license: Synthesis | INFO: [Common 17-83] Releasing license: Synthesis | ||||
| 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. | 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. | ||||
| synth_design completed successfully | synth_design completed successfully | ||||
| synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613 | |||||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. | INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. | ||||
| INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | ||||
| INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:59:52 2022... | |||||
| INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022... |
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.pb
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+ 27
- 27
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler_utilization_synth.rpt
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| Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | ||||
| ------------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------- | ||||
| | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | ||||
| | Date : Mon May 23 22:59:52 2022 | |||||
| | Date : Tue May 31 21:52:26 2022 | |||||
| | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | ||||
| | Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | | Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | ||||
| | Design : regler | | Design : regler | ||||
| 1. Slice Logic | 1. Slice Logic | ||||
| -------------- | -------------- | ||||
| +-------------------------+------+-------+------------+-----------+-------+ | |||||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||||
| +-------------------------+------+-------+------------+-----------+-------+ | |||||
| | Slice LUTs* | 7673 | 0 | 0 | 17600 | 43.60 | | |||||
| | LUT as Logic | 7673 | 0 | 0 | 17600 | 43.60 | | |||||
| | LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | | |||||
| | Slice Registers | 128 | 0 | 0 | 35200 | 0.36 | | |||||
| | Register as Flip Flop | 128 | 0 | 0 | 35200 | 0.36 | | |||||
| | Register as Latch | 0 | 0 | 0 | 35200 | 0.00 | | |||||
| | F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 | | |||||
| | F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 | | |||||
| +-------------------------+------+-------+------------+-----------+-------+ | |||||
| +-------------------------+-------+-------+------------+-----------+-------+ | |||||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | |||||
| +-------------------------+-------+-------+------------+-----------+-------+ | |||||
| | Slice LUTs* | 11151 | 0 | 0 | 17600 | 63.36 | | |||||
| | LUT as Logic | 11151 | 0 | 0 | 17600 | 63.36 | | |||||
| | LUT as Memory | 0 | 0 | 0 | 6000 | 0.00 | | |||||
| | Slice Registers | 212 | 0 | 0 | 35200 | 0.60 | | |||||
| | Register as Flip Flop | 212 | 0 | 0 | 35200 | 0.60 | | |||||
| | Register as Latch | 0 | 0 | 0 | 35200 | 0.00 | | |||||
| | F7 Muxes | 0 | 0 | 0 | 8800 | 0.00 | | |||||
| | F8 Muxes | 0 | 0 | 0 | 4400 | 0.00 | | |||||
| +-------------------------+-------+-------+------------+-----------+-------+ | |||||
| * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. | * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. | ||||
| | 0 | Yes | - | Set | | | 0 | Yes | - | Set | | ||||
| | 0 | Yes | - | Reset | | | 0 | Yes | - | Reset | | ||||
| | 0 | Yes | Set | - | | | 0 | Yes | Set | - | | ||||
| | 128 | Yes | Reset | - | | |||||
| | 212 | Yes | Reset | - | | |||||
| +-------+--------------+-------------+--------------+ | +-------+--------------+-------------+--------------+ | ||||
| +----------------+------+-------+------------+-----------+-------+ | +----------------+------+-------+------------+-----------+-------+ | ||||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | | Site Type | Used | Fixed | Prohibited | Available | Util% | | ||||
| +----------------+------+-------+------------+-----------+-------+ | +----------------+------+-------+------------+-----------+-------+ | ||||
| | DSPs | 13 | 0 | 0 | 80 | 16.25 | | |||||
| | DSP48E1 only | 13 | | | | | | |||||
| | DSPs | 28 | 0 | 0 | 80 | 35.00 | | |||||
| | DSP48E1 only | 28 | | | | | | |||||
| +----------------+------+-------+------------+-----------+-------+ | +----------------+------+-------+------------+-----------+-------+ | ||||
| +-----------------------------+------+-------+------------+-----------+--------+ | +-----------------------------+------+-------+------------+-----------+--------+ | ||||
| | Site Type | Used | Fixed | Prohibited | Available | Util% | | | Site Type | Used | Fixed | Prohibited | Available | Util% | | ||||
| +-----------------------------+------+-------+------------+-----------+--------+ | +-----------------------------+------+-------+------------+-----------+--------+ | ||||
| | Bonded IOB | 223 | 0 | 0 | 100 | 223.00 | | |||||
| | Bonded IOB | 288 | 0 | 0 | 100 | 288.00 | | |||||
| | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | | Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | | ||||
| | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | | | Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 | | ||||
| | PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | | | PHY_CONTROL | 0 | 0 | 0 | 2 | 0.00 | | ||||
| +----------+------+---------------------+ | +----------+------+---------------------+ | ||||
| | Ref Name | Used | Functional Category | | | Ref Name | Used | Functional Category | | ||||
| +----------+------+---------------------+ | +----------+------+---------------------+ | ||||
| | LUT6 | 3246 | LUT | | |||||
| | LUT3 | 2638 | LUT | | |||||
| | LUT4 | 2484 | LUT | | |||||
| | CARRY4 | 1613 | CarryLogic | | |||||
| | LUT2 | 1000 | LUT | | |||||
| | LUT5 | 799 | LUT | | |||||
| | LUT1 | 165 | LUT | | |||||
| | IBUF | 159 | IO | | |||||
| | FDRE | 128 | Flop & Latch | | |||||
| | LUT5 | 9401 | LUT | | |||||
| | CARRY4 | 2830 | CarryLogic | | |||||
| | LUT2 | 665 | LUT | | |||||
| | LUT4 | 564 | LUT | | |||||
| | LUT3 | 460 | LUT | | |||||
| | LUT1 | 235 | LUT | | |||||
| | IBUF | 224 | IO | | |||||
| | FDRE | 212 | Flop & Latch | | |||||
| | LUT6 | 140 | LUT | | |||||
| | OBUF | 64 | IO | | | OBUF | 64 | IO | | ||||
| | DSP48E1 | 13 | Block Arithmetic | | |||||
| | DSP48E1 | 28 | Block Arithmetic | | |||||
| | BUFG | 1 | Clock | | | BUFG | 1 | Clock | | ||||
| +----------+------+---------------------+ | +----------+------+---------------------+ | ||||
+ 156
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log
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| ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. | ||||
| source regler.tcl -notrace | source regler.tcl -notrace | ||||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 8.066 | |||||
| create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859 | |||||
| Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp | Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp | ||||
| INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis | INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis | ||||
| INFO: [Vivado 12-7989] Please ensure there are no constraint changes | INFO: [Vivado 12-7989] Please ensure there are no constraint changes | ||||
| INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | ||||
| INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. | INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. | ||||
| INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes | INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes | ||||
| INFO: [Synth 8-7075] Helper process launched with PID 25492 | |||||
| INFO: [Synth 8-7075] Helper process launched with PID 7236 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48] | |||||
| WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:110] | |||||
| WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:121] | |||||
| INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48] | |||||
| INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] | |||||
| WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115] | |||||
| WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:126] | |||||
| INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] | |||||
| WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Handling Custom Attributes | Start Handling Custom Attributes | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1261.043 ; gain = 0.000 | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000 | |||||
| INFO: [Project 1-570] Preparing netlist for logic optimization | INFO: [Project 1-570] Preparing netlist for logic optimization | ||||
| Processing XDC Constraints | Processing XDC Constraints | ||||
| Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. | ||||
| Completed Processing XDC Constraints | Completed Processing XDC Constraints | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1273.594 ; gain = 0.000 | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000 | |||||
| INFO: [Project 1-111] Unisim Transformation Summary: | INFO: [Project 1-111] Unisim Transformation Summary: | ||||
| No Unisim elements were transformed. | No Unisim elements were transformed. | ||||
| Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1273.594 ; gain = 0.000 | |||||
| Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000 | |||||
| WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis | WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis | ||||
| INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Loading Part and Timing Information | Start Loading Part and Timing Information | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Loading part: xc7z010clg400-1 | Loading part: xc7z010clg400-1 | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Applying 'set_property' XDC Constraints | Start Applying 'set_property' XDC Constraints | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start RTL Component Statistics | Start RTL Component Statistics | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Detailed RTL Component Info : | Detailed RTL Component Info : | ||||
| +---Adders : | +---Adders : | ||||
| 10 Input 148 Bit Adders := 1 | |||||
| 2 Input 148 Bit Adders := 2 | 2 Input 148 Bit Adders := 2 | ||||
| 3 Input 64 Bit Adders := 1 | 3 Input 64 Bit Adders := 1 | ||||
| 2 Input 64 Bit Adders := 1 | 2 Input 64 Bit Adders := 1 | ||||
| +---Registers : | +---Registers : | ||||
| 64 Bit Registers := 1 | 64 Bit Registers := 1 | ||||
| +---Multipliers : | +---Multipliers : | ||||
| 41x64 Multipliers := 1 | |||||
| 20x64 Multipliers := 1 | |||||
| 10x64 Multipliers := 1 | 10x64 Multipliers := 1 | ||||
| +---Muxes : | +---Muxes : | ||||
| 2 Input 148 Bit Muxes := 2 | |||||
| 2 Input 148 Bit Muxes := 1 | |||||
| 2 Input 64 Bit Muxes := 3 | |||||
| 2 Input 20 Bit Muxes := 2 | 2 Input 20 Bit Muxes := 2 | ||||
| 2 Input 10 Bit Muxes := 1 | 2 Input 10 Bit Muxes := 1 | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Cross Boundary and Area Optimization | Start Cross Boundary and Area Optimization | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| WARNING: [Synth 8-7080] Parallel synthesis criteria is not met | WARNING: [Synth 8-7080] Parallel synthesis criteria is not met | ||||
| DSP Report: Generating DSP I_k5, operation Mode is: (A:0xf4240)*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: operator I_k4 is absorbed into DSP I_k4. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: operator u_reg1 is absorbed into DSP u_reg1. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k6, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: operator I_k6 is absorbed into DSP I_k6. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: PCIN+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP I_k5, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: operator I_k5 is absorbed into DSP I_k5. | |||||
| DSP Report: Generating DSP u3, operation Mode is: A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: Generating DSP u3, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: Generating DSP u3, operation Mode is: A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: Generating DSP u3, operation Mode is: (PCIN>>17)+A*B. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| DSP Report: operator u3 is absorbed into DSP u3. | |||||
| WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load | ||||
| WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1273.594 ; gain = 12.551 | |||||
| Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start ROM, RAM, DSP, Shift Register and Retiming Reporting | Start ROM, RAM, DSP, Shift Register and Retiming Reporting | ||||
| +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | ||||
| |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | | |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | | ||||
| +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ | ||||
| |regler | (A:0xf4240)*B | 21 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 24 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 20 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 16 | 13 | - | - | 29 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 18 | 13 | - | - | 46 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 18 | 13 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | PCIN+A*B | 24 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |||||
| |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | (PCIN>>17)+A*B | 13 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | (PCIN>>17)+A*B | 13 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | |regler | A*B | 18 | 10 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | | ||||
| Start Applying XDC Timing Constraints | Start Applying XDC Timing Constraints | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1288.984 ; gain = 27.941 | |||||
| Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Timing Optimization | Start Timing Optimization | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1297.449 ; gain = 36.406 | |||||
| Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Technology Mapping | Start Technology Mapping | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1507.957 ; gain = 246.914 | |||||
| Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start IO Insertion | Start IO Insertion | ||||
| Finished Final Netlist Cleanup | Finished Final Netlist Cleanup | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Renaming Generated Instances | Start Renaming Generated Instances | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Rebuilding User Hierarchy | Start Rebuilding User Hierarchy | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Renaming Generated Ports | Start Renaming Generated Ports | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Handling Custom Attributes | Start Handling Custom Attributes | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Renaming Generated Nets | Start Renaming Generated Nets | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Start Writing Synthesis Report | Start Writing Synthesis Report | ||||
| | |Cell |Count | | | |Cell |Count | | ||||
| +------+--------+------+ | +------+--------+------+ | ||||
| |1 |BUFG | 1| | |1 |BUFG | 1| | ||||
| |2 |CARRY4 | 1613| | |||||
| |3 |DSP48E1 | 13| | |||||
| |4 |LUT1 | 165| | |||||
| |5 |LUT2 | 1000| | |||||
| |6 |LUT3 | 2638| | |||||
| |7 |LUT4 | 2484| | |||||
| |8 |LUT5 | 799| | |||||
| |9 |LUT6 | 3246| | |||||
| |10 |FDRE | 128| | |||||
| |11 |IBUF | 159| | |||||
| |2 |CARRY4 | 2830| | |||||
| |3 |DSP48E1 | 28| | |||||
| |4 |LUT1 | 235| | |||||
| |5 |LUT2 | 665| | |||||
| |6 |LUT3 | 460| | |||||
| |7 |LUT4 | 564| | |||||
| |8 |LUT5 | 9401| | |||||
| |9 |LUT6 | 140| | |||||
| |10 |FDRE | 212| | |||||
| |11 |IBUF | 224| | |||||
| |12 |OBUF | 64| | |12 |OBUF | 64| | ||||
| +------+--------+------+ | +------+--------+------+ | ||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| --------------------------------------------------------------------------------- | --------------------------------------------------------------------------------- | ||||
| Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. | Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. | ||||
| Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 1517.203 ; gain = 243.609 | |||||
| Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137 | |||||
| Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 | |||||
| INFO: [Project 1-571] Translating synthesized netlist | INFO: [Project 1-571] Translating synthesized netlist | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1517.203 ; gain = 0.000 | |||||
| INFO: [Netlist 29-17] Analyzing 1626 Unisim elements for replacement | |||||
| INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000 | |||||
| INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement | |||||
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |||||
| WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. | WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. | ||||
| INFO: [Project 1-570] Preparing netlist for logic optimization | INFO: [Project 1-570] Preparing netlist for logic optimization | ||||
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | ||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1517.203 ; gain = 0.000 | |||||
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000 | |||||
| INFO: [Project 1-111] Unisim Transformation Summary: | INFO: [Project 1-111] Unisim Transformation Summary: | ||||
| No Unisim elements were transformed. | No Unisim elements were transformed. | ||||
| Synth Design complete, checksum: b5ea81b7 | |||||
| Synth Design complete, checksum: 6d8170b6 | |||||
| INFO: [Common 17-83] Releasing license: Synthesis | INFO: [Common 17-83] Releasing license: Synthesis | ||||
| 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. | 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. | ||||
| synth_design completed successfully | synth_design completed successfully | ||||
| synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 1517.203 ; gain = 256.160 | |||||
| synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613 | |||||
| INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. | INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. | ||||
| INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | ||||
| INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:59:52 2022... | |||||
| INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022... |
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/vivado.jou
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| # Vivado v2021.2 (64-bit) | # Vivado v2021.2 (64-bit) | ||||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | ||||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | ||||
| # Start of session at: Mon May 23 22:58:42 2022 | |||||
| # Process ID: 23388 | |||||
| # Start of session at: Tue May 31 21:51:15 2022 | |||||
| # Process ID: 7140 | |||||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | ||||
| # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl | # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl | ||||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds | # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds |
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| REM Simulator : Xilinx Vivado Simulator | REM Simulator : Xilinx Vivado Simulator | ||||
| REM Description : Script for compiling the simulation design source files | REM Description : Script for compiling the simulation design source files | ||||
| REM | REM | ||||
| REM Generated by Vivado on Mon May 23 23:00:16 +0200 2022 | |||||
| REM Generated by Vivado on Tue May 31 21:54:27 +0200 2022 | |||||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | ||||
| REM | REM | ||||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 |
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| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' |
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| REM Simulator : Xilinx Vivado Simulator | REM Simulator : Xilinx Vivado Simulator | ||||
| REM Description : Script for elaborating the compiled design | REM Description : Script for elaborating the compiled design | ||||
| REM | REM | ||||
| REM Generated by Vivado on Mon May 23 23:00:17 +0200 2022 | |||||
| REM Generated by Vivado on Tue May 31 21:54:29 +0200 2022 | |||||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | ||||
| REM | REM | ||||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 |
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| Compiling package ieee.numeric_std | Compiling package ieee.numeric_std | ||||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | ||||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | ||||
| Compiling architecture behavioral of entity xil_defaultlib.autoTuning [autotuning_default] | |||||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | ||||
| Built simulation snapshot pwm_test_db_behav | Built simulation snapshot pwm_test_db_behav |
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| REM Simulator : Xilinx Vivado Simulator | REM Simulator : Xilinx Vivado Simulator | ||||
| REM Description : Script for simulating the design by launching the simulator | REM Description : Script for simulating the design by launching the simulator | ||||
| REM | REM | ||||
| REM Generated by Vivado on Mon May 23 23:00:20 +0200 2022 | |||||
| REM Generated by Vivado on Tue May 31 21:54:32 +0200 2022 | |||||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | ||||
| REM | REM | ||||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 |
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| Time resolution is 1 ps |
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj
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| #endif | #endif | ||||
| typedef void (*funcp)(char *, char *); | typedef void (*funcp)(char *, char *); | ||||
| extern int main(int, char**); | extern int main(int, char**); | ||||
| IKI_DLLESPEC extern void execute_40(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_41(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_37(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_39(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_52(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_53(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_47(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_49(char*, char *); | |||||
| IKI_DLLESPEC extern void execute_51(char*, char *); | |||||
| IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); | IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); | ||||
| IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); | IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); | ||||
| IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); | IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); | ||||
| funcp funcTab[7] = {(funcp)execute_40, (funcp)execute_41, (funcp)execute_37, (funcp)execute_39, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; | |||||
| const int NumRelocateId= 7; | |||||
| funcp funcTab[8] = {(funcp)execute_52, (funcp)execute_53, (funcp)execute_47, (funcp)execute_49, (funcp)execute_51, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; | |||||
| const int NumRelocateId= 8; | |||||
| void relocate(char *dp) | void relocate(char *dp) | ||||
| { | { | ||||
| iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 7); | |||||
| iki_vhdl_file_variable_register(dp + 6264); | |||||
| iki_vhdl_file_variable_register(dp + 6320); | |||||
| iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 8); | |||||
| iki_vhdl_file_variable_register(dp + 6952); | |||||
| iki_vhdl_file_variable_register(dp + 7008); | |||||
| /*Populate the transaction function pointer field in the whole net structure */ | /*Populate the transaction function pointer field in the whole net structure */ |
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| { | { | ||||
| crc : 6733451111524596900 , | |||||
| crc : 15251868591865205496 , | |||||
| ccp_crc : 0 , | ccp_crc : 0 , | ||||
| cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , | cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , | ||||
| buildDate : "Oct 19 2021" , | buildDate : "Oct 19 2021" , |
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| Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 57651 | |||||
| Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 50859 | |||||
| Design successfully loaded | Design successfully loaded | ||||
| Design Loading Memory Usage: 7284 KB (Peak: 7284 KB) | |||||
| Design Loading CPU Usage: 61 ms | |||||
| Simulation completed | |||||
| Simulation Memory Usage: 15804 KB (Peak: 15804 KB) | |||||
| Simulation CPU Usage: 7905 ms | |||||
| Design Loading Memory Usage: 7440 KB (Peak: 7440 KB) | |||||
| Design Loading CPU Usage: 15 ms |
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| 2020.2 | 2020.2 | ||||
| Oct 19 2021 | Oct 19 2021 | ||||
| 03:16:22 | 03:16:22 | ||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1653337595,vhdl,,,,pwm_test_db,,,,,,,, | |||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1653339512,vhdl,,,,pt1,,,,,,,, | |||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1653338461,vhdl,,,,regler,,,,,,,, | |||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1654026861,vhdl,,,,pwm_test_db,,,,,,,, | |||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd,1654026641,vhdl,,,,autotuning,,,,,,,, | |||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1653978411,vhdl,,,,pt1,,,,,,,, | |||||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1653978349,vhdl,,,,regler,,,,,,,, |
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| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' |
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| component regler is | component regler is | ||||
| Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor | Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor | ||||
| prescaler : in signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| w : in signed(63 downto 0) := (others => '0'); --Sollwert | w : in signed(63 downto 0) := (others => '0'); --Sollwert | ||||
| y : in signed(63 downto 0) := (others => '0'); --Istwert | y : in signed(63 downto 0) := (others => '0'); --Istwert | ||||
| u : inout signed(63 downto 0) := (others => '0'); --Stellgöße | u : inout signed(63 downto 0) := (others => '0'); --Stellgöße | ||||
| KR : in signed(9 downto 0) := to_signed(1,10); -- Verstärkung | KR : in signed(9 downto 0) := to_signed(1,10); -- Verstärkung | ||||
| T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us | T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us | ||||
| TV : signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt | TV : signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt | ||||
| TN : in signed(9 downto 0) := to_signed(1,10)); -- Nachstellzeit | |||||
| TN : in signed(9 downto 0) := to_signed(1,10); -- Nachstellzeit | |||||
| regler_bruecken : in STD_LOGIC := '0'); | |||||
| end component; | end component; | ||||
| component pt1 is | component pt1 is | ||||
| Port ( | Port ( | ||||
| clk : in STD_LOGIC; | clk : in STD_LOGIC; | ||||
| prescaler : in signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| u : in signed(63 downto 0) := to_signed(1,64); | u : in signed(63 downto 0) := to_signed(1,64); | ||||
| y : inout signed(63 downto 0) := to_signed(1,64); -- muss vielleicht initalisiert werden vorher!? | y : inout signed(63 downto 0) := to_signed(1,64); -- muss vielleicht initalisiert werden vorher!? | ||||
| a : in signed(9 downto 0) := to_signed(1,10); | a : in signed(9 downto 0) := to_signed(1,10); | ||||
| end component; | end component; | ||||
| component autoTuning is | |||||
| Port ( clk : in STD_LOGIC; | |||||
| prescaler : in signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| duration : in signed(63 downto 0) := to_signed(5000000, 64); -- Zeit in Microsekunden/ oder Clk-Ticks? | |||||
| start_Tuning : inout std_logic := '1'; | |||||
| regler_bruecken : out STD_LOGIC := '0'; | |||||
| w : in signed(63 downto 0) := (others => '0'); --Sollwert für Regler -> während Outotuing konst! | |||||
| y : in signed(63 downto 0) := (others => '0'); --Istwert | |||||
| --u : inout signed(63 downto 0) := (others => '0'); --Stellgöße | |||||
| KR : out signed(9 downto 0) := to_signed(1, 10); -- Verstärkung | |||||
| T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us | |||||
| TV : out signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt | |||||
| TN : out signed(9 downto 0) := to_signed(1, 10)); -- Nachstellzeit); -- u <= w); | |||||
| end component; | |||||
| signal clk : std_logic := '0'; | signal clk : std_logic := '0'; | ||||
| signal clk_100 : std_logic := '0'; | signal clk_100 : std_logic := '0'; | ||||
| signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit | |||||
| signal w : signed(63 downto 0) := to_signed(1000000, 64); | signal w : signed(63 downto 0) := to_signed(1000000, 64); | ||||
| signal u : signed(63 downto 0) := to_signed(0, 64); | signal u : signed(63 downto 0) := to_signed(0, 64); | ||||
| signal y : signed(63 downto 0) := to_signed(0, 64); | signal y : signed(63 downto 0) := to_signed(0, 64); | ||||
| signal TV : signed(9 downto 0) := to_signed(0, 10); -- Vorhaltezeit für Differenzierer interesannt | signal TV : signed(9 downto 0) := to_signed(0, 10); -- Vorhaltezeit für Differenzierer interesannt | ||||
| signal TN : signed(9 downto 0) := to_signed(100000, 10); -- Nachstellzeit in us | signal TN : signed(9 downto 0) := to_signed(100000, 10); -- Nachstellzeit in us | ||||
| --Autotuning | |||||
| signal duration : signed(63 downto 0) := to_signed(2000000, 64); | |||||
| signal start_Tuning : std_logic := '1'; | |||||
| signal regler_bruecken : std_logic := '0'; | |||||
| begin | begin | ||||
| uut_regler: regler PORT MAP ( | uut_regler: regler PORT MAP ( | ||||
| clk => clk_100, | clk => clk_100, | ||||
| prescaler => prescaler, | |||||
| w => w, | w => w, | ||||
| y => y, | y => y, | ||||
| u => u, | u => u, | ||||
| KR => KR, | KR => KR, | ||||
| T => T, | T => T, | ||||
| TV => TV, | TV => TV, | ||||
| TN => TN | |||||
| TN => TN, | |||||
| regler_bruecken => regler_bruecken | |||||
| ); | ); | ||||
| uut_pt1: pt1 PORT MAP ( | uut_pt1: pt1 PORT MAP ( | ||||
| clk => clk, | clk => clk, | ||||
| prescaler => prescaler, | |||||
| u => u, | u => u, | ||||
| y => y, | y => y, | ||||
| a => a, | a => a, | ||||
| stepWidth => stepWidth | stepWidth => stepWidth | ||||
| ); | ); | ||||
| uut_autoTuning: autoTuning PORT MAP ( | |||||
| clk => clk_100, | |||||
| prescaler => prescaler, | |||||
| duration => duration, | |||||
| start_Tuning => start_Tuning, | |||||
| regler_bruecken => regler_bruecken, | |||||
| w => w, | |||||
| y => y, | |||||
| KR => KR, | |||||
| T => T, | |||||
| TV => TV, | |||||
| TN => TN | |||||
| ); | |||||
| --generate clock | --generate clock | ||||
| clk <= not clk after 5 us; | clk <= not clk after 5 us; | ||||
| process | process | ||||
| begin | begin | ||||
| --w <= 100000000; | --w <= 100000000; | ||||
| w <= to_signed(1000000, 64); --muss >= 1000000 sein! | |||||
| --w <= to_signed(100000000, 64); --muss >= 1000000 sein! | |||||
| w <= to_signed(10000000, 64); --INTwert darf nicht über Maximalen wert von 32-Bit sein | |||||
| start_Tuning <= '1'; | |||||
| -- w <= w * prescaler; | |||||
| -- if rising_edge(clk) and ( cnt >= 100) then | -- if rising_edge(clk) and ( cnt >= 100) then | ||||
| -- clk_100 <= not clk_100; | -- clk_100 <= not clk_100; | ||||
| -- cnt <= 0; | -- cnt <= 0; |
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| ---------------------------------------------------------------------------------- | |||||
| -- Company: | |||||
| -- Engineer: | |||||
| -- | |||||
| -- Create Date: 31.05.2022 08:04:28 | |||||
| -- Design Name: | |||||
| -- Module Name: autoTuning - Behavioral | |||||
| -- Project Name: | |||||
| -- Target Devices: | |||||
| -- Tool Versions: | |||||
| -- Description: | |||||
| -- | |||||
| -- Dependencies: | |||||
| -- | |||||
| -- Revision: | |||||
| -- Revision 0.01 - File Created | |||||
| -- Additional Comments: | |||||
| -- | |||||
| ---------------------------------------------------------------------------------- | |||||
| library IEEE; | |||||
| use IEEE.STD_LOGIC_1164.ALL; | |||||
| use IEEE.numeric_std.ALL; | |||||
| -- Uncomment the following library declaration if using | |||||
| -- arithmetic functions with Signed or Unsigned values | |||||
| --use IEEE.NUMERIC_STD.ALL; | |||||
| -- Uncomment the following library declaration if instantiating | |||||
| -- any Xilinx leaf cells in this code. | |||||
| --library UNISIM; | |||||
| --use UNISIM.VComponents.all; | |||||
| -- Sollwert/Startsignal (CTRL-Unit) -> AutoTuning -> Regler -> Strecke | |||||
| entity autoTuning is | |||||
| Port ( clk : in STD_LOGIC; | |||||
| prescaler : in signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| duration : in signed(63 downto 0) := to_signed(5000000, 64); -- Zeit in Microsekunden/ oder Clk-Ticks? | |||||
| start_Tuning : inout std_logic := '0'; | |||||
| regler_bruecken : out STD_LOGIC := '0'; | |||||
| w : in signed(63 downto 0) := (others => '0'); --Sollwert für Regler -> während Outotuing konst! | |||||
| y : in signed(63 downto 0) := (others => '0'); --Istwert | |||||
| --u : inout signed(63 downto 0) := (others => '0'); --Stellgöße | |||||
| KR : out signed(9 downto 0) := to_signed(1, 10); -- Verstärkung | |||||
| T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us | |||||
| TV : out signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt | |||||
| TN : out signed(9 downto 0) := to_signed(1, 10)); -- Nachstellzeit); -- u <= w); | |||||
| end autoTuning; | |||||
| architecture Behavioral of autoTuning is | |||||
| --signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| type data_array is array (0 to 2000) of signed(63 downto 0); | |||||
| begin | |||||
| process(clk) | |||||
| variable counter : signed(63 downto 0) := to_signed(0, 64); | |||||
| variable counter_us : signed(63 downto 0) := to_signed(0, 64); --Prescaler für Clk-Ticks | |||||
| variable dt : signed(63 downto 0) := to_signed(0, 64); -- Zeit zwischen Messwerte Scrhittweite (us/Wert) | |||||
| variable data : data_array; --Array mit Messwerten | |||||
| variable data_pos : integer := 0; --iterator für Array | |||||
| variable steigung : signed(63 downto 0) := to_signed(0, 64); | |||||
| variable steigung_last : signed(63 downto 0) := to_signed(0, 64); | |||||
| variable data_pos_wendetangente : integer := 0; | |||||
| --Hilfsgerade Wendetangente | |||||
| variable b : signed(63 downto 0) := to_signed(0, 64); | |||||
| --Messwerte aus Sprungantwort | |||||
| variable Tu : signed(63 downto 0) := to_signed(0, 64); -- Verzugszeit us | |||||
| variable Tg : signed(63 downto 0) := to_signed(0, 64); -- Ausgleichstzeit us | |||||
| variable Ks : signed(63 downto 0) := to_signed(0, 64); -- Verstärkungsfaktor us | |||||
| begin | |||||
| if(rising_edge(clk)) then | |||||
| if(start_Tuning = '1') then | |||||
| --Messvorgang starten | |||||
| regler_bruecken <= '1'; | |||||
| counter_us := counter_us + 1; | |||||
| --125 MHZ CLK !!! -> 125 Ticks = 1 us | |||||
| if(counter_us >= 125) then | |||||
| counter_us := to_signed(0, 64); | |||||
| counter := counter + 1; | |||||
| --Messwerte aufzeichnen: | |||||
| dt := duration / to_signed(2000, 64); --schrittweite | |||||
| if(counter >= dt * to_signed(data_pos,64)) then | |||||
| --Wert abspeichern -> nicht rdy | |||||
| data(data_pos) := y; | |||||
| end if; | |||||
| if(counter >= duration) then | |||||
| counter := to_signed(0, 64); | |||||
| start_Tuning <= '0'; --Messvorgang beenden | |||||
| end if; | |||||
| end if; | |||||
| else | |||||
| -- autoTuning beenden | |||||
| regler_bruecken <= '0'; | |||||
| counter := to_signed(0, 64); | |||||
| counter_us := to_signed(0, 64); | |||||
| data_pos := 0; | |||||
| --Parameter berechnen/setzen: | |||||
| dt := duration / to_signed(2000, 64); --schrittweite | |||||
| for i in 1 to 2000 loop | |||||
| steigung_last := steigung; | |||||
| --steigung := (data(i) - data(i-1)) / dt; --"Richtig" | |||||
| steigung := (data(i) - data(i-1)); | |||||
| if (steigung < steigung_last) then | |||||
| data_pos_wendetangente := i; | |||||
| exit; | |||||
| end if; | |||||
| end loop; | |||||
| -- y = mx + b | |||||
| b := data(data_pos_wendetangente) - steigung * to_signed(data_pos_wendetangente, 32); | |||||
| Ks := data(2000); | |||||
| Tu := -b * dt / steigung; | |||||
| Tg := (Ks - b) * dt / steigung - Tu; | |||||
| --PI-Regler berechnen: | |||||
| --chien, hrones Reswick aperiodischer Verlauf Störung | |||||
| KR <= 6*Tg/Tu/Ks/10; | |||||
| TV <= to_signed(0, 10); | |||||
| TN <= 4 * Tu; | |||||
| end if; | |||||
| end if; | |||||
| end process; | |||||
| end Behavioral; |
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| entity pt1 is | entity pt1 is | ||||
| Port ( | Port ( | ||||
| clk : in STD_LOGIC; | clk : in STD_LOGIC; | ||||
| prescaler : in signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| u : in signed(63 downto 0) := to_signed(0, 64); | u : in signed(63 downto 0) := to_signed(0, 64); | ||||
| y : inout signed(63 downto 0) := to_signed(0, 64); -- muss vielleicht initalisiert werden vorher!? | y : inout signed(63 downto 0) := to_signed(0, 64); -- muss vielleicht initalisiert werden vorher!? | ||||
| a : in signed(9 downto 0) := to_signed(1, 10); | a : in signed(9 downto 0) := to_signed(1, 10); | ||||
| --signal stepWidth : integer := 10; -- in us -> 10 us später berechnet aus Clk und Prescaler | --signal stepWidth : integer := 10; -- in us -> 10 us später berechnet aus Clk und Prescaler | ||||
| signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit | |||||
| --signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit | |||||
| -- Konstanten Streckenparameter | -- Konstanten Streckenparameter | ||||
| --signal a : integer := 1; | --signal a : integer := 1; |
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| entity regler is | entity regler is | ||||
| Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor | Port ( clk : in STD_LOGIC; --Clk -> Gibt abtastzeit vor | ||||
| prescaler : in signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| w : in signed(63 downto 0) := (others => '0'); --Sollwert | w : in signed(63 downto 0) := (others => '0'); --Sollwert | ||||
| y : in signed(63 downto 0) := (others => '0'); --Istwert | y : in signed(63 downto 0) := (others => '0'); --Istwert | ||||
| u : inout signed(63 downto 0) := (others => '0'); --Stellgöße | u : inout signed(63 downto 0) := (others => '0'); --Stellgöße | ||||
| KR : in signed(9 downto 0) := to_signed(1, 10); -- Verstärkung | KR : in signed(9 downto 0) := to_signed(1, 10); -- Verstärkung | ||||
| T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us | T : in signed(9 downto 0) := to_signed(1000, 10); -- Abtastzeit in us 1000us | ||||
| TV : signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt | TV : signed(9 downto 0) := (others => '0'); -- Vorhaltezeit für Differenzierer interesannt | ||||
| TN : in signed(9 downto 0) := to_signed(1, 10)); -- Nachstellzeit | |||||
| TN : in signed(9 downto 0) := to_signed(1, 10); -- Nachstellzeit | |||||
| regler_bruecken : in STD_LOGIC := '0'); -- u <= w | |||||
| end regler; | end regler; | ||||
| architecture Behavioral of regler is | architecture Behavioral of regler is | ||||
| --signal stepWidth : integer := 1; -- 10 us später berechnet aus Clk und Prescaler | --signal stepWidth : integer := 1; -- 10 us später berechnet aus Clk und Prescaler | ||||
| signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| --signal prescaler : signed(63 downto 0) := to_signed(1000000, 64); -- prescaler für Zeit 1000000 | |||||
| -- Parameter aus Sprungantwort etc. | -- Parameter aus Sprungantwort etc. | ||||
| --variable I_k1 : integer := 0; -- letzer I-Anteil | --variable I_k1 : integer := 0; -- letzer I-Anteil | ||||
| variable u_var : signed(147 downto 0) := to_signed(0, 148); | variable u_var : signed(147 downto 0) := to_signed(0, 148); | ||||
| variable uMax : signed(63 downto 0) := (63 =>'0', others=>'1'); | |||||
| begin | begin | ||||
| if rising_edge(clk) then | if rising_edge(clk) then | ||||
| -- PI-Regler ---------------------------------------- | -- PI-Regler ---------------------------------------- | ||||
| I_k <= I_k + T * 1 / TN * prescaler * e_k / prescaler; -- I-Anteil berechnen | I_k <= I_k + T * 1 / TN * prescaler * e_k / prescaler; -- I-Anteil berechnen | ||||
| u_var := KR * e_k + I_k; | u_var := KR * e_k + I_k; | ||||
| u <= u_var(63 downto 0); | |||||
| --Overflow abfangen | |||||
| if (u_var(147 downto 64) > 0) then | |||||
| u <= uMax; | |||||
| elsif(u_var < to_signed(0, 64)) then | |||||
| u <= to_signed(0, 64); | |||||
| else | |||||
| u <= u_var(63 downto 0); | |||||
| end if; | |||||
| ----------------------------------------------------- | ----------------------------------------------------- | ||||
| --u <= w; -- Regler überbrücken! | |||||
| if regler_bruecken = '1' then | |||||
| u <= w; -- Regler überbrücken! | |||||
| end if; | |||||
| end if; | end if; | ||||
+ 8
- 1
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
View File
| <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> | <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> | ||||
| <Option Name="EnableBDX" Val="FALSE"/> | <Option Name="EnableBDX" Val="FALSE"/> | ||||
| <Option Name="DSABoardId" Val="zybo-z7-10"/> | <Option Name="DSABoardId" Val="zybo-z7-10"/> | ||||
| <Option Name="WTXSimLaunchSim" Val="161"/> | |||||
| <Option Name="WTXSimLaunchSim" Val="173"/> | |||||
| <Option Name="WTModelSimLaunchSim" Val="0"/> | <Option Name="WTModelSimLaunchSim" Val="0"/> | ||||
| <Option Name="WTQuestaLaunchSim" Val="0"/> | <Option Name="WTQuestaLaunchSim" Val="0"/> | ||||
| <Option Name="WTIesLaunchSim" Val="0"/> | <Option Name="WTIesLaunchSim" Val="0"/> | ||||
| <Attr Name="UsedIn" Val="simulation"/> | <Attr Name="UsedIn" Val="simulation"/> | ||||
| </FileInfo> | </FileInfo> | ||||
| </File> | </File> | ||||
| <File Path="$PSRCDIR/sources_1/new/autoTuning.vhd"> | |||||
| <FileInfo> | |||||
| <Attr Name="AutoDisabled" Val="1"/> | |||||
| <Attr Name="UsedIn" Val="synthesis"/> | |||||
| <Attr Name="UsedIn" Val="simulation"/> | |||||
| </FileInfo> | |||||
| </File> | |||||
| <Config> | <Config> | ||||
| <Option Name="DesignMode" Val="RTL"/> | <Option Name="DesignMode" Val="RTL"/> | ||||
| <Option Name="TopModule" Val="regler"/> | <Option Name="TopModule" Val="regler"/> |
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