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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid10504.str

vivado_pid10504.str 7.6KB
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  1. /*

  2. 

  3. Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]

  4. SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021

  5. IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021

  6. 

  7. Process ID (PID): 10504

  8. License: Customer

  9. Mode: GUI Mode

  10. 

  11. Current time: 	Mon May 23 20:31:24 CEST 2022

  12. Time zone: 	Central European Standard Time (Europe/Berlin)

  13. 

  14. OS: Windows 10

  15. OS Version: 10.0

  16. OS Architecture: amd64

  17. Available processors (cores): 12

  18. 

  19. Screen size: 1920x1080

  20. Screen resolution (DPI): 100

  21. Available screens: 2

  22. Default font: family=Dialog,name=Dialog,style=plain,size=12

  23. Scale size: 12

  24. 

  25. Java version: 	11.0.11 64-bit

  26. Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9

  27. Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe

  28. Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]

  29. Java initial memory (-Xms): 	256 MB

  30. Java maximum memory (-Xmx):	 3 GB

  31. 

  32. 

  33. User name: 	Felix

  34. User home directory: C:/Users/Felix

  35. User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  36. User country: 	DE

  37. User language: 	de

  38. User locale: 	de_DE

  39. 

  40. RDI_BASEROOT: C:/Xilinx/Vivado

  41. HDI_APPROOT: C:/Xilinx/Vivado/2021.2

  42. RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data

  43. RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin

  44. 

  45. Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml

  46. Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/

  47. Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts

  48. PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar

  49. Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  50. Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou

  51. Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-10504-DESKTOP-PAACOM8

  52. 

  53. Xilinx Environment Variables

  54. ----------------------------

  55. TWINCATSDK: C:\TwinCAT\3.1\SDK\

  56. XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE

  57. XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE

  58. XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2

  59. XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2

  60. XILINX_VIVADO: C:/Xilinx/Vivado/2021.2

  61. XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2

  62. 

  63. 

  64. GUI allocated memory:	319 MB

  65. GUI max memory:		3,072 MB

  66. Engine allocated memory: 1,307 MB

  67. 

  68. Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  69. 

  70. */

  71. 

  72. // TclEventType: START_GUI

  73. // Tcl Message: start_gui 

  74. // TclEventType: PROJECT_OPEN_DIALOG

  75. // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 

  76. // TclEventType: DEBUG_PROBE_SET_CHANGE

  77. // TclEventType: FLOW_ADDED

  78. // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 

  79. // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 

  80. // HMemoryUtils.trashcanNow. Engine heap size: 1,307 MB. GUI used memory: 55 MB. Current time: 5/23/22, 8:31:25 PM CEST

  81. // TclEventType: MSGMGR_MOVEMSG

  82. // TclEventType: FILE_SET_CHANGE

  83. // TclEventType: FILE_SET_NEW

  84. // TclEventType: RUN_CURRENT

  85. // TclEventType: PROJECT_DASHBOARD_NEW

  86. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  87. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  88. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  89. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  90. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  91. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  92. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  93. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  94. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  95. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  96. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  97. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  98. // TclEventType: PROJECT_NEW

  99. // [GUI Memory]: 70 MB (+71283kb) [00:00:14]

  100. // [Engine Memory]: 1,307 MB (+1219381kb) [00:00:14]

  101. // [GUI Memory]: 109 MB (+37180kb) [00:00:15]

  102. // WARNING: HEventQueue.dispatchEvent() is taking  2465 ms.

  103. // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 

  104. // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 

  105. // Tcl Message: INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 

  106. // Tcl Message: Scanning sources... Finished scanning sources 

  107. // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 

  108. // [GUI Memory]: 117 MB (+2679kb) [00:00:16]

  109. // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1

  110. // Tcl Message: open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000 

  111. dismissDialog("Open Project"); // bA

  112. // Tcl Message: update_compile_order -fileset sources_1