initial commit
This commit is contained in:
commit
b4e75e651c
49
U1_Datentypen/DataTypesExample.vhd
Normal file
49
U1_Datentypen/DataTypesExample.vhd
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@ -0,0 +1,49 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL; -- Fuer std_logic und std_logic_vector
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use IEEE.NUMERIC_STD.ALL; -- Fuer signed und unsigned Datentypen
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entity DataTypesExample is
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port (
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input_slv : in std_logic_vector(7 downto 0); -- std_logic_vector Eingang
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output_slv_calc : out std_logic_vector(7 downto 0); -- std_logic_vector Ausgang (Ergebnis einer Berechnuung)
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output_slv_mask : out std_logic_vector(7 downto 0); -- std_logic_vector Ausgang (Ergebnis einer Maksierung)
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output_slv_set : out std_logic_vector(7 downto 0) -- std_logic_vector Ausgang (Setzvorgang)
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);
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end DataTypesExample;
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architecture Behavioral of DataTypesExample is
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-- constant/signal Deklarationen
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--Legen Sie ein Konstante DataWidth als integer mit Wert 8 an
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--Legen Sie ein Konstante on als std_logic mit 1 an
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--Legen Sie ein Konstante mask als std_logic_vector mit 5Ah an
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--Legen Sie ein signal internal_int als integer mit Wertebreich -128 to 127 an
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--Legen Sie ein signal internal_int als integer mit Wertebreich -128 to 127 an
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--Legen Sie ein signal internal_slv als std_logic_vector mit Laenge 8 an
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--Legen Sie ein signal internal_s als signed mit Laenge 8 an
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begin
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-- Maskieren (UND) Sie den Eingang input_slv mit der Maske mask und weisen Sie den Wert dem Ausgang output_slv_mask zu
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-- Der Wert des Ausgangs output_slv_set soll dem Eingang input_slv entsprechen wobei immer das 5 Bit (von 8 Bit) per Bitverkettung gesetzt sein soll
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-- Koonstante one kann verwendet werden
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-- Weisen Sie dem signal internal_slv dein Eingang input_slv zu
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-- Weisen Sie dem signal internal_int das Signal internal_slv zu (Datentypen beachten Konvetierung noetig, mit Vorzeichen)
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-- Rechnen Sie die Subtraktion internal_int - der Konstante eight und weisen Sie das Ergebnis internal_int2 zu
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-- Weisen Sie dem signal das Signal internal_int2 zu (Datentypen beachten Konvetierung noetig)
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-- Weisen Sie dem Ausgang output_slv_calc das signal internal_s zu (Datentypen beachten Konvetierung noetig)
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end Behavioral;
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10
U1_Datentypen/Makefile
Normal file
10
U1_Datentypen/Makefile
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@ -0,0 +1,10 @@
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vhdl_srcs = DataTypesExample.vhd \
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test_DataTypesExample.vhd \
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main = test_DataTypesExample
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CHECK_RESULTS = true
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include ../scripts/vhdl.mk
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33
U1_Datentypen/test_DataTypesExample.vhd
Normal file
33
U1_Datentypen/test_DataTypesExample.vhd
Normal file
@ -0,0 +1,33 @@
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library ieee;
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use ieee.std_logic_1164.all;
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library std;
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use std.env.all;
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entity test_DataTypesExample is
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generic( CHECK_RESULTS : boolean );
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end entity test_DataTypesExample;
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architecture test of test_DataTypesExample is
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signal input_slv : std_logic_vector(7 downto 0);
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signal output_slv_calc : std_logic_vector(7 downto 0);
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signal output_slv_mask : std_logic_vector(7 downto 0);
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signal output_slv_set : std_logic_vector(7 downto 0);
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begin
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u_DataTypesExample : entity work.DataTypesExample
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port map (
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input_slv => input_slv,
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output_slv_calc => output_slv_calc,
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output_slv_mask => output_slv_mask,
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output_slv_set => output_slv_set
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);
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input_slv <= x"5a";
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delay : process
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begin
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wait for 100 ns;
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stop;
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end process delay;
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end architecture test;
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2
U1_Datentypen/test_DataTypesExample.wave
Normal file
2
U1_Datentypen/test_DataTypesExample.wave
Normal file
@ -0,0 +1,2 @@
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$ version 1.1
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/test_DataTypesExample/u_DataTypesExample/*
|
3
U1_Datentypen/vsim.wave
Normal file
3
U1_Datentypen/vsim.wave
Normal file
@ -0,0 +1,3 @@
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|
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /test_DataTypesExample/u_DataTypesExample/*
|
BIN
U2_Entity_Component/.test_top_entity.vhd.swp
Normal file
BIN
U2_Entity_Component/.test_top_entity.vhd.swp
Normal file
Binary file not shown.
11
U2_Entity_Component/Makefile
Normal file
11
U2_Entity_Component/Makefile
Normal file
@ -0,0 +1,11 @@
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vhdl_srcs = down_counter_int.vhd \
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top_entity.vhd \
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test_top_entity.vhd \
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main = test_top_entity
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CHECK_RESULTS = true
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include ../scripts/vhdl.mk
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31
U2_Entity_Component/down_counter_int.vhd
Normal file
31
U2_Entity_Component/down_counter_int.vhd
Normal file
@ -0,0 +1,31 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Backward_Counter is
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|
port (
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CLK : in std_logic; -- Eingangssignal fuer den Takt
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RESET : in std_logic; -- Eingangssignal zum Zuruecksetzen des Zaehlers
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INITIAL_VALUE : in integer range 0 to 127; -- Anfangswert fuer den Zaehler
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COUNT_OUT : out integer range 0 to 127 -- Ausgangssignal fuer den aktuellen Zaehlerstand
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);
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|
end Backward_Counter;
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architecture Behavioral of Backward_Counter is
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signal count : integer range 0 to 127; -- Signal fuer den Zaehler
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|
begin
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|
process(CLK, RESET)
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|
begin
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|
if RESET = '1' then -- Wenn RESET aktiv ist
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|
count <= INITIAL_VALUE; -- setze den Zaehler auf den Anfangswert
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|
elsif rising_edge(CLK) then -- Bei steigender Taktflanke
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|
if count = 0 then -- Wenn der Zaehlerstand 0 ist
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count <= 127; -- setze den Zaehlerstand auf den maximalen Wert (127)
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|
else
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|
count <= count - 1; -- Verringere den Zaehlerstand um 1
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|
end if;
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|
end if;
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|
end process;
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COUNT_OUT <= count; -- Weise den aktuellen Zaehlerstand dem Ausgangssignal zu
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|
end Behavioral;
|
42
U2_Entity_Component/test_top_entity.vhd
Normal file
42
U2_Entity_Component/test_top_entity.vhd
Normal file
@ -0,0 +1,42 @@
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|
library ieee;
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|
use ieee.std_logic_1164.all;
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|
library std;
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|
use std.env.all;
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|
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|
entity test_top_entity is
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generic( CHECK_RESULTS : boolean );
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end entity test_top_entity;
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architecture test of test_top_entity is
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '1';
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signal CNT : std_logic_vector(6 downto 0);
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begin
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u_top_entity : entity work.top_entity
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|
port map (
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|
CLK => CLK,
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|
RESET => RESET,
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|
CNT => CNT
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|
);
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|
CLK <= not CLK after 10 ns;
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|
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|
p_reset : process( CLK )
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|
begin
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|
if falling_edge( CLK ) then
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|
RESET <= '0';
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|
end if;
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|
end process p_reset;
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|
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|
p_run : process
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|
begin
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|
wait until falling_edge( RESET );
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|
for i in 0 to 128 loop
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|
wait until rising_edge( CLK );
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|
end loop;
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|
wait until rising_edge( CLK );
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|
stop;
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|
end process p_run;
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|
end architecture test;
|
2
U2_Entity_Component/test_top_entity.wave
Normal file
2
U2_Entity_Component/test_top_entity.wave
Normal file
@ -0,0 +1,2 @@
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|
$ version 1.1
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|
/test_DataTypesExample/u_DataTypesExample/*
|
29
U2_Entity_Component/top_entity.vhd
Normal file
29
U2_Entity_Component/top_entity.vhd
Normal file
@ -0,0 +1,29 @@
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|
library ieee;
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|
use ieee.std_logic_1164.all;
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|
use ieee.numeric_std.all;
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|
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|
entity top_entity is
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|
port (
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|
CLK : in std_logic; -- Eingangssignal fuer den Takt
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|
RESET : in std_logic; -- Eingangssignal zum Zuruecksetzen des Zaehlers
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|
CNT : out std_logic_vector(6 downto 0) -- Ausgangssignal fuer den aktuellen Zaehlerstand
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|
);
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|
end top_entity;
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|
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architecture Behavioral of top_entity is
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|
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|
-- Legen Sie eine Konstante mit den Wert 57 an, welche Sie der Komponente Backward_Counter als INITIAL_VALUE uebergeben koennen
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|
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|
-- Legen Sie ein Signal an um das Ergebnis aus COUNT_OUT der Komponente entgegenzunehmen zu koennen
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|
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|
begin
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|
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||||||
|
-- Instanzieren Sie direkt die Backward_Counter Komponente
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|
-- Als Takt und Reset sollen die jeweiligen Eingaenge der top_entity uebergeben werden
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||||||
|
-- Als Anfangswert fuer den Zaehler Ihre angelegte Konstante
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||||||
|
-- Der aktuelle Zaehlerstand soll Ihrem angelegten signal uebergeben werden
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||||||
|
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||||||
|
|
||||||
|
-- Machhen Sie eine Zuweisung damit der Ausgang CNT der top_entity dem aktuellen Zaehlerstand entspricht
|
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|
|
||||||
|
end Behavioral;
|
3
U2_Entity_Component/vsim.wave
Normal file
3
U2_Entity_Component/vsim.wave
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
onerror {resume}
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||||||
|
quietly WaveActivateNextPane {} 0
|
||||||
|
add wave -noupdate /test_top_entity/u_top_entity/*
|
11
U4_FSM/Makefile
Normal file
11
U4_FSM/Makefile
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
|
||||||
|
vhdl_srcs = down_counter_int.vhd \
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||||||
|
top_entity.vhd \
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||||||
|
test_top_entity.vhd \
|
||||||
|
|
||||||
|
main = test_top_entity
|
||||||
|
|
||||||
|
CHECK_RESULTS = true
|
||||||
|
|
||||||
|
include ../scripts/vhdl.mk
|
||||||
|
|
15
scripts/check_test_results.sh
Executable file
15
scripts/check_test_results.sh
Executable file
@ -0,0 +1,15 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
script_dir=$(cd $(dirname "${BASH_SOURCE[0]}") && pwd)
|
||||||
|
|
||||||
|
if [ $# -ne 1 ]
|
||||||
|
then
|
||||||
|
echo Usage $0 test-output-file
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
||||||
|
cat $1 | sed -z -e 's/\(py_.* \[\)/ \[/g' | ${script_dir}/highlight_test_results.sh
|
||||||
|
|
||||||
|
if grep -q FAIL $1
|
||||||
|
then
|
||||||
|
exit 1
|
||||||
|
fi
|
14
scripts/execute_and_highlight.sh
Executable file
14
scripts/execute_and_highlight.sh
Executable file
@ -0,0 +1,14 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
script_path="$( dirname "$( readlink -f "${BASH_SOURCE[0]}" )" )"
|
||||||
|
|
||||||
|
if [ $# -lt 1 ]
|
||||||
|
then
|
||||||
|
echo " usage: execute_and_highlight command arguments"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
||||||
|
cmd=$1
|
||||||
|
shift 1
|
||||||
|
$cmd $@ | $script_path/highlight_test_results.sh
|
||||||
|
test ${PIPESTATUS[0]} -eq 0
|
||||||
|
|
64
scripts/ghdl.mk
Normal file
64
scripts/ghdl.mk
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
#
|
||||||
|
#
|
||||||
|
#
|
||||||
|
#
|
||||||
|
|
||||||
|
# Make sure that the top level is assigned to main
|
||||||
|
$(if $(main),,\
|
||||||
|
$(error Assign top level entity name to variable "main"))
|
||||||
|
|
||||||
|
# Make sure that at least on vhdl source is assigned
|
||||||
|
$(if $(vhdl_srcs),,\
|
||||||
|
$(error Assign at least on vhdl source to variable "vhdl_srcs"))
|
||||||
|
|
||||||
|
# Append prefix -d to all generics
|
||||||
|
generics = $(addprefix -g,$(generics))
|
||||||
|
|
||||||
|
# Add VHDL 2008 as default build standard
|
||||||
|
vhdl_flags += --std=08
|
||||||
|
vhdl_flags += -frelaxed-rules
|
||||||
|
#vhdl_flags += --ieee-asserts=disable-at-0
|
||||||
|
|
||||||
|
vhdl_objs = $(vhdl_srcs:.vhd=.o)
|
||||||
|
|
||||||
|
assert_level := error
|
||||||
|
|
||||||
|
.PHONY: sim clean
|
||||||
|
|
||||||
|
sim: ${main}
|
||||||
|
@../scripts/execute_and_highlight.sh \
|
||||||
|
ghdl \
|
||||||
|
-r ${vhdl_flags} ${main} \
|
||||||
|
-gCHECK_RESULTS=${CHECK_RESULTS} \
|
||||||
|
--read-wave-opt=${main}.wave \
|
||||||
|
--assert-level=${assert_level}
|
||||||
|
|
||||||
|
gui: ${main}.ghw
|
||||||
|
@echo "Viewing $<"
|
||||||
|
@gtkwave $< --script=gtkwave.view
|
||||||
|
|
||||||
|
${main}.ghw: ${main} ${main}.wave
|
||||||
|
@ghdl -r ${vhdl_flags} ${main} \
|
||||||
|
--read-wave-opt=${main}.wave \
|
||||||
|
--wave=$@
|
||||||
|
|
||||||
|
${main}: $(vhdl_objs)
|
||||||
|
@echo "Elaborating ${main}"
|
||||||
|
@ghdl -e ${vhdl_flags} ${main}
|
||||||
|
|
||||||
|
%.o: %.vhd
|
||||||
|
@echo "Analysing $<"
|
||||||
|
@ghdl -a ${vhdl_flags} $<
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@ghdl --clean
|
||||||
|
@rm -rf ${main}.ghw work-obj08.cf ${vhdl_objs} ${main} ${artifacts}
|
||||||
|
|
||||||
|
help:
|
||||||
|
@echo Use ghdl to simulate and synthesis a vhdl design.
|
||||||
|
@echo
|
||||||
|
@echo Build configuration variables:
|
||||||
|
@echo main main entity
|
||||||
|
@echo vhdl_flags
|
||||||
|
@echo generics
|
||||||
|
|
7
scripts/highlight_test_results.sh
Executable file
7
scripts/highlight_test_results.sh
Executable file
@ -0,0 +1,7 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
|
||||||
|
red=$(tput setaf 1)
|
||||||
|
green=$(tput setaf 2)
|
||||||
|
default=$(tput sgr0)
|
||||||
|
|
||||||
|
sed "s/FAIL/${red}FAIL${default}/" | sed "s/OK/${green}OK${default}/"
|
64
scripts/questa-sim.mk
Normal file
64
scripts/questa-sim.mk
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
#
|
||||||
|
#
|
||||||
|
#
|
||||||
|
#
|
||||||
|
|
||||||
|
# Make sure that the top level is assigned to main
|
||||||
|
$(if $(main),,\
|
||||||
|
$(error Assign top level entity name to variable "main"))
|
||||||
|
|
||||||
|
# Make sure that at least on vhdl source is assigned
|
||||||
|
$(if $(vhdl_srcs),,\
|
||||||
|
$(error Assign at least on vhdl source to variable "vhdl_srcs"))
|
||||||
|
|
||||||
|
# Add VHDL 2008 as default build standard
|
||||||
|
vhdl_flags += -2008
|
||||||
|
|
||||||
|
vhdl_objs = $(vhdl_srcs:.vhd=.vhdo)
|
||||||
|
verilog_objs = $(verilog_srcs:.v=.vo)
|
||||||
|
|
||||||
|
assert_level := error
|
||||||
|
|
||||||
|
.PHONY: sim clean
|
||||||
|
|
||||||
|
gui: ${verilog_objs} ${vhdl_objs}
|
||||||
|
@vsim \
|
||||||
|
-gCHECK_RESULTS=$(CHECK_RESULTS) \
|
||||||
|
-voptargs=+acc work.${main} -do "do vsim.wave; run -all"
|
||||||
|
|
||||||
|
sim: ${verilog_objs} ${vhdl_objs}
|
||||||
|
@vsim \
|
||||||
|
-gCHECK_RESULTS=$(CHECK_RESULTS) \
|
||||||
|
-voptargs=+acc -c work.${main} -do "run -all" \
|
||||||
|
| ../scripts/highlight_test_results.sh
|
||||||
|
|
||||||
|
%.vo: %.v .libwork
|
||||||
|
@echo "Analysing $<"
|
||||||
|
@vlog -work work ${verilog_flags} $<
|
||||||
|
|
||||||
|
%.vhdo: %.vhd .libwork
|
||||||
|
@echo "Analysing $<"
|
||||||
|
@vcom -work work ${vhdl_flags} $<
|
||||||
|
|
||||||
|
|
||||||
|
.libwork:
|
||||||
|
@vlib work && vmap work work && touch $@
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@rm -rf work \
|
||||||
|
.libwork \
|
||||||
|
transcript \
|
||||||
|
modelsim.ini \
|
||||||
|
vlog.opt \
|
||||||
|
vsim.wlf \
|
||||||
|
data.py \
|
||||||
|
data.pyc \
|
||||||
|
|
||||||
|
help:
|
||||||
|
@echo Use ghdl to simulate and synthesis a vhdl design.
|
||||||
|
@echo
|
||||||
|
@echo Build configuration variables:
|
||||||
|
@echo main main entity
|
||||||
|
@echo vhdl_flags
|
||||||
|
@echo generics
|
||||||
|
|
23
scripts/vhdl.mk
Normal file
23
scripts/vhdl.mk
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
|
||||||
|
ghdl_version = $(shell ghdl --version 2> /dev/null)
|
||||||
|
vsim_version = $(shell vsim -version 2> /dev/null)
|
||||||
|
|
||||||
|
# in case verilog is part of the build a verilog capable simulator is required
|
||||||
|
ifdef verilog_srcs
|
||||||
|
ifneq (${vsim_version},)
|
||||||
|
include ../scripts/questa-sim.mk
|
||||||
|
else
|
||||||
|
$(error No HDL simulation tool found for verilog!)
|
||||||
|
endif
|
||||||
|
else
|
||||||
|
ifneq (${vsim_version},)
|
||||||
|
include ../scripts/questa-sim.mk
|
||||||
|
else
|
||||||
|
ifneq (${ghdl_version},)
|
||||||
|
include ../scripts/ghdl.mk
|
||||||
|
else
|
||||||
|
$(error No HDL simulation tool found!)
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
Loading…
x
Reference in New Issue
Block a user