Browse Source

restructured level shifter

master
Dominik Bartsch 3 years ago
parent
commit
2ccacbc295

+ 722
- 682
Wortuhr_SK6812.kicad_pcb
File diff suppressed because it is too large
View File


+ 35
- 12
Wortuhr_SK6812.sch View File

@@ -989,17 +989,6 @@ F 3 "https://assets.nexperia.com/documents/data-sheet/74HC_HCT04.pdf" H 9450 495
$EndComp
$Comp
L 74xx:74HCT04 U5
U 3 1 60EDB88A
P 8700 5400
F 0 "U5" H 8700 5717 50 0000 C CNN
F 1 "74HCT04" H 8700 5626 50 0000 C CNN
F 2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" H 8700 5400 50 0001 C CNN
F 3 "https://assets.nexperia.com/documents/data-sheet/74HC_HCT04.pdf" H 8700 5400 50 0001 C CNN
3 8700 5400
1 0 0 -1
$EndComp
$Comp
L 74xx:74HCT04 U5
U 4 1 60EDD68A
P 9450 5400
F 0 "U5" H 9450 5717 50 0000 C CNN
@@ -1078,7 +1067,7 @@ F 3 "" H 6250 5000 50 0001 C CNN
1 0 0 -1
$EndComp
Wire Wire Line
6250 5550 6250 5400
6250 5550 6250 5450
Wire Wire Line
6250 5100 6250 5000
Wire Wire Line
@@ -1162,4 +1151,38 @@ Text Label 5250 4450 0 50 ~ 0
D3.3
Text Label 5250 4950 0 50 ~ 0
C3.3
$Comp
L 74xx:74HCT04 U5
U 5 1 60F1CCCD
P 8700 5400
F 0 "U5" H 8700 5717 50 0000 C CNN
F 1 "74HCT04" H 8700 5626 50 0000 C CNN
F 2 "" H 8700 5400 50 0001 C CNN
F 3 "https://assets.nexperia.com/documents/data-sheet/74HC_HCT04.pdf" H 8700 5400 50 0001 C CNN
5 8700 5400
1 0 0 -1
$EndComp
$Comp
L Device:C C8
U 1 1 60F2ACCA
P 5750 6050
F 0 "C8" H 5865 6096 50 0000 L CNN
F 1 "C" H 5865 6005 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 5788 5900 50 0001 C CNN
F 3 "~" H 5750 6050 50 0001 C CNN
1 5750 6050
1 0 0 -1
$EndComp
Wire Wire Line
6250 6550 5750 6550
Wire Wire Line
5750 6550 5750 6200
Connection ~ 6250 6550
Wire Wire Line
5750 5900 5750 5450
Wire Wire Line
5750 5450 6250 5450
Connection ~ 6250 5450
Wire Wire Line
6250 5450 6250 5400
$EndSCHEMATC

+ 63
- 18
Wortuhr_SK6812.sch-bak View File

@@ -230,10 +230,6 @@ F 3 "~" H 7050 3800 50 0001 C CNN
$EndComp
Wire Wire Line
6250 2900 6250 1750
Wire Wire Line
5550 3000 6350 3000
Wire Wire Line
6350 3000 6350 2400
Wire Wire Line
6350 2400 6800 2400
Wire Wire Line
@@ -251,8 +247,6 @@ F 3 "~" H 7050 3100 50 0001 C CNN
$EndComp
Wire Wire Line
6350 3800 6800 3800
Wire Wire Line
5550 3100 6800 3100
$Comp
L power:GND #PWR019
U 1 1 60E2F432
@@ -857,9 +851,6 @@ Wire Wire Line
5600 1750 5600 1900
Wire Wire Line
5600 2500 5600 2200
Connection ~ 5600 2500
Wire Wire Line
5600 2500 5750 2500
$Comp
L Timer_RTC:DS3231M U4
U 1 1 60E5E3D0
@@ -954,13 +945,8 @@ Wire Wire Line
Wire Wire Line
3150 5950 2750 5950
Connection ~ 2750 5950
Connection ~ 6200 3200
Wire Wire Line
6200 3200 6350 3200
Wire Wire Line
5550 3200 6200 3200
Wire Wire Line
5550 3300 5750 3300
$Comp
L Connector:Conn_01x14_Female J1
U 1 1 60EAC831
@@ -1035,10 +1021,6 @@ Wire Wire Line
9500 2700 10000 2700
Wire Wire Line
10000 2800 9500 2800
Text Label 5750 2500 0 50 ~ 0
D3.3
Text Label 5750 3300 0 50 ~ 0
C3.3
Text Label 8200 4950 2 50 ~ 0
D3.3
Text Label 8200 5400 2 50 ~ 0
@@ -1117,4 +1099,67 @@ Wire Wire Line
Wire Wire Line
9850 3400 10000 3400
Connection ~ 9850 2100
$Comp
L Jumper:SolderJumper_3_Open JP2
U 1 1 60E8A0F5
P 4850 4250
F 0 "JP2" V 4896 4317 50 0000 L CNN
F 1 "SolderJumper_3_Open" V 4805 4317 50 0000 L CNN
F 2 "Jumper:SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm" H 4850 4250 50 0001 C CNN
F 3 "~" H 4850 4250 50 0001 C CNN
1 4850 4250
0 1 1 0
$EndComp
$Comp
L Jumper:SolderJumper_3_Open JP3
U 1 1 60E9407D
P 4850 4750
F 0 "JP3" V 4896 4817 50 0000 L CNN
F 1 "SolderJumper_3_Open" V 4805 4817 50 0000 L CNN
F 2 "Jumper:SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm" H 4850 4750 50 0001 C CNN
F 3 "~" H 4850 4750 50 0001 C CNN
1 4850 4750
0 1 1 0
$EndComp
Wire Wire Line
4850 4050 5250 4050
Wire Wire Line
4700 4250 4450 4250
Wire Wire Line
4850 4450 5250 4450
Connection ~ 6200 3200
Wire Wire Line
5550 3200 6200 3200
Text Label 6350 2400 0 50 ~ 0
MOS1_G
Wire Wire Line
6800 3100 6350 3100
Text Label 6350 3100 0 50 ~ 0
MOS4_G
Wire Wire Line
5550 3000 5750 3000
Wire Wire Line
5550 3100 5750 3100
Text Label 5750 3000 0 50 ~ 0
GPIO13
Text Label 5750 3100 0 50 ~ 0
GPIO14
Text Label 4450 4250 0 50 ~ 0
GPIO13
Wire Wire Line
4700 4750 4450 4750
Wire Wire Line
4850 4550 5250 4550
Wire Wire Line
4850 4950 5250 4950
Text Label 4450 4750 0 50 ~ 0
GPIO14
Text Label 5250 4050 0 50 ~ 0
MOS1_G
Text Label 5250 4550 0 50 ~ 0
MOS4_G
Text Label 5250 4450 0 50 ~ 0
D3.3
Text Label 5250 4950 0 50 ~ 0
C3.3
$EndSCHEMATC

+ 0
- 56
loadbox/loadbox-cache.lib View File

@@ -1,56 +0,0 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device_D_Zener
#
DEF Device_D_Zener D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_D_Zener" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 3 0 1 10 -50 -50 -50 50 -30 50 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

+ 0
- 1
loadbox/loadbox.kicad_pcb View File

@@ -1 +0,0 @@
(kicad_pcb (version 4) (host kicad "dummy file") )

+ 0
- 33
loadbox/loadbox.pro View File

@@ -1,33 +0,0 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

+ 0
- 64
loadbox/loadbox.sch View File

@@ -1,64 +0,0 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Device:D_Zener D1
U 1 1 5FFF41D4
P 5400 3150
F 0 "D1" V 5354 3230 50 0000 L CNN
F 1 "ZPY9.1" V 5445 3230 50 0000 L CNN
F 2 "" H 5400 3150 50 0001 C CNN
F 3 "~" H 5400 3150 50 0001 C CNN
1 5400 3150
0 1 1 0
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5FFF5E5D
P 5400 3500
F 0 "#PWR?" H 5400 3250 50 0001 C CNN
F 1 "GND" H 5405 3327 50 0000 C CNN
F 2 "" H 5400 3500 50 0001 C CNN
F 3 "" H 5400 3500 50 0001 C CNN
1 5400 3500
1 0 0 -1
$EndComp
$Comp
L Device:R R1
U 1 1 5FFF711E
P 5400 2650
F 0 "R1" H 5470 2696 50 0000 L CNN
F 1 "1k2" H 5470 2605 50 0000 L CNN
F 2 "" V 5330 2650 50 0001 C CNN
F 3 "~" H 5400 2650 50 0001 C CNN
1 5400 2650
1 0 0 -1
$EndComp
Wire Wire Line
5400 3500 5400 3300
Text GLabel 5050 2500 0 50 Input ~ 0
Signal_Controllino
Text GLabel 5850 2900 2 50 Input ~ 0
Signal_Treiber
Wire Wire Line
5400 2800 5400 2900
Wire Wire Line
5050 2500 5400 2500
Wire Wire Line
5400 2900 5850 2900
Connection ~ 5400 2900
Wire Wire Line
5400 2900 5400 3000
$EndSCHEMATC

+ 0
- 4
loadbox/loadbox.sch-bak View File

@@ -1,4 +0,0 @@
EESchema Schematic File Version 2
EELAYER 25 0
EELAYER END
$EndSCHEMATC

BIN
plot.zip View File


+ 0
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plot/Wortuhr_SK6812-B_Cu.gbr
File diff suppressed because it is too large
View File


+ 0
- 58
plot/Wortuhr_SK6812-B_Mask.gbr View File

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%TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10)-1*%
%TF.CreationDate,2021-07-07T23:24:12+02:00*%
%TF.ProjectId,Wortuhr_SK6812,576f7274-7568-4725-9f53-4b363831322e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Bot*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.10)-1) date 2021-07-07 23:24:12*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
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%ADD11R,1.700000X1.700000*%
%ADD12C,1.600000*%
%ADD13R,2.350000X2.350000*%
%ADD14C,2.000000*%
%ADD15R,2.000000X2.000000*%
G04 APERTURE END LIST*
D10*
%TO.C,J2*%
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D11*
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%TD*%
D12*
%TO.C,BT1*%
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D13*
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%TD*%
D10*
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D11*
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%TD*%
D14*
%TO.C,C1*%
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D15*
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%TD*%
M02*

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plot/Wortuhr_SK6812-B_Paste.gbr View File

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%TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10)-1*%
%TF.CreationDate,2021-07-07T23:24:12+02:00*%
%TF.ProjectId,Wortuhr_SK6812,576f7274-7568-4725-9f53-4b363831322e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Paste,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.10)-1) date 2021-07-07 23:24:12*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
G04 APERTURE END LIST*
M02*

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plot/Wortuhr_SK6812-B_SilkS.gbr View File

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%TF.GenerationSoftware,KiCad,Pcbnew,(5.1.10)-1*%
%TF.CreationDate,2021-07-07T23:24:12+02:00*%
%TF.ProjectId,Wortuhr_SK6812,576f7274-7568-4725-9f53-4b363831322e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Legend,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.10)-1) date 2021-07-07 23:24:12*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%ADD10C,0.150000*%
G04 APERTURE END LIST*
D10*
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"Path": "Wortuhr_SK6812-F_Mask.gbr",
"FileFunction": "SolderMask,Top",
"FilePolarity": "Negative"
},
{
"Path": "Wortuhr_SK6812-B_Mask.gbr",
"FileFunction": "SolderMask,Bot",
"FilePolarity": "Negative"
},
{
"Path": "Wortuhr_SK6812-Edge_Cuts.gbr",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup":
[
{
"Type": "Legend",
"Notes": "Layer F.SilkS"
},
{
"Type": "SolderPaste",
"Notes": "Layer F.Paste"
},
{
"Type": "SolderMask",
"Notes": "Layer F.Mask"
},
{
"Type": "Copper",
"Notes": "Layer F.Cu"
},
{
"Type": "Dielectric",
"Material": "FR4",
"Notes": "Layers L1/L2"
},
{
"Type": "Copper",
"Notes": "Layer B.Cu"
},
{
"Type": "SolderMask",
"Notes": "Layer B.Mask"
},
{
"Type": "SolderPaste",
"Notes": "Layer B.Paste"
},
{
"Type": "Legend",
"Notes": "Layer B.SilkS"
}
]
}

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