Florian Brandl brandlfl78731
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  • Joined on 2021-10-01
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brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-12-18 09:04:15 +00:00
baa5aa4c74 FPGA programmiert
brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-12-18 08:16:40 +00:00
c9ca4d965a Versuch 3 Hardware funktioniert Juhu!
brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-12-11 10:24:39 +00:00
509e01e501 Versuch 3 CRC Hardware vorlaeufig
brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-12-04 10:17:36 +00:00
118d08219e Versuch 3 CRC, Software fertig
brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-11-27 10:23:08 +00:00
45db9f89e2 Versuch 3 Software so halb
de8d181dde Versuch 2 Hardware funktioniert
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brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-11-20 10:30:21 +00:00
cfe1e2927c Versuch 2 Hardware vorlaeufig
03a4e64337 Versuch 2 Software funktioniert
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brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-11-20 08:42:33 +00:00
00fd3908d8 Versuch add abgeschlossen. Funktioniert auch praktisch!
brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-11-20 08:27:11 +00:00
641e3a6945 Sollte theoretisch funktionieren
c4491f89e0 Sollte theoretisch funktionieren - mit muell
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brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-11-13 10:17:35 +00:00
f5940ef807 Task4 hardware add.vhd vorlaeufig
brandlfl78731 pushed to master at hauselthe74767/signal_processing_vorlage 2024-11-13 08:16:41 +00:00
b1adcc892a Task4 software add.c